1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ***************************************************************************/
38 * fm10k_reset_hw_pf - PF hardware reset
39 * @hw: pointer to hardware structure
41 * This function should return the hardware to a state similar to the
42 * one it is in after being powered on.
44 STATIC s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
50 DEBUGFUNC("fm10k_reset_hw_pf");
52 /* Disable interrupts */
53 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
55 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
56 FM10K_WRITE_REG(hw, FM10K_ITR2(0), 0);
57 FM10K_WRITE_REG(hw, FM10K_INT_CTRL, 0);
59 /* We assume here Tx and Rx queue 0 are owned by the PF */
61 /* Shut off VF access to their queues forcing them to queue 0 */
62 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
63 FM10K_WRITE_REG(hw, FM10K_TQMAP(i), 0);
64 FM10K_WRITE_REG(hw, FM10K_RQMAP(i), 0);
67 /* shut down all rings */
68 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
72 /* Verify that DMA is no longer active */
73 reg = FM10K_READ_REG(hw, FM10K_DMA_CTRL);
74 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
75 return FM10K_ERR_DMA_PENDING;
77 /* verify the switch is ready for reset */
78 reg = FM10K_READ_REG(hw, FM10K_DMA_CTRL2);
79 if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY))
82 /* Inititate data path reset */
83 reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
84 FM10K_WRITE_REG(hw, FM10K_DMA_CTRL, reg);
86 /* Flush write and allow 100us for reset to complete */
87 FM10K_WRITE_FLUSH(hw);
88 usec_delay(FM10K_RESET_TIMEOUT);
90 /* Verify we made it out of reset */
91 reg = FM10K_READ_REG(hw, FM10K_IP);
92 if (!(reg & FM10K_IP_NOTINRESET))
93 err = FM10K_ERR_RESET_FAILED;
100 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
101 * @hw: pointer to hardware structure
103 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
105 STATIC bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
107 u16 sriov_ctrl = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_SRIOV_CTRL);
109 DEBUGFUNC("fm10k_is_ari_hierarchy_pf");
111 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
115 * fm10k_init_hw_pf - PF hardware initialization
116 * @hw: pointer to hardware structure
119 STATIC s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
121 u32 dma_ctrl, txqctl;
124 DEBUGFUNC("fm10k_init_hw_pf");
126 /* Establish default VSI as valid */
127 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
128 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
129 FM10K_DGLORTMAP_ANY);
131 /* Invalidate all other GLORT entries */
132 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
133 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
135 /* reset ITR2(0) to point to itself */
136 FM10K_WRITE_REG(hw, FM10K_ITR2(0), 0);
138 /* reset VF ITR2(0) to point to 0 avoid PF registers */
139 FM10K_WRITE_REG(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
141 /* loop through all PF ITR2 registers pointing them to the previous */
142 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
143 FM10K_WRITE_REG(hw, FM10K_ITR2(i), i - 1);
145 /* Enable interrupt moderator if not already enabled */
146 FM10K_WRITE_REG(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
148 /* compute the default txqctl configuration */
149 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
150 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
152 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
153 /* configure rings for 256 Queue / 32 Descriptor cache mode */
154 FM10K_WRITE_REG(hw, FM10K_TQDLOC(i),
155 (i * FM10K_TQDLOC_BASE_32_DESC) |
156 FM10K_TQDLOC_SIZE_32_DESC);
157 FM10K_WRITE_REG(hw, FM10K_TXQCTL(i), txqctl);
159 /* configure rings to provide TPH processing hints */
160 FM10K_WRITE_REG(hw, FM10K_TPH_TXCTRL(i),
161 FM10K_TPH_TXCTRL_DESC_TPHEN |
162 FM10K_TPH_TXCTRL_DESC_RROEN |
163 FM10K_TPH_TXCTRL_DESC_WROEN |
164 FM10K_TPH_TXCTRL_DATA_RROEN);
165 FM10K_WRITE_REG(hw, FM10K_TPH_RXCTRL(i),
166 FM10K_TPH_RXCTRL_DESC_TPHEN |
167 FM10K_TPH_RXCTRL_DESC_RROEN |
168 FM10K_TPH_RXCTRL_DATA_WROEN |
169 FM10K_TPH_RXCTRL_HDR_WROEN);
172 /* set max hold interval to align with 1.024 usec in all modes and
175 switch (hw->bus.speed) {
176 case fm10k_bus_speed_2500:
177 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
178 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1;
180 case fm10k_bus_speed_5000:
181 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
182 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2;
184 case fm10k_bus_speed_8000:
185 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
186 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
190 /* just in case, assume Gen3 ITR scale */
191 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
195 /* Configure TSO flags */
196 FM10K_WRITE_REG(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
197 FM10K_WRITE_REG(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
200 * Set Rx Descriptor size to 32
201 * Set Minimum MSS to 64
202 * Set Maximum number of Rx queues to 256 / 32 Descriptor
204 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
205 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
206 FM10K_DMA_CTRL_32_DESC;
208 FM10K_WRITE_REG(hw, FM10K_DMA_CTRL, dma_ctrl);
210 /* record maximum queue count, we limit ourselves to 128 */
211 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
213 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
214 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
216 return FM10K_SUCCESS;
219 #ifndef NO_IS_SLOT_APPROPRIATE_CHECK
221 * fm10k_is_slot_appropriate_pf - Indicate appropriate slot for this SKU
222 * @hw: pointer to hardware structure
224 * Looks at the PCIe bus info to confirm whether or not this slot can support
225 * the necessary bandwidth for this device.
227 STATIC bool fm10k_is_slot_appropriate_pf(struct fm10k_hw *hw)
229 DEBUGFUNC("fm10k_is_slot_appropriate_pf");
231 return (hw->bus.speed == hw->bus_caps.speed) &&
232 (hw->bus.width == hw->bus_caps.width);
237 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
238 * @hw: pointer to hardware structure
239 * @vid: VLAN ID to add to table
240 * @vsi: Index indicating VF ID or PF ID in table
241 * @set: Indicates if this is a set or clear operation
243 * This function adds or removes the corresponding VLAN ID from the VLAN
244 * filter table for the corresponding function. In addition to the
245 * standard set/clear that supports one bit a multi-bit write is
246 * supported to set 64 bits at a time.
248 STATIC s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
250 u32 vlan_table, reg, mask, bit, len;
252 /* verify the VSI index is valid */
253 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
254 return FM10K_ERR_PARAM;
256 /* VLAN multi-bit write:
257 * The multi-bit write has several parts to it.
259 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
260 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
261 * | RSVD0 | Length |C|RSVD0| VLAN ID |
262 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
264 * VLAN ID: Vlan Starting value
265 * RSVD0: Reserved section, must be 0
266 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
267 * Length: Number of times to repeat the bit being set
270 vid = (vid << 17) >> 17;
272 /* verify the reserved 0 fields are 0 */
273 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)
274 return FM10K_ERR_PARAM;
276 /* Loop through the table updating all required VLANs */
277 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
278 len < FM10K_VLAN_TABLE_VID_MAX;
279 len -= 32 - bit, reg++, bit = 0) {
280 /* record the initial state of the register */
281 vlan_table = FM10K_READ_REG(hw, reg);
283 /* truncate mask if we are at the start or end of the run */
284 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
286 /* make necessary modifications to the register */
287 mask &= set ? ~vlan_table : vlan_table;
289 FM10K_WRITE_REG(hw, reg, vlan_table ^ mask);
292 return FM10K_SUCCESS;
296 * fm10k_read_mac_addr_pf - Read device MAC address
297 * @hw: pointer to the HW structure
299 * Reads the device MAC address from the SM_AREA and stores the value.
301 STATIC s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
303 u8 perm_addr[ETH_ALEN];
306 DEBUGFUNC("fm10k_read_mac_addr_pf");
308 serial_num = FM10K_READ_REG(hw, FM10K_SM_AREA(1));
310 /* last byte should be all 1's */
311 if ((~serial_num) << 24)
312 return FM10K_ERR_INVALID_MAC_ADDR;
314 perm_addr[0] = (u8)(serial_num >> 24);
315 perm_addr[1] = (u8)(serial_num >> 16);
316 perm_addr[2] = (u8)(serial_num >> 8);
318 serial_num = FM10K_READ_REG(hw, FM10K_SM_AREA(0));
320 /* first byte should be all 1's */
321 if ((~serial_num) >> 24)
322 return FM10K_ERR_INVALID_MAC_ADDR;
324 perm_addr[3] = (u8)(serial_num >> 16);
325 perm_addr[4] = (u8)(serial_num >> 8);
326 perm_addr[5] = (u8)(serial_num);
328 memcpy(hw->mac.perm_addr, perm_addr, ETH_ALEN);
329 memcpy(hw->mac.addr, perm_addr, ETH_ALEN);
331 return FM10K_SUCCESS;
335 * fm10k_glort_valid_pf - Validate that the provided glort is valid
336 * @hw: pointer to the HW structure
337 * @glort: base glort to be validated
339 * This function will return an error if the provided glort is invalid
341 bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
343 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
345 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
349 * fm10k_update_xc_addr_pf - Update device addresses
350 * @hw: pointer to the HW structure
351 * @glort: base resource tag for this request
352 * @mac: MAC address to add/remove from table
353 * @vid: VLAN ID to add/remove from table
354 * @add: Indicates if this is an add or remove operation
355 * @flags: flags field to indicate add and secure
357 * This function generates a message to the Switch API requesting
358 * that the given logical port add/remove the given L2 MAC/VLAN address.
360 STATIC s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
361 const u8 *mac, u16 vid, bool add, u8 flags)
363 struct fm10k_mbx_info *mbx = &hw->mbx;
364 struct fm10k_mac_update mac_update;
367 DEBUGFUNC("fm10k_update_xc_addr_pf");
369 /* clear set bit from VLAN ID */
370 vid &= ~FM10K_VLAN_CLEAR;
372 /* if glort or VLAN are not valid return error */
373 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
374 return FM10K_ERR_PARAM;
377 mac_update.mac_lower = FM10K_CPU_TO_LE32(((u32)mac[2] << 24) |
378 ((u32)mac[3] << 16) |
381 mac_update.mac_upper = FM10K_CPU_TO_LE16(((u16)mac[0] << 8) |
383 mac_update.vlan = FM10K_CPU_TO_LE16(vid);
384 mac_update.glort = FM10K_CPU_TO_LE16(glort);
385 mac_update.action = add ? 0 : 1;
386 mac_update.flags = flags;
388 /* populate mac_update fields */
389 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
390 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
391 &mac_update, sizeof(mac_update));
393 /* load onto outgoing mailbox */
394 return mbx->ops.enqueue_tx(hw, mbx, msg);
398 * fm10k_update_uc_addr_pf - Update device unicast addresses
399 * @hw: pointer to the HW structure
400 * @glort: base resource tag for this request
401 * @mac: MAC address to add/remove from table
402 * @vid: VLAN ID to add/remove from table
403 * @add: Indicates if this is an add or remove operation
404 * @flags: flags field to indicate add and secure
406 * This function is used to add or remove unicast addresses for
409 STATIC s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
410 const u8 *mac, u16 vid, bool add, u8 flags)
412 DEBUGFUNC("fm10k_update_uc_addr_pf");
414 /* verify MAC address is valid */
415 if (!FM10K_IS_VALID_ETHER_ADDR(mac))
416 return FM10K_ERR_PARAM;
418 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
422 * fm10k_update_mc_addr_pf - Update device multicast addresses
423 * @hw: pointer to the HW structure
424 * @glort: base resource tag for this request
425 * @mac: MAC address to add/remove from table
426 * @vid: VLAN ID to add/remove from table
427 * @add: Indicates if this is an add or remove operation
429 * This function is used to add or remove multicast MAC addresses for
432 STATIC s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
433 const u8 *mac, u16 vid, bool add)
435 DEBUGFUNC("fm10k_update_mc_addr_pf");
437 /* verify multicast address is valid */
438 if (!FM10K_IS_MULTICAST_ETHER_ADDR(mac))
439 return FM10K_ERR_PARAM;
441 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
445 * fm10k_update_xcast_mode_pf - Request update of multicast mode
446 * @hw: pointer to hardware structure
447 * @glort: base resource tag for this request
448 * @mode: integer value indicating mode being requested
450 * This function will attempt to request a higher mode for the port
451 * so that it can enable either multicast, multicast promiscuous, or
452 * promiscuous mode of operation.
454 STATIC s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
456 struct fm10k_mbx_info *mbx = &hw->mbx;
457 u32 msg[3], xcast_mode;
459 DEBUGFUNC("fm10k_update_xcast_mode_pf");
461 if (mode > FM10K_XCAST_MODE_NONE)
462 return FM10K_ERR_PARAM;
464 /* if glort is not valid return error */
465 if (!fm10k_glort_valid_pf(hw, glort))
466 return FM10K_ERR_PARAM;
468 /* write xcast mode as a single u32 value,
469 * lower 16 bits: glort
470 * upper 16 bits: mode
472 xcast_mode = ((u32)mode << 16) | glort;
474 /* generate message requesting to change xcast mode */
475 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
476 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
478 /* load onto outgoing mailbox */
479 return mbx->ops.enqueue_tx(hw, mbx, msg);
483 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
484 * @hw: pointer to hardware structure
486 * This function walks through the MSI-X vector table to determine the
487 * number of active interrupts and based on that information updates the
488 * interrupt moderator linked list.
490 STATIC void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
494 /* Disable interrupt moderator */
495 FM10K_WRITE_REG(hw, FM10K_INT_CTRL, 0);
497 /* loop through PF from last to first looking enabled vectors */
498 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
499 if (!FM10K_READ_REG(hw, FM10K_MSIX_VECTOR_MASK(i)))
503 /* always reset VFITR2[0] to point to last enabled PF vector */
504 FM10K_WRITE_REG(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
506 /* reset ITR2[0] to point to last enabled PF vector */
507 if (!hw->iov.num_vfs)
508 FM10K_WRITE_REG(hw, FM10K_ITR2(0), i);
510 /* Enable interrupt moderator */
511 FM10K_WRITE_REG(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
515 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
516 * @hw: pointer to the HW structure
517 * @glort: base resource tag for this request
518 * @count: number of logical ports being updated
519 * @enable: boolean value indicating enable or disable
521 * This function is used to add/remove a logical port from the switch.
523 STATIC s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
524 u16 count, bool enable)
526 struct fm10k_mbx_info *mbx = &hw->mbx;
527 u32 msg[3], lport_msg;
529 DEBUGFUNC("fm10k_lport_state_pf");
531 /* do nothing if we are being asked to create or destroy 0 ports */
533 return FM10K_SUCCESS;
535 /* if glort is not valid return error */
536 if (!fm10k_glort_valid_pf(hw, glort))
537 return FM10K_ERR_PARAM;
539 /* reset multicast mode if deleting lport */
541 fm10k_update_xcast_mode_pf(hw, glort, FM10K_XCAST_MODE_NONE);
543 /* construct the lport message from the 2 pieces of data we have */
544 lport_msg = ((u32)count << 16) | glort;
546 /* generate lport create/delete message */
547 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
548 FM10K_PF_MSG_ID_LPORT_DELETE);
549 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
551 /* load onto outgoing mailbox */
552 return mbx->ops.enqueue_tx(hw, mbx, msg);
556 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
557 * @hw: pointer to hardware structure
558 * @dglort: pointer to dglort configuration structure
560 * Reads the configuration structure contained in dglort_cfg and uses
561 * that information to then populate a DGLORTMAP/DEC entry and the queues
562 * to which it has been assigned.
564 STATIC s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
565 struct fm10k_dglort_cfg *dglort)
567 u16 glort, queue_count, vsi_count, pc_count;
568 u16 vsi, queue, pc, q_idx;
569 u32 txqctl, dglortdec, dglortmap;
571 /* verify the dglort pointer */
573 return FM10K_ERR_PARAM;
575 /* verify the dglort values */
576 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
577 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
578 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
579 return FM10K_ERR_PARAM;
581 /* determine count of VSIs and queues */
582 queue_count = BIT(dglort->rss_l + dglort->pc_l);
583 vsi_count = BIT(dglort->vsi_l + dglort->queue_l);
584 glort = dglort->glort;
585 q_idx = dglort->queue_b;
587 /* configure SGLORT for queues */
588 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
589 for (queue = 0; queue < queue_count; queue++, q_idx++) {
590 if (q_idx >= FM10K_MAX_QUEUES)
593 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(q_idx), glort);
594 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(q_idx), glort);
598 /* determine count of PCs and queues */
599 queue_count = BIT(dglort->queue_l + dglort->rss_l + dglort->vsi_l);
600 pc_count = BIT(dglort->pc_l);
602 /* configure PC for Tx queues */
603 for (pc = 0; pc < pc_count; pc++) {
604 q_idx = pc + dglort->queue_b;
605 for (queue = 0; queue < queue_count; queue++) {
606 if (q_idx >= FM10K_MAX_QUEUES)
609 txqctl = FM10K_READ_REG(hw, FM10K_TXQCTL(q_idx));
610 txqctl &= ~FM10K_TXQCTL_PC_MASK;
611 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
612 FM10K_WRITE_REG(hw, FM10K_TXQCTL(q_idx), txqctl);
618 /* configure DGLORTDEC */
619 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
620 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
621 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
622 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
623 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
624 ((u32)(dglort->queue_l));
625 if (dglort->inner_rss)
626 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
628 /* configure DGLORTMAP */
629 dglortmap = (dglort->idx == fm10k_dglort_default) ?
630 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
631 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
632 dglortmap |= dglort->glort;
634 /* write values to hardware */
635 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
636 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
638 return FM10K_SUCCESS;
641 u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
643 u16 num_pools = hw->iov.num_pools;
645 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
646 8 : FM10K_MAX_QUEUES_POOL;
649 u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
651 u16 num_vfs = hw->iov.num_vfs;
652 u16 vf_q_idx = FM10K_MAX_QUEUES;
654 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
659 STATIC u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
661 u16 num_pools = hw->iov.num_pools;
663 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
664 FM10K_MAX_VECTORS_POOL;
667 STATIC u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
669 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
671 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
677 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
678 * @hw: pointer to the HW structure
679 * @num_vfs: number of VFs to be allocated
680 * @num_pools: number of virtualization pools to be allocated
682 * Allocates queues and traffic classes to virtualization entities to prepare
683 * the PF for SR-IOV and VMDq
685 STATIC s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
688 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
689 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
692 /* hardware only supports up to 64 pools */
694 return FM10K_ERR_PARAM;
696 /* the number of VFs cannot exceed the number of pools */
697 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
698 return FM10K_ERR_PARAM;
700 /* record number of virtualization entities */
701 hw->iov.num_vfs = num_vfs;
702 hw->iov.num_pools = num_pools;
704 /* determine qmap offsets and counts */
705 qmap_stride = (num_vfs > 8) ? 32 : 256;
706 qpp = fm10k_queues_per_pool(hw);
707 vpp = fm10k_vectors_per_pool(hw);
709 /* calculate starting index for queues */
710 vf_q_idx = fm10k_vf_queue_index(hw, 0);
713 /* establish TCs with -1 credits and no quanta to prevent transmit */
714 for (i = 0; i < num_vfs; i++) {
715 FM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(i), 0);
716 FM10K_WRITE_REG(hw, FM10K_TC_RATE(i), 0);
717 FM10K_WRITE_REG(hw, FM10K_TC_CREDIT(i),
718 FM10K_TC_CREDIT_CREDIT_MASK);
721 /* zero out all mbmem registers */
722 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
723 FM10K_WRITE_REG(hw, FM10K_MBMEM(i), 0);
725 /* clear event notification of VF FLR */
726 FM10K_WRITE_REG(hw, FM10K_PFVFLREC(0), ~0);
727 FM10K_WRITE_REG(hw, FM10K_PFVFLREC(1), ~0);
729 /* loop through unallocated rings assigning them back to PF */
730 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
731 FM10K_WRITE_REG(hw, FM10K_TXDCTL(i), 0);
732 FM10K_WRITE_REG(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF |
733 FM10K_TXQCTL_UNLIMITED_BW | vid);
734 FM10K_WRITE_REG(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
737 /* PF should have already updated VFITR2[0] */
739 /* update all ITR registers to flow to VFITR2[0] */
740 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
741 if (!(i & (vpp - 1)))
742 FM10K_WRITE_REG(hw, FM10K_ITR2(i), i - vpp);
744 FM10K_WRITE_REG(hw, FM10K_ITR2(i), i - 1);
747 /* update PF ITR2[0] to reference the last vector */
748 FM10K_WRITE_REG(hw, FM10K_ITR2(0),
749 fm10k_vf_vector_index(hw, num_vfs - 1));
751 /* loop through rings populating rings and TCs */
752 for (i = 0; i < num_vfs; i++) {
753 /* record index for VF queue 0 for use in end of loop */
754 vf_q_idx0 = vf_q_idx;
756 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
757 /* assign VF and locked TC to queues */
758 FM10K_WRITE_REG(hw, FM10K_TXDCTL(vf_q_idx), 0);
759 FM10K_WRITE_REG(hw, FM10K_TXQCTL(vf_q_idx),
760 (i << FM10K_TXQCTL_TC_SHIFT) | i |
761 FM10K_TXQCTL_VF | vid);
762 FM10K_WRITE_REG(hw, FM10K_RXDCTL(vf_q_idx),
763 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
764 FM10K_RXDCTL_DROP_ON_EMPTY);
765 FM10K_WRITE_REG(hw, FM10K_RXQCTL(vf_q_idx),
766 (i << FM10K_RXQCTL_VF_SHIFT) |
769 /* map queue pair to VF */
770 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
771 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
774 /* repeat the first ring for all of the remaining VF rings */
775 for (; j < qmap_stride; j++, qmap_idx++) {
776 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
777 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
781 /* loop through remaining indexes assigning all to queue 0 */
782 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
783 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), 0);
784 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), 0);
788 return FM10K_SUCCESS;
792 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
793 * @hw: pointer to the HW structure
794 * @vf_idx: index of VF receiving GLORT
795 * @rate: Rate indicated in Mb/s
797 * Configured the TC for a given VF to allow only up to a given number
798 * of Mb/s of outgoing Tx throughput.
800 STATIC s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
802 /* configure defaults */
803 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
804 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
806 /* verify vf is in range */
807 if (vf_idx >= hw->iov.num_vfs)
808 return FM10K_ERR_PARAM;
810 /* set interval to align with 4.096 usec in all modes */
811 switch (hw->bus.speed) {
812 case fm10k_bus_speed_2500:
813 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
815 case fm10k_bus_speed_5000:
816 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
823 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
824 return FM10K_ERR_PARAM;
826 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
827 * The rate is provided in Mbits per second
828 * To tralslate from rate to quanta we need to multiply the
829 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
830 * dealing with floating point we can round the values up
831 * to the nearest whole number ratio which gives us 128 / 125.
833 tc_rate = (rate * 128) / 125;
835 /* try to keep the rate limiting accurate by increasing
836 * the number of credits and interval for rates less than 4Gb/s
844 /* update rate limiter with new values */
845 FM10K_WRITE_REG(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
846 FM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
847 FM10K_WRITE_REG(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
849 return FM10K_SUCCESS;
853 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
854 * @hw: pointer to the HW structure
855 * @vf_idx: index of VF receiving GLORT
857 * Update the interrupt moderator linked list to include any MSI-X
858 * interrupts which the VF has enabled in the MSI-X vector table.
860 STATIC s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
862 u16 vf_v_idx, vf_v_limit, i;
864 /* verify vf is in range */
865 if (vf_idx >= hw->iov.num_vfs)
866 return FM10K_ERR_PARAM;
868 /* determine vector offset and count */
869 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
870 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
872 /* search for first vector that is not masked */
873 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
874 if (!FM10K_READ_REG(hw, FM10K_MSIX_VECTOR_MASK(i)))
878 /* reset linked list so it now includes our active vectors */
879 if (vf_idx == (hw->iov.num_vfs - 1))
880 FM10K_WRITE_REG(hw, FM10K_ITR2(0), i);
882 FM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_limit), i);
884 return FM10K_SUCCESS;
888 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
889 * @hw: pointer to the HW structure
890 * @vf_info: pointer to VF information structure
892 * Assign a MAC address and default VLAN to a VF and notify it of the update
894 STATIC s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
895 struct fm10k_vf_info *vf_info)
897 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
898 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
899 s32 err = FM10K_SUCCESS;
902 /* verify vf is in range */
903 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
904 return FM10K_ERR_PARAM;
906 /* determine qmap offsets and counts */
907 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
908 queues_per_pool = fm10k_queues_per_pool(hw);
910 /* calculate starting index for queues */
911 vf_idx = vf_info->vf_idx;
912 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
913 qmap_idx = qmap_stride * vf_idx;
915 /* MAP Tx queue back to 0 temporarily, and disable it */
916 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), 0);
917 FM10K_WRITE_REG(hw, FM10K_TXDCTL(vf_q_idx), 0);
919 /* determine correct default VLAN ID */
921 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;
923 vf_vid = vf_info->sw_vid;
925 /* generate MAC_ADDR request */
926 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
927 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
928 vf_info->mac, vf_vid);
930 /* load onto outgoing mailbox, ignore any errors on enqueue */
931 if (vf_info->mbx.ops.enqueue_tx)
932 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
934 /* verify ring has disabled before modifying base address registers */
935 txdctl = FM10K_READ_REG(hw, FM10K_TXDCTL(vf_q_idx));
936 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
937 /* limit ourselves to a 1ms timeout */
939 err = FM10K_ERR_DMA_PENDING;
944 txdctl = FM10K_READ_REG(hw, FM10K_TXDCTL(vf_q_idx));
947 /* Update base address registers to contain MAC address */
948 if (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac)) {
949 tdbal = (((u32)vf_info->mac[3]) << 24) |
950 (((u32)vf_info->mac[4]) << 16) |
951 (((u32)vf_info->mac[5]) << 8);
953 tdbah = (((u32)0xFF) << 24) |
954 (((u32)vf_info->mac[0]) << 16) |
955 (((u32)vf_info->mac[1]) << 8) |
956 ((u32)vf_info->mac[2]);
959 /* Record the base address into queue 0 */
960 FM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx), tdbal);
961 FM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx), tdbah);
963 /* Provide the VF the ITR scale, using software-defined fields in TDLEN
964 * to pass the information during VF initialization. See definition of
965 * FM10K_TDLEN_ITR_SCALE_SHIFT for more details.
967 FM10K_WRITE_REG(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale <<
968 FM10K_TDLEN_ITR_SCALE_SHIFT);
971 /* configure Queue control register */
972 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
973 FM10K_TXQCTL_VID_MASK;
974 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
975 FM10K_TXQCTL_VF | vf_idx;
978 for (i = 0; i < queues_per_pool; i++)
979 FM10K_WRITE_REG(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
981 /* restore the queue back to VF ownership */
982 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
987 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
988 * @hw: pointer to the HW structure
989 * @vf_info: pointer to VF information structure
991 * Reassign the interrupts and queues to a VF following an FLR
993 STATIC s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
994 struct fm10k_vf_info *vf_info)
996 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
997 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
998 u16 vf_v_idx, vf_v_limit, vf_vid;
999 u8 vf_idx = vf_info->vf_idx;
1002 /* verify vf is in range */
1003 if (vf_idx >= hw->iov.num_vfs)
1004 return FM10K_ERR_PARAM;
1006 /* clear event notification of VF FLR */
1007 FM10K_WRITE_REG(hw, FM10K_PFVFLREC(vf_idx / 32), BIT(vf_idx % 32));
1009 /* force timeout and then disconnect the mailbox */
1010 vf_info->mbx.timeout = 0;
1011 if (vf_info->mbx.ops.disconnect)
1012 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
1014 /* determine vector offset and count */
1015 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
1016 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
1018 /* determine qmap offsets and counts */
1019 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
1020 queues_per_pool = fm10k_queues_per_pool(hw);
1021 qmap_idx = qmap_stride * vf_idx;
1023 /* make all the queues inaccessible to the VF */
1024 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
1025 FM10K_WRITE_REG(hw, FM10K_TQMAP(i), 0);
1026 FM10K_WRITE_REG(hw, FM10K_RQMAP(i), 0);
1029 /* calculate starting index for queues */
1030 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
1032 /* determine correct default VLAN ID */
1033 if (vf_info->pf_vid)
1034 vf_vid = vf_info->pf_vid;
1036 vf_vid = vf_info->sw_vid;
1038 /* configure Queue control register */
1039 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
1040 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
1041 FM10K_TXQCTL_VF | vf_idx;
1042 rxqctl = (vf_idx << FM10K_RXQCTL_VF_SHIFT) | FM10K_RXQCTL_VF;
1044 /* stop further DMA and reset queue ownership back to VF */
1045 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
1046 FM10K_WRITE_REG(hw, FM10K_TXDCTL(i), 0);
1047 FM10K_WRITE_REG(hw, FM10K_TXQCTL(i), txqctl);
1048 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i),
1049 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
1050 FM10K_RXDCTL_DROP_ON_EMPTY);
1051 FM10K_WRITE_REG(hw, FM10K_RXQCTL(i), rxqctl);
1054 /* reset TC with -1 credits and no quanta to prevent transmit */
1055 FM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
1056 FM10K_WRITE_REG(hw, FM10K_TC_RATE(vf_idx), 0);
1057 FM10K_WRITE_REG(hw, FM10K_TC_CREDIT(vf_idx),
1058 FM10K_TC_CREDIT_CREDIT_MASK);
1060 /* update our first entry in the table based on previous VF */
1062 hw->mac.ops.update_int_moderator(hw);
1064 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1066 /* reset linked list so it now includes our active vectors */
1067 if (vf_idx == (hw->iov.num_vfs - 1))
1068 FM10K_WRITE_REG(hw, FM10K_ITR2(0), vf_v_idx);
1070 FM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1072 /* link remaining vectors so that next points to previous */
1073 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1074 FM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1076 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1077 for (i = FM10K_VFMBMEM_LEN; i--;)
1078 FM10K_WRITE_REG(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1079 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1080 FM10K_WRITE_REG(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1081 for (i = FM10K_RETA_SIZE; i--;)
1082 FM10K_WRITE_REG(hw, FM10K_RETA(vf_info->vsi, i), 0);
1083 for (i = FM10K_RSSRK_SIZE; i--;)
1084 FM10K_WRITE_REG(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1085 FM10K_WRITE_REG(hw, FM10K_MRQC(vf_info->vsi), 0);
1087 /* Update base address registers to contain MAC address */
1088 if (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac)) {
1089 tdbal = (((u32)vf_info->mac[3]) << 24) |
1090 (((u32)vf_info->mac[4]) << 16) |
1091 (((u32)vf_info->mac[5]) << 8);
1092 tdbah = (((u32)0xFF) << 24) |
1093 (((u32)vf_info->mac[0]) << 16) |
1094 (((u32)vf_info->mac[1]) << 8) |
1095 ((u32)vf_info->mac[2]);
1098 /* map queue pairs back to VF from last to first */
1099 for (i = queues_per_pool; i--;) {
1100 FM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1101 FM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1102 /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an
1103 * explanation of how TDLEN is used.
1105 FM10K_WRITE_REG(hw, FM10K_TDLEN(vf_q_idx + i),
1106 hw->mac.itr_scale <<
1107 FM10K_TDLEN_ITR_SCALE_SHIFT);
1108 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1109 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1112 /* repeat the first ring for all the remaining VF rings */
1113 for (i = queues_per_pool; i < qmap_stride; i++) {
1114 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx);
1115 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx);
1118 return FM10K_SUCCESS;
1122 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1123 * @hw: pointer to hardware structure
1124 * @vf_info: pointer to VF information structure
1125 * @lport_idx: Logical port offset from the hardware glort
1126 * @flags: Set of capability flags to extend port beyond basic functionality
1128 * This function allows enabling a VF port by assigning it a GLORT and
1129 * setting the flags so that it can enable an Rx mode.
1131 STATIC s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1132 struct fm10k_vf_info *vf_info,
1133 u16 lport_idx, u8 flags)
1135 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1137 DEBUGFUNC("fm10k_iov_set_lport_state_pf");
1139 /* if glort is not valid return error */
1140 if (!fm10k_glort_valid_pf(hw, glort))
1141 return FM10K_ERR_PARAM;
1143 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1144 vf_info->glort = glort;
1146 return FM10K_SUCCESS;
1150 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1151 * @hw: pointer to hardware structure
1152 * @vf_info: pointer to VF information structure
1154 * This function disables a VF port by stripping it of a GLORT and
1155 * setting the flags so that it cannot enable any Rx mode.
1157 STATIC void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1158 struct fm10k_vf_info *vf_info)
1162 DEBUGFUNC("fm10k_iov_reset_lport_state_pf");
1164 /* need to disable the port if it is already enabled */
1165 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1166 /* notify switch that this port has been disabled */
1167 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1169 /* generate port state response to notify VF it is not ready */
1170 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1171 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1174 /* clear flags and glort if it exists */
1175 vf_info->vf_flags = 0;
1180 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1181 * @hw: pointer to hardware structure
1182 * @q: stats for all queues of a VF
1183 * @vf_idx: index of VF
1185 * This function collects queue stats for VFs.
1187 STATIC void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1188 struct fm10k_hw_stats_q *q,
1193 /* get stats for all of the queues */
1194 qpp = fm10k_queues_per_pool(hw);
1195 idx = fm10k_vf_queue_index(hw, vf_idx);
1196 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1200 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1201 * @hw: Pointer to hardware structure
1202 * @results: Pointer array to message, results[0] is pointer to message
1203 * @mbx: Pointer to mailbox information structure
1205 * This function is a default handler for MSI-X requests from the VF. The
1206 * assumption is that in this case it is acceptable to just directly
1207 * hand off the message from the VF to the underlying shared code.
1209 s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,
1210 struct fm10k_mbx_info *mbx)
1212 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1213 u8 vf_idx = vf_info->vf_idx;
1215 UNREFERENCED_1PARAMETER(results);
1216 DEBUGFUNC("fm10k_iov_msg_msix_pf");
1218 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1222 * fm10k_iov_select_vid - Select correct default VLAN ID
1223 * @hw: Pointer to hardware structure
1224 * @vid: VLAN ID to correct
1226 * Will report an error if the VLAN ID is out of range. For VID = 0, it will
1227 * return either the pf_vid or sw_vid depending on which one is set.
1229 STATIC s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid)
1232 return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid;
1233 else if (vf_info->pf_vid && vid != vf_info->pf_vid)
1234 return FM10K_ERR_PARAM;
1240 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1241 * @hw: Pointer to hardware structure
1242 * @results: Pointer array to message, results[0] is pointer to message
1243 * @mbx: Pointer to mailbox information structure
1245 * This function is a default handler for MAC/VLAN requests from the VF.
1246 * The assumption is that in this case it is acceptable to just directly
1247 * hand off the message from the VF to the underlying shared code.
1249 s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1250 struct fm10k_mbx_info *mbx)
1252 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1255 int err = FM10K_SUCCESS;
1260 DEBUGFUNC("fm10k_iov_msg_mac_vlan_pf");
1262 /* we shouldn't be updating rules on a disabled interface */
1263 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1264 err = FM10K_ERR_PARAM;
1266 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1267 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1269 /* record VLAN id requested */
1270 err = fm10k_tlv_attr_get_u32(result, &vid);
1274 /* verify upper 16 bits are zero */
1276 return FM10K_ERR_PARAM;
1278 set = !(vid & FM10K_VLAN_CLEAR);
1279 vid &= ~FM10K_VLAN_CLEAR;
1281 err = fm10k_iov_select_vid(vf_info, (u16)vid);
1287 /* update VSI info for VF in regards to VLAN table */
1288 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set);
1291 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1292 result = results[FM10K_MAC_VLAN_MSG_MAC];
1294 /* record unicast MAC address requested */
1295 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1299 /* block attempts to set MAC for a locked device */
1300 if (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac) &&
1301 memcmp(mac, vf_info->mac, ETH_ALEN))
1302 return FM10K_ERR_PARAM;
1304 set = !(vlan & FM10K_VLAN_CLEAR);
1305 vlan &= ~FM10K_VLAN_CLEAR;
1307 err = fm10k_iov_select_vid(vf_info, vlan);
1313 /* notify switch of request for new unicast address */
1314 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort,
1318 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1319 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1321 /* record multicast MAC address requested */
1322 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1326 /* verify that the VF is allowed to request multicast */
1327 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1328 return FM10K_ERR_PARAM;
1330 set = !(vlan & FM10K_VLAN_CLEAR);
1331 vlan &= ~FM10K_VLAN_CLEAR;
1333 err = fm10k_iov_select_vid(vf_info, vlan);
1339 /* notify switch of request for new multicast address */
1340 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort,
1348 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1349 * @vf_info: VF info structure containing capability flags
1350 * @mode: Requested xcast mode
1352 * This function outputs the mode that most closely matches the requested
1353 * mode. If not modes match it will request we disable the port
1355 STATIC u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1358 u8 vf_flags = vf_info->vf_flags;
1360 /* match up mode to capabilities as best as possible */
1362 case FM10K_XCAST_MODE_PROMISC:
1363 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1364 return FM10K_XCAST_MODE_PROMISC;
1366 case FM10K_XCAST_MODE_ALLMULTI:
1367 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1368 return FM10K_XCAST_MODE_ALLMULTI;
1370 case FM10K_XCAST_MODE_MULTI:
1371 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1372 return FM10K_XCAST_MODE_MULTI;
1374 case FM10K_XCAST_MODE_NONE:
1375 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1376 return FM10K_XCAST_MODE_NONE;
1382 /* disable interface as it should not be able to request any */
1383 return FM10K_XCAST_MODE_DISABLE;
1387 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1388 * @hw: Pointer to hardware structure
1389 * @results: Pointer array to message, results[0] is pointer to message
1390 * @mbx: Pointer to mailbox information structure
1392 * This function is a default handler for port state requests. The port
1393 * state requests for now are basic and consist of enabling or disabling
1396 s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1397 struct fm10k_mbx_info *mbx)
1399 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1401 s32 err = FM10K_SUCCESS;
1405 DEBUGFUNC("fm10k_iov_msg_lport_state_pf");
1407 /* verify VF is allowed to enable even minimal mode */
1408 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1409 return FM10K_ERR_PARAM;
1411 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1412 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1414 /* XCAST mode update requested */
1415 err = fm10k_tlv_attr_get_u8(result, &mode);
1417 return FM10K_ERR_PARAM;
1419 /* prep for possible demotion depending on capabilities */
1420 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1422 /* if mode is not currently enabled, enable it */
1423 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & BIT(mode)))
1424 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1426 /* swap mode back to a bit flag */
1427 mode = FM10K_VF_FLAG_SET_MODE(mode);
1428 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1429 /* need to disable the port if it is already enabled */
1430 if (FM10K_VF_FLAG_ENABLED(vf_info))
1431 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1434 /* we need to clear VF_FLAG_ENABLED flags in order to ensure
1435 * that we actually re-enable the LPORT state below. Note that
1436 * this has no impact if the VF is already disabled, as the
1437 * flags are already cleared.
1440 vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info);
1442 /* when enabling the port we should reset the rate limiters */
1443 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1445 /* set mode for minimal functionality */
1446 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1448 /* generate port state response to notify VF it is ready */
1449 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1450 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1451 mbx->ops.enqueue_tx(hw, mbx, msg);
1454 /* if enable state toggled note the update */
1455 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1456 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1459 /* if state change succeeded, then update our stored state */
1460 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1462 vf_info->vf_flags = mode;
1467 #ifndef NO_DEFAULT_SRIOV_MSG_HANDLERS
1468 const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = {
1469 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1470 FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf),
1471 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf),
1472 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf),
1473 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1478 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1479 * @hw: pointer to hardware structure
1480 * @stats: pointer to the stats structure to update
1482 * This function collects and aggregates global and per queue hardware
1485 STATIC void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1486 struct fm10k_hw_stats *stats)
1488 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1491 DEBUGFUNC("fm10k_update_hw_stats_pf");
1493 /* Use Tx queue 0 as a canary to detect a reset */
1494 id = FM10K_READ_REG(hw, FM10K_TXQCTL(0));
1496 /* Read Global Statistics */
1498 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1500 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1501 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1502 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1503 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1504 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1507 fm10k_read_hw_stats_32b(hw,
1508 FM10K_STATS_LOOPBACK_DROP,
1509 &stats->loopback_drop);
1510 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1511 FM10K_STATS_NODESC_DROP,
1512 &stats->nodesc_drop);
1514 /* if value has not changed then we have consistent data */
1516 id = FM10K_READ_REG(hw, FM10K_TXQCTL(0));
1517 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1519 /* drop non-ID bits and set VALID ID bit */
1520 id &= FM10K_TXQCTL_ID_MASK;
1521 id |= FM10K_STAT_VALID;
1523 /* Update Global Statistics */
1524 if (stats->stats_idx == id) {
1525 stats->timeout.count += timeout;
1526 stats->ur.count += ur;
1527 stats->ca.count += ca;
1528 stats->um.count += um;
1529 stats->xec.count += xec;
1530 stats->vlan_drop.count += vlan_drop;
1531 stats->loopback_drop.count += loopback_drop;
1532 stats->nodesc_drop.count += nodesc_drop;
1535 /* Update bases and record current PF id */
1536 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1537 fm10k_update_hw_base_32b(&stats->ur, ur);
1538 fm10k_update_hw_base_32b(&stats->ca, ca);
1539 fm10k_update_hw_base_32b(&stats->um, um);
1540 fm10k_update_hw_base_32b(&stats->xec, xec);
1541 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1542 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1543 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1544 stats->stats_idx = id;
1546 /* Update Queue Statistics */
1547 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1551 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1552 * @hw: pointer to hardware structure
1553 * @stats: pointer to the stats structure to update
1555 * This function resets the base for global and per queue hardware
1558 STATIC void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1559 struct fm10k_hw_stats *stats)
1561 DEBUGFUNC("fm10k_rebind_hw_stats_pf");
1563 /* Unbind Global Statistics */
1564 fm10k_unbind_hw_stats_32b(&stats->timeout);
1565 fm10k_unbind_hw_stats_32b(&stats->ur);
1566 fm10k_unbind_hw_stats_32b(&stats->ca);
1567 fm10k_unbind_hw_stats_32b(&stats->um);
1568 fm10k_unbind_hw_stats_32b(&stats->xec);
1569 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1570 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1571 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1573 /* Unbind Queue Statistics */
1574 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1576 /* Reinitialize bases for all stats */
1577 fm10k_update_hw_stats_pf(hw, stats);
1581 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1582 * @hw: pointer to hardware structure
1583 * @dma_mask: 64 bit DMA mask required for platform
1585 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1586 * to limit the access to memory beyond what is physically in the system.
1588 STATIC void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1590 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1591 u32 phyaddr = (u32)(dma_mask >> 32);
1593 DEBUGFUNC("fm10k_set_dma_mask_pf");
1595 FM10K_WRITE_REG(hw, FM10K_PHYADDR, phyaddr);
1599 * fm10k_get_fault_pf - Record a fault in one of the interface units
1600 * @hw: pointer to hardware structure
1601 * @type: pointer to fault type register offset
1602 * @fault: pointer to memory location to record the fault
1604 * Record the fault register contents to the fault data structure and
1605 * clear the entry from the register.
1607 * Returns ERR_PARAM if invalid register is specified or no error is present.
1609 STATIC s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1610 struct fm10k_fault *fault)
1614 DEBUGFUNC("fm10k_get_fault_pf");
1616 /* verify the fault register is in range and is aligned */
1618 case FM10K_PCA_FAULT:
1619 case FM10K_THI_FAULT:
1620 case FM10K_FUM_FAULT:
1623 return FM10K_ERR_PARAM;
1626 /* only service faults that are valid */
1627 func = FM10K_READ_REG(hw, type + FM10K_FAULT_FUNC);
1628 if (!(func & FM10K_FAULT_FUNC_VALID))
1629 return FM10K_ERR_PARAM;
1631 /* read remaining fields */
1632 fault->address = FM10K_READ_REG(hw, type + FM10K_FAULT_ADDR_HI);
1633 fault->address <<= 32;
1634 fault->address = FM10K_READ_REG(hw, type + FM10K_FAULT_ADDR_LO);
1635 fault->specinfo = FM10K_READ_REG(hw, type + FM10K_FAULT_SPECINFO);
1637 /* clear valid bit to allow for next error */
1638 FM10K_WRITE_REG(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1640 /* Record which function triggered the error */
1641 if (func & FM10K_FAULT_FUNC_PF)
1644 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1645 FM10K_FAULT_FUNC_VF_SHIFT);
1647 /* record fault type */
1648 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1650 return FM10K_SUCCESS;
1654 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1655 * @hw: pointer to hardware structure
1658 STATIC s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1660 struct fm10k_mbx_info *mbx = &hw->mbx;
1663 DEBUGFUNC("fm10k_request_lport_pf");
1665 /* issue request asking for LPORT map */
1666 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1668 /* load onto outgoing mailbox */
1669 return mbx->ops.enqueue_tx(hw, mbx, msg);
1673 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1674 * @hw: pointer to hardware structure
1675 * @switch_ready: pointer to boolean value that will record switch state
1677 * This funciton will check the DMA_CTRL2 register and mailbox in order
1678 * to determine if the switch is ready for the PF to begin requesting
1679 * addresses and mapping traffic to the local interface.
1681 STATIC s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1683 s32 ret_val = FM10K_SUCCESS;
1686 DEBUGFUNC("fm10k_get_host_state_pf");
1688 /* verify the switch is ready for interaction */
1689 dma_ctrl2 = FM10K_READ_REG(hw, FM10K_DMA_CTRL2);
1690 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1693 /* retrieve generic host state info */
1694 ret_val = fm10k_get_host_state_generic(hw, switch_ready);
1698 /* interface cannot receive traffic without logical ports */
1699 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)
1700 ret_val = fm10k_request_lport_map_pf(hw);
1706 /* This structure defines the attibutes to be parsed below */
1707 const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1708 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1709 sizeof(struct fm10k_swapi_error)),
1710 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1715 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1716 * @hw: Pointer to hardware structure
1717 * @results: pointer array containing parsed data
1718 * @mbx: Pointer to mailbox information structure
1720 * This handler configures the lport mapping based on the reply from the
1723 s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1724 struct fm10k_mbx_info *mbx)
1730 UNREFERENCED_1PARAMETER(mbx);
1731 DEBUGFUNC("fm10k_msg_lport_map_pf");
1733 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1738 /* extract values out of the header */
1739 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1740 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1742 /* verify mask is set and none of the masked bits in glort are set */
1743 if (!mask || (glort & ~mask))
1744 return FM10K_ERR_PARAM;
1746 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1747 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1748 return FM10K_ERR_PARAM;
1750 /* record the glort, mask, and port count */
1751 hw->mac.dglort_map = dglort_map;
1753 return FM10K_SUCCESS;
1756 const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1757 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1762 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1763 * @hw: Pointer to hardware structure
1764 * @results: pointer array containing parsed data
1765 * @mbx: Pointer to mailbox information structure
1767 * This handler configures the default VLAN for the PF
1769 static s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1770 struct fm10k_mbx_info *mbx)
1776 UNREFERENCED_1PARAMETER(mbx);
1777 DEBUGFUNC("fm10k_msg_update_pvid_pf");
1779 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1784 /* extract values from the pvid update */
1785 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1786 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1788 /* if glort is not valid return error */
1789 if (!fm10k_glort_valid_pf(hw, glort))
1790 return FM10K_ERR_PARAM;
1792 /* verify VLAN ID is valid */
1793 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1794 return FM10K_ERR_PARAM;
1796 /* record the port VLAN ID value */
1797 hw->mac.default_vid = pvid;
1799 return FM10K_SUCCESS;
1803 * fm10k_record_global_table_data - Move global table data to swapi table info
1804 * @from: pointer to source table data structure
1805 * @to: pointer to destination table info structure
1807 * This function is will copy table_data to the table_info contained in
1810 static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1811 struct fm10k_swapi_table_info *to)
1813 /* convert from le32 struct to CPU byte ordered values */
1814 to->used = FM10K_LE32_TO_CPU(from->used);
1815 to->avail = FM10K_LE32_TO_CPU(from->avail);
1818 const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1819 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1820 sizeof(struct fm10k_swapi_error)),
1825 * fm10k_msg_err_pf - Message handler for error reply
1826 * @hw: Pointer to hardware structure
1827 * @results: pointer array containing parsed data
1828 * @mbx: Pointer to mailbox information structure
1830 * This handler will capture the data for any error replies to previous
1831 * messages that the PF has sent.
1833 s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1834 struct fm10k_mbx_info *mbx)
1836 struct fm10k_swapi_error err_msg;
1839 UNREFERENCED_1PARAMETER(mbx);
1840 DEBUGFUNC("fm10k_msg_err_pf");
1842 /* extract structure from message */
1843 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1844 &err_msg, sizeof(err_msg));
1848 /* record table status */
1849 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1850 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1851 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1853 /* record SW API status value */
1854 hw->swapi.status = FM10K_LE32_TO_CPU(err_msg.status);
1856 return FM10K_SUCCESS;
1859 /* currently there is no shared 1588 timestamp handler */
1861 const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {
1862 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP,
1863 sizeof(struct fm10k_swapi_1588_timestamp)),
1867 const struct fm10k_tlv_attr fm10k_1588_clock_owner_attr[] = {
1868 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_CLOCK_OWNER,
1869 sizeof(struct fm10k_swapi_1588_clock_owner)),
1873 const struct fm10k_tlv_attr fm10k_master_clk_offset_attr[] = {
1874 FM10K_TLV_ATTR_U64(FM10K_PF_ATTR_ID_MASTER_CLK_OFFSET),
1879 * fm10k_iov_notify_offset_pf - Notify VF of change in PTP offset
1880 * @hw: pointer to hardware structure
1881 * @vf_info: pointer to the vf info structure
1882 * @offset: 64bit unsigned offset from hardware SYSTIME
1884 * This function sends a message to a given VF to notify it of PTP offset
1887 STATIC void fm10k_iov_notify_offset_pf(struct fm10k_hw *hw,
1888 struct fm10k_vf_info *vf_info,
1893 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588);
1894 fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_CLK_OFFSET, offset);
1896 if (vf_info->mbx.ops.enqueue_tx)
1897 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1901 * fm10k_msg_1588_clock_owner_pf - Message handler for clock ownership from SM
1902 * @hw: pointer to hardware structure
1903 * @results: pointer to array containing parsed data,
1904 * @mbx: Pointer to mailbox information structure
1906 * This handler configures the FM10K_HW_FLAG_CLOCK_OWNER field for the PF
1908 s32 fm10k_msg_1588_clock_owner_pf(struct fm10k_hw *hw, u32 **results,
1909 struct fm10k_mbx_info *mbx)
1911 struct fm10k_swapi_1588_clock_owner msg;
1915 UNREFERENCED_1PARAMETER(mbx);
1916 DEBUGFUNC("fm10k_msg_1588_clock_owner");
1918 err = fm10k_tlv_attr_get_le_struct(
1919 results[FM10K_PF_ATTR_ID_1588_CLOCK_OWNER],
1924 /* We own the clock iff the glort matches us and the enabled field is
1925 * true. Otherwise, the clock must belong to some other port.
1927 glort = le16_to_cpu(msg.glort);
1928 if (fm10k_glort_valid_pf(hw, glort) && msg.enabled)
1929 hw->flags |= FM10K_HW_FLAG_CLOCK_OWNER;
1931 hw->flags &= ~FM10K_HW_FLAG_CLOCK_OWNER;
1933 return FM10K_SUCCESS;
1937 * fm10k_adjust_systime_pf - Adjust systime frequency
1938 * @hw: pointer to hardware structure
1939 * @ppb: adjustment rate in parts per billion
1941 * This function will adjust the SYSTIME_CFG register contained in BAR 4
1942 * if this function is supported for BAR 4 access. The adjustment amount
1943 * is based on the parts per billion value provided and adjusted to a
1944 * value based on parts per 2^48 clock cycles.
1946 * If adjustment is not supported or the requested value is too large
1947 * we will return an error.
1949 STATIC s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)
1953 DEBUGFUNC("fm10k_adjust_systime_pf");
1955 /* ensure that we control the clock */
1956 if (!(hw->flags & FM10K_HW_FLAG_CLOCK_OWNER))
1957 return FM10K_ERR_DEVICE_NOT_SUPPORTED;
1959 /* if sw_addr is not set we don't have switch register access */
1961 return ppb ? FM10K_ERR_PARAM : FM10K_SUCCESS;
1963 /* we must convert the value from parts per billion to parts per
1964 * 2^48 cycles. In addition I have opted to only use the 30 most
1965 * significant bits of the adjustment value as the 8 least
1966 * significant bits are located in another register and represent
1967 * a value significantly less than a part per billion, the result
1968 * of dropping the 8 least significant bits is that the adjustment
1969 * value is effectively multiplied by 2^8 when we write it.
1971 * As a result of all this the math for this breaks down as follows:
1972 * ppb / 10^9 == adjust * 2^8 / 2^48
1973 * If we solve this for adjust, and simplify it comes out as:
1974 * ppb * 2^31 / 5^9 == adjust
1976 systime_adjust = (ppb < 0) ? -ppb : ppb;
1977 systime_adjust <<= 31;
1978 do_div(systime_adjust, 1953125);
1980 /* verify the requested adjustment value is in range */
1981 if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK)
1982 return FM10K_ERR_PARAM;
1985 systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE;
1987 FM10K_WRITE_SW_REG(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust);
1989 return FM10K_SUCCESS;
1993 * fm10k_notify_offset_pf - Notify switch of change in PTP offset
1994 * @hw: pointer to hardware structure
1995 * @offset: 64bit unsigned offset of SYSTIME
1997 * This function sends a message to the switch to indicate a change in the
1998 * offset of the hardware SYSTIME registers. The switch manager is
1999 * responsible for transmitting this message to other hosts.
2001 STATIC s32 fm10k_notify_offset_pf(struct fm10k_hw *hw, u64 offset)
2003 struct fm10k_mbx_info *mbx = &hw->mbx;
2006 DEBUGFUNC("fm10k_notify_offset_pf");
2008 /* ensure that we control the clock */
2009 if (!(hw->flags & FM10K_HW_FLAG_CLOCK_OWNER))
2010 return FM10K_ERR_DEVICE_NOT_SUPPORTED;
2012 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_MASTER_CLK_OFFSET);
2013 fm10k_tlv_attr_put_u64(msg, FM10K_PF_ATTR_ID_MASTER_CLK_OFFSET, offset);
2015 /* load onto outgoing mailbox */
2016 return mbx->ops.enqueue_tx(hw, mbx, msg);
2020 * fm10k_read_systime_pf - Reads value of systime registers
2021 * @hw: pointer to the hardware structure
2023 * Function reads the content of 2 registers, combined to represent a 64 bit
2024 * value measured in nanosecods. In order to guarantee the value is accurate
2025 * we check the 32 most significant bits both before and after reading the
2026 * 32 least significant bits to verify they didn't change as we were reading
2029 static u64 fm10k_read_systime_pf(struct fm10k_hw *hw)
2031 u32 systime_l, systime_h, systime_tmp;
2033 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
2036 systime_tmp = systime_h;
2037 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME);
2038 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
2039 } while (systime_tmp != systime_h);
2041 return ((u64)systime_h << 32) | systime_l;
2044 static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
2045 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
2046 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
2047 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
2048 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
2049 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
2050 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
2051 FM10K_PF_MSG_1588_CLOCK_OWNER_HANDLER(fm10k_msg_1588_clock_owner_pf),
2052 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2056 * fm10k_init_ops_pf - Inits func ptrs and MAC type
2057 * @hw: pointer to hardware structure
2059 * Initialize the function pointers and assign the MAC type for PF.
2060 * Does not touch the hardware.
2062 s32 fm10k_init_ops_pf(struct fm10k_hw *hw)
2064 struct fm10k_mac_info *mac = &hw->mac;
2065 struct fm10k_iov_info *iov = &hw->iov;
2067 DEBUGFUNC("fm10k_init_ops_pf");
2069 fm10k_init_ops_generic(hw);
2071 mac->ops.reset_hw = &fm10k_reset_hw_pf;
2072 mac->ops.init_hw = &fm10k_init_hw_pf;
2073 mac->ops.start_hw = &fm10k_start_hw_generic;
2074 mac->ops.stop_hw = &fm10k_stop_hw_generic;
2075 #ifndef NO_IS_SLOT_APPROPRIATE_CHECK
2076 mac->ops.is_slot_appropriate = &fm10k_is_slot_appropriate_pf;
2078 mac->ops.update_vlan = &fm10k_update_vlan_pf;
2079 mac->ops.read_mac_addr = &fm10k_read_mac_addr_pf;
2080 mac->ops.update_uc_addr = &fm10k_update_uc_addr_pf;
2081 mac->ops.update_mc_addr = &fm10k_update_mc_addr_pf;
2082 mac->ops.update_xcast_mode = &fm10k_update_xcast_mode_pf;
2083 mac->ops.update_int_moderator = &fm10k_update_int_moderator_pf;
2084 mac->ops.update_lport_state = &fm10k_update_lport_state_pf;
2085 mac->ops.update_hw_stats = &fm10k_update_hw_stats_pf;
2086 mac->ops.rebind_hw_stats = &fm10k_rebind_hw_stats_pf;
2087 mac->ops.configure_dglort_map = &fm10k_configure_dglort_map_pf;
2088 mac->ops.set_dma_mask = &fm10k_set_dma_mask_pf;
2089 mac->ops.get_fault = &fm10k_get_fault_pf;
2090 mac->ops.get_host_state = &fm10k_get_host_state_pf;
2091 mac->ops.adjust_systime = &fm10k_adjust_systime_pf;
2092 mac->ops.notify_offset = &fm10k_notify_offset_pf;
2093 mac->ops.read_systime = &fm10k_read_systime_pf;
2095 mac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw);
2097 iov->ops.assign_resources = &fm10k_iov_assign_resources_pf;
2098 iov->ops.configure_tc = &fm10k_iov_configure_tc_pf;
2099 iov->ops.assign_int_moderator = &fm10k_iov_assign_int_moderator_pf;
2100 iov->ops.assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf;
2101 iov->ops.reset_resources = &fm10k_iov_reset_resources_pf;
2102 iov->ops.set_lport = &fm10k_iov_set_lport_pf;
2103 iov->ops.reset_lport = &fm10k_iov_reset_lport_pf;
2104 iov->ops.update_stats = &fm10k_iov_update_stats_pf;
2105 iov->ops.notify_offset = &fm10k_iov_notify_offset_pf;
2107 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);