1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ***************************************************************************/
38 * fm10k_reset_hw_pf - PF hardware reset
39 * @hw: pointer to hardware structure
41 * This function should return the hardware to a state similar to the
42 * one it is in after being powered on.
44 STATIC s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
50 DEBUGFUNC("fm10k_reset_hw_pf");
52 /* Disable interrupts */
53 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
55 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
56 FM10K_WRITE_REG(hw, FM10K_ITR2(0), 0);
57 FM10K_WRITE_REG(hw, FM10K_INT_CTRL, 0);
59 /* We assume here Tx and Rx queue 0 are owned by the PF */
61 /* Shut off VF access to their queues forcing them to queue 0 */
62 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
63 FM10K_WRITE_REG(hw, FM10K_TQMAP(i), 0);
64 FM10K_WRITE_REG(hw, FM10K_RQMAP(i), 0);
67 /* shut down all rings */
68 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
72 /* Verify that DMA is no longer active */
73 reg = FM10K_READ_REG(hw, FM10K_DMA_CTRL);
74 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
75 return FM10K_ERR_DMA_PENDING;
77 /* verify the switch is ready for reset */
78 reg = FM10K_READ_REG(hw, FM10K_DMA_CTRL2);
79 if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY))
82 /* Inititate data path reset */
83 reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
84 FM10K_WRITE_REG(hw, FM10K_DMA_CTRL, reg);
86 /* Flush write and allow 100us for reset to complete */
87 FM10K_WRITE_FLUSH(hw);
88 usec_delay(FM10K_RESET_TIMEOUT);
90 /* Verify we made it out of reset */
91 reg = FM10K_READ_REG(hw, FM10K_IP);
92 if (!(reg & FM10K_IP_NOTINRESET))
93 err = FM10K_ERR_RESET_FAILED;
100 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
101 * @hw: pointer to hardware structure
103 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
105 STATIC bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
107 u16 sriov_ctrl = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_SRIOV_CTRL);
109 DEBUGFUNC("fm10k_is_ari_hierarchy_pf");
111 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
115 * fm10k_init_hw_pf - PF hardware initialization
116 * @hw: pointer to hardware structure
119 STATIC s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
121 u32 dma_ctrl, txqctl;
124 DEBUGFUNC("fm10k_init_hw_pf");
126 /* Establish default VSI as valid */
127 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
128 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
129 FM10K_DGLORTMAP_ANY);
131 /* Invalidate all other GLORT entries */
132 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
133 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
135 /* reset ITR2(0) to point to itself */
136 FM10K_WRITE_REG(hw, FM10K_ITR2(0), 0);
138 /* reset VF ITR2(0) to point to 0 avoid PF registers */
139 FM10K_WRITE_REG(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
141 /* loop through all PF ITR2 registers pointing them to the previous */
142 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
143 FM10K_WRITE_REG(hw, FM10K_ITR2(i), i - 1);
145 /* Enable interrupt moderator if not already enabled */
146 FM10K_WRITE_REG(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
148 /* compute the default txqctl configuration */
149 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
150 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
152 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
153 /* configure rings for 256 Queue / 32 Descriptor cache mode */
154 FM10K_WRITE_REG(hw, FM10K_TQDLOC(i),
155 (i * FM10K_TQDLOC_BASE_32_DESC) |
156 FM10K_TQDLOC_SIZE_32_DESC);
157 FM10K_WRITE_REG(hw, FM10K_TXQCTL(i), txqctl);
159 /* configure rings to provide TPH processing hints */
160 FM10K_WRITE_REG(hw, FM10K_TPH_TXCTRL(i),
161 FM10K_TPH_TXCTRL_DESC_TPHEN |
162 FM10K_TPH_TXCTRL_DESC_RROEN |
163 FM10K_TPH_TXCTRL_DESC_WROEN |
164 FM10K_TPH_TXCTRL_DATA_RROEN);
165 FM10K_WRITE_REG(hw, FM10K_TPH_RXCTRL(i),
166 FM10K_TPH_RXCTRL_DESC_TPHEN |
167 FM10K_TPH_RXCTRL_DESC_RROEN |
168 FM10K_TPH_RXCTRL_DATA_WROEN |
169 FM10K_TPH_RXCTRL_HDR_WROEN);
172 /* set max hold interval to align with 1.024 usec in all modes */
173 switch (hw->bus.speed) {
174 case fm10k_bus_speed_2500:
175 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
177 case fm10k_bus_speed_5000:
178 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
180 case fm10k_bus_speed_8000:
181 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
188 /* Configure TSO flags */
189 FM10K_WRITE_REG(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
190 FM10K_WRITE_REG(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
193 * Set Rx Descriptor size to 32
194 * Set Minimum MSS to 64
195 * Set Maximum number of Rx queues to 256 / 32 Descriptor
197 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
198 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
199 FM10K_DMA_CTRL_32_DESC;
201 FM10K_WRITE_REG(hw, FM10K_DMA_CTRL, dma_ctrl);
203 /* record maximum queue count, we limit ourselves to 128 */
204 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
206 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
207 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
209 return FM10K_SUCCESS;
213 * fm10k_is_slot_appropriate_pf - Indicate appropriate slot for this SKU
214 * @hw: pointer to hardware structure
216 * Looks at the PCIe bus info to confirm whether or not this slot can support
217 * the necessary bandwidth for this device.
219 STATIC bool fm10k_is_slot_appropriate_pf(struct fm10k_hw *hw)
221 DEBUGFUNC("fm10k_is_slot_appropriate_pf");
223 return (hw->bus.speed == hw->bus_caps.speed) &&
224 (hw->bus.width == hw->bus_caps.width);
228 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
229 * @hw: pointer to hardware structure
230 * @vid: VLAN ID to add to table
231 * @vsi: Index indicating VF ID or PF ID in table
232 * @set: Indicates if this is a set or clear operation
234 * This function adds or removes the corresponding VLAN ID from the VLAN
235 * filter table for the corresponding function. In addition to the
236 * standard set/clear that supports one bit a multi-bit write is
237 * supported to set 64 bits at a time.
239 STATIC s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
241 u32 vlan_table, reg, mask, bit, len;
243 /* verify the VSI index is valid */
244 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
245 return FM10K_ERR_PARAM;
247 /* VLAN multi-bit write:
248 * The multi-bit write has several parts to it.
250 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
251 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
252 * | RSVD0 | Length |C|RSVD0| VLAN ID |
253 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
255 * VLAN ID: Vlan Starting value
256 * RSVD0: Reserved section, must be 0
257 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
258 * Length: Number of times to repeat the bit being set
261 vid = (vid << 17) >> 17;
263 /* verify the reserved 0 fields are 0 */
264 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)
265 return FM10K_ERR_PARAM;
267 /* Loop through the table updating all required VLANs */
268 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
269 len < FM10K_VLAN_TABLE_VID_MAX;
270 len -= 32 - bit, reg++, bit = 0) {
271 /* record the initial state of the register */
272 vlan_table = FM10K_READ_REG(hw, reg);
274 /* truncate mask if we are at the start or end of the run */
275 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
277 /* make necessary modifications to the register */
278 mask &= set ? ~vlan_table : vlan_table;
280 FM10K_WRITE_REG(hw, reg, vlan_table ^ mask);
283 return FM10K_SUCCESS;
287 * fm10k_read_mac_addr_pf - Read device MAC address
288 * @hw: pointer to the HW structure
290 * Reads the device MAC address from the SM_AREA and stores the value.
292 STATIC s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
294 u8 perm_addr[ETH_ALEN];
298 DEBUGFUNC("fm10k_read_mac_addr_pf");
300 serial_num = FM10K_READ_REG(hw, FM10K_SM_AREA(1));
302 /* last byte should be all 1's */
303 if ((~serial_num) << 24)
304 return FM10K_ERR_INVALID_MAC_ADDR;
306 perm_addr[0] = (u8)(serial_num >> 24);
307 perm_addr[1] = (u8)(serial_num >> 16);
308 perm_addr[2] = (u8)(serial_num >> 8);
310 serial_num = FM10K_READ_REG(hw, FM10K_SM_AREA(0));
312 /* first byte should be all 1's */
313 if ((~serial_num) >> 24)
314 return FM10K_ERR_INVALID_MAC_ADDR;
316 perm_addr[3] = (u8)(serial_num >> 16);
317 perm_addr[4] = (u8)(serial_num >> 8);
318 perm_addr[5] = (u8)(serial_num);
320 for (i = 0; i < ETH_ALEN; i++) {
321 hw->mac.perm_addr[i] = perm_addr[i];
322 hw->mac.addr[i] = perm_addr[i];
325 return FM10K_SUCCESS;
329 * fm10k_glort_valid_pf - Validate that the provided glort is valid
330 * @hw: pointer to the HW structure
331 * @glort: base glort to be validated
333 * This function will return an error if the provided glort is invalid
335 bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
337 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
339 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
343 * fm10k_update_xc_addr_pf - Update device addresses
344 * @hw: pointer to the HW structure
345 * @glort: base resource tag for this request
346 * @mac: MAC address to add/remove from table
347 * @vid: VLAN ID to add/remove from table
348 * @add: Indicates if this is an add or remove operation
349 * @flags: flags field to indicate add and secure
351 * This function generates a message to the Switch API requesting
352 * that the given logical port add/remove the given L2 MAC/VLAN address.
354 STATIC s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
355 const u8 *mac, u16 vid, bool add, u8 flags)
357 struct fm10k_mbx_info *mbx = &hw->mbx;
358 struct fm10k_mac_update mac_update;
361 DEBUGFUNC("fm10k_update_xc_addr_pf");
363 /* if glort or VLAN are not valid return error */
364 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
365 return FM10K_ERR_PARAM;
368 mac_update.mac_lower = FM10K_CPU_TO_LE32(((u32)mac[2] << 24) |
369 ((u32)mac[3] << 16) |
372 mac_update.mac_upper = FM10K_CPU_TO_LE16(((u32)mac[0] << 8) |
374 mac_update.vlan = FM10K_CPU_TO_LE16(vid);
375 mac_update.glort = FM10K_CPU_TO_LE16(glort);
376 mac_update.action = add ? 0 : 1;
377 mac_update.flags = flags;
379 /* populate mac_update fields */
380 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
381 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
382 &mac_update, sizeof(mac_update));
384 /* load onto outgoing mailbox */
385 return mbx->ops.enqueue_tx(hw, mbx, msg);
389 * fm10k_update_uc_addr_pf - Update device unicast addresses
390 * @hw: pointer to the HW structure
391 * @glort: base resource tag for this request
392 * @mac: MAC address to add/remove from table
393 * @vid: VLAN ID to add/remove from table
394 * @add: Indicates if this is an add or remove operation
395 * @flags: flags field to indicate add and secure
397 * This function is used to add or remove unicast addresses for
400 STATIC s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
401 const u8 *mac, u16 vid, bool add, u8 flags)
403 DEBUGFUNC("fm10k_update_uc_addr_pf");
405 /* verify MAC address is valid */
406 if (!FM10K_IS_VALID_ETHER_ADDR(mac))
407 return FM10K_ERR_PARAM;
409 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
413 * fm10k_update_mc_addr_pf - Update device multicast addresses
414 * @hw: pointer to the HW structure
415 * @glort: base resource tag for this request
416 * @mac: MAC address to add/remove from table
417 * @vid: VLAN ID to add/remove from table
418 * @add: Indicates if this is an add or remove operation
420 * This function is used to add or remove multicast MAC addresses for
423 STATIC s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
424 const u8 *mac, u16 vid, bool add)
426 DEBUGFUNC("fm10k_update_mc_addr_pf");
428 /* verify multicast address is valid */
429 if (!FM10K_IS_MULTICAST_ETHER_ADDR(mac))
430 return FM10K_ERR_PARAM;
432 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
436 * fm10k_update_xcast_mode_pf - Request update of multicast mode
437 * @hw: pointer to hardware structure
438 * @glort: base resource tag for this request
439 * @mode: integer value indicating mode being requested
441 * This function will attempt to request a higher mode for the port
442 * so that it can enable either multicast, multicast promiscuous, or
443 * promiscuous mode of operation.
445 STATIC s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
447 struct fm10k_mbx_info *mbx = &hw->mbx;
448 u32 msg[3], xcast_mode;
450 DEBUGFUNC("fm10k_update_xcast_mode_pf");
452 if (mode > FM10K_XCAST_MODE_NONE)
453 return FM10K_ERR_PARAM;
455 /* if glort is not valid return error */
456 if (!fm10k_glort_valid_pf(hw, glort))
457 return FM10K_ERR_PARAM;
459 /* write xcast mode as a single u32 value,
460 * lower 16 bits: glort
461 * upper 16 bits: mode
463 xcast_mode = ((u32)mode << 16) | glort;
465 /* generate message requesting to change xcast mode */
466 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
467 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
469 /* load onto outgoing mailbox */
470 return mbx->ops.enqueue_tx(hw, mbx, msg);
474 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
475 * @hw: pointer to hardware structure
477 * This function walks through the MSI-X vector table to determine the
478 * number of active interrupts and based on that information updates the
479 * interrupt moderator linked list.
481 STATIC void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
485 /* Disable interrupt moderator */
486 FM10K_WRITE_REG(hw, FM10K_INT_CTRL, 0);
488 /* loop through PF from last to first looking enabled vectors */
489 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
490 if (!FM10K_READ_REG(hw, FM10K_MSIX_VECTOR_MASK(i)))
494 /* always reset VFITR2[0] to point to last enabled PF vector */
495 FM10K_WRITE_REG(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
497 /* reset ITR2[0] to point to last enabled PF vector */
498 if (!hw->iov.num_vfs)
499 FM10K_WRITE_REG(hw, FM10K_ITR2(0), i);
501 /* Enable interrupt moderator */
502 FM10K_WRITE_REG(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
506 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
507 * @hw: pointer to the HW structure
508 * @glort: base resource tag for this request
509 * @count: number of logical ports being updated
510 * @enable: boolean value indicating enable or disable
512 * This function is used to add/remove a logical port from the switch.
514 STATIC s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
515 u16 count, bool enable)
517 struct fm10k_mbx_info *mbx = &hw->mbx;
518 u32 msg[3], lport_msg;
520 DEBUGFUNC("fm10k_lport_state_pf");
522 /* do nothing if we are being asked to create or destroy 0 ports */
524 return FM10K_SUCCESS;
526 /* if glort is not valid return error */
527 if (!fm10k_glort_valid_pf(hw, glort))
528 return FM10K_ERR_PARAM;
530 /* construct the lport message from the 2 pieces of data we have */
531 lport_msg = ((u32)count << 16) | glort;
533 /* generate lport create/delete message */
534 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
535 FM10K_PF_MSG_ID_LPORT_DELETE);
536 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
538 /* load onto outgoing mailbox */
539 return mbx->ops.enqueue_tx(hw, mbx, msg);
543 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
544 * @hw: pointer to hardware structure
545 * @dglort: pointer to dglort configuration structure
547 * Reads the configuration structure contained in dglort_cfg and uses
548 * that information to then populate a DGLORTMAP/DEC entry and the queues
549 * to which it has been assigned.
551 STATIC s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
552 struct fm10k_dglort_cfg *dglort)
554 u16 glort, queue_count, vsi_count, pc_count;
555 u16 vsi, queue, pc, q_idx;
556 u32 txqctl, dglortdec, dglortmap;
558 /* verify the dglort pointer */
560 return FM10K_ERR_PARAM;
562 /* verify the dglort values */
563 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
564 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
565 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
566 return FM10K_ERR_PARAM;
568 /* determine count of VSIs and queues */
569 queue_count = 1 << (dglort->rss_l + dglort->pc_l);
570 vsi_count = 1 << (dglort->vsi_l + dglort->queue_l);
571 glort = dglort->glort;
572 q_idx = dglort->queue_b;
574 /* configure SGLORT for queues */
575 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
576 for (queue = 0; queue < queue_count; queue++, q_idx++) {
577 if (q_idx >= FM10K_MAX_QUEUES)
580 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(q_idx), glort);
581 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(q_idx), glort);
585 /* determine count of PCs and queues */
586 queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l);
587 pc_count = 1 << dglort->pc_l;
589 /* configure PC for Tx queues */
590 for (pc = 0; pc < pc_count; pc++) {
591 q_idx = pc + dglort->queue_b;
592 for (queue = 0; queue < queue_count; queue++) {
593 if (q_idx >= FM10K_MAX_QUEUES)
596 txqctl = FM10K_READ_REG(hw, FM10K_TXQCTL(q_idx));
597 txqctl &= ~FM10K_TXQCTL_PC_MASK;
598 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
599 FM10K_WRITE_REG(hw, FM10K_TXQCTL(q_idx), txqctl);
605 /* configure DGLORTDEC */
606 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
607 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
608 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
609 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
610 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
611 ((u32)(dglort->queue_l));
612 if (dglort->inner_rss)
613 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
615 /* configure DGLORTMAP */
616 dglortmap = (dglort->idx == fm10k_dglort_default) ?
617 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
618 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
619 dglortmap |= dglort->glort;
621 /* write values to hardware */
622 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
623 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
625 return FM10K_SUCCESS;
628 u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
630 u16 num_pools = hw->iov.num_pools;
632 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
633 8 : FM10K_MAX_QUEUES_POOL;
636 u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
638 u16 num_vfs = hw->iov.num_vfs;
639 u16 vf_q_idx = FM10K_MAX_QUEUES;
641 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
646 STATIC u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
648 u16 num_pools = hw->iov.num_pools;
650 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
651 FM10K_MAX_VECTORS_POOL;
654 STATIC u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
656 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
658 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
664 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
665 * @hw: pointer to the HW structure
666 * @num_vfs: number of VFs to be allocated
667 * @num_pools: number of virtualization pools to be allocated
669 * Allocates queues and traffic classes to virtualization entities to prepare
670 * the PF for SR-IOV and VMDq
672 STATIC s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
675 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
676 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
679 /* hardware only supports up to 64 pools */
681 return FM10K_ERR_PARAM;
683 /* the number of VFs cannot exceed the number of pools */
684 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
685 return FM10K_ERR_PARAM;
687 /* record number of virtualization entities */
688 hw->iov.num_vfs = num_vfs;
689 hw->iov.num_pools = num_pools;
691 /* determine qmap offsets and counts */
692 qmap_stride = (num_vfs > 8) ? 32 : 256;
693 qpp = fm10k_queues_per_pool(hw);
694 vpp = fm10k_vectors_per_pool(hw);
696 /* calculate starting index for queues */
697 vf_q_idx = fm10k_vf_queue_index(hw, 0);
700 /* establish TCs with -1 credits and no quanta to prevent transmit */
701 for (i = 0; i < num_vfs; i++) {
702 FM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(i), 0);
703 FM10K_WRITE_REG(hw, FM10K_TC_RATE(i), 0);
704 FM10K_WRITE_REG(hw, FM10K_TC_CREDIT(i),
705 FM10K_TC_CREDIT_CREDIT_MASK);
708 /* zero out all mbmem registers */
709 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
710 FM10K_WRITE_REG(hw, FM10K_MBMEM(i), 0);
712 /* clear event notification of VF FLR */
713 FM10K_WRITE_REG(hw, FM10K_PFVFLREC(0), ~0);
714 FM10K_WRITE_REG(hw, FM10K_PFVFLREC(1), ~0);
716 /* loop through unallocated rings assigning them back to PF */
717 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
718 FM10K_WRITE_REG(hw, FM10K_TXDCTL(i), 0);
719 FM10K_WRITE_REG(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | vid);
720 FM10K_WRITE_REG(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
723 /* PF should have already updated VFITR2[0] */
725 /* update all ITR registers to flow to VFITR2[0] */
726 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
727 if (!(i & (vpp - 1)))
728 FM10K_WRITE_REG(hw, FM10K_ITR2(i), i - vpp);
730 FM10K_WRITE_REG(hw, FM10K_ITR2(i), i - 1);
733 /* update PF ITR2[0] to reference the last vector */
734 FM10K_WRITE_REG(hw, FM10K_ITR2(0),
735 fm10k_vf_vector_index(hw, num_vfs - 1));
737 /* loop through rings populating rings and TCs */
738 for (i = 0; i < num_vfs; i++) {
739 /* record index for VF queue 0 for use in end of loop */
740 vf_q_idx0 = vf_q_idx;
742 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
743 /* assign VF and locked TC to queues */
744 FM10K_WRITE_REG(hw, FM10K_TXDCTL(vf_q_idx), 0);
745 FM10K_WRITE_REG(hw, FM10K_TXQCTL(vf_q_idx),
746 (i << FM10K_TXQCTL_TC_SHIFT) | i |
747 FM10K_TXQCTL_VF | vid);
748 FM10K_WRITE_REG(hw, FM10K_RXDCTL(vf_q_idx),
749 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
750 FM10K_RXDCTL_DROP_ON_EMPTY);
751 FM10K_WRITE_REG(hw, FM10K_RXQCTL(vf_q_idx),
753 (i << FM10K_RXQCTL_VF_SHIFT));
755 /* map queue pair to VF */
756 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
757 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
760 /* repeat the first ring for all of the remaining VF rings */
761 for (; j < qmap_stride; j++, qmap_idx++) {
762 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
763 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
767 /* loop through remaining indexes assigning all to queue 0 */
768 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
769 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), 0);
770 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), 0);
774 return FM10K_SUCCESS;
778 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
779 * @hw: pointer to the HW structure
780 * @vf_idx: index of VF receiving GLORT
781 * @rate: Rate indicated in Mb/s
783 * Configured the TC for a given VF to allow only up to a given number
784 * of Mb/s of outgoing Tx throughput.
786 STATIC s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
788 /* configure defaults */
789 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
790 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
792 /* verify vf is in range */
793 if (vf_idx >= hw->iov.num_vfs)
794 return FM10K_ERR_PARAM;
796 /* set interval to align with 4.096 usec in all modes */
797 switch (hw->bus.speed) {
798 case fm10k_bus_speed_2500:
799 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
801 case fm10k_bus_speed_5000:
802 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
809 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
810 return FM10K_ERR_PARAM;
812 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
813 * The rate is provided in Mbits per second
814 * To tralslate from rate to quanta we need to multiply the
815 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
816 * dealing with floating point we can round the values up
817 * to the nearest whole number ratio which gives us 128 / 125.
819 tc_rate = (rate * 128) / 125;
821 /* try to keep the rate limiting accurate by increasing
822 * the number of credits and interval for rates less than 4Gb/s
830 /* update rate limiter with new values */
831 FM10K_WRITE_REG(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
832 FM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
833 FM10K_WRITE_REG(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
835 return FM10K_SUCCESS;
839 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
840 * @hw: pointer to the HW structure
841 * @vf_idx: index of VF receiving GLORT
843 * Update the interrupt moderator linked list to include any MSI-X
844 * interrupts which the VF has enabled in the MSI-X vector table.
846 STATIC s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
848 u16 vf_v_idx, vf_v_limit, i;
850 /* verify vf is in range */
851 if (vf_idx >= hw->iov.num_vfs)
852 return FM10K_ERR_PARAM;
854 /* determine vector offset and count */
855 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
856 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
858 /* search for first vector that is not masked */
859 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
860 if (!FM10K_READ_REG(hw, FM10K_MSIX_VECTOR_MASK(i)))
864 /* reset linked list so it now includes our active vectors */
865 if (vf_idx == (hw->iov.num_vfs - 1))
866 FM10K_WRITE_REG(hw, FM10K_ITR2(0), i);
868 FM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_limit), i);
870 return FM10K_SUCCESS;
874 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
875 * @hw: pointer to the HW structure
876 * @vf_info: pointer to VF information structure
878 * Assign a MAC address and default VLAN to a VF and notify it of the update
880 STATIC s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
881 struct fm10k_vf_info *vf_info)
883 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
884 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
885 s32 err = FM10K_SUCCESS;
888 /* verify vf is in range */
889 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
890 return FM10K_ERR_PARAM;
892 /* determine qmap offsets and counts */
893 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
894 queues_per_pool = fm10k_queues_per_pool(hw);
896 /* calculate starting index for queues */
897 vf_idx = vf_info->vf_idx;
898 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
899 qmap_idx = qmap_stride * vf_idx;
901 /* MAP Tx queue back to 0 temporarily, and disable it */
902 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), 0);
903 FM10K_WRITE_REG(hw, FM10K_TXDCTL(vf_q_idx), 0);
905 /* determine correct default VLAN ID */
907 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;
909 vf_vid = vf_info->sw_vid;
911 /* generate MAC_ADDR request */
912 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
913 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
914 vf_info->mac, vf_vid);
916 /* load onto outgoing mailbox, ignore any errors on enqueue */
917 if (vf_info->mbx.ops.enqueue_tx)
918 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
920 /* verify ring has disabled before modifying base address registers */
921 txdctl = FM10K_READ_REG(hw, FM10K_TXDCTL(vf_q_idx));
922 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
923 /* limit ourselves to a 1ms timeout */
925 err = FM10K_ERR_DMA_PENDING;
930 txdctl = FM10K_READ_REG(hw, FM10K_TXDCTL(vf_q_idx));
933 /* Update base address registers to contain MAC address */
934 if (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac)) {
935 tdbal = (((u32)vf_info->mac[3]) << 24) |
936 (((u32)vf_info->mac[4]) << 16) |
937 (((u32)vf_info->mac[5]) << 8);
939 tdbah = (((u32)0xFF) << 24) |
940 (((u32)vf_info->mac[0]) << 16) |
941 (((u32)vf_info->mac[1]) << 8) |
942 ((u32)vf_info->mac[2]);
945 /* Record the base address into queue 0 */
946 FM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx), tdbal);
947 FM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx), tdbah);
950 /* configure Queue control register */
951 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
952 FM10K_TXQCTL_VID_MASK;
953 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
954 FM10K_TXQCTL_VF | vf_idx;
957 for (i = 0; i < queues_per_pool; i++)
958 FM10K_WRITE_REG(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
960 /* restore the queue back to VF ownership */
961 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
966 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
967 * @hw: pointer to the HW structure
968 * @vf_info: pointer to VF information structure
970 * Reassign the interrupts and queues to a VF following an FLR
972 STATIC s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
973 struct fm10k_vf_info *vf_info)
975 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
976 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
977 u16 vf_v_idx, vf_v_limit, vf_vid;
978 u8 vf_idx = vf_info->vf_idx;
981 /* verify vf is in range */
982 if (vf_idx >= hw->iov.num_vfs)
983 return FM10K_ERR_PARAM;
985 /* clear event notification of VF FLR */
986 FM10K_WRITE_REG(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32));
988 /* force timeout and then disconnect the mailbox */
989 vf_info->mbx.timeout = 0;
990 if (vf_info->mbx.ops.disconnect)
991 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
993 /* determine vector offset and count */
994 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
995 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
997 /* determine qmap offsets and counts */
998 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
999 queues_per_pool = fm10k_queues_per_pool(hw);
1000 qmap_idx = qmap_stride * vf_idx;
1002 /* make all the queues inaccessible to the VF */
1003 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
1004 FM10K_WRITE_REG(hw, FM10K_TQMAP(i), 0);
1005 FM10K_WRITE_REG(hw, FM10K_RQMAP(i), 0);
1008 /* calculate starting index for queues */
1009 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
1011 /* determine correct default VLAN ID */
1012 if (vf_info->pf_vid)
1013 vf_vid = vf_info->pf_vid;
1015 vf_vid = vf_info->sw_vid;
1017 /* configure Queue control register */
1018 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
1019 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
1020 FM10K_TXQCTL_VF | vf_idx;
1021 rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT);
1023 /* stop further DMA and reset queue ownership back to VF */
1024 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
1025 FM10K_WRITE_REG(hw, FM10K_TXDCTL(i), 0);
1026 FM10K_WRITE_REG(hw, FM10K_TXQCTL(i), txqctl);
1027 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i),
1028 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
1029 FM10K_RXDCTL_DROP_ON_EMPTY);
1030 FM10K_WRITE_REG(hw, FM10K_RXQCTL(i), rxqctl);
1033 /* reset TC with -1 credits and no quanta to prevent transmit */
1034 FM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
1035 FM10K_WRITE_REG(hw, FM10K_TC_RATE(vf_idx), 0);
1036 FM10K_WRITE_REG(hw, FM10K_TC_CREDIT(vf_idx),
1037 FM10K_TC_CREDIT_CREDIT_MASK);
1039 /* update our first entry in the table based on previous VF */
1041 hw->mac.ops.update_int_moderator(hw);
1043 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1045 /* reset linked list so it now includes our active vectors */
1046 if (vf_idx == (hw->iov.num_vfs - 1))
1047 FM10K_WRITE_REG(hw, FM10K_ITR2(0), vf_v_idx);
1049 FM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1051 /* link remaining vectors so that next points to previous */
1052 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1053 FM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1055 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1056 for (i = FM10K_VFMBMEM_LEN; i--;)
1057 FM10K_WRITE_REG(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1058 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1059 FM10K_WRITE_REG(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1060 for (i = FM10K_RETA_SIZE; i--;)
1061 FM10K_WRITE_REG(hw, FM10K_RETA(vf_info->vsi, i), 0);
1062 for (i = FM10K_RSSRK_SIZE; i--;)
1063 FM10K_WRITE_REG(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1064 FM10K_WRITE_REG(hw, FM10K_MRQC(vf_info->vsi), 0);
1066 /* Update base address registers to contain MAC address */
1067 if (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac)) {
1068 tdbal = (((u32)vf_info->mac[3]) << 24) |
1069 (((u32)vf_info->mac[4]) << 16) |
1070 (((u32)vf_info->mac[5]) << 8);
1071 tdbah = (((u32)0xFF) << 24) |
1072 (((u32)vf_info->mac[0]) << 16) |
1073 (((u32)vf_info->mac[1]) << 8) |
1074 ((u32)vf_info->mac[2]);
1077 /* map queue pairs back to VF from last to first */
1078 for (i = queues_per_pool; i--;) {
1079 FM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1080 FM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1081 FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1082 FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1085 return FM10K_SUCCESS;
1089 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1090 * @hw: pointer to hardware structure
1091 * @vf_info: pointer to VF information structure
1092 * @lport_idx: Logical port offset from the hardware glort
1093 * @flags: Set of capability flags to extend port beyond basic functionality
1095 * This function allows enabling a VF port by assigning it a GLORT and
1096 * setting the flags so that it can enable an Rx mode.
1098 STATIC s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1099 struct fm10k_vf_info *vf_info,
1100 u16 lport_idx, u8 flags)
1102 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1104 DEBUGFUNC("fm10k_iov_set_lport_state_pf");
1106 /* if glort is not valid return error */
1107 if (!fm10k_glort_valid_pf(hw, glort))
1108 return FM10K_ERR_PARAM;
1110 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1111 vf_info->glort = glort;
1113 return FM10K_SUCCESS;
1117 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1118 * @hw: pointer to hardware structure
1119 * @vf_info: pointer to VF information structure
1121 * This function disables a VF port by stripping it of a GLORT and
1122 * setting the flags so that it cannot enable any Rx mode.
1124 STATIC void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1125 struct fm10k_vf_info *vf_info)
1129 DEBUGFUNC("fm10k_iov_reset_lport_state_pf");
1131 /* need to disable the port if it is already enabled */
1132 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1133 /* notify switch that this port has been disabled */
1134 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1136 /* generate port state response to notify VF it is not ready */
1137 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1138 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1141 /* clear flags and glort if it exists */
1142 vf_info->vf_flags = 0;
1147 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1148 * @hw: pointer to hardware structure
1149 * @q: stats for all queues of a VF
1150 * @vf_idx: index of VF
1152 * This function collects queue stats for VFs.
1154 STATIC void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1155 struct fm10k_hw_stats_q *q,
1160 /* get stats for all of the queues */
1161 qpp = fm10k_queues_per_pool(hw);
1162 idx = fm10k_vf_queue_index(hw, vf_idx);
1163 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1166 STATIC s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw,
1167 struct fm10k_vf_info *vf_info,
1172 /* generate port state response to notify VF it is not ready */
1173 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588);
1174 fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp);
1176 return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1180 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1181 * @hw: Pointer to hardware structure
1182 * @results: Pointer array to message, results[0] is pointer to message
1183 * @mbx: Pointer to mailbox information structure
1185 * This function is a default handler for MSI-X requests from the VF. The
1186 * assumption is that in this case it is acceptable to just directly
1187 * hand off the message from the VF to the underlying shared code.
1189 s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,
1190 struct fm10k_mbx_info *mbx)
1192 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1193 u8 vf_idx = vf_info->vf_idx;
1195 UNREFERENCED_1PARAMETER(results);
1196 DEBUGFUNC("fm10k_iov_msg_msix_pf");
1198 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1202 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1203 * @hw: Pointer to hardware structure
1204 * @results: Pointer array to message, results[0] is pointer to message
1205 * @mbx: Pointer to mailbox information structure
1207 * This function is a default handler for MAC/VLAN requests from the VF.
1208 * The assumption is that in this case it is acceptable to just directly
1209 * hand off the message from the VF to the underlying shared code.
1211 s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1212 struct fm10k_mbx_info *mbx)
1214 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1215 int err = FM10K_SUCCESS;
1221 DEBUGFUNC("fm10k_iov_msg_mac_vlan_pf");
1223 /* we shouldn't be updating rules on a disabled interface */
1224 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1225 err = FM10K_ERR_PARAM;
1227 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1228 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1230 /* record VLAN id requested */
1231 err = fm10k_tlv_attr_get_u32(result, &vid);
1235 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1236 if (!vid || (vid == FM10K_VLAN_CLEAR)) {
1237 if (vf_info->pf_vid)
1238 vid |= vf_info->pf_vid;
1240 vid |= vf_info->sw_vid;
1241 } else if (vid != vf_info->pf_vid) {
1242 return FM10K_ERR_PARAM;
1245 /* update VSI info for VF in regards to VLAN table */
1246 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi,
1247 !(vid & FM10K_VLAN_CLEAR));
1250 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1251 result = results[FM10K_MAC_VLAN_MSG_MAC];
1253 /* record unicast MAC address requested */
1254 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1258 /* block attempts to set MAC for a locked device */
1259 if (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac) &&
1260 memcmp(mac, vf_info->mac, ETH_ALEN))
1261 return FM10K_ERR_PARAM;
1263 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1264 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1265 if (vf_info->pf_vid)
1266 vlan |= vf_info->pf_vid;
1268 vlan |= vf_info->sw_vid;
1269 } else if (vf_info->pf_vid) {
1270 return FM10K_ERR_PARAM;
1273 /* notify switch of request for new unicast address */
1274 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, mac, vlan,
1275 !(vlan & FM10K_VLAN_CLEAR), 0);
1278 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1279 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1281 /* record multicast MAC address requested */
1282 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1286 /* verify that the VF is allowed to request multicast */
1287 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1288 return FM10K_ERR_PARAM;
1290 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1291 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1292 if (vf_info->pf_vid)
1293 vlan |= vf_info->pf_vid;
1295 vlan |= vf_info->sw_vid;
1296 } else if (vf_info->pf_vid) {
1297 return FM10K_ERR_PARAM;
1300 /* notify switch of request for new multicast address */
1301 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac,
1302 !(vlan & FM10K_VLAN_CLEAR), 0);
1309 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1310 * @vf_info: VF info structure containing capability flags
1311 * @mode: Requested xcast mode
1313 * This function outputs the mode that most closely matches the requested
1314 * mode. If not modes match it will request we disable the port
1316 STATIC u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1319 u8 vf_flags = vf_info->vf_flags;
1321 /* match up mode to capabilities as best as possible */
1323 case FM10K_XCAST_MODE_PROMISC:
1324 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1325 return FM10K_XCAST_MODE_PROMISC;
1327 case FM10K_XCAST_MODE_ALLMULTI:
1328 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1329 return FM10K_XCAST_MODE_ALLMULTI;
1331 case FM10K_XCAST_MODE_MULTI:
1332 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1333 return FM10K_XCAST_MODE_MULTI;
1335 case FM10K_XCAST_MODE_NONE:
1336 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1337 return FM10K_XCAST_MODE_NONE;
1343 /* disable interface as it should not be able to request any */
1344 return FM10K_XCAST_MODE_DISABLE;
1348 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1349 * @hw: Pointer to hardware structure
1350 * @results: Pointer array to message, results[0] is pointer to message
1351 * @mbx: Pointer to mailbox information structure
1353 * This function is a default handler for port state requests. The port
1354 * state requests for now are basic and consist of enabling or disabling
1357 s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1358 struct fm10k_mbx_info *mbx)
1360 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1362 s32 err = FM10K_SUCCESS;
1366 DEBUGFUNC("fm10k_iov_msg_lport_state_pf");
1368 /* verify VF is allowed to enable even minimal mode */
1369 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1370 return FM10K_ERR_PARAM;
1372 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1373 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1375 /* XCAST mode update requested */
1376 err = fm10k_tlv_attr_get_u8(result, &mode);
1378 return FM10K_ERR_PARAM;
1380 /* prep for possible demotion depending on capabilities */
1381 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1383 /* if mode is not currently enabled, enable it */
1384 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode)))
1385 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1387 /* swap mode back to a bit flag */
1388 mode = FM10K_VF_FLAG_SET_MODE(mode);
1389 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1390 /* need to disable the port if it is already enabled */
1391 if (FM10K_VF_FLAG_ENABLED(vf_info))
1392 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1395 /* when enabling the port we should reset the rate limiters */
1396 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1398 /* set mode for minimal functionality */
1399 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1401 /* generate port state response to notify VF it is ready */
1402 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1403 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1404 mbx->ops.enqueue_tx(hw, mbx, msg);
1407 /* if enable state toggled note the update */
1408 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1409 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1412 /* if state change succeeded, then update our stored state */
1413 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1415 vf_info->vf_flags = mode;
1420 const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = {
1421 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1422 FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf),
1423 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf),
1424 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf),
1425 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1429 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1430 * @hw: pointer to hardware structure
1431 * @stats: pointer to the stats structure to update
1433 * This function collects and aggregates global and per queue hardware
1436 STATIC void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1437 struct fm10k_hw_stats *stats)
1439 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1442 DEBUGFUNC("fm10k_update_hw_stats_pf");
1444 /* Use Tx queue 0 as a canary to detect a reset */
1445 id = FM10K_READ_REG(hw, FM10K_TXQCTL(0));
1447 /* Read Global Statistics */
1449 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1451 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1452 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1453 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1454 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1455 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1457 loopback_drop = fm10k_read_hw_stats_32b(hw,
1458 FM10K_STATS_LOOPBACK_DROP,
1459 &stats->loopback_drop);
1460 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1461 FM10K_STATS_NODESC_DROP,
1462 &stats->nodesc_drop);
1464 /* if value has not changed then we have consistent data */
1466 id = FM10K_READ_REG(hw, FM10K_TXQCTL(0));
1467 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1469 /* drop non-ID bits and set VALID ID bit */
1470 id &= FM10K_TXQCTL_ID_MASK;
1471 id |= FM10K_STAT_VALID;
1473 /* Update Global Statistics */
1474 if (stats->stats_idx == id) {
1475 stats->timeout.count += timeout;
1476 stats->ur.count += ur;
1477 stats->ca.count += ca;
1478 stats->um.count += um;
1479 stats->xec.count += xec;
1480 stats->vlan_drop.count += vlan_drop;
1481 stats->loopback_drop.count += loopback_drop;
1482 stats->nodesc_drop.count += nodesc_drop;
1485 /* Update bases and record current PF id */
1486 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1487 fm10k_update_hw_base_32b(&stats->ur, ur);
1488 fm10k_update_hw_base_32b(&stats->ca, ca);
1489 fm10k_update_hw_base_32b(&stats->um, um);
1490 fm10k_update_hw_base_32b(&stats->xec, xec);
1491 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1492 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1493 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1494 stats->stats_idx = id;
1496 /* Update Queue Statistics */
1497 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1501 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1502 * @hw: pointer to hardware structure
1503 * @stats: pointer to the stats structure to update
1505 * This function resets the base for global and per queue hardware
1508 STATIC void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1509 struct fm10k_hw_stats *stats)
1511 DEBUGFUNC("fm10k_rebind_hw_stats_pf");
1513 /* Unbind Global Statistics */
1514 fm10k_unbind_hw_stats_32b(&stats->timeout);
1515 fm10k_unbind_hw_stats_32b(&stats->ur);
1516 fm10k_unbind_hw_stats_32b(&stats->ca);
1517 fm10k_unbind_hw_stats_32b(&stats->um);
1518 fm10k_unbind_hw_stats_32b(&stats->xec);
1519 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1520 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1521 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1523 /* Unbind Queue Statistics */
1524 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1526 /* Reinitialize bases for all stats */
1527 fm10k_update_hw_stats_pf(hw, stats);
1531 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1532 * @hw: pointer to hardware structure
1533 * @dma_mask: 64 bit DMA mask required for platform
1535 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1536 * to limit the access to memory beyond what is physically in the system.
1538 STATIC void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1540 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1541 u32 phyaddr = (u32)(dma_mask >> 32);
1543 DEBUGFUNC("fm10k_set_dma_mask_pf");
1545 FM10K_WRITE_REG(hw, FM10K_PHYADDR, phyaddr);
1549 * fm10k_get_fault_pf - Record a fault in one of the interface units
1550 * @hw: pointer to hardware structure
1551 * @type: pointer to fault type register offset
1552 * @fault: pointer to memory location to record the fault
1554 * Record the fault register contents to the fault data structure and
1555 * clear the entry from the register.
1557 * Returns ERR_PARAM if invalid register is specified or no error is present.
1559 STATIC s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1560 struct fm10k_fault *fault)
1564 DEBUGFUNC("fm10k_get_fault_pf");
1566 /* verify the fault register is in range and is aligned */
1568 case FM10K_PCA_FAULT:
1569 case FM10K_THI_FAULT:
1570 case FM10K_FUM_FAULT:
1573 return FM10K_ERR_PARAM;
1576 /* only service faults that are valid */
1577 func = FM10K_READ_REG(hw, type + FM10K_FAULT_FUNC);
1578 if (!(func & FM10K_FAULT_FUNC_VALID))
1579 return FM10K_ERR_PARAM;
1581 /* read remaining fields */
1582 fault->address = FM10K_READ_REG(hw, type + FM10K_FAULT_ADDR_HI);
1583 fault->address <<= 32;
1584 fault->address = FM10K_READ_REG(hw, type + FM10K_FAULT_ADDR_LO);
1585 fault->specinfo = FM10K_READ_REG(hw, type + FM10K_FAULT_SPECINFO);
1587 /* clear valid bit to allow for next error */
1588 FM10K_WRITE_REG(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1590 /* Record which function triggered the error */
1591 if (func & FM10K_FAULT_FUNC_PF)
1594 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1595 FM10K_FAULT_FUNC_VF_SHIFT);
1597 /* record fault type */
1598 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1600 return FM10K_SUCCESS;
1604 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1605 * @hw: pointer to hardware structure
1608 STATIC s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1610 struct fm10k_mbx_info *mbx = &hw->mbx;
1613 DEBUGFUNC("fm10k_request_lport_pf");
1615 /* issue request asking for LPORT map */
1616 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1618 /* load onto outgoing mailbox */
1619 return mbx->ops.enqueue_tx(hw, mbx, msg);
1623 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1624 * @hw: pointer to hardware structure
1625 * @switch_ready: pointer to boolean value that will record switch state
1627 * This funciton will check the DMA_CTRL2 register and mailbox in order
1628 * to determine if the switch is ready for the PF to begin requesting
1629 * addresses and mapping traffic to the local interface.
1631 STATIC s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1633 s32 ret_val = FM10K_SUCCESS;
1636 DEBUGFUNC("fm10k_get_host_state_pf");
1638 /* verify the switch is ready for interaction */
1639 dma_ctrl2 = FM10K_READ_REG(hw, FM10K_DMA_CTRL2);
1640 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1643 /* retrieve generic host state info */
1644 ret_val = fm10k_get_host_state_generic(hw, switch_ready);
1648 /* interface cannot receive traffic without logical ports */
1649 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)
1650 ret_val = fm10k_request_lport_map_pf(hw);
1656 /* This structure defines the attibutes to be parsed below */
1657 const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1658 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1663 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1664 * @hw: Pointer to hardware structure
1665 * @results: pointer array containing parsed data
1666 * @mbx: Pointer to mailbox information structure
1668 * This handler configures the lport mapping based on the reply from the
1671 s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1672 struct fm10k_mbx_info *mbx)
1678 UNREFERENCED_1PARAMETER(mbx);
1679 DEBUGFUNC("fm10k_msg_lport_map_pf");
1681 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1686 /* extract values out of the header */
1687 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1688 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1690 /* verify mask is set and none of the masked bits in glort are set */
1691 if (!mask || (glort & ~mask))
1692 return FM10K_ERR_PARAM;
1694 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1695 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1696 return FM10K_ERR_PARAM;
1698 /* record the glort, mask, and port count */
1699 hw->mac.dglort_map = dglort_map;
1701 return FM10K_SUCCESS;
1704 const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1705 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1710 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1711 * @hw: Pointer to hardware structure
1712 * @results: pointer array containing parsed data
1713 * @mbx: Pointer to mailbox information structure
1715 * This handler configures the default VLAN for the PF
1717 s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1718 struct fm10k_mbx_info *mbx)
1724 UNREFERENCED_1PARAMETER(mbx);
1725 DEBUGFUNC("fm10k_msg_update_pvid_pf");
1727 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1732 /* extract values from the pvid update */
1733 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1734 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1736 /* if glort is not valid return error */
1737 if (!fm10k_glort_valid_pf(hw, glort))
1738 return FM10K_ERR_PARAM;
1740 /* verify VID is valid */
1741 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1742 return FM10K_ERR_PARAM;
1744 /* record the port VLAN ID value */
1745 hw->mac.default_vid = pvid;
1747 return FM10K_SUCCESS;
1751 * fm10k_record_global_table_data - Move global table data to swapi table info
1752 * @from: pointer to source table data structure
1753 * @to: pointer to destination table info structure
1755 * This function is will copy table_data to the table_info contained in
1758 static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1759 struct fm10k_swapi_table_info *to)
1761 /* convert from le32 struct to CPU byte ordered values */
1762 to->used = FM10K_LE32_TO_CPU(from->used);
1763 to->avail = FM10K_LE32_TO_CPU(from->avail);
1766 const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1767 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1768 sizeof(struct fm10k_swapi_error)),
1773 * fm10k_msg_err_pf - Message handler for error reply
1774 * @hw: Pointer to hardware structure
1775 * @results: pointer array containing parsed data
1776 * @mbx: Pointer to mailbox information structure
1778 * This handler will capture the data for any error replies to previous
1779 * messages that the PF has sent.
1781 s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1782 struct fm10k_mbx_info *mbx)
1784 struct fm10k_swapi_error err_msg;
1787 UNREFERENCED_1PARAMETER(mbx);
1788 DEBUGFUNC("fm10k_msg_err_pf");
1790 /* extract structure from message */
1791 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1792 &err_msg, sizeof(err_msg));
1796 /* record table status */
1797 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1798 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1799 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1801 /* record SW API status value */
1802 hw->swapi.status = FM10K_LE32_TO_CPU(err_msg.status);
1804 return FM10K_SUCCESS;
1807 const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {
1808 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP,
1809 sizeof(struct fm10k_swapi_1588_timestamp)),
1813 /* currently there is no shared 1588 timestamp handler */
1816 * fm10k_request_tx_timestamp_mode_pf - Request a specific Tx timestamping mode
1817 * @hw: pointer to hardware structure
1818 * @glort: base resource tag for this request
1819 * @mode: integer value indicating the requested mode
1821 * This function will attempt to request a specific timestamp mode for the
1822 * port so that it can receive Tx timestamp messages.
1824 STATIC s32 fm10k_request_tx_timestamp_mode_pf(struct fm10k_hw *hw,
1828 struct fm10k_mbx_info *mbx = &hw->mbx;
1829 u32 msg[3], timestamp_mode;
1831 DEBUGFUNC("fm10k_request_timestamp_mode_pf");
1833 if (mode > FM10K_TIMESTAMP_MODE_PEP_TO_ANY)
1834 return FM10K_ERR_PARAM;
1836 /* if glort is not valid return error */
1837 if (!fm10k_glort_valid_pf(hw, glort))
1838 return FM10K_ERR_PARAM;
1840 /* write timestamp mode as a single u32 value,
1841 * lower 16 bits: glort
1842 * upper 16 bits: mode
1844 timestamp_mode = ((u32)mode << 16) | glort;
1846 /* generate message requesting change to xcast mode */
1847 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_TX_TIMESTAMP_MODE);
1848 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_TIMESTAMP_MODE_REQ, timestamp_mode);
1850 /* load onto outgoing mailbox */
1851 return mbx->ops.enqueue_tx(hw, mbx, msg);
1855 * fm10k_adjust_systime_pf - Adjust systime frequency
1856 * @hw: pointer to hardware structure
1857 * @ppb: adjustment rate in parts per billion
1859 * This function will adjust the SYSTIME_CFG register contained in BAR 4
1860 * if this function is supported for BAR 4 access. The adjustment amount
1861 * is based on the parts per billion value provided and adjusted to a
1862 * value based on parts per 2^48 clock cycles.
1864 * If adjustment is not supported or the requested value is too large
1865 * we will return an error.
1867 STATIC s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)
1871 DEBUGFUNC("fm10k_adjust_systime_vf");
1873 /* if sw_addr is not set we don't have switch register access */
1875 return ppb ? FM10K_ERR_PARAM : FM10K_SUCCESS;
1877 /* we must convert the value from parts per billion to parts per
1878 * 2^48 cycles. In addition I have opted to only use the 30 most
1879 * significant bits of the adjustment value as the 8 least
1880 * significant bits are located in another register and represent
1881 * a value significantly less than a part per billion, the result
1882 * of dropping the 8 least significant bits is that the adjustment
1883 * value is effectively multiplied by 2^8 when we write it.
1885 * As a result of all this the math for this breaks down as follows:
1886 * ppb / 10^9 == adjust * 2^8 / 2^48
1887 * If we solve this for adjust, and simplify it comes out as:
1888 * ppb * 2^31 / 5^9 == adjust
1890 systime_adjust = (ppb < 0) ? -ppb : ppb;
1891 systime_adjust <<= 31;
1892 do_div(systime_adjust, 1953125);
1894 /* verify the requested adjustment value is in range */
1895 if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK)
1896 return FM10K_ERR_PARAM;
1899 systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_NEGATIVE;
1901 FM10K_WRITE_SW_REG(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust);
1903 return FM10K_SUCCESS;
1907 * fm10k_read_systime_pf - Reads value of systime registers
1908 * @hw: pointer to the hardware structure
1910 * Function reads the content of 2 registers, combined to represent a 64 bit
1911 * value measured in nanosecods. In order to guarantee the value is accurate
1912 * we check the 32 most significant bits both before and after reading the
1913 * 32 least significant bits to verify they didn't change as we were reading
1916 static u64 fm10k_read_systime_pf(struct fm10k_hw *hw)
1918 u32 systime_l, systime_h, systime_tmp;
1920 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1923 systime_tmp = systime_h;
1924 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME);
1925 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1926 } while (systime_tmp != systime_h);
1928 return ((u64)systime_h << 32) | systime_l;
1931 static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1932 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1933 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1934 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1935 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1936 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1937 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1938 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1942 * fm10k_init_ops_pf - Inits func ptrs and MAC type
1943 * @hw: pointer to hardware structure
1945 * Initialize the function pointers and assign the MAC type for PF.
1946 * Does not touch the hardware.
1948 s32 fm10k_init_ops_pf(struct fm10k_hw *hw)
1950 struct fm10k_mac_info *mac = &hw->mac;
1951 struct fm10k_iov_info *iov = &hw->iov;
1953 DEBUGFUNC("fm10k_init_ops_pf");
1955 fm10k_init_ops_generic(hw);
1957 mac->ops.reset_hw = &fm10k_reset_hw_pf;
1958 mac->ops.init_hw = &fm10k_init_hw_pf;
1959 mac->ops.start_hw = &fm10k_start_hw_generic;
1960 mac->ops.stop_hw = &fm10k_stop_hw_generic;
1961 mac->ops.is_slot_appropriate = &fm10k_is_slot_appropriate_pf;
1962 mac->ops.update_vlan = &fm10k_update_vlan_pf;
1963 mac->ops.read_mac_addr = &fm10k_read_mac_addr_pf;
1964 mac->ops.update_uc_addr = &fm10k_update_uc_addr_pf;
1965 mac->ops.update_mc_addr = &fm10k_update_mc_addr_pf;
1966 mac->ops.update_xcast_mode = &fm10k_update_xcast_mode_pf;
1967 mac->ops.update_int_moderator = &fm10k_update_int_moderator_pf;
1968 mac->ops.update_lport_state = &fm10k_update_lport_state_pf;
1969 mac->ops.update_hw_stats = &fm10k_update_hw_stats_pf;
1970 mac->ops.rebind_hw_stats = &fm10k_rebind_hw_stats_pf;
1971 mac->ops.configure_dglort_map = &fm10k_configure_dglort_map_pf;
1972 mac->ops.set_dma_mask = &fm10k_set_dma_mask_pf;
1973 mac->ops.get_fault = &fm10k_get_fault_pf;
1974 mac->ops.get_host_state = &fm10k_get_host_state_pf;
1975 mac->ops.adjust_systime = &fm10k_adjust_systime_pf;
1976 mac->ops.read_systime = &fm10k_read_systime_pf;
1977 mac->ops.request_tx_timestamp_mode = &fm10k_request_tx_timestamp_mode_pf;
1979 mac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw);
1981 iov->ops.assign_resources = &fm10k_iov_assign_resources_pf;
1982 iov->ops.configure_tc = &fm10k_iov_configure_tc_pf;
1983 iov->ops.assign_int_moderator = &fm10k_iov_assign_int_moderator_pf;
1984 iov->ops.assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf;
1985 iov->ops.reset_resources = &fm10k_iov_reset_resources_pf;
1986 iov->ops.set_lport = &fm10k_iov_set_lport_pf;
1987 iov->ops.reset_lport = &fm10k_iov_reset_lport_pf;
1988 iov->ops.update_stats = &fm10k_iov_update_stats_pf;
1989 iov->ops.report_timestamp = &fm10k_iov_report_timestamp_pf;
1991 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);