1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #ifndef _FM10K_TYPE_H_
35 #define _FM10K_TYPE_H_
37 /* forward declaration */
40 #include "fm10k_osdep.h"
41 #include "fm10k_mbx.h"
43 #define FM10K_INTEL_VENDOR_ID 0x8086
44 #define FM10K_DEV_ID_PF 0x15A4
45 #define FM10K_DEV_ID_VF 0x15A5
46 #ifdef BOULDER_RAPIDS_HW
47 #define FM10K_DEV_ID_SDI_FM10420_QDA2 0x15D0
48 #endif /* BOULDER_RAPIDS_HW */
49 #ifdef ATWOOD_CHANNEL_HW
50 #define FM10K_DEV_ID_SDI_FM10420_DA2 0x15D5
51 #endif /* ATWOOD_CHANNEL_HW */
55 #define BIT(a) (1UL << (a))
57 #endif /* LINUX_MACROS */
59 #define FM10K_MAX_QUEUES 256
60 #define FM10K_MAX_QUEUES_PF 128
61 #define FM10K_MAX_QUEUES_POOL 16
63 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
64 #define FM10K_STAT_VALID 0x80000000
67 #define FM10K_PCIE_LINK_CAP 0x7C
68 #define FM10K_PCIE_LINK_STATUS 0x82
69 #define FM10K_PCIE_LINK_WIDTH 0x3F0
70 #define FM10K_PCIE_LINK_WIDTH_1 0x10
71 #define FM10K_PCIE_LINK_WIDTH_2 0x20
72 #define FM10K_PCIE_LINK_WIDTH_4 0x40
73 #define FM10K_PCIE_LINK_WIDTH_8 0x80
74 #define FM10K_PCIE_LINK_SPEED 0xF
75 #define FM10K_PCIE_LINK_SPEED_2500 0x1
76 #define FM10K_PCIE_LINK_SPEED_5000 0x2
77 #define FM10K_PCIE_LINK_SPEED_8000 0x3
79 /* PCIe payload size */
80 #define FM10K_PCIE_DEV_CAP 0x74
81 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
82 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
83 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
84 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
85 #define FM10K_PCIE_DEV_CTRL 0x78
86 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
87 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
88 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
89 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
91 /* PCIe MSI-X Capability info */
92 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2
93 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
94 #define FM10K_MAX_MSIX_VECTORS 256
95 #define FM10K_MAX_VECTORS_PF 256
96 #define FM10K_MAX_VECTORS_POOL 32
98 /* PCIe SR-IOV Info */
99 #define FM10K_PCIE_SRIOV_CTRL 0x190
100 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
102 #define FM10K_SUCCESS 0
103 #define FM10K_ERR_DEVICE_NOT_SUPPORTED -1
104 #define FM10K_ERR_PARAM -2
105 #define FM10K_ERR_NO_RESOURCES -3
106 #define FM10K_ERR_REQUESTS_PENDING -4
107 #define FM10K_ERR_RESET_REQUESTED -5
108 #define FM10K_ERR_DMA_PENDING -6
109 #define FM10K_ERR_RESET_FAILED -7
110 #define FM10K_ERR_INVALID_MAC_ADDR -8
111 #define FM10K_ERR_INVALID_VALUE -9
112 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
114 #define UNREFERENCED_XPARAMETER
115 #define UNREFERENCED_1PARAMETER(_p) (_p)
116 #define UNREFERENCED_2PARAMETER(_p, _q) do { (_p); (_q); } while (0)
117 #define UNREFERENCED_3PARAMETER(_p, _q, _r) do { (_p); (_q); (_r); } while (0)
119 /* Start of PF registers */
120 #define FM10K_CTRL 0x0000
121 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004
123 #define FM10K_CTRL_EXT 0x0001
124 #define FM10K_GCR 0x0003
125 #define FM10K_GCR_EXT 0x0005
127 /* Interrupt control registers */
128 #define FM10K_EICR 0x0006
129 #define FM10K_EICR_PCA_FAULT 0x00000001
130 #define FM10K_EICR_THI_FAULT 0x00000004
131 #define FM10K_EICR_FUM_FAULT 0x00000020
132 #define FM10K_EICR_FAULT_MASK 0x0000003F
133 #define FM10K_EICR_MAILBOX 0x00000040
134 #define FM10K_EICR_SWITCHREADY 0x00000080
135 #define FM10K_EICR_SWITCHNOTREADY 0x00000100
136 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200
137 #define FM10K_EICR_SRAMERROR 0x00000400
138 #define FM10K_EICR_VFLR 0x00000800
139 #define FM10K_EICR_MAXHOLDTIME 0x00001000
140 #define FM10K_EIMR 0x0007
141 #define FM10K_EIMR_PCA_FAULT 0x00000001
142 #define FM10K_EIMR_THI_FAULT 0x00000010
143 #define FM10K_EIMR_FUM_FAULT 0x00000400
144 #define FM10K_EIMR_MAILBOX 0x00001000
145 #define FM10K_EIMR_SWITCHREADY 0x00004000
146 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000
147 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
148 #define FM10K_EIMR_SRAMERROR 0x00100000
149 #define FM10K_EIMR_VFLR 0x00400000
150 #define FM10K_EIMR_MAXHOLDTIME 0x01000000
151 #define FM10K_EIMR_ALL 0x55555555
152 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
153 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
154 #define FM10K_FAULT_ADDR_LO 0x0
155 #define FM10K_FAULT_ADDR_HI 0x1
156 #define FM10K_FAULT_SPECINFO 0x2
157 #define FM10K_FAULT_FUNC 0x3
158 #define FM10K_FAULT_SIZE 0x4
159 #define FM10K_FAULT_FUNC_VALID 0x00008000
160 #define FM10K_FAULT_FUNC_PF 0x00004000
161 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
162 #define FM10K_FAULT_FUNC_VF_SHIFT 8
163 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
165 #define FM10K_PCA_FAULT 0x0008
166 #define FM10K_THI_FAULT 0x0010
167 #define FM10K_FUM_FAULT 0x001C
169 /* Rx queue timeout indicator */
170 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
172 /* Switch Manager info */
173 #define FM10K_SM_AREA(_n) ((_n) + 0x0028)
175 /* GLORT mapping registers */
176 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
177 #define FM10K_DGLORT_COUNT 8
178 #define FM10K_DGLORTMAP_MASK_SHIFT 16
179 #define FM10K_DGLORTMAP_ANY 0x00000000
180 #define FM10K_DGLORTMAP_NONE 0x0000FFFF
181 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000
182 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
183 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
184 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
185 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
186 #define FM10K_DGLORTDEC_QBASE_SHIFT 16
187 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
188 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
189 #define FM10K_TUNNEL_CFG 0x0040
190 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
191 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
192 #define FM10K_SWPRI_MAX 16
193 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
194 #define FM10K_RSSRK_SIZE 10
195 #define FM10K_RSSRK_ENTRIES_PER_REG 4
196 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
197 #define FM10K_RETA_SIZE 32
198 #define FM10K_RETA_ENTRIES_PER_REG 4
199 #define FM10K_MAX_RSS_INDICES 128
201 /* Rate limiting registers */
202 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
203 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
204 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
205 #define FM10K_TC_MAXCREDIT_64K 0x00010000
206 #define FM10K_TC_RATE(_n) ((_n) + 0x2080)
207 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
208 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
209 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
210 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
212 /* DMA control registers */
213 #define FM10K_DMA_CTRL 0x20C3
214 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
215 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
216 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
217 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
218 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
219 #define FM10K_DMA_CTRL_MINMSS_SHIFT 9
220 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000
221 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
222 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
223 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
224 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
225 #define FM10K_DMA_CTRL_32_DESC 0x00000000
227 #define FM10K_DMA_CTRL2 0x20C4
228 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
230 /* TSO flags configuration
231 * First packet contains all flags except for fin and psh
232 * Middle packet contains only urg and ack
233 * Last packet contains urg, ack, fin, and psh
235 #define FM10K_TSO_FLAGS_LOW 0x00300FF6
236 #define FM10K_TSO_FLAGS_HI 0x00000039
237 #define FM10K_DTXTCPFLGL 0x20C5
238 #define FM10K_DTXTCPFLGH 0x20C6
240 #define FM10K_TPH_CTRL 0x20C7
241 #define FM10K_MRQC(_n) ((_n) + 0x2100)
242 #define FM10K_MRQC_TCP_IPV4 0x00000001
243 #define FM10K_MRQC_IPV4 0x00000002
244 #define FM10K_MRQC_IPV6 0x00000010
245 #define FM10K_MRQC_TCP_IPV6 0x00000020
246 #define FM10K_MRQC_UDP_IPV4 0x00000040
247 #define FM10K_MRQC_UDP_IPV6 0x00000080
249 #define FM10K_TQMAP(_n) ((_n) + 0x2800)
250 #define FM10K_TQMAP_TABLE_SIZE 2048
251 #define FM10K_RQMAP(_n) ((_n) + 0x3000)
253 /* Hardware Statistics */
254 #define FM10K_STATS_TIMEOUT 0x3800
255 #define FM10K_STATS_UR 0x3801
256 #define FM10K_STATS_CA 0x3802
257 #define FM10K_STATS_UM 0x3803
258 #define FM10K_STATS_XEC 0x3804
259 #define FM10K_STATS_VLAN_DROP 0x3805
260 #define FM10K_STATS_LOOPBACK_DROP 0x3806
261 #define FM10K_STATS_NODESC_DROP 0x3807
263 /* Timesync registers */
264 #define FM10K_SYSTIME 0x3814
265 #define FM10K_SYSTIME_CFG 0x3818
266 #define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F
268 /* PCIe state registers */
269 #define FM10K_PHYADDR 0x381C
271 /* Rx ring registers */
272 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000)
273 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001)
274 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002)
275 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003)
276 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020
277 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200
278 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000
279 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000
280 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004)
281 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005)
282 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006)
283 #define FM10K_RXQCTL_ENABLE 0x00000001
284 #define FM10K_RXQCTL_PF 0x000000FC
285 #define FM10K_RXQCTL_VF_SHIFT 2
286 #define FM10K_RXQCTL_VF 0x00000100
287 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
288 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007)
289 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001
290 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200
291 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008)
292 #define FM10K_RXINT_TIMER_SHIFT 8
293 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009)
294 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */
295 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000
296 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000
299 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A)
300 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B)
301 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C)
302 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D)
304 /* Rx GLORT register */
305 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E)
307 /* Tx ring registers */
308 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000)
309 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001)
310 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002)
311 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR)
312 * scale which is based on the PCIe speed but the speed information in the PCI
313 * configuration space may not be accurate. The PF already knows the ITR scale
314 * but there is no defined method to pass that information from the PF to the
315 * VF. This is accomplished during VF initialization by temporarily co-opting
316 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for
317 * the VF to retrieve before the VF needs to use the TDLEN register for its
318 * intended purpose, i.e. before the Tx resources are allocated.
320 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9
321 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00
322 #define FM10K_TDLEN_ITR_SCALE_GEN1 2
323 #define FM10K_TDLEN_ITR_SCALE_GEN2 1
324 #define FM10K_TDLEN_ITR_SCALE_GEN3 0
325 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003)
326 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020
327 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200
328 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800
329 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000
330 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004)
331 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005)
332 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006)
333 #define FM10K_TXDCTL_ENABLE 0x00004000
334 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16
335 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007)
336 #define FM10K_TXQCTL_PF 0x0000003F
337 #define FM10K_TXQCTL_VF 0x00000040
338 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
339 #define FM10K_TXQCTL_PC_SHIFT 7
340 #define FM10K_TXQCTL_PC_MASK 0x00000380
341 #define FM10K_TXQCTL_TC_SHIFT 10
342 #define FM10K_TXQCTL_VID_SHIFT 16
343 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000
344 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000
345 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008)
346 #define FM10K_TXINT_TIMER_SHIFT 8
349 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009)
350 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A)
351 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B)
353 /* Tx Push registers */
354 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C)
355 #define FM10K_TQDLOC_BASE_32_DESC 0x08
356 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000
358 /* Tx GLORT registers */
359 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D)
360 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E)
361 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001
363 /* Interrupt moderation and control registers */
364 #define FM10K_INT_MAP(_n) ((_n) + 0x10080)
365 #define FM10K_INT_MAP_TIMER0 0x00000000
366 #define FM10K_INT_MAP_TIMER1 0x00000100
367 #define FM10K_INT_MAP_IMMEDIATE 0x00000200
368 #define FM10K_INT_MAP_DISABLE 0x00000300
369 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003)
370 #define FM10K_INT_CTRL 0x12000
371 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400
372 #define FM10K_ITR(_n) ((_n) + 0x12400)
373 #define FM10K_ITR_INTERVAL1_SHIFT 12
374 #define FM10K_ITR_PENDING2 0x10000000
375 #define FM10K_ITR_AUTOMASK 0x20000000
376 #define FM10K_ITR_MASK_SET 0x40000000
377 #define FM10K_ITR_MASK_CLEAR 0x80000000
378 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800)
379 #define FM10K_ITR_REG_COUNT 768
380 #define FM10K_ITR_REG_COUNT_PF 256
382 /* Switch manager interrupt registers */
383 #define FM10K_IP 0x13000
384 #define FM10K_IP_NOTINRESET 0x00000100
385 #define FM10K_SRAM_IP 0x13003
388 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000)
389 #define FM10K_VLAN_TABLE_SIZE 128
391 /* VLAN specific message offsets */
392 #define FM10K_VLAN_TABLE_VID_MAX 4096
393 #define FM10K_VLAN_TABLE_VSI_MAX 64
394 #define FM10K_VLAN_LENGTH_SHIFT 16
395 #define FM10K_VLAN_CLEAR BIT(15)
396 #define FM10K_VLAN_OVERRIDE FM10K_VLAN_CLEAR
397 #define FM10K_VLAN_ALL \
398 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
400 /* VF FLR event notification registers */
401 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844)
402 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846)
404 /* Defines for size of uncacheable and write-combining memories */
405 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */
406 #define FM10K_WC_ADDR_START 0x100000 /* start of Tx Desc Cache */
407 #define FM10K_DBI_ADDR_START 0x200000 /* start of debug registers */
408 #define FM10K_UC_ADDR_SIZE (FM10K_WC_ADDR_START - FM10K_UC_ADDR_START)
409 #define FM10K_WC_ADDR_SIZE (FM10K_DBI_ADDR_START - FM10K_WC_ADDR_START)
411 /* Define timeouts for resets and disables */
412 #define FM10K_QUEUE_DISABLE_TIMEOUT 100
413 #define FM10K_RESET_TIMEOUT 150
415 /* Maximum supported combined inner and outer header length for encapsulation */
416 #define FM10K_TUNNEL_HEADER_LENGTH 184
419 #define FM10K_VFCTRL 0x00000
420 #define FM10K_VFCTRL_RST 0x00000008
421 #define FM10K_VFINT_MAP 0x00030
422 #define FM10K_VFSYSTIME 0x00040
423 #define FM10K_VFITR(_n) ((_n) + 0x00060)
425 /* Registers contained in BAR 4 for Switch management */
426 #define FM10K_SW_SYSTIME_ADJUST 0x0224D
427 #define FM10K_SW_SYSTIME_ADJUST_MASK 0x3FFFFFFF
428 #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE 0x80000000
429 #define FM10K_SW_SYSTIME_PULSE(_n) ((_n) + 0x02252)
433 #endif /* ETH_ALEN */
435 #ifndef FM10K_IS_ZERO_ETHER_ADDR
436 /* make certain address is not 0 */
437 #define FM10K_IS_ZERO_ETHER_ADDR(addr) \
438 (!((addr)[0] | (addr)[1] | (addr)[2] | (addr)[3] | (addr)[4] | (addr)[5]))
441 #ifndef FM10K_IS_MULTICAST_ETHER_ADDR
442 #define FM10K_IS_MULTICAST_ETHER_ADDR(addr) ((addr)[0] & 0x1)
445 #ifndef FM10K_IS_VALID_ETHER_ADDR
446 /* make certain address is not multicast or 0 */
447 #define FM10K_IS_VALID_ETHER_ADDR(addr) \
448 (!FM10K_IS_MULTICAST_ETHER_ADDR(addr) && !FM10K_IS_ZERO_ETHER_ADDR(addr))
451 enum fm10k_int_source {
452 fm10k_int_mailbox = 0,
453 fm10k_int_pcie_fault = 1,
454 fm10k_int_switch_up_down = 2,
455 fm10k_int_switch_event = 3,
458 fm10k_int_max_hold_time = 6,
459 fm10k_int_sources_max_pf
462 /* PCIe bus speeds */
463 enum fm10k_bus_speed {
464 fm10k_bus_speed_unknown = 0,
465 fm10k_bus_speed_2500 = 2500,
466 fm10k_bus_speed_5000 = 5000,
467 fm10k_bus_speed_8000 = 8000,
468 fm10k_bus_speed_reserved
471 /* PCIe bus widths */
472 enum fm10k_bus_width {
473 fm10k_bus_width_unknown = 0,
474 fm10k_bus_width_pcie_x1 = 1,
475 fm10k_bus_width_pcie_x2 = 2,
476 fm10k_bus_width_pcie_x4 = 4,
477 fm10k_bus_width_pcie_x8 = 8,
478 fm10k_bus_width_reserved
481 /* PCIe payload sizes */
482 enum fm10k_bus_payload {
483 fm10k_bus_payload_unknown = 0,
484 fm10k_bus_payload_128 = 1,
485 fm10k_bus_payload_256 = 2,
486 fm10k_bus_payload_512 = 3,
487 fm10k_bus_payload_reserved
491 struct fm10k_bus_info {
492 enum fm10k_bus_speed speed;
493 enum fm10k_bus_width width;
494 enum fm10k_bus_payload payload;
497 /* Statistics related declarations */
498 struct fm10k_hw_stat {
504 struct fm10k_hw_stats_q {
505 struct fm10k_hw_stat tx_bytes;
506 struct fm10k_hw_stat tx_packets;
507 #define tx_stats_idx tx_packets.base_h
508 struct fm10k_hw_stat rx_bytes;
509 struct fm10k_hw_stat rx_packets;
510 #define rx_stats_idx rx_packets.base_h
511 struct fm10k_hw_stat rx_drops;
514 struct fm10k_hw_stats {
515 struct fm10k_hw_stat timeout;
516 #define stats_idx timeout.base_h
517 struct fm10k_hw_stat ur;
518 struct fm10k_hw_stat ca;
519 struct fm10k_hw_stat um;
520 struct fm10k_hw_stat xec;
521 struct fm10k_hw_stat vlan_drop;
522 struct fm10k_hw_stat loopback_drop;
523 struct fm10k_hw_stat nodesc_drop;
524 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];
527 /* Establish DGLORT feature priority */
528 enum fm10k_dglortdec_idx {
529 fm10k_dglort_default = 0,
530 fm10k_dglort_vf_rsvd0 = 1,
531 fm10k_dglort_vf_rss = 2,
532 fm10k_dglort_pf_rsvd0 = 3,
533 fm10k_dglort_pf_queue = 4,
534 fm10k_dglort_pf_vsi = 5,
535 fm10k_dglort_pf_rsvd1 = 6,
536 fm10k_dglort_pf_rss = 7
539 struct fm10k_dglort_cfg {
540 u16 glort; /* GLORT base */
541 u16 queue_b; /* Base value for queue */
542 u8 vsi_b; /* Base value for VSI */
543 u8 idx; /* index of DGLORTDEC entry */
544 u8 rss_l; /* RSS indices */
545 u8 pc_l; /* Priority Class indices */
546 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */
547 u8 queue_l; /* Number of bits from GLORT used to determine queue */
548 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */
549 u8 inner_rss; /* Boolean value if inner header is used for RSS */
552 enum fm10k_pca_fault {
563 enum fm10k_thi_fault {
569 enum fm10k_fum_fault {
586 u64 address; /* Address at the time fault was detected */
587 u32 specinfo; /* Extra info on this fault (fault dependent) */
588 u8 type; /* Fault value dependent on subunit */
589 u8 func; /* Function number of the fault */
592 struct fm10k_mac_ops {
593 /* basic bring-up and tear-down */
594 s32 (*reset_hw)(struct fm10k_hw *);
595 s32 (*init_hw)(struct fm10k_hw *);
596 s32 (*start_hw)(struct fm10k_hw *);
597 s32 (*stop_hw)(struct fm10k_hw *);
598 s32 (*get_bus_info)(struct fm10k_hw *);
599 s32 (*get_host_state)(struct fm10k_hw *, bool *);
600 s32 (*request_lport_map)(struct fm10k_hw *);
601 #ifndef NO_IS_SLOT_APPROPRIATE_CHECK
602 bool (*is_slot_appropriate)(struct fm10k_hw *);
604 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);
605 s32 (*read_mac_addr)(struct fm10k_hw *);
606 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,
608 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);
609 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);
610 void (*update_int_moderator)(struct fm10k_hw *);
611 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);
612 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
613 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
614 s32 (*configure_dglort_map)(struct fm10k_hw *,
615 struct fm10k_dglort_cfg *);
616 void (*set_dma_mask)(struct fm10k_hw *, u64);
617 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);
618 s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb);
619 s32 (*notify_offset)(struct fm10k_hw *, u64 offset);
620 u64 (*read_systime)(struct fm10k_hw *);
623 enum fm10k_mac_type {
624 fm10k_mac_unknown = 0,
630 struct fm10k_mac_info {
631 struct fm10k_mac_ops ops;
632 enum fm10k_mac_type type;
634 u8 perm_addr[ETH_ALEN];
636 u16 max_msix_vectors;
645 struct fm10k_swapi_table_info {
650 struct fm10k_swapi_info {
652 struct fm10k_swapi_table_info mac;
653 struct fm10k_swapi_table_info nexthop;
654 struct fm10k_swapi_table_info ffu;
657 enum fm10k_xcast_modes {
658 FM10K_XCAST_MODE_ALLMULTI = 0,
659 FM10K_XCAST_MODE_MULTI = 1,
660 FM10K_XCAST_MODE_PROMISC = 2,
661 FM10K_XCAST_MODE_NONE = 3,
662 FM10K_XCAST_MODE_DISABLE = 4
665 enum fm10k_timestamp_modes {
666 FM10K_TIMESTAMP_MODE_NONE = 0,
667 FM10K_TIMESTAMP_MODE_PEP_TO_PEP = 1,
668 FM10K_TIMESTAMP_MODE_PEP_TO_ANY = 2,
671 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */
672 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */
674 struct fm10k_vf_info {
675 /* mbx must be first field in struct unless all default IOV message
676 * handlers are redone as the assumption is that vf_info starts
677 * at the same offset as the mailbox
679 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */
680 int rate; /* Tx BW cap as defined by OS */
681 u16 glort; /* resource tag for this VF */
682 u16 sw_vid; /* Switch API assigned VLAN */
683 u16 pf_vid; /* PF assigned Default VLAN */
684 u8 mac[ETH_ALEN]; /* PF Default MAC address */
685 u8 vsi; /* VSI identifier */
686 u8 vf_idx; /* which VF this is */
687 u8 vf_flags; /* flags indicating what modes
688 * are supported for the port
690 #ifndef NO_FM10K_VF_TRUSTED_MODE
691 bool trusted; /* VF trust mode */
695 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI))
696 #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI))
697 #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC))
698 #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE))
699 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF)
700 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4)
701 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode))
702 #define FM10K_VF_FLAG_SET_MODE_NONE \
703 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
704 #define FM10K_VF_FLAG_MULTI_ENABLED \
705 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \
706 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \
707 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))
709 struct fm10k_iov_ops {
710 /* IOV related bring-up and tear-down */
711 s32 (*assign_resources)(struct fm10k_hw *, u16, u16);
712 s32 (*configure_tc)(struct fm10k_hw *, u16, int);
713 s32 (*assign_int_moderator)(struct fm10k_hw *, u16);
714 s32 (*assign_default_mac_vlan)(struct fm10k_hw *,
715 struct fm10k_vf_info *);
716 s32 (*reset_resources)(struct fm10k_hw *,
717 struct fm10k_vf_info *);
718 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8);
719 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *);
720 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16);
721 void (*notify_offset)(struct fm10k_hw *, struct fm10k_vf_info*, u64);
724 struct fm10k_iov_info {
725 struct fm10k_iov_ops ops;
735 struct fm10k_mac_info mac;
736 struct fm10k_bus_info bus;
737 struct fm10k_bus_info bus_caps;
738 struct fm10k_iov_info iov;
739 struct fm10k_mbx_info mbx;
740 struct fm10k_swapi_info swapi;
743 u16 subsystem_device_id;
744 u16 subsystem_vendor_id;
747 #define FM10K_HW_FLAG_CLOCK_OWNER BIT(0)
750 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
751 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8
752 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8
754 /* Transmit Descriptor */
755 struct fm10k_tx_desc {
756 __le64 buffer_addr; /* Address of the descriptor's data buffer */
757 __le16 buflen; /* Length of data to be DMAed */
758 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */
759 __le16 mss; /* MSS for segmentation offload */
760 u8 hdrlen; /* Header size for segmentation offload */
761 u8 flags; /* Status and offload request flags */
764 /* Transmit Descriptor Cache Structure */
765 struct fm10k_tx_desc_cache {
766 struct fm10k_tx_desc tx_desc[256];
769 #define FM10K_TXD_FLAG_INT 0x01
770 #define FM10K_TXD_FLAG_TIME 0x02
771 #define FM10K_TXD_FLAG_CSUM 0x04
772 #define FM10K_TXD_FLAG_FTAG 0x10
773 #define FM10K_TXD_FLAG_RS 0x20
774 #define FM10K_TXD_FLAG_LAST 0x40
775 #define FM10K_TXD_FLAG_DONE 0x80
778 /* These macros are meant to enable optimal placement of the RS and INT
779 * bits. It will point us to the last descriptor in the cache for either the
780 * start of the packet, or the end of the packet. If the index is actually
781 * at the start of the FIFO it will point to the offset for the last index
782 * in the FIFO to prevent an unnecessary write.
784 #define FM10K_TXD_WB_FIFO_SIZE 4
786 /* Receive Descriptor - 32B */
787 union fm10k_rx_desc {
789 __le64 pkt_addr; /* Packet buffer address */
790 __le64 hdr_addr; /* Header buffer address */
791 __le64 reserved; /* Empty space, RSS hash */
793 } q; /* Read, Writeback, 64b quad-words */
795 __le32 data; /* RSS and header data */
796 __le32 rss; /* RSS Hash */
799 __le32 glort; /* sglort/dglort */
800 } d; /* Writeback, 32b double-words */
802 __le16 pkt_info; /* RSS, Pkt type */
803 __le16 hdr_info; /* Splithdr, hdrlen, xC */
806 __le16 status; /* status/error */
807 __le16 csum_err; /* checksum or extended error value */
808 __le16 length; /* Packet length */
809 __le16 vlan; /* VLAN tag */
812 } w; /* Writeback, 16b words */
815 #define FM10K_RXD_RSSTYPE_MASK 0x000F
816 enum fm10k_rdesc_rss_type {
817 FM10K_RSSTYPE_NONE = 0x0,
818 FM10K_RSSTYPE_IPV4_TCP = 0x1,
819 FM10K_RSSTYPE_IPV4 = 0x2,
820 FM10K_RSSTYPE_IPV6_TCP = 0x3,
822 FM10K_RSSTYPE_IPV6 = 0x5,
824 FM10K_RSSTYPE_IPV4_UDP = 0x7,
825 FM10K_RSSTYPE_IPV6_UDP = 0x8
826 /* Reserved 0x9 - 0xF */
829 #define FM10K_RXD_PKTTYPE_MASK 0x03F0
830 #define FM10K_RXD_PKTTYPE_SHIFT 4
831 enum fm10k_rdesc_pkt_type {
833 FM10K_PKTTYPE_OTHER = 0x00,
834 FM10K_PKTTYPE_IPV4 = 0x01,
835 FM10K_PKTTYPE_IPV4_EX = 0x02,
836 FM10K_PKTTYPE_IPV6 = 0x03,
837 FM10K_PKTTYPE_IPV6_EX = 0x04,
840 FM10K_PKTTYPE_TCP = 0x08,
841 FM10K_PKTTYPE_UDP = 0x10,
842 FM10K_PKTTYPE_GRE = 0x18,
843 FM10K_PKTTYPE_VXLAN = 0x20,
844 FM10K_PKTTYPE_NVGRE = 0x28,
845 FM10K_PKTTYPE_GENEVE = 0x30
848 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006
849 enum fm10k_rxdesc_xc {
850 FM10K_XC_UNICAST = 0x0,
851 FM10K_XC_MULTICAST = 0x4,
852 FM10K_XC_BROADCAST = 0x6
856 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */
857 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */
858 #define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */
859 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */
860 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */
861 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */
862 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */
863 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */
864 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */
865 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */
867 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */
868 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */
869 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */
870 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */
871 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */
875 __be16 swpri_type_user;
881 #endif /* _FM10K_TYPE_H */