1 /*******************************************************************************
3 Copyright (c) 2013 - 2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #ifndef _FM10K_TYPE_H_
35 #define _FM10K_TYPE_H_
37 /* forward declaration */
40 #include "fm10k_osdep.h"
41 #include "fm10k_mbx.h"
43 #define FM10K_INTEL_VENDOR_ID 0x8086
44 #define FM10K_DEV_ID_PF 0x15A4
45 #define FM10K_DEV_ID_VF 0x15A5
46 #ifdef BOULDER_RAPIDS_HW
47 #define FM10K_DEV_ID_SDI_FM10420_QDA2 0x15D0
48 #endif /* BOULDER_RAPIDS_HW */
49 #ifdef ATWOOD_CHANNEL_HW
50 #define FM10K_DEV_ID_SDI_FM10420_DA2 0x15D5
51 #endif /* ATWOOD_CHANNEL_HW */
53 #define FM10K_MAX_QUEUES 256
54 #define FM10K_MAX_QUEUES_PF 128
55 #define FM10K_MAX_QUEUES_POOL 16
57 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
58 #define FM10K_STAT_VALID 0x80000000
61 #define FM10K_PCIE_LINK_CAP 0x7C
62 #define FM10K_PCIE_LINK_STATUS 0x82
63 #define FM10K_PCIE_LINK_WIDTH 0x3F0
64 #define FM10K_PCIE_LINK_WIDTH_1 0x10
65 #define FM10K_PCIE_LINK_WIDTH_2 0x20
66 #define FM10K_PCIE_LINK_WIDTH_4 0x40
67 #define FM10K_PCIE_LINK_WIDTH_8 0x80
68 #define FM10K_PCIE_LINK_SPEED 0xF
69 #define FM10K_PCIE_LINK_SPEED_2500 0x1
70 #define FM10K_PCIE_LINK_SPEED_5000 0x2
71 #define FM10K_PCIE_LINK_SPEED_8000 0x3
73 /* PCIe payload size */
74 #define FM10K_PCIE_DEV_CAP 0x74
75 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
76 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
77 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
78 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
79 #define FM10K_PCIE_DEV_CTRL 0x78
80 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
81 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
82 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
83 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
85 /* PCIe MSI-X Capability info */
86 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2
87 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
88 #define FM10K_MAX_MSIX_VECTORS 256
89 #define FM10K_MAX_VECTORS_PF 256
90 #define FM10K_MAX_VECTORS_POOL 32
92 /* PCIe SR-IOV Info */
93 #define FM10K_PCIE_SRIOV_CTRL 0x190
94 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
96 #define FM10K_SUCCESS 0
97 #define FM10K_ERR_DEVICE_NOT_SUPPORTED -1
98 #define FM10K_ERR_PARAM -2
99 #define FM10K_ERR_NO_RESOURCES -3
100 #define FM10K_ERR_REQUESTS_PENDING -4
101 #define FM10K_ERR_RESET_REQUESTED -5
102 #define FM10K_ERR_DMA_PENDING -6
103 #define FM10K_ERR_RESET_FAILED -7
104 #define FM10K_ERR_INVALID_MAC_ADDR -8
105 #define FM10K_ERR_INVALID_VALUE -9
106 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
108 #define UNREFERENCED_XPARAMETER
109 #define UNREFERENCED_1PARAMETER(_p) (_p)
110 #define UNREFERENCED_2PARAMETER(_p, _q) do { (_p); (_q); } while (0)
111 #define UNREFERENCED_3PARAMETER(_p, _q, _r) do { (_p); (_q); (_r); } while (0)
113 /* Start of PF registers */
114 #define FM10K_CTRL 0x0000
115 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004
117 #define FM10K_CTRL_EXT 0x0001
118 #define FM10K_CTRL_EXT_NS_DIS 0x00000001
119 #define FM10K_CTRL_EXT_RO_DIS 0x00000002
120 #define FM10K_CTRL_EXT_SWITCH_LOOPBACK 0x00000004
121 #define FM10K_EXVET 0x0002
122 #define FM10K_EXVET_ETHERTYPE_MASK 0x000000FF
123 #define FM10K_EXVET_TAG_SIZE_SHIFT 16
124 #define FM10K_EXVET_AFTER_VLAN 0x00040000
125 #define FM10K_GCR 0x0003
126 #define FM10K_FACTPS 0x0004
127 #define FM10K_GCR_EXT 0x0005
129 /* Interrupt control registers */
130 #define FM10K_EICR 0x0006
131 #define FM10K_EICR_PCA_FAULT 0x00000001
132 #define FM10K_EICR_THI_FAULT 0x00000004
133 #define FM10K_EICR_FUM_FAULT 0x00000020
134 #define FM10K_EICR_FAULT_MASK 0x0000003F
135 #define FM10K_EICR_MAILBOX 0x00000040
136 #define FM10K_EICR_SWITCHREADY 0x00000080
137 #define FM10K_EICR_SWITCHNOTREADY 0x00000100
138 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200
139 #define FM10K_EICR_SRAMERROR 0x00000400
140 #define FM10K_EICR_VFLR 0x00000800
141 #define FM10K_EICR_MAXHOLDTIME 0x00001000
142 #define FM10K_EIMR 0x0007
143 #define FM10K_EIMR_PCA_FAULT 0x00000001
144 #define FM10K_EIMR_THI_FAULT 0x00000010
145 #define FM10K_EIMR_FUM_FAULT 0x00000400
146 #define FM10K_EIMR_MAILBOX 0x00001000
147 #define FM10K_EIMR_SWITCHREADY 0x00004000
148 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000
149 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
150 #define FM10K_EIMR_SRAMERROR 0x00100000
151 #define FM10K_EIMR_VFLR 0x00400000
152 #define FM10K_EIMR_MAXHOLDTIME 0x01000000
153 #define FM10K_EIMR_ALL 0x55555555
154 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
155 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
156 #define FM10K_FAULT_ADDR_LO 0x0
157 #define FM10K_FAULT_ADDR_HI 0x1
158 #define FM10K_FAULT_SPECINFO 0x2
159 #define FM10K_FAULT_FUNC 0x3
160 #define FM10K_FAULT_SIZE 0x4
161 #define FM10K_FAULT_FUNC_VALID 0x00008000
162 #define FM10K_FAULT_FUNC_PF 0x00004000
163 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
164 #define FM10K_FAULT_FUNC_VF_SHIFT 8
165 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
167 #define FM10K_PCA_FAULT 0x0008
168 #define FM10K_THI_FAULT 0x0010
169 #define FM10K_FUM_FAULT 0x001C
171 /* Rx queue timeout indicator */
172 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
174 /* Switch Manager info */
175 #define FM10K_SM_AREA(_n) ((_n) + 0x0028)
177 /* GLORT mapping registers */
178 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
179 #define FM10K_DGLORT_COUNT 8
180 #define FM10K_DGLORTMAP_MASK_SHIFT 16
181 #define FM10K_DGLORTMAP_ANY 0x00000000
182 #define FM10K_DGLORTMAP_NONE 0x0000FFFF
183 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000
184 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
185 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
186 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
187 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
188 #define FM10K_DGLORTDEC_QBASE_SHIFT 16
189 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
190 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
191 #define FM10K_TUNNEL_CFG 0x0040
192 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
193 #define FM10K_TUNNEL_CFG_GENEVE 0x0041
194 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
195 #define FM10K_SWPRI_MAX 16
196 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
197 #define FM10K_RSSRK_SIZE 10
198 #define FM10K_RSSRK_ENTRIES_PER_REG 4
199 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
200 #define FM10K_RETA_SIZE 32
201 #define FM10K_RETA_ENTRIES_PER_REG 4
202 #define FM10K_MAX_RSS_INDICES 128
204 /* Rate limiting registers */
205 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
206 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
207 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
208 #define FM10K_TC_MAXCREDIT_64K 0x00010000
209 #define FM10K_TC_RATE(_n) ((_n) + 0x2080)
210 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
211 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
212 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
213 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
214 #define FM10K_TC_RATE_STATUS 0x20C0
215 #define FM10K_PAUSE 0x20C2
217 /* DMA control registers */
218 #define FM10K_DMA_CTRL 0x20C3
219 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
220 #define FM10K_DMA_CTRL_TX_HOST_PENDING 0x00000002
221 #define FM10K_DMA_CTRL_TX_DATA 0x00000004
222 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
223 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
224 #define FM10K_DMA_CTRL_RX_HOST_PENDING 0x00000020
225 #define FM10K_DMA_CTRL_RX_DATA 0x00000040
226 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
227 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
228 #define FM10K_DMA_CTRL_MINMSS_SHIFT 9
229 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000
230 #define FM10K_DMA_CTRL_MAX_HOLD_TIME_SHIFT 23
231 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
232 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
233 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
234 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
235 #define FM10K_DMA_CTRL_MAXNUMOFQ_MASK 0xC0000000
236 #define FM10K_DMA_CTRL_32_DESC 0x00000000
237 #define FM10K_DMA_CTRL_64_DESC 0x40000000
238 #define FM10K_DMA_CTRL_128_DESC 0x80000000
240 #define FM10K_DMA_CTRL2 0x20C4
241 #define FM10K_DMA_CTRL2_TX_FRAME_SPACING_SHIFT 5
242 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
243 #define FM10K_DMA_CTRL2_RX_DESC_READ_PRIO_SHIFT 14
244 #define FM10K_DMA_CTRL2_TX_DESC_READ_PRIO_SHIFT 17
245 #define FM10K_DMA_CTRL2_TX_DATA_READ_PRIO_SHIFT 20
247 /* TSO flags configuration
248 * First packet contains all flags except for fin and psh
249 * Middle packet contains only urg and ack
250 * Last packet contains urg, ack, fin, and psh
252 #define FM10K_TSO_FLAGS_LOW 0x00300FF6
253 #define FM10K_TSO_FLAGS_HI 0x00000039
254 #define FM10K_DTXTCPFLGL 0x20C5
255 #define FM10K_DTXTCPFLGH 0x20C6
257 #define FM10K_TPH_CTRL 0x20C7
258 #define FM10K_TPH_CTRL_DISABLE_READ_HINT 0x00000080
259 #define FM10K_MRQC(_n) ((_n) + 0x2100)
260 #define FM10K_MRQC_TCP_IPV4 0x00000001
261 #define FM10K_MRQC_IPV4 0x00000002
262 #define FM10K_MRQC_IPV6 0x00000010
263 #define FM10K_MRQC_TCP_IPV6 0x00000020
264 #define FM10K_MRQC_UDP_IPV4 0x00000040
265 #define FM10K_MRQC_UDP_IPV6 0x00000080
267 #define FM10K_TQMAP(_n) ((_n) + 0x2800)
268 #define FM10K_TQMAP_TABLE_SIZE 2048
269 #define FM10K_RQMAP(_n) ((_n) + 0x3000)
270 #define FM10K_RQMAP_TABLE_SIZE 2048
272 /* Hardware Statistics */
273 #define FM10K_STATS_TIMEOUT 0x3800
274 #define FM10K_STATS_UR 0x3801
275 #define FM10K_STATS_CA 0x3802
276 #define FM10K_STATS_UM 0x3803
277 #define FM10K_STATS_XEC 0x3804
278 #define FM10K_STATS_VLAN_DROP 0x3805
279 #define FM10K_STATS_LOOPBACK_DROP 0x3806
280 #define FM10K_STATS_NODESC_DROP 0x3807
282 /* Timesync registers */
283 #define FM10K_RRTIME_CFG 0x3808
284 #define FM10K_RRTIME_LIMIT(_n) ((_n) + 0x380C)
285 #define FM10K_RRTIME_COUNT(_n) ((_n) + 0x3810)
286 #define FM10K_SYSTIME 0x3814
287 #define FM10K_SYSTIME0 0x3816
288 #define FM10K_SYSTIME_CFG 0x3818
289 #define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F
291 /* PCIe state registers */
292 #define FM10K_PFVFBME(_n) ((_n) + 0x381A)
293 #define FM10K_PHYADDR 0x381C
295 /* Rx ring registers */
296 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000)
297 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001)
298 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002)
299 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003)
300 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020
301 #define FM10K_TPH_RXCTRL_HDR_TPHEN 0x00000040
302 #define FM10K_TPH_RXCTRL_DATA_TPHEN 0x00000080
303 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200
304 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000
305 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000
306 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004)
307 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005)
308 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006)
309 #define FM10K_RXQCTL_ENABLE 0x00000001
310 #define FM10K_RXQCTL_PF 0x000000FC
311 #define FM10K_RXQCTL_VF_SHIFT 2
312 #define FM10K_RXQCTL_VF 0x00000100
313 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
314 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007)
315 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001
316 #define FM10K_RXDCTL_WRITE_BACK_IMM 0x00000100
317 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200
318 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008)
319 #define FM10K_RXINT_TIMER_SHIFT 8
320 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009)
321 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */
322 #define FM10K_SRRCTL_BSIZEHDR_SHIFT 2 /* shift _left_ */
323 #define FM10K_SRRCTL_BSIZEHDR_MASK 0x00003F00
324 #define FM10K_SRRCTL_DESCTYPE_HDR_SPLIT 0x00004000
325 #define FM10K_SRRCTL_DESCTYPE_SIZE_SPLIT 0x00008000
326 #define FM10K_SRRCTL_PSRTYPE_INNER_TCPHDR 0x00010000
327 #define FM10K_SRRCTL_PSRTYPE_INNER_UDPHDR 0x00020000
328 #define FM10K_SRRCTL_PSRTYPE_INNER_IPV4HDR 0x00040000
329 #define FM10K_SRRCTL_PSRTYPE_INNER_IPV6HDR 0x00080000
330 #define FM10K_SRRCTL_PSRTYPE_INNER_L2HDR 0x00100000
331 #define FM10K_SRRCTL_PSRTYPE_ENCAPHDR 0x00200000
332 #define FM10K_SRRCTL_PSRTYPE_TCPHDR 0x00400000
333 #define FM10K_SRRCTL_PSRTYPE_UDPHDR 0x00800000
334 #define FM10K_SRRCTL_PSRTYPE_IPV4HDR 0x01000000
335 #define FM10K_SRRCTL_PSRTYPE_IPV6HDR 0x02000000
336 #define FM10K_SRRCTL_PSRTYPE_L2HDR 0x04000000
337 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000
338 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000
341 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A)
342 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B)
343 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C)
344 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D)
346 /* Rx GLORT register */
347 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E)
349 /* Tx ring registers */
350 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000)
351 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001)
352 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002)
353 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR)
354 * scale which is based on the PCIe speed but the speed information in the PCI
355 * configuration space may not be accurate. The PF already knows the ITR scale
356 * but there is no defined method to pass that information from the PF to the
357 * VF. This is accomplished during VF initialization by temporarily co-opting
358 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for
359 * the VF to retrieve before the VF needs to use the TDLEN register for its
360 * intended purpose, i.e. before the Tx resources are allocated.
362 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9
363 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00
364 #define FM10K_TDLEN_ITR_SCALE_GEN1 2
365 #define FM10K_TDLEN_ITR_SCALE_GEN2 1
366 #define FM10K_TDLEN_ITR_SCALE_GEN3 0
367 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003)
368 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020
369 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200
370 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800
371 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000
372 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004)
373 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005)
374 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006)
375 #define FM10K_TXDCTL_ENABLE 0x00004000
376 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16
377 #define FM10K_TXDCTL_PUSH_DESC 0x10000000
378 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007)
379 #define FM10K_TXQCTL_PF 0x0000003F
380 #define FM10K_TXQCTL_VF 0x00000040
381 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
382 #define FM10K_TXQCTL_PC_SHIFT 7
383 #define FM10K_TXQCTL_PC_MASK 0x00000380
384 #define FM10K_TXQCTL_TC_SHIFT 10
385 #define FM10K_TXQCTL_TC_MASK 0x0000FC00
386 #define FM10K_TXQCTL_VID_SHIFT 16
387 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000
388 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000
389 #define FM10K_TXQCTL_PUSHMODEDIS 0x20000000
390 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008)
391 #define FM10K_TXINT_TIMER_SHIFT 8
394 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009)
395 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A)
396 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B)
398 /* Tx Push registers */
399 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C)
400 #define FM10K_TQDLOC_BASE_32_DESC 0x08
401 #define FM10K_TQDLOC_BASE_64_DESC 0x10
402 #define FM10K_TQDLOC_BASE_128_DESC 0x20
403 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000
404 #define FM10K_TQDLOC_SIZE_64_DESC 0x00060000
405 #define FM10K_TQDLOC_SIZE_128_DESC 0x00070000
406 #define FM10K_TQDLOC_SIZE_SHIFT 16
407 #define FM10K_TX_DCACHE(_n, _m) ((0x400 * (_n)) + (0x4 * (_m)) + 0x40000)
409 /* Tx GLORT registers */
410 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D)
411 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E)
412 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001
414 /* Interrupt moderation and control registers */
415 #define FM10K_PBACL(_n) ((_n) + 0x10000)
416 #define FM10K_INT_MAP(_n) ((_n) + 0x10080)
417 #define FM10K_INT_MAP_TIMER0 0x00000000
418 #define FM10K_INT_MAP_TIMER1 0x00000100
419 #define FM10K_INT_MAP_IMMEDIATE 0x00000200
420 #define FM10K_INT_MAP_DISABLE 0x00000300
421 #define FM10K_MSIX_VECTOR_ADDR_LO(_n) ((0x4 * (_n)) + 0x11000)
422 #define FM10K_MSIX_VECTOR_ADDR_HI(_n) ((0x4 * (_n)) + 0x11001)
423 #define FM10K_MSIX_VECTOR_DATA(_n) ((0x4 * (_n)) + 0x11002)
424 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003)
425 #define FM10K_INT_CTRL 0x12000
426 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400
427 #define FM10K_ITR(_n) ((_n) + 0x12400)
428 #define FM10K_ITR_INTERVAL1_SHIFT 12
429 #define FM10K_ITR_TIMER0_EXPIRED 0x01000000
430 #define FM10K_ITR_TIMER1_EXPIRED 0x02000000
431 #define FM10K_ITR_PENDING0 0x04000000
432 #define FM10K_ITR_PENDING1 0x08000000
433 #define FM10K_ITR_PENDING2 0x10000000
434 #define FM10K_ITR_AUTOMASK 0x20000000
435 #define FM10K_ITR_MASK_SET 0x40000000
436 #define FM10K_ITR_MASK_CLEAR 0x80000000
437 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800)
438 #define FM10K_ITR2_LP(_n) ((0x2 * (_n)) + 0x12801)
439 #define FM10K_ITR_REG_COUNT 768
440 #define FM10K_ITR_REG_COUNT_PF 256
442 /* Switch manager interrupt registers */
443 #define FM10K_IP 0x13000
444 #define FM10K_IP_HOT_RESET 0x00000001
445 #define FM10K_IP_DEVICE_STATE_CHANGE 0x00000002
446 #define FM10K_IP_MAILBOX 0x00000004
447 #define FM10K_IP_VPD_REQUEST 0x00000008
448 #define FM10K_IP_SRAMERROR 0x00000010
449 #define FM10K_IP_PFLR 0x00000020
450 #define FM10K_IP_DATAPATHRESET 0x00000040
451 #define FM10K_IP_OUTOFRESET 0x00000080
452 #define FM10K_IP_NOTINRESET 0x00000100
453 #define FM10K_IP_TIMEOUT 0x00000200
454 #define FM10K_IP_VFLR 0x00000400
455 #define FM10K_IM 0x13001
456 #define FM10K_IB 0x13002
457 #define FM10K_SRAM_IP 0x13003
458 #define FM10K_SRAM_IM 0x13004
461 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000)
462 #define FM10K_VLAN_TABLE_SIZE 128
464 /* VLAN specific message offsets */
465 #define FM10K_VLAN_TABLE_VID_MAX 4096
466 #define FM10K_VLAN_TABLE_VSI_MAX 64
467 #define FM10K_VLAN_LENGTH_SHIFT 16
468 #define FM10K_VLAN_CLEAR (1 << 15)
469 #define FM10K_VLAN_ALL \
470 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
472 /* VF FLR event notification registers */
473 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844)
474 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846)
476 /* Defines for size of uncacheable and write-combining memories */
477 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */
478 #define FM10K_WC_ADDR_START 0x100000 /* start of Tx Desc Cache */
479 #define FM10K_DBI_ADDR_START 0x200000 /* start of debug registers */
480 #define FM10K_UC_ADDR_SIZE (FM10K_WC_ADDR_START - FM10K_UC_ADDR_START)
481 #define FM10K_WC_ADDR_SIZE (FM10K_DBI_ADDR_START - FM10K_WC_ADDR_START)
483 /* Define timeouts for resets and disables */
484 #define FM10K_QUEUE_DISABLE_TIMEOUT 100
485 #define FM10K_RESET_TIMEOUT 150
487 /* Maximum supported combined inner and outer header length for encapsulation */
488 #define FM10K_TUNNEL_HEADER_LENGTH 184
491 #define FM10K_VFCTRL 0x00000
492 #define FM10K_VFCTRL_RST 0x00000008
493 #define FM10K_VFINT_MAP 0x00030
494 #define FM10K_VFSYSTIME 0x00040
495 #define FM10K_VFITR(_n) ((_n) + 0x00060)
496 #define FM10K_VFPBACL(_n) ((_n) + 0x00008)
498 /* Registers contained in BAR 4 for Switch management */
499 #define FM10K_SW_SYSTIME_CFG 0x0224C
500 #define FM10K_SW_SYSTIME_CFG_STEP_SHIFT 4
501 #define FM10K_SW_SYSTIME_CFG_ADJUST_MASK 0xFF000000
502 #define FM10K_SW_SYSTIME_ADJUST 0x0224D
503 #define FM10K_SW_SYSTIME_ADJUST_MASK 0x3FFFFFFF
504 #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE 0x80000000
505 #define FM10K_SW_SYSTIME_PULSE(_n) ((_n) + 0x02252)
509 #endif /* ETH_ALEN */
511 #ifndef FM10K_IS_ZERO_ETHER_ADDR
512 /* make certain address is not 0 */
513 #define FM10K_IS_ZERO_ETHER_ADDR(addr) \
514 (!((addr)[0] | (addr)[1] | (addr)[2] | (addr)[3] | (addr)[4] | (addr)[5]))
517 #ifndef FM10K_IS_MULTICAST_ETHER_ADDR
518 #define FM10K_IS_MULTICAST_ETHER_ADDR(addr) ((addr)[0] & 0x1)
521 #ifndef FM10K_IS_VALID_ETHER_ADDR
522 /* make certain address is not multicast or 0 */
523 #define FM10K_IS_VALID_ETHER_ADDR(addr) \
524 (!FM10K_IS_MULTICAST_ETHER_ADDR(addr) && !FM10K_IS_ZERO_ETHER_ADDR(addr))
527 enum fm10k_int_source {
528 fm10k_int_Mailbox = 0,
529 fm10k_int_PCIeFault = 1,
530 fm10k_int_SwitchUpDown = 2,
531 fm10k_int_SwitchEvent = 3,
534 fm10k_int_MaxHoldTime = 6,
535 fm10k_int_sources_max_pf
538 /* PCIe bus speeds */
539 enum fm10k_bus_speed {
540 fm10k_bus_speed_unknown = 0,
541 fm10k_bus_speed_2500 = 2500,
542 fm10k_bus_speed_5000 = 5000,
543 fm10k_bus_speed_8000 = 8000,
544 fm10k_bus_speed_reserved
547 /* PCIe bus widths */
548 enum fm10k_bus_width {
549 fm10k_bus_width_unknown = 0,
550 fm10k_bus_width_pcie_x1 = 1,
551 fm10k_bus_width_pcie_x2 = 2,
552 fm10k_bus_width_pcie_x4 = 4,
553 fm10k_bus_width_pcie_x8 = 8,
554 fm10k_bus_width_reserved
557 /* PCIe payload sizes */
558 enum fm10k_bus_payload {
559 fm10k_bus_payload_unknown = 0,
560 fm10k_bus_payload_128 = 1,
561 fm10k_bus_payload_256 = 2,
562 fm10k_bus_payload_512 = 3,
563 fm10k_bus_payload_reserved
567 struct fm10k_bus_info {
568 enum fm10k_bus_speed speed;
569 enum fm10k_bus_width width;
570 enum fm10k_bus_payload payload;
573 /* Statistics related declarations */
574 struct fm10k_hw_stat {
580 struct fm10k_hw_stats_q {
581 struct fm10k_hw_stat tx_bytes;
582 struct fm10k_hw_stat tx_packets;
583 #define tx_stats_idx tx_packets.base_h
584 struct fm10k_hw_stat rx_bytes;
585 struct fm10k_hw_stat rx_packets;
586 #define rx_stats_idx rx_packets.base_h
587 struct fm10k_hw_stat rx_drops;
590 struct fm10k_hw_stats {
591 struct fm10k_hw_stat timeout;
592 #define stats_idx timeout.base_h
593 struct fm10k_hw_stat ur;
594 struct fm10k_hw_stat ca;
595 struct fm10k_hw_stat um;
596 struct fm10k_hw_stat xec;
597 struct fm10k_hw_stat vlan_drop;
598 struct fm10k_hw_stat loopback_drop;
599 struct fm10k_hw_stat nodesc_drop;
600 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];
603 /* Establish DGLORT feature priority */
604 enum fm10k_dglortdec_idx {
605 fm10k_dglort_default = 0,
606 fm10k_dglort_vf_rsvd0 = 1,
607 fm10k_dglort_vf_rss = 2,
608 fm10k_dglort_pf_rsvd0 = 3,
609 fm10k_dglort_pf_queue = 4,
610 fm10k_dglort_pf_vsi = 5,
611 fm10k_dglort_pf_rsvd1 = 6,
612 fm10k_dglort_pf_rss = 7
615 struct fm10k_dglort_cfg {
616 u16 glort; /* GLORT base */
617 u16 queue_b; /* Base value for queue */
618 u8 vsi_b; /* Base value for VSI */
619 u8 idx; /* index of DGLORTDEC entry */
620 u8 rss_l; /* RSS indices */
621 u8 pc_l; /* Priority Class indices */
622 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */
623 u8 queue_l; /* Number of bits from GLORT used to determine queue */
624 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */
625 u8 inner_rss; /* Boolean value if inner header is used for RSS */
628 enum fm10k_pca_fault {
639 enum fm10k_thi_fault {
645 enum fm10k_fum_fault {
662 u64 address; /* Address at the time fault was detected */
663 u32 specinfo; /* Extra info on this fault (fault dependent) */
664 u8 type; /* Fault value dependent on subunit */
665 u8 func; /* Function number of the fault */
668 struct fm10k_mac_ops {
669 /* basic bring-up and tear-down */
670 s32 (*reset_hw)(struct fm10k_hw *);
671 s32 (*init_hw)(struct fm10k_hw *);
672 s32 (*start_hw)(struct fm10k_hw *);
673 s32 (*stop_hw)(struct fm10k_hw *);
674 s32 (*get_bus_info)(struct fm10k_hw *);
675 s32 (*get_host_state)(struct fm10k_hw *, bool *);
676 bool (*is_slot_appropriate)(struct fm10k_hw *);
677 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);
678 s32 (*read_mac_addr)(struct fm10k_hw *);
679 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,
681 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);
682 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);
683 void (*update_int_moderator)(struct fm10k_hw *);
684 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);
685 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
686 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
687 s32 (*configure_dglort_map)(struct fm10k_hw *,
688 struct fm10k_dglort_cfg *);
689 void (*set_dma_mask)(struct fm10k_hw *, u64);
690 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);
691 void (*request_lport_map)(struct fm10k_hw *);
692 s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb);
693 s32 (*notify_offset)(struct fm10k_hw *, u64 offset);
694 u64 (*read_systime)(struct fm10k_hw *);
697 enum fm10k_mac_type {
698 fm10k_mac_unknown = 0,
704 struct fm10k_mac_info {
705 struct fm10k_mac_ops ops;
706 enum fm10k_mac_type type;
708 u8 perm_addr[ETH_ALEN];
710 u16 max_msix_vectors;
719 struct fm10k_swapi_table_info {
724 struct fm10k_swapi_info {
726 struct fm10k_swapi_table_info mac;
727 struct fm10k_swapi_table_info nexthop;
728 struct fm10k_swapi_table_info ffu;
731 enum fm10k_xcast_modes {
732 FM10K_XCAST_MODE_ALLMULTI = 0,
733 FM10K_XCAST_MODE_MULTI = 1,
734 FM10K_XCAST_MODE_PROMISC = 2,
735 FM10K_XCAST_MODE_NONE = 3,
736 FM10K_XCAST_MODE_DISABLE = 4
739 enum fm10k_timestamp_modes {
740 FM10K_TIMESTAMP_MODE_NONE = 0,
741 FM10K_TIMESTAMP_MODE_PEP_TO_PEP = 1,
742 FM10K_TIMESTAMP_MODE_PEP_TO_ANY = 2,
745 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */
746 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */
748 struct fm10k_vf_info {
749 /* mbx must be first field in struct unless all default IOV message
750 * handlers are redone as the assumption is that vf_info starts
751 * at the same offset as the mailbox
753 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */
754 int rate; /* Tx BW cap as defined by OS */
755 u16 glort; /* resource tag for this VF */
756 u16 sw_vid; /* Switch API assigned VLAN */
757 u16 pf_vid; /* PF assigned Default VLAN */
758 u8 mac[ETH_ALEN]; /* PF Default MAC address */
759 u8 vsi; /* VSI identifier */
760 u8 vf_idx; /* which VF this is */
761 u8 vf_flags; /* flags indicating what modes
762 * are supported for the port
766 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE ((u8)1 << FM10K_XCAST_MODE_ALLMULTI)
767 #define FM10K_VF_FLAG_MULTI_CAPABLE ((u8)1 << FM10K_XCAST_MODE_MULTI)
768 #define FM10K_VF_FLAG_PROMISC_CAPABLE ((u8)1 << FM10K_XCAST_MODE_PROMISC)
769 #define FM10K_VF_FLAG_NONE_CAPABLE ((u8)1 << FM10K_XCAST_MODE_NONE)
770 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF)
771 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4)
772 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode))
773 #define FM10K_VF_FLAG_ENABLED_MODE_SHIFT 4
774 #define FM10K_VF_FLAG_SET_MODE_MASK ((u8)0xF0)
775 #define FM10K_VF_FLAG_SET_MODE_NONE \
776 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
777 #define FM10K_VF_FLAG_MULTI_ENABLED \
778 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \
779 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \
780 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))
782 struct fm10k_iov_ops {
783 /* IOV related bring-up and tear-down */
784 s32 (*assign_resources)(struct fm10k_hw *, u16, u16);
785 s32 (*configure_tc)(struct fm10k_hw *, u16, int);
786 s32 (*assign_int_moderator)(struct fm10k_hw *, u16);
787 s32 (*assign_default_mac_vlan)(struct fm10k_hw *,
788 struct fm10k_vf_info *);
789 s32 (*reset_resources)(struct fm10k_hw *,
790 struct fm10k_vf_info *);
791 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8);
792 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *);
793 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16);
794 void (*notify_offset)(struct fm10k_hw *, struct fm10k_vf_info*, u64);
797 struct fm10k_iov_info {
798 struct fm10k_iov_ops ops;
808 struct fm10k_mac_info mac;
809 struct fm10k_bus_info bus;
810 struct fm10k_bus_info bus_caps;
811 struct fm10k_iov_info iov;
812 struct fm10k_mbx_info mbx;
813 struct fm10k_swapi_info swapi;
816 u16 subsystem_device_id;
817 u16 subsystem_vendor_id;
820 #define FM10K_HW_FLAG_CLOCK_OWNER (u32)(1 << 0)
823 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
824 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8
825 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8
827 /* Transmit Descriptor */
828 struct fm10k_tx_desc {
829 __le64 buffer_addr; /* Address of the descriptor's data buffer */
830 __le16 buflen; /* Length of data to be DMAed */
831 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */
832 __le16 mss; /* MSS for segmentation offload */
833 u8 hdrlen; /* Header size for segmentation offload */
834 u8 flags; /* Status and offload request flags */
837 /* Transmit Descriptor Cache Structure */
838 struct fm10k_tx_desc_cache {
839 struct fm10k_tx_desc tx_desc[256];
842 #define FM10K_TXD_FLAG_INT 0x01
843 #define FM10K_TXD_FLAG_TIME 0x02
844 #define FM10K_TXD_FLAG_CSUM 0x04
845 #define FM10K_TXD_FLAG_CSUM2 0x08
846 #define FM10K_TXD_FLAG_FTAG 0x10
847 #define FM10K_TXD_FLAG_RS 0x20
848 #define FM10K_TXD_FLAG_LAST 0x40
849 #define FM10K_TXD_FLAG_DONE 0x80
851 #define FM10K_TXD_VLAN_PRI_SHIFT 12
853 /* These macros are meant to enable optimal placement of the RS and INT
854 * bits. It will point us to the last descriptor in the cache for either the
855 * start of the packet, or the end of the packet. If the index is actually
856 * at the start of the FIFO it will point to the offset for the last index
857 * in the FIFO to prevent an unnecessary write.
859 #define FM10K_TXD_WB_FIFO_SIZE 4
860 #define FM10K_TXD_WB_IDX(idx) \
861 (((idx) - 1) | (FM10K_TXD_WB_FIFO_SIZE - 1))
863 /* Receive Descriptor - 32B */
864 union fm10k_rx_desc {
866 __le64 pkt_addr; /* Packet buffer address */
867 __le64 hdr_addr; /* Header buffer address */
868 __le64 reserved; /* Empty space, RSS hash */
870 } q; /* Read, Writeback, 64b quad-words */
872 __le32 data; /* RSS and header data */
873 __le32 rss; /* RSS Hash */
876 __le32 glort; /* sglort/dglort */
877 } d; /* Writeback, 32b double-words */
879 __le16 pkt_info; /* RSS, Pkt type */
880 __le16 hdr_info; /* Splithdr, hdrlen, xC */
883 __le16 status; /* status/error */
884 __le16 csum_err; /* checksum or extended error value */
885 __le16 length; /* Packet length */
886 __le16 vlan; /* VLAN tag */
889 } w; /* Writeback, 16b words */
892 #define FM10K_RXD_RSSTYPE_MASK 0x000F
893 enum fm10k_rdesc_rss_type {
894 FM10K_RSSTYPE_NONE = 0x0,
895 FM10K_RSSTYPE_IPV4_TCP = 0x1,
896 FM10K_RSSTYPE_IPV4 = 0x2,
897 FM10K_RSSTYPE_IPV6_TCP = 0x3,
899 FM10K_RSSTYPE_IPV6 = 0x5,
901 FM10K_RSSTYPE_IPV4_UDP = 0x7,
902 FM10K_RSSTYPE_IPV6_UDP = 0x8
903 /* Reserved 0x9 - 0xF */
906 #define FM10K_RXD_PKTTYPE_MASK 0x03F0
907 #define FM10K_RXD_PKTTYPE_MASK_L3 0x0070
908 #define FM10K_RXD_PKTTYPE_MASK_L4 0x0380
909 #define FM10K_RXD_PKTTYPE_SHIFT 4
910 #define FM10K_RXD_PKTTYPE_INNER_MASK_L3 0x1C00
911 #define FM10K_RXD_PKTTYPE_INNER_MASK_L4 0xE000
912 #define FM10K_RXD_PKTTYPE_INNER_SHIFT 10
913 enum fm10k_rdesc_pkt_type {
915 FM10K_PKTTYPE_OTHER = 0x00,
916 FM10K_PKTTYPE_IPV4 = 0x01,
917 FM10K_PKTTYPE_IPV4_EX = 0x02,
918 FM10K_PKTTYPE_IPV6 = 0x03,
919 FM10K_PKTTYPE_IPV6_EX = 0x04,
922 FM10K_PKTTYPE_TCP = 0x08,
923 FM10K_PKTTYPE_UDP = 0x10,
924 FM10K_PKTTYPE_GRE = 0x18,
925 FM10K_PKTTYPE_VXLAN = 0x20,
926 FM10K_PKTTYPE_NVGRE = 0x28,
927 FM10K_PKTTYPE_GENEVE = 0x30
930 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006
931 enum fm10k_rxdesc_xc {
932 FM10K_XC_UNICAST = 0x0,
933 FM10K_XC_MULTICAST = 0x4,
934 FM10K_XC_BROADCAST = 0x6
937 #define FM10K_RXD_HDR_INFO_LEN_SHIFT 5
938 #define FM10K_RXD_HDR_INFO_SPH 0x8000
940 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */
941 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */
942 #define FM10K_RXD_STATUS_VEXT 0x0004 /* A VLAN tag is present */
943 #define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */
944 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */
945 #define FM10K_RXD_STATUS_IPCS2 0x0020 /* Inner header IPv4 csum */
946 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */
947 #define FM10K_RXD_STATUS_IPFRAG_MASK 0x0180 /* Fragment mask */
948 #define FM10K_RXD_STATUS_IPFRAG_CSUM 0x0100 /* Fragment w/ CSUM field */
949 #define FM10K_RXD_STATUS_VEXT2 0x0200 /* A custom tag is present */
950 #define FM10K_RXD_STATUS_HBO 0x0400 /* header buffer overrun */
951 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */
952 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */
953 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */
954 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */
955 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */
957 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */
958 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */
959 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */
960 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */
961 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */
963 #define FM10K_RXD_VLAN_ID_MASK 0x0FFF
964 #define FM10K_RXD_VLAN_PRI_SHIFT FM10K_TXD_VLAN_PRI_SHIFT
967 __be16 swpri_type_user;
973 #endif /* _FM10K_TYPE_H */