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39 #include <rte_mempool.h>
40 #include <rte_malloc.h>
41 #include <rte_spinlock.h>
42 #include "fm10k_logs.h"
43 #include "base/fm10k_type.h"
45 /* descriptor ring base addresses must be aligned to the following */
46 #define FM10K_ALIGN_RX_DESC 128
47 #define FM10K_ALIGN_TX_DESC 128
49 /* The maximum packet size that FM10K supports */
50 #define FM10K_MAX_PKT_SIZE (15 * 1024)
52 /* Minimum size of RX buffer FM10K supported */
53 #define FM10K_MIN_RX_BUF_SIZE 256
55 /* The maximum of SRIOV VFs per port supported */
56 #define FM10K_MAX_VF_NUM 64
58 /* number of descriptors must be a multiple of the following */
59 #define FM10K_MULT_RX_DESC FM10K_REQ_RX_DESCRIPTOR_MULTIPLE
60 #define FM10K_MULT_TX_DESC FM10K_REQ_TX_DESCRIPTOR_MULTIPLE
62 /* maximum size of descriptor rings */
63 #define FM10K_MAX_RX_RING_SZ (512 * 1024)
64 #define FM10K_MAX_TX_RING_SZ (512 * 1024)
66 /* minimum and maximum number of descriptors in a ring */
67 #define FM10K_MIN_RX_DESC 32
68 #define FM10K_MIN_TX_DESC 32
69 #define FM10K_MAX_RX_DESC (FM10K_MAX_RX_RING_SZ / sizeof(union fm10k_rx_desc))
70 #define FM10K_MAX_TX_DESC (FM10K_MAX_TX_RING_SZ / sizeof(struct fm10k_tx_desc))
72 #define FM10K_TX_MAX_SEG UINT8_MAX
73 #define FM10K_TX_MAX_MTU_SEG UINT8_MAX
76 * byte aligment for HW RX data buffer
77 * Datasheet requires RX buffer addresses shall either be 512-byte aligned or
78 * be 8-byte aligned but without crossing host memory pages (4KB alignment
79 * boundaries). Satisfy first option.
81 #define FM10K_RX_DATABUF_ALIGN 512
84 * threshold default, min, max, and divisor constraints
85 * the configured values must satisfy the following:
89 #define FM10K_RX_FREE_THRESH_DEFAULT(rxq) 32
90 #define FM10K_RX_FREE_THRESH_MIN(rxq) 1
91 #define FM10K_RX_FREE_THRESH_MAX(rxq) ((rxq)->nb_desc - 1)
92 #define FM10K_RX_FREE_THRESH_DIV(rxq) ((rxq)->nb_desc)
94 #define FM10K_TX_FREE_THRESH_DEFAULT(txq) 32
95 #define FM10K_TX_FREE_THRESH_MIN(txq) 1
96 #define FM10K_TX_FREE_THRESH_MAX(txq) ((txq)->nb_desc - 3)
97 #define FM10K_TX_FREE_THRESH_DIV(txq) 0
99 #define FM10K_DEFAULT_RX_PTHRESH 8
100 #define FM10K_DEFAULT_RX_HTHRESH 8
101 #define FM10K_DEFAULT_RX_WTHRESH 0
103 #define FM10K_DEFAULT_TX_PTHRESH 32
104 #define FM10K_DEFAULT_TX_HTHRESH 0
105 #define FM10K_DEFAULT_TX_WTHRESH 0
107 #define FM10K_TX_RS_THRESH_DEFAULT(txq) 32
108 #define FM10K_TX_RS_THRESH_MIN(txq) 1
109 #define FM10K_TX_RS_THRESH_MAX(txq) \
110 RTE_MIN(((txq)->nb_desc - 2), (txq)->free_thresh)
111 #define FM10K_TX_RS_THRESH_DIV(txq) ((txq)->nb_desc)
113 #define FM10K_VLAN_TAG_SIZE 4
115 /* Maximum number of MAC addresses per PF/VF */
116 #define FM10K_MAX_MACADDR_NUM 64
118 #define FM10K_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
119 #define FM10K_VFTA_SIZE (4096 / FM10K_UINT32_BIT_SIZE)
121 /* vlan_id is a 12 bit number.
122 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
123 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
124 * The higher 7 bit val specifies VFTA array index.
126 #define FM10K_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
127 #define FM10K_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
129 #define RTE_FM10K_RXQ_REARM_THRESH 32
130 #define RTE_FM10K_VPMD_TX_BURST 32
131 #define RTE_FM10K_MAX_RX_BURST RTE_FM10K_RXQ_REARM_THRESH
132 #define RTE_FM10K_TX_MAX_FREE_BUF_SZ 64
133 #define RTE_FM10K_DESCS_PER_LOOP 4
135 #define FM10K_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
136 #define FM10K_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
138 #define FM10K_SIMPLE_TX_FLAG ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
139 ETH_TXQ_FLAGS_NOOFFLOADS)
141 struct fm10k_macvlan_filter_info {
142 uint16_t vlan_num; /* Total VLAN number */
143 uint16_t mac_num; /* Total mac number */
144 uint16_t nb_queue_pools; /* Active queue pools number */
145 /* VMDQ ID for each MAC address */
146 uint8_t mac_vmdq_id[FM10K_MAX_MACADDR_NUM];
147 uint32_t vfta[FM10K_VFTA_SIZE]; /* VLAN bitmap */
150 struct fm10k_dev_info {
151 volatile uint32_t enable;
152 volatile uint32_t glort;
153 /* Protect the mailbox to avoid race condition */
154 rte_spinlock_t mbx_lock;
155 struct fm10k_macvlan_filter_info macvlan;
156 /* Flag to indicate if RX vector conditions satisfied */
162 * Structure to store private data for each driver instance.
164 struct fm10k_adapter {
166 struct fm10k_hw_stats stats;
167 struct fm10k_dev_info info;
170 #define FM10K_DEV_PRIVATE_TO_HW(adapter) \
171 (&((struct fm10k_adapter *)adapter)->hw)
173 #define FM10K_DEV_PRIVATE_TO_STATS(adapter) \
174 (&((struct fm10k_adapter *)adapter)->stats)
176 #define FM10K_DEV_PRIVATE_TO_INFO(adapter) \
177 (&((struct fm10k_adapter *)adapter)->info)
179 #define FM10K_DEV_PRIVATE_TO_MBXLOCK(adapter) \
180 (&(((struct fm10k_adapter *)adapter)->info.mbx_lock))
182 #define FM10K_DEV_PRIVATE_TO_MACVLAN(adapter) \
183 (&(((struct fm10k_adapter *)adapter)->info.macvlan))
185 struct fm10k_rx_queue {
186 struct rte_mempool *mp;
187 struct rte_mbuf **sw_ring;
188 volatile union fm10k_rx_desc *hw_ring;
189 struct rte_mbuf *pkt_first_seg; /* First segment of current packet. */
190 struct rte_mbuf *pkt_last_seg; /* Last segment of current packet. */
191 uint64_t hw_ring_phys_addr;
192 uint64_t mbuf_initializer; /* value to init mbufs */
193 /* need to alloc dummy mbuf, for wraparound when scanning hw ring */
194 struct rte_mbuf fake_mbuf;
197 uint16_t next_trigger;
198 uint16_t alloc_thresh;
199 volatile uint32_t *tail_ptr;
201 /* Number of faked desc added at the tail for Vector RX function */
202 uint16_t nb_fake_desc;
204 /* Below 2 fields only valid in case vPMD is applied. */
205 uint16_t rxrearm_nb; /* number of remaining to be re-armed */
206 uint16_t rxrearm_start; /* the idx we start the re-arming from */
207 uint16_t rx_using_sse; /* indicates that vector RX is in use */
210 uint8_t rx_deferred_start; /* don't start this queue in dev start. */
211 uint16_t rx_ftag_en; /* indicates FTAG RX supported */
215 * a FIFO is used to track which descriptors have their RS bit set for Tx
216 * queues which are configured to allow multiple descriptors per packet
225 struct fm10k_txq_ops;
227 struct fm10k_tx_queue {
228 struct rte_mbuf **sw_ring;
229 struct fm10k_tx_desc *hw_ring;
230 uint64_t hw_ring_phys_addr;
231 struct fifo rs_tracker;
232 const struct fm10k_txq_ops *ops; /* txq ops */
237 uint16_t free_thresh;
239 /* Below 2 fields only valid in case vPMD is applied. */
240 uint16_t next_rs; /* Next pos to set RS flag */
241 uint16_t next_dd; /* Next pos to check DD flag */
242 volatile uint32_t *tail_ptr;
243 uint32_t txq_flags; /* Holds flags for this TXq */
246 uint8_t tx_deferred_start; /** don't start this queue in dev start. */
248 uint16_t tx_ftag_en; /* indicates FTAG TX supported */
251 struct fm10k_txq_ops {
252 void (*reset)(struct fm10k_tx_queue *txq);
255 #define MBUF_DMA_ADDR(mb) \
256 ((uint64_t) ((mb)->buf_iova + (mb)->data_off))
258 /* enforce 512B alignment on default Rx DMA addresses */
259 #define MBUF_DMA_ADDR_DEFAULT(mb) \
260 ((uint64_t) RTE_ALIGN(((mb)->buf_iova + RTE_PKTMBUF_HEADROOM),\
261 FM10K_RX_DATABUF_ALIGN))
263 static inline void fifo_reset(struct fifo *fifo, uint32_t len)
265 fifo->head = fifo->tail = fifo->list;
266 fifo->endp = fifo->list + len;
269 static inline void fifo_insert(struct fifo *fifo, uint16_t val)
272 if (++fifo->head == fifo->endp)
273 fifo->head = fifo->list;
276 /* do not worry about list being empty since we only check it once we know
277 * we have used enough descriptors to set the RS bit at least once */
278 static inline uint16_t fifo_peek(struct fifo *fifo)
283 static inline uint16_t fifo_remove(struct fifo *fifo)
287 if (++fifo->tail == fifo->endp)
288 fifo->tail = fifo->list;
293 fm10k_pktmbuf_reset(struct rte_mbuf *mb, uint16_t in_port)
295 rte_mbuf_refcnt_set(mb, 1);
299 /* enforce 512B alignment on default Rx virtual addresses */
300 mb->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb->buf_addr +
301 RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
302 - (char *)mb->buf_addr);
307 * Verify Rx packet buffer alignment is valid.
309 * Hardware requires specific alignment for Rx packet buffers. At
310 * least one of the following two conditions must be satisfied.
311 * 1. Address is 512B aligned
312 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
314 * Return 1 if buffer alignment satisfies at least one condition,
315 * otherwise return 0.
317 * Note: Alignment is checked by the driver when the Rx queue is reset. It
318 * is assumed that if an entire descriptor ring can be filled with
319 * buffers containing valid alignment, then all buffers in that mempool
320 * have valid address alignment. It is the responsibility of the user
321 * to ensure all buffers have valid alignment, as it is the user who
322 * creates the mempool.
323 * Note: It is assumed the buffer needs only to store a maximum size Ethernet
327 fm10k_addr_alignment_valid(struct rte_mbuf *mb)
329 uint64_t addr = MBUF_DMA_ADDR_DEFAULT(mb);
330 uint64_t boundary1, boundary2;
333 if (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr)
336 /* 8B aligned, and max Ethernet frame would not cross a 4KB boundary? */
337 if (RTE_ALIGN(addr, 8) == addr) {
338 boundary1 = RTE_ALIGN_FLOOR(addr, 4096);
339 boundary2 = RTE_ALIGN_FLOOR(addr + ETHER_MAX_VLAN_FRAME_LEN,
341 if (boundary1 == boundary2)
345 PMD_INIT_LOG(ERR, "Error: Invalid buffer alignment!");
350 /* Rx and Tx prototypes */
351 uint16_t fm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
354 uint16_t fm10k_recv_scattered_pkts(void *rx_queue,
355 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
358 fm10k_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
360 uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
363 uint16_t fm10k_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
366 int fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq);
367 int fm10k_rx_vec_condition_check(struct rte_eth_dev *);
368 void fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq);
369 uint16_t fm10k_recv_pkts_vec(void *, struct rte_mbuf **, uint16_t);
370 uint16_t fm10k_recv_scattered_pkts_vec(void *, struct rte_mbuf **,
372 uint16_t fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
374 void fm10k_txq_vec_setup(struct fm10k_tx_queue *txq);
375 int fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq);