1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2013-2016 Intel Corporation
5 #include <rte_ethdev_driver.h>
6 #include <rte_ethdev_pci.h>
7 #include <rte_malloc.h>
8 #include <rte_memzone.h>
9 #include <rte_string_fns.h>
11 #include <rte_spinlock.h>
12 #include <rte_kvargs.h>
15 #include "base/fm10k_api.h"
17 /* Default delay to acquire mailbox lock */
18 #define FM10K_MBXLOCK_DELAY_US 20
19 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
21 #define MAIN_VSI_POOL_NUMBER 0
23 /* Max try times to acquire switch status */
24 #define MAX_QUERY_SWITCH_STATE_TIMES 10
25 /* Wait interval to get switch status */
26 #define WAIT_SWITCH_MSG_US 100000
27 /* A period of quiescence for switch */
28 #define FM10K_SWITCH_QUIESCE_US 100000
29 /* Number of chars per uint32 type */
30 #define CHARS_PER_UINT32 (sizeof(uint32_t))
31 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
33 /* default 1:1 map from queue ID to interrupt vector ID */
34 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
36 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
37 #define MAX_LPORT_NUM 128
38 #define GLORT_FD_Q_BASE 0x40
39 #define GLORT_PF_MASK 0xFFC0
40 #define GLORT_FD_MASK GLORT_PF_MASK
41 #define GLORT_FD_INDEX GLORT_FD_Q_BASE
43 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
44 static int fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
45 static int fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
46 static int fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
47 static int fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
48 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
50 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
51 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
52 const u8 *mac, bool add, uint32_t pool);
53 static void fm10k_tx_queue_release(void *queue);
54 static void fm10k_rx_queue_release(void *queue);
55 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
56 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
57 static int fm10k_check_ftag(struct rte_devargs *devargs);
58 static int fm10k_link_update(struct rte_eth_dev *dev, int wait_to_complete);
60 static int fm10k_dev_infos_get(struct rte_eth_dev *dev,
61 struct rte_eth_dev_info *dev_info);
62 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev);
63 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev);
64 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev);
65 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev);
67 struct fm10k_xstats_name_off {
68 char name[RTE_ETH_XSTATS_NAME_SIZE];
72 static const struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
73 {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
74 {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
75 {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
76 {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
77 {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
78 {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
79 {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
80 {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
84 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
85 sizeof(fm10k_hw_stats_strings[0]))
87 static const struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
88 {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
89 {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
90 {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
93 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
94 sizeof(fm10k_hw_stats_rx_q_strings[0]))
96 static const struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
97 {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
98 {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
101 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
102 sizeof(fm10k_hw_stats_tx_q_strings[0]))
104 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
105 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
107 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
110 fm10k_mbx_initlock(struct fm10k_hw *hw)
112 rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
116 fm10k_mbx_lock(struct fm10k_hw *hw)
118 while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
119 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
123 fm10k_mbx_unlock(struct fm10k_hw *hw)
125 rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
128 /* Stubs needed for linkage when vPMD is disabled */
130 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
137 __rte_unused void *rx_queue,
138 __rte_unused struct rte_mbuf **rx_pkts,
139 __rte_unused uint16_t nb_pkts)
145 fm10k_recv_scattered_pkts_vec(
146 __rte_unused void *rx_queue,
147 __rte_unused struct rte_mbuf **rx_pkts,
148 __rte_unused uint16_t nb_pkts)
154 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
161 fm10k_rx_queue_release_mbufs_vec(
162 __rte_unused struct fm10k_rx_queue *rxq)
168 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
174 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
180 fm10k_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
181 __rte_unused struct rte_mbuf **tx_pkts,
182 __rte_unused uint16_t nb_pkts)
188 * reset queue to initial state, allocate software buffers used when starting
190 * return 0 on success
191 * return -ENOMEM if buffers cannot be allocated
192 * return -EINVAL if buffers do not satisfy alignment condition
195 rx_queue_reset(struct fm10k_rx_queue *q)
197 static const union fm10k_rx_desc zero = {{0} };
200 PMD_INIT_FUNC_TRACE();
202 diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
206 for (i = 0; i < q->nb_desc; ++i) {
207 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
208 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
209 rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
213 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
214 q->hw_ring[i].q.pkt_addr = dma_addr;
215 q->hw_ring[i].q.hdr_addr = dma_addr;
218 /* initialize extra software ring entries. Space for these extra
219 * entries is always allocated.
221 memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
222 for (i = 0; i < q->nb_fake_desc; ++i) {
223 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
224 q->hw_ring[q->nb_desc + i] = zero;
229 q->next_trigger = q->alloc_thresh - 1;
230 FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
231 q->rxrearm_start = 0;
238 * clean queue, descriptor rings, free software buffers used when stopping
242 rx_queue_clean(struct fm10k_rx_queue *q)
244 union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
246 PMD_INIT_FUNC_TRACE();
248 /* zero descriptor rings */
249 for (i = 0; i < q->nb_desc; ++i)
250 q->hw_ring[i] = zero;
252 /* zero faked descriptors */
253 for (i = 0; i < q->nb_fake_desc; ++i)
254 q->hw_ring[q->nb_desc + i] = zero;
256 /* vPMD driver has a different way of releasing mbufs. */
257 if (q->rx_using_sse) {
258 fm10k_rx_queue_release_mbufs_vec(q);
262 /* free software buffers */
263 for (i = 0; i < q->nb_desc; ++i) {
265 rte_pktmbuf_free_seg(q->sw_ring[i]);
266 q->sw_ring[i] = NULL;
272 * free all queue memory used when releasing the queue (i.e. configure)
275 rx_queue_free(struct fm10k_rx_queue *q)
277 PMD_INIT_FUNC_TRACE();
279 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
282 rte_free(q->sw_ring);
291 * disable RX queue, wait unitl HW finished necessary flush operation
294 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
298 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
299 FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
300 reg & ~FM10K_RXQCTL_ENABLE);
302 /* Wait 100us at most */
303 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
305 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
306 if (!(reg & FM10K_RXQCTL_ENABLE))
310 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
317 * reset queue to initial state, allocate software buffers used when starting
321 tx_queue_reset(struct fm10k_tx_queue *q)
323 PMD_INIT_FUNC_TRACE();
327 q->nb_free = q->nb_desc - 1;
328 fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
329 FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
333 * clean queue, descriptor rings, free software buffers used when stopping
337 tx_queue_clean(struct fm10k_tx_queue *q)
339 struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
341 PMD_INIT_FUNC_TRACE();
343 /* zero descriptor rings */
344 for (i = 0; i < q->nb_desc; ++i)
345 q->hw_ring[i] = zero;
347 /* free software buffers */
348 for (i = 0; i < q->nb_desc; ++i) {
350 rte_pktmbuf_free_seg(q->sw_ring[i]);
351 q->sw_ring[i] = NULL;
357 * free all queue memory used when releasing the queue (i.e. configure)
360 tx_queue_free(struct fm10k_tx_queue *q)
362 PMD_INIT_FUNC_TRACE();
364 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
366 if (q->rs_tracker.list) {
367 rte_free(q->rs_tracker.list);
368 q->rs_tracker.list = NULL;
371 rte_free(q->sw_ring);
380 * disable TX queue, wait unitl HW finished necessary flush operation
383 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
387 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
388 FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
389 reg & ~FM10K_TXDCTL_ENABLE);
391 /* Wait 100us at most */
392 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
394 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
395 if (!(reg & FM10K_TXDCTL_ENABLE))
399 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
406 fm10k_check_mq_mode(struct rte_eth_dev *dev)
408 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
409 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
410 struct rte_eth_vmdq_rx_conf *vmdq_conf;
411 uint16_t nb_rx_q = dev->data->nb_rx_queues;
413 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
415 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
416 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
420 if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
423 if (hw->mac.type == fm10k_mac_vf) {
424 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
428 /* Check VMDQ queue pool number */
429 if (vmdq_conf->nb_queue_pools >
430 sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
431 vmdq_conf->nb_queue_pools > nb_rx_q) {
432 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
433 vmdq_conf->nb_queue_pools);
440 static const struct fm10k_txq_ops def_txq_ops = {
441 .reset = tx_queue_reset,
445 fm10k_dev_configure(struct rte_eth_dev *dev)
449 PMD_INIT_FUNC_TRACE();
451 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
452 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
454 /* multipe queue mode checking */
455 ret = fm10k_check_mq_mode(dev);
457 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
462 dev->data->scattered_rx = 0;
468 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
470 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
471 struct rte_eth_vmdq_rx_conf *vmdq_conf;
474 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
476 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
477 if (!vmdq_conf->pool_map[i].pools)
480 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
481 fm10k_mbx_unlock(hw);
486 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
488 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
490 /* Add default mac address */
491 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
492 MAIN_VSI_POOL_NUMBER);
496 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
498 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
499 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
500 uint32_t mrqc, *key, i, reta, j;
503 #define RSS_KEY_SIZE 40
504 static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
505 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
506 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
507 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
508 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
509 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
512 if (dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
513 dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
514 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
518 /* random key is rss_intel_key (default) or user provided (rss_key) */
519 if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
520 key = (uint32_t *)rss_intel_key;
522 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
524 /* Now fill our hash function seeds, 4 bytes at a time */
525 for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
526 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
529 * Fill in redirection table
530 * The byte-swap is needed because NIC registers are in
531 * little-endian order.
534 for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
535 if (j == dev->data->nb_rx_queues)
537 reta = (reta << CHAR_BIT) | j;
539 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
544 * Generate RSS hash based on packet types, TCP/UDP
545 * port numbers and/or IPv4/v6 src and dst addresses
547 hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
549 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
550 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
551 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
552 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
553 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
554 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
555 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
556 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
557 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
560 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
565 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
569 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
571 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
574 for (i = 0; i < nb_lport_new; i++) {
575 /* Set unicast mode by default. App can change
576 * to other mode in other API func.
579 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
580 FM10K_XCAST_MODE_NONE);
581 fm10k_mbx_unlock(hw);
586 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
588 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
589 struct rte_eth_vmdq_rx_conf *vmdq_conf;
590 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
591 struct fm10k_macvlan_filter_info *macvlan;
592 uint16_t nb_queue_pools = 0; /* pool number in configuration */
593 uint16_t nb_lport_new;
595 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
596 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
598 fm10k_dev_rss_configure(dev);
600 /* only PF supports VMDQ */
601 if (hw->mac.type != fm10k_mac_pf)
604 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
605 nb_queue_pools = vmdq_conf->nb_queue_pools;
607 /* no pool number change, no need to update logic port and VLAN/MAC */
608 if (macvlan->nb_queue_pools == nb_queue_pools)
611 nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
612 fm10k_dev_logic_port_update(dev, nb_lport_new);
614 /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
615 memset(dev->data->mac_addrs, 0,
616 RTE_ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
617 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
618 &dev->data->mac_addrs[0]);
619 memset(macvlan, 0, sizeof(*macvlan));
620 macvlan->nb_queue_pools = nb_queue_pools;
623 fm10k_dev_vmdq_rx_configure(dev);
625 fm10k_dev_pf_main_vsi_reset(dev);
629 fm10k_dev_tx_init(struct rte_eth_dev *dev)
631 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 struct fm10k_tx_queue *txq;
637 /* Disable TXINT to avoid possible interrupt */
638 for (i = 0; i < hw->mac.max_queues; i++)
639 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
640 3 << FM10K_TXINT_TIMER_SHIFT);
643 for (i = 0; i < dev->data->nb_tx_queues; ++i) {
644 txq = dev->data->tx_queues[i];
645 base_addr = txq->hw_ring_phys_addr;
646 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
648 /* disable queue to avoid issues while updating state */
649 ret = tx_queue_disable(hw, i);
651 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
654 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
655 * register is read-only for VF.
657 if (fm10k_check_ftag(dev->device->devargs)) {
658 if (hw->mac.type == fm10k_mac_pf) {
659 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
660 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
661 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
663 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
668 /* set location and size for descriptor ring */
669 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
670 base_addr & UINT64_LOWER_32BITS_MASK);
671 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
672 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
673 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
675 /* assign default SGLORT for each TX queue by PF */
676 if (hw->mac.type == fm10k_mac_pf)
677 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
680 /* set up vector or scalar TX function as appropriate */
681 fm10k_set_tx_function(dev);
687 fm10k_dev_rx_init(struct rte_eth_dev *dev)
689 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
690 struct fm10k_macvlan_filter_info *macvlan;
691 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
692 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
694 struct fm10k_rx_queue *rxq;
697 uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
698 uint32_t logic_port = hw->mac.dglort_map;
700 uint16_t queue_stride = 0;
702 /* enable RXINT for interrupt mode */
704 if (rte_intr_dp_is_en(intr_handle)) {
705 for (; i < dev->data->nb_rx_queues; i++) {
706 FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
707 if (hw->mac.type == fm10k_mac_pf)
708 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
710 FM10K_ITR_MASK_CLEAR);
712 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
714 FM10K_ITR_MASK_CLEAR);
717 /* Disable other RXINT to avoid possible interrupt */
718 for (; i < hw->mac.max_queues; i++)
719 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
720 3 << FM10K_RXINT_TIMER_SHIFT);
722 /* Setup RX queues */
723 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
724 rxq = dev->data->rx_queues[i];
725 base_addr = rxq->hw_ring_phys_addr;
726 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
728 /* disable queue to avoid issues while updating state */
729 ret = rx_queue_disable(hw, i);
731 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
735 /* Setup the Base and Length of the Rx Descriptor Ring */
736 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
737 base_addr & UINT64_LOWER_32BITS_MASK);
738 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
739 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
740 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
742 /* Configure the Rx buffer size for one buff without split */
743 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
744 RTE_PKTMBUF_HEADROOM);
745 /* As RX buffer is aligned to 512B within mbuf, some bytes are
746 * reserved for this purpose, and the worst case could be 511B.
747 * But SRR reg assumes all buffers have the same size. In order
748 * to fill the gap, we'll have to consider the worst case and
749 * assume 512B is reserved. If we don't do so, it's possible
750 * for HW to overwrite data to next mbuf.
752 buf_size -= FM10K_RX_DATABUF_ALIGN;
754 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
755 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
756 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
758 /* It adds dual VLAN length for supporting dual VLAN */
759 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
760 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
761 rxq->offloads & DEV_RX_OFFLOAD_SCATTER) {
763 dev->data->scattered_rx = 1;
764 reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
765 reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
766 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
769 /* Enable drop on empty, it's RO for VF */
770 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
771 rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
773 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
774 FM10K_WRITE_FLUSH(hw);
777 /* Configure VMDQ/RSS if applicable */
778 fm10k_dev_mq_rx_configure(dev);
780 /* Decide the best RX function */
781 fm10k_set_rx_function(dev);
783 /* update RX_SGLORT for loopback suppress*/
784 if (hw->mac.type != fm10k_mac_pf)
786 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
787 if (macvlan->nb_queue_pools)
788 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
789 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
790 if (i && queue_stride && !(i % queue_stride))
792 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
799 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
801 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
804 struct fm10k_rx_queue *rxq;
806 PMD_INIT_FUNC_TRACE();
808 rxq = dev->data->rx_queues[rx_queue_id];
809 err = rx_queue_reset(rxq);
810 if (err == -ENOMEM) {
811 PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
813 } else if (err == -EINVAL) {
814 PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
819 /* Setup the HW Rx Head and Tail Descriptor Pointers
820 * Note: this must be done AFTER the queue is enabled on real
821 * hardware, but BEFORE the queue is enabled when using the
822 * emulation platform. Do it in both places for now and remove
823 * this comment and the following two register writes when the
824 * emulation platform is no longer being used.
826 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
827 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
829 /* Set PF ownership flag for PF devices */
830 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
831 if (hw->mac.type == fm10k_mac_pf)
832 reg |= FM10K_RXQCTL_PF;
833 reg |= FM10K_RXQCTL_ENABLE;
834 /* enable RX queue */
835 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
836 FM10K_WRITE_FLUSH(hw);
838 /* Setup the HW Rx Head and Tail Descriptor Pointers
839 * Note: this must be done AFTER the queue is enabled
841 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
842 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
843 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
849 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
851 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
853 PMD_INIT_FUNC_TRACE();
855 /* Disable RX queue */
856 rx_queue_disable(hw, rx_queue_id);
858 /* Free mbuf and clean HW ring */
859 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
860 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
866 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
868 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
869 /** @todo - this should be defined in the shared code */
870 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY 0x00010000
871 uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
872 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
874 PMD_INIT_FUNC_TRACE();
878 /* reset head and tail pointers */
879 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
880 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
882 /* enable TX queue */
883 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
884 FM10K_TXDCTL_ENABLE | txdctl);
885 FM10K_WRITE_FLUSH(hw);
886 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
892 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
894 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
896 PMD_INIT_FUNC_TRACE();
898 tx_queue_disable(hw, tx_queue_id);
899 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
900 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
905 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
907 return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
908 != FM10K_DGLORTMAP_NONE);
912 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
914 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
917 PMD_INIT_FUNC_TRACE();
919 /* Return if it didn't acquire valid glort range */
920 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
924 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
925 FM10K_XCAST_MODE_PROMISC);
926 fm10k_mbx_unlock(hw);
928 if (status != FM10K_SUCCESS) {
929 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
937 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
939 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
943 PMD_INIT_FUNC_TRACE();
945 /* Return if it didn't acquire valid glort range */
946 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
949 if (dev->data->all_multicast == 1)
950 mode = FM10K_XCAST_MODE_ALLMULTI;
952 mode = FM10K_XCAST_MODE_NONE;
955 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
957 fm10k_mbx_unlock(hw);
959 if (status != FM10K_SUCCESS) {
960 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
968 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
970 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 PMD_INIT_FUNC_TRACE();
975 /* Return if it didn't acquire valid glort range */
976 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
979 /* If promiscuous mode is enabled, it doesn't make sense to enable
980 * allmulticast and disable promiscuous since fm10k only can select
983 if (dev->data->promiscuous) {
984 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
985 "needn't enable allmulticast");
990 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
991 FM10K_XCAST_MODE_ALLMULTI);
992 fm10k_mbx_unlock(hw);
994 if (status != FM10K_SUCCESS) {
995 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1003 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1005 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1008 PMD_INIT_FUNC_TRACE();
1010 /* Return if it didn't acquire valid glort range */
1011 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1014 if (dev->data->promiscuous) {
1015 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1016 "since promisc mode is enabled");
1021 /* Change mode to unicast mode */
1022 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1023 FM10K_XCAST_MODE_NONE);
1024 fm10k_mbx_unlock(hw);
1026 if (status != FM10K_SUCCESS) {
1027 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1035 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1037 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038 uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1039 uint16_t nb_queue_pools;
1040 struct fm10k_macvlan_filter_info *macvlan;
1042 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1043 nb_queue_pools = macvlan->nb_queue_pools;
1044 pool_len = nb_queue_pools ? rte_fls_u32(nb_queue_pools - 1) : 0;
1045 rss_len = rte_fls_u32(dev->data->nb_rx_queues - 1) - pool_len;
1047 /* GLORT 0x0-0x3F are used by PF and VMDQ, 0x40-0x7F used by FD */
1048 dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1049 dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1051 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1052 /* Configure VMDQ/RSS DGlort Decoder */
1053 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1055 /* Flow Director configurations, only queue number is valid. */
1056 dglortdec = rte_fls_u32(dev->data->nb_rx_queues - 1);
1057 dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1058 (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1059 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1060 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1062 /* Invalidate all other GLORT entries */
1063 for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1064 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1065 FM10K_DGLORTMAP_NONE);
1068 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1070 fm10k_dev_start(struct rte_eth_dev *dev)
1072 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1075 PMD_INIT_FUNC_TRACE();
1077 /* stop, init, then start the hw */
1078 diag = fm10k_stop_hw(hw);
1079 if (diag != FM10K_SUCCESS) {
1080 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1084 diag = fm10k_init_hw(hw);
1085 if (diag != FM10K_SUCCESS) {
1086 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1090 diag = fm10k_start_hw(hw);
1091 if (diag != FM10K_SUCCESS) {
1092 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1096 diag = fm10k_dev_tx_init(dev);
1098 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1102 if (fm10k_dev_rxq_interrupt_setup(dev))
1105 diag = fm10k_dev_rx_init(dev);
1107 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1111 if (hw->mac.type == fm10k_mac_pf)
1112 fm10k_dev_dglort_map_configure(dev);
1114 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1115 struct fm10k_rx_queue *rxq;
1116 rxq = dev->data->rx_queues[i];
1118 if (rxq->rx_deferred_start)
1120 diag = fm10k_dev_rx_queue_start(dev, i);
1123 for (j = 0; j < i; ++j)
1124 rx_queue_clean(dev->data->rx_queues[j]);
1129 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1130 struct fm10k_tx_queue *txq;
1131 txq = dev->data->tx_queues[i];
1133 if (txq->tx_deferred_start)
1135 diag = fm10k_dev_tx_queue_start(dev, i);
1138 for (j = 0; j < i; ++j)
1139 tx_queue_clean(dev->data->tx_queues[j]);
1140 for (j = 0; j < dev->data->nb_rx_queues; ++j)
1141 rx_queue_clean(dev->data->rx_queues[j]);
1146 /* Update default vlan when not in VMDQ mode */
1147 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1148 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1150 fm10k_link_update(dev, 0);
1156 fm10k_dev_stop(struct rte_eth_dev *dev)
1158 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1160 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1163 PMD_INIT_FUNC_TRACE();
1164 dev->data->dev_started = 0;
1166 if (dev->data->tx_queues)
1167 for (i = 0; i < dev->data->nb_tx_queues; i++)
1168 fm10k_dev_tx_queue_stop(dev, i);
1170 if (dev->data->rx_queues)
1171 for (i = 0; i < dev->data->nb_rx_queues; i++)
1172 fm10k_dev_rx_queue_stop(dev, i);
1174 /* Disable datapath event */
1175 if (rte_intr_dp_is_en(intr_handle)) {
1176 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1177 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1178 3 << FM10K_RXINT_TIMER_SHIFT);
1179 if (hw->mac.type == fm10k_mac_pf)
1180 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1181 FM10K_ITR_MASK_SET);
1183 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1184 FM10K_ITR_MASK_SET);
1187 /* Clean datapath event and queue/vec mapping */
1188 rte_intr_efd_disable(intr_handle);
1189 rte_free(intr_handle->intr_vec);
1190 intr_handle->intr_vec = NULL;
1196 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1200 PMD_INIT_FUNC_TRACE();
1202 if (dev->data->tx_queues) {
1203 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1204 struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1210 if (dev->data->rx_queues) {
1211 for (i = 0; i < dev->data->nb_rx_queues; i++)
1212 fm10k_rx_queue_release(dev->data->rx_queues[i]);
1217 fm10k_link_update(struct rte_eth_dev *dev,
1218 __rte_unused int wait_to_complete)
1220 struct fm10k_dev_info *dev_info =
1221 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1222 PMD_INIT_FUNC_TRACE();
1224 dev->data->dev_link.link_speed = ETH_SPEED_NUM_50G;
1225 dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1226 dev->data->dev_link.link_status =
1227 dev_info->sm_down ? ETH_LINK_DOWN : ETH_LINK_UP;
1228 dev->data->dev_link.link_autoneg = ETH_LINK_FIXED;
1233 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1234 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1239 if (xstats_names != NULL) {
1240 /* Note: limit checked in rte_eth_xstats_names() */
1243 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1244 snprintf(xstats_names[count].name,
1245 sizeof(xstats_names[count].name),
1246 "%s", fm10k_hw_stats_strings[count].name);
1250 /* PF queue stats */
1251 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1252 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1253 snprintf(xstats_names[count].name,
1254 sizeof(xstats_names[count].name),
1256 fm10k_hw_stats_rx_q_strings[i].name);
1259 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1260 snprintf(xstats_names[count].name,
1261 sizeof(xstats_names[count].name),
1263 fm10k_hw_stats_tx_q_strings[i].name);
1268 return FM10K_NB_XSTATS;
1272 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1275 struct fm10k_hw_stats *hw_stats =
1276 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1277 unsigned i, q, count = 0;
1279 if (n < FM10K_NB_XSTATS)
1280 return FM10K_NB_XSTATS;
1283 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1284 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1285 fm10k_hw_stats_strings[count].offset);
1286 xstats[count].id = count;
1290 /* PF queue stats */
1291 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1292 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1293 xstats[count].value =
1294 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1295 fm10k_hw_stats_rx_q_strings[i].offset);
1296 xstats[count].id = count;
1299 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1300 xstats[count].value =
1301 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1302 fm10k_hw_stats_tx_q_strings[i].offset);
1303 xstats[count].id = count;
1308 return FM10K_NB_XSTATS;
1312 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1314 uint64_t ipackets, opackets, ibytes, obytes, imissed;
1315 struct fm10k_hw *hw =
1316 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1317 struct fm10k_hw_stats *hw_stats =
1318 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1321 PMD_INIT_FUNC_TRACE();
1323 fm10k_update_hw_stats(hw, hw_stats);
1325 ipackets = opackets = ibytes = obytes = imissed = 0;
1326 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1327 (i < hw->mac.max_queues); ++i) {
1328 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1329 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1330 stats->q_ibytes[i] = hw_stats->q[i].rx_bytes.count;
1331 stats->q_obytes[i] = hw_stats->q[i].tx_bytes.count;
1332 stats->q_errors[i] = hw_stats->q[i].rx_drops.count;
1333 ipackets += stats->q_ipackets[i];
1334 opackets += stats->q_opackets[i];
1335 ibytes += stats->q_ibytes[i];
1336 obytes += stats->q_obytes[i];
1337 imissed += stats->q_errors[i];
1339 stats->ipackets = ipackets;
1340 stats->opackets = opackets;
1341 stats->ibytes = ibytes;
1342 stats->obytes = obytes;
1343 stats->imissed = imissed;
1348 fm10k_stats_reset(struct rte_eth_dev *dev)
1350 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351 struct fm10k_hw_stats *hw_stats =
1352 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1354 PMD_INIT_FUNC_TRACE();
1356 memset(hw_stats, 0, sizeof(*hw_stats));
1357 fm10k_rebind_hw_stats(hw, hw_stats);
1363 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1364 struct rte_eth_dev_info *dev_info)
1366 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1367 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1369 PMD_INIT_FUNC_TRACE();
1371 dev_info->min_rx_bufsize = FM10K_MIN_RX_BUF_SIZE;
1372 dev_info->max_rx_pktlen = FM10K_MAX_PKT_SIZE;
1373 dev_info->max_rx_queues = hw->mac.max_queues;
1374 dev_info->max_tx_queues = hw->mac.max_queues;
1375 dev_info->max_mac_addrs = FM10K_MAX_MACADDR_NUM;
1376 dev_info->max_hash_mac_addrs = 0;
1377 dev_info->max_vfs = pdev->max_vfs;
1378 dev_info->vmdq_pool_base = 0;
1379 dev_info->vmdq_queue_base = 0;
1380 dev_info->max_vmdq_pools = ETH_32_POOLS;
1381 dev_info->vmdq_queue_num = FM10K_MAX_QUEUES_PF;
1382 dev_info->rx_queue_offload_capa = fm10k_get_rx_queue_offloads_capa(dev);
1383 dev_info->rx_offload_capa = fm10k_get_rx_port_offloads_capa(dev) |
1384 dev_info->rx_queue_offload_capa;
1385 dev_info->tx_queue_offload_capa = fm10k_get_tx_queue_offloads_capa(dev);
1386 dev_info->tx_offload_capa = fm10k_get_tx_port_offloads_capa(dev) |
1387 dev_info->tx_queue_offload_capa;
1389 dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1390 dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1391 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1394 ETH_RSS_NONFRAG_IPV4_TCP |
1395 ETH_RSS_NONFRAG_IPV6_TCP |
1396 ETH_RSS_IPV6_TCP_EX |
1397 ETH_RSS_NONFRAG_IPV4_UDP |
1398 ETH_RSS_NONFRAG_IPV6_UDP |
1399 ETH_RSS_IPV6_UDP_EX;
1401 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1403 .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1404 .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1405 .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1407 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1412 dev_info->default_txconf = (struct rte_eth_txconf) {
1414 .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1415 .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1416 .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1418 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1419 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1423 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1424 .nb_max = FM10K_MAX_RX_DESC,
1425 .nb_min = FM10K_MIN_RX_DESC,
1426 .nb_align = FM10K_MULT_RX_DESC,
1429 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1430 .nb_max = FM10K_MAX_TX_DESC,
1431 .nb_min = FM10K_MIN_TX_DESC,
1432 .nb_align = FM10K_MULT_TX_DESC,
1433 .nb_seg_max = FM10K_TX_MAX_SEG,
1434 .nb_mtu_seg_max = FM10K_TX_MAX_MTU_SEG,
1437 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1438 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1439 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1444 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1445 static const uint32_t *
1446 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1448 if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1449 dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1450 static uint32_t ptypes[] = {
1451 /* refers to rx_desc_to_ol_flags() */
1454 RTE_PTYPE_L3_IPV4_EXT,
1456 RTE_PTYPE_L3_IPV6_EXT,
1463 } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1464 dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1465 static uint32_t ptypes_vec[] = {
1466 /* refers to fm10k_desc_to_pktype_v() */
1468 RTE_PTYPE_L3_IPV4_EXT,
1470 RTE_PTYPE_L3_IPV6_EXT,
1473 RTE_PTYPE_TUNNEL_GENEVE,
1474 RTE_PTYPE_TUNNEL_NVGRE,
1475 RTE_PTYPE_TUNNEL_VXLAN,
1476 RTE_PTYPE_TUNNEL_GRE,
1486 static const uint32_t *
1487 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1494 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1497 uint16_t mac_num = 0;
1498 uint32_t vid_idx, vid_bit, mac_index;
1499 struct fm10k_hw *hw;
1500 struct fm10k_macvlan_filter_info *macvlan;
1501 struct rte_eth_dev_data *data = dev->data;
1503 hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1506 if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1507 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1511 if (vlan_id > ETH_VLAN_ID_MAX) {
1512 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1516 vid_idx = FM10K_VFTA_IDX(vlan_id);
1517 vid_bit = FM10K_VFTA_BIT(vlan_id);
1518 /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1519 if (on && (macvlan->vfta[vid_idx] & vid_bit))
1521 /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1522 if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1523 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1524 "in the VLAN filter table");
1529 result = fm10k_update_vlan(hw, vlan_id, 0, on);
1530 fm10k_mbx_unlock(hw);
1531 if (result != FM10K_SUCCESS) {
1532 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1536 for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1537 (result == FM10K_SUCCESS); mac_index++) {
1538 if (rte_is_zero_ether_addr(&data->mac_addrs[mac_index]))
1540 if (mac_num > macvlan->mac_num - 1) {
1541 PMD_INIT_LOG(ERR, "MAC address number "
1546 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1547 data->mac_addrs[mac_index].addr_bytes,
1549 fm10k_mbx_unlock(hw);
1552 if (result != FM10K_SUCCESS) {
1553 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1558 macvlan->vlan_num++;
1559 macvlan->vfta[vid_idx] |= vid_bit;
1561 macvlan->vlan_num--;
1562 macvlan->vfta[vid_idx] &= ~vid_bit;
1568 fm10k_vlan_offload_set(struct rte_eth_dev *dev __rte_unused,
1569 int mask __rte_unused)
1574 /* Add/Remove a MAC address, and update filters to main VSI */
1575 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1576 const u8 *mac, bool add, uint32_t pool)
1578 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 struct fm10k_macvlan_filter_info *macvlan;
1582 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1584 if (pool != MAIN_VSI_POOL_NUMBER) {
1585 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1586 "mac to pool %u", pool);
1589 for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1590 if (!macvlan->vfta[j])
1592 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1593 if (!(macvlan->vfta[j] & (1 << k)))
1595 if (i + 1 > macvlan->vlan_num) {
1596 PMD_INIT_LOG(ERR, "vlan number not match");
1600 fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1601 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1602 fm10k_mbx_unlock(hw);
1608 /* Add/Remove a MAC address, and update filters to VMDQ */
1609 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1610 const u8 *mac, bool add, uint32_t pool)
1612 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613 struct fm10k_macvlan_filter_info *macvlan;
1614 struct rte_eth_vmdq_rx_conf *vmdq_conf;
1617 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1618 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1620 if (pool > macvlan->nb_queue_pools) {
1621 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1623 pool, macvlan->nb_queue_pools);
1626 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1627 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1630 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1631 vmdq_conf->pool_map[i].vlan_id, add, 0);
1632 fm10k_mbx_unlock(hw);
1636 /* Add/Remove a MAC address, and update filters */
1637 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1638 const u8 *mac, bool add, uint32_t pool)
1640 struct fm10k_macvlan_filter_info *macvlan;
1642 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1644 if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1645 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1647 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1655 /* Add a MAC address, and update filters */
1657 fm10k_macaddr_add(struct rte_eth_dev *dev,
1658 struct rte_ether_addr *mac_addr,
1662 struct fm10k_macvlan_filter_info *macvlan;
1664 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1665 fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1666 macvlan->mac_vmdq_id[index] = pool;
1670 /* Remove a MAC address, and update filters */
1672 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1674 struct rte_eth_dev_data *data = dev->data;
1675 struct fm10k_macvlan_filter_info *macvlan;
1677 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1678 fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1679 FALSE, macvlan->mac_vmdq_id[index]);
1680 macvlan->mac_vmdq_id[index] = 0;
1684 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1686 if ((request < min) || (request > max) || ((request % mult) != 0))
1694 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1696 if ((request < min) || (request > max) || ((div % request) != 0))
1703 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1705 uint16_t rx_free_thresh;
1707 if (conf->rx_free_thresh == 0)
1708 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1710 rx_free_thresh = conf->rx_free_thresh;
1712 /* make sure the requested threshold satisfies the constraints */
1713 if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1714 FM10K_RX_FREE_THRESH_MAX(q),
1715 FM10K_RX_FREE_THRESH_DIV(q),
1717 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1718 "less than or equal to %u, "
1719 "greater than or equal to %u, "
1720 "and a divisor of %u",
1721 rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1722 FM10K_RX_FREE_THRESH_MIN(q),
1723 FM10K_RX_FREE_THRESH_DIV(q));
1727 q->alloc_thresh = rx_free_thresh;
1728 q->drop_en = conf->rx_drop_en;
1729 q->rx_deferred_start = conf->rx_deferred_start;
1735 * Hardware requires specific alignment for Rx packet buffers. At
1736 * least one of the following two conditions must be satisfied.
1737 * 1. Address is 512B aligned
1738 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
1740 * As such, the driver may need to adjust the DMA address within the
1741 * buffer by up to 512B.
1743 * return 1 if the element size is valid, otherwise return 0.
1746 mempool_element_size_valid(struct rte_mempool *mp)
1750 /* elt_size includes mbuf header and headroom */
1751 min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1752 RTE_PKTMBUF_HEADROOM;
1754 /* account for up to 512B of alignment */
1755 min_size -= FM10K_RX_DATABUF_ALIGN;
1757 /* sanity check for overflow */
1758 if (min_size > mp->elt_size)
1765 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev)
1769 return (uint64_t)(DEV_RX_OFFLOAD_SCATTER);
1772 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)
1776 return (uint64_t)(DEV_RX_OFFLOAD_VLAN_STRIP |
1777 DEV_RX_OFFLOAD_VLAN_FILTER |
1778 DEV_RX_OFFLOAD_IPV4_CKSUM |
1779 DEV_RX_OFFLOAD_UDP_CKSUM |
1780 DEV_RX_OFFLOAD_TCP_CKSUM |
1781 DEV_RX_OFFLOAD_JUMBO_FRAME |
1782 DEV_RX_OFFLOAD_HEADER_SPLIT |
1783 DEV_RX_OFFLOAD_RSS_HASH);
1787 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1788 uint16_t nb_desc, unsigned int socket_id,
1789 const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1791 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1792 struct fm10k_dev_info *dev_info =
1793 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1794 struct fm10k_rx_queue *q;
1795 const struct rte_memzone *mz;
1798 PMD_INIT_FUNC_TRACE();
1800 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1802 /* make sure the mempool element size can account for alignment. */
1803 if (!mempool_element_size_valid(mp)) {
1804 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1808 /* make sure a valid number of descriptors have been requested */
1809 if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1810 FM10K_MULT_RX_DESC, nb_desc)) {
1811 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1812 "less than or equal to %"PRIu32", "
1813 "greater than or equal to %u, "
1814 "and a multiple of %u",
1815 nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1816 FM10K_MULT_RX_DESC);
1821 * if this queue existed already, free the associated memory. The
1822 * queue cannot be reused in case we need to allocate memory on
1823 * different socket than was previously used.
1825 if (dev->data->rx_queues[queue_id] != NULL) {
1826 rx_queue_free(dev->data->rx_queues[queue_id]);
1827 dev->data->rx_queues[queue_id] = NULL;
1830 /* allocate memory for the queue structure */
1831 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1834 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1840 q->nb_desc = nb_desc;
1841 q->nb_fake_desc = FM10K_MULT_RX_DESC;
1842 q->port_id = dev->data->port_id;
1843 q->queue_id = queue_id;
1844 q->tail_ptr = (volatile uint32_t *)
1845 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1846 q->offloads = offloads;
1847 if (handle_rxconf(q, conf)) {
1851 /* allocate memory for the software ring */
1852 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1853 (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1854 RTE_CACHE_LINE_SIZE, socket_id);
1855 if (q->sw_ring == NULL) {
1856 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1862 * allocate memory for the hardware descriptor ring. A memzone large
1863 * enough to hold the maximum ring size is requested to allow for
1864 * resizing in later calls to the queue setup function.
1866 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1867 FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1870 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1871 rte_free(q->sw_ring);
1875 q->hw_ring = mz->addr;
1876 q->hw_ring_phys_addr = mz->iova;
1878 /* Check if number of descs satisfied Vector requirement */
1879 if (!rte_is_power_of_2(nb_desc)) {
1880 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1881 "preconditions - canceling the feature for "
1882 "the whole port[%d]",
1883 q->queue_id, q->port_id);
1884 dev_info->rx_vec_allowed = false;
1886 fm10k_rxq_vec_setup(q);
1888 dev->data->rx_queues[queue_id] = q;
1893 fm10k_rx_queue_release(void *queue)
1895 PMD_INIT_FUNC_TRACE();
1897 rx_queue_free(queue);
1901 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1903 uint16_t tx_free_thresh;
1904 uint16_t tx_rs_thresh;
1906 /* constraint MACROs require that tx_free_thresh is configured
1907 * before tx_rs_thresh */
1908 if (conf->tx_free_thresh == 0)
1909 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1911 tx_free_thresh = conf->tx_free_thresh;
1913 /* make sure the requested threshold satisfies the constraints */
1914 if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1915 FM10K_TX_FREE_THRESH_MAX(q),
1916 FM10K_TX_FREE_THRESH_DIV(q),
1918 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1919 "less than or equal to %u, "
1920 "greater than or equal to %u, "
1921 "and a divisor of %u",
1922 tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1923 FM10K_TX_FREE_THRESH_MIN(q),
1924 FM10K_TX_FREE_THRESH_DIV(q));
1928 q->free_thresh = tx_free_thresh;
1930 if (conf->tx_rs_thresh == 0)
1931 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1933 tx_rs_thresh = conf->tx_rs_thresh;
1935 q->tx_deferred_start = conf->tx_deferred_start;
1937 /* make sure the requested threshold satisfies the constraints */
1938 if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1939 FM10K_TX_RS_THRESH_MAX(q),
1940 FM10K_TX_RS_THRESH_DIV(q),
1942 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1943 "less than or equal to %u, "
1944 "greater than or equal to %u, "
1945 "and a divisor of %u",
1946 tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1947 FM10K_TX_RS_THRESH_MIN(q),
1948 FM10K_TX_RS_THRESH_DIV(q));
1952 q->rs_thresh = tx_rs_thresh;
1957 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1964 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1968 return (uint64_t)(DEV_TX_OFFLOAD_VLAN_INSERT |
1969 DEV_TX_OFFLOAD_MULTI_SEGS |
1970 DEV_TX_OFFLOAD_IPV4_CKSUM |
1971 DEV_TX_OFFLOAD_UDP_CKSUM |
1972 DEV_TX_OFFLOAD_TCP_CKSUM |
1973 DEV_TX_OFFLOAD_TCP_TSO);
1977 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1978 uint16_t nb_desc, unsigned int socket_id,
1979 const struct rte_eth_txconf *conf)
1981 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1982 struct fm10k_tx_queue *q;
1983 const struct rte_memzone *mz;
1986 PMD_INIT_FUNC_TRACE();
1988 offloads = conf->offloads | dev->data->dev_conf.txmode.offloads;
1990 /* make sure a valid number of descriptors have been requested */
1991 if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1992 FM10K_MULT_TX_DESC, nb_desc)) {
1993 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1994 "less than or equal to %"PRIu32", "
1995 "greater than or equal to %u, "
1996 "and a multiple of %u",
1997 nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1998 FM10K_MULT_TX_DESC);
2003 * if this queue existed already, free the associated memory. The
2004 * queue cannot be reused in case we need to allocate memory on
2005 * different socket than was previously used.
2007 if (dev->data->tx_queues[queue_id] != NULL) {
2008 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
2011 dev->data->tx_queues[queue_id] = NULL;
2014 /* allocate memory for the queue structure */
2015 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2018 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2023 q->nb_desc = nb_desc;
2024 q->port_id = dev->data->port_id;
2025 q->queue_id = queue_id;
2026 q->offloads = offloads;
2027 q->ops = &def_txq_ops;
2028 q->tail_ptr = (volatile uint32_t *)
2029 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2030 if (handle_txconf(q, conf)) {
2035 /* allocate memory for the software ring */
2036 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2037 nb_desc * sizeof(struct rte_mbuf *),
2038 RTE_CACHE_LINE_SIZE, socket_id);
2039 if (q->sw_ring == NULL) {
2040 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2046 * allocate memory for the hardware descriptor ring. A memzone large
2047 * enough to hold the maximum ring size is requested to allow for
2048 * resizing in later calls to the queue setup function.
2050 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2051 FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2054 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2055 rte_free(q->sw_ring);
2059 q->hw_ring = mz->addr;
2060 q->hw_ring_phys_addr = mz->iova;
2063 * allocate memory for the RS bit tracker. Enough slots to hold the
2064 * descriptor index for each RS bit needing to be set are required.
2066 q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2067 ((nb_desc + 1) / q->rs_thresh) *
2069 RTE_CACHE_LINE_SIZE, socket_id);
2070 if (q->rs_tracker.list == NULL) {
2071 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2072 rte_free(q->sw_ring);
2077 dev->data->tx_queues[queue_id] = q;
2082 fm10k_tx_queue_release(void *queue)
2084 struct fm10k_tx_queue *q = queue;
2085 PMD_INIT_FUNC_TRACE();
2091 fm10k_reta_update(struct rte_eth_dev *dev,
2092 struct rte_eth_rss_reta_entry64 *reta_conf,
2095 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 uint16_t i, j, idx, shift;
2100 PMD_INIT_FUNC_TRACE();
2102 if (reta_size > FM10K_MAX_RSS_INDICES) {
2103 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2104 "(%d) doesn't match the number hardware can supported "
2105 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2110 * Update Redirection Table RETA[n], n=0..31. The redirection table has
2111 * 128-entries in 32 registers
2113 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2114 idx = i / RTE_RETA_GROUP_SIZE;
2115 shift = i % RTE_RETA_GROUP_SIZE;
2116 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2117 BIT_MASK_PER_UINT32);
2122 if (mask != BIT_MASK_PER_UINT32)
2123 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2125 for (j = 0; j < CHARS_PER_UINT32; j++) {
2126 if (mask & (0x1 << j)) {
2128 reta &= ~(UINT8_MAX << CHAR_BIT * j);
2129 reta |= reta_conf[idx].reta[shift + j] <<
2133 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2140 fm10k_reta_query(struct rte_eth_dev *dev,
2141 struct rte_eth_rss_reta_entry64 *reta_conf,
2144 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 uint16_t i, j, idx, shift;
2149 PMD_INIT_FUNC_TRACE();
2151 if (reta_size < FM10K_MAX_RSS_INDICES) {
2152 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2153 "(%d) doesn't match the number hardware can supported "
2154 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2159 * Read Redirection Table RETA[n], n=0..31. The redirection table has
2160 * 128-entries in 32 registers
2162 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2163 idx = i / RTE_RETA_GROUP_SIZE;
2164 shift = i % RTE_RETA_GROUP_SIZE;
2165 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2166 BIT_MASK_PER_UINT32);
2170 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2171 for (j = 0; j < CHARS_PER_UINT32; j++) {
2172 if (mask & (0x1 << j))
2173 reta_conf[idx].reta[shift + j] = ((reta >>
2174 CHAR_BIT * j) & UINT8_MAX);
2182 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2183 struct rte_eth_rss_conf *rss_conf)
2185 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2188 uint64_t hf = rss_conf->rss_hf;
2191 PMD_INIT_FUNC_TRACE();
2193 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2194 FM10K_RSSRK_ENTRIES_PER_REG))
2201 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
2202 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
2203 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
2204 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
2205 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
2206 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
2207 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
2208 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
2209 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
2211 /* If the mapping doesn't fit any supported, return */
2216 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2217 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2219 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2225 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2226 struct rte_eth_rss_conf *rss_conf)
2228 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2229 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2234 PMD_INIT_FUNC_TRACE();
2236 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2237 FM10K_RSSRK_ENTRIES_PER_REG))
2241 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2242 key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2244 mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2246 hf |= (mrqc & FM10K_MRQC_IPV4) ? ETH_RSS_IPV4 : 0;
2247 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6 : 0;
2248 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6_EX : 0;
2249 hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP : 0;
2250 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP : 0;
2251 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX : 0;
2252 hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP : 0;
2253 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP : 0;
2254 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX : 0;
2256 rss_conf->rss_hf = hf;
2262 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2264 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2267 /* Bind all local non-queue interrupt to vector 0 */
2268 int_map |= FM10K_MISC_VEC_ID;
2270 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2271 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2272 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2273 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2274 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2275 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2277 /* Enable misc causes */
2278 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2279 FM10K_EIMR_ENABLE(THI_FAULT) |
2280 FM10K_EIMR_ENABLE(FUM_FAULT) |
2281 FM10K_EIMR_ENABLE(MAILBOX) |
2282 FM10K_EIMR_ENABLE(SWITCHREADY) |
2283 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2284 FM10K_EIMR_ENABLE(SRAMERROR) |
2285 FM10K_EIMR_ENABLE(VFLR));
2288 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2289 FM10K_ITR_MASK_CLEAR);
2290 FM10K_WRITE_FLUSH(hw);
2294 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2296 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2299 int_map |= FM10K_MISC_VEC_ID;
2301 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2302 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2303 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2304 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2305 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2306 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2308 /* Disable misc causes */
2309 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2310 FM10K_EIMR_DISABLE(THI_FAULT) |
2311 FM10K_EIMR_DISABLE(FUM_FAULT) |
2312 FM10K_EIMR_DISABLE(MAILBOX) |
2313 FM10K_EIMR_DISABLE(SWITCHREADY) |
2314 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2315 FM10K_EIMR_DISABLE(SRAMERROR) |
2316 FM10K_EIMR_DISABLE(VFLR));
2319 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2320 FM10K_WRITE_FLUSH(hw);
2324 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2326 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2327 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2329 /* Bind all local non-queue interrupt to vector 0 */
2330 int_map |= FM10K_MISC_VEC_ID;
2332 /* Only INT 0 available, other 15 are reserved. */
2333 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2336 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2337 FM10K_ITR_MASK_CLEAR);
2338 FM10K_WRITE_FLUSH(hw);
2342 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2344 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2347 int_map |= FM10K_MISC_VEC_ID;
2349 /* Only INT 0 available, other 15 are reserved. */
2350 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2353 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2354 FM10K_WRITE_FLUSH(hw);
2358 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2360 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2364 if (hw->mac.type == fm10k_mac_pf)
2365 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2366 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2368 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2369 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2370 rte_intr_ack(&pdev->intr_handle);
2375 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2377 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2378 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2381 if (hw->mac.type == fm10k_mac_pf)
2382 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2383 FM10K_ITR_MASK_SET);
2385 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2386 FM10K_ITR_MASK_SET);
2391 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2393 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2395 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2396 uint32_t intr_vector, vec;
2400 /* fm10k needs one separate interrupt for mailbox,
2401 * so only drivers which support multiple interrupt vectors
2402 * e.g. vfio-pci can work for fm10k interrupt mode
2404 if (!rte_intr_cap_multiple(intr_handle) ||
2405 dev->data->dev_conf.intr_conf.rxq == 0)
2408 intr_vector = dev->data->nb_rx_queues;
2410 /* disable interrupt first */
2411 rte_intr_disable(intr_handle);
2412 if (hw->mac.type == fm10k_mac_pf)
2413 fm10k_dev_disable_intr_pf(dev);
2415 fm10k_dev_disable_intr_vf(dev);
2417 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2418 PMD_INIT_LOG(ERR, "Failed to init event fd");
2422 if (rte_intr_dp_is_en(intr_handle) && !result) {
2423 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2424 dev->data->nb_rx_queues * sizeof(int), 0);
2425 if (intr_handle->intr_vec) {
2426 for (queue_id = 0, vec = FM10K_RX_VEC_START;
2427 queue_id < dev->data->nb_rx_queues;
2429 intr_handle->intr_vec[queue_id] = vec;
2430 if (vec < intr_handle->nb_efd - 1
2431 + FM10K_RX_VEC_START)
2435 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2436 " intr_vec", dev->data->nb_rx_queues);
2437 rte_intr_efd_disable(intr_handle);
2442 if (hw->mac.type == fm10k_mac_pf)
2443 fm10k_dev_enable_intr_pf(dev);
2445 fm10k_dev_enable_intr_vf(dev);
2446 rte_intr_enable(intr_handle);
2447 hw->mac.ops.update_int_moderator(hw);
2452 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2454 struct fm10k_fault fault;
2456 const char *estr = "Unknown error";
2458 /* Process PCA fault */
2459 if (eicr & FM10K_EICR_PCA_FAULT) {
2460 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2463 switch (fault.type) {
2465 estr = "PCA_NO_FAULT"; break;
2466 case PCA_UNMAPPED_ADDR:
2467 estr = "PCA_UNMAPPED_ADDR"; break;
2468 case PCA_BAD_QACCESS_PF:
2469 estr = "PCA_BAD_QACCESS_PF"; break;
2470 case PCA_BAD_QACCESS_VF:
2471 estr = "PCA_BAD_QACCESS_VF"; break;
2472 case PCA_MALICIOUS_REQ:
2473 estr = "PCA_MALICIOUS_REQ"; break;
2474 case PCA_POISONED_TLP:
2475 estr = "PCA_POISONED_TLP"; break;
2477 estr = "PCA_TLP_ABORT"; break;
2481 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2482 estr, fault.func ? "VF" : "PF", fault.func,
2483 fault.address, fault.specinfo);
2486 /* Process THI fault */
2487 if (eicr & FM10K_EICR_THI_FAULT) {
2488 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2491 switch (fault.type) {
2493 estr = "THI_NO_FAULT"; break;
2494 case THI_MAL_DIS_Q_FAULT:
2495 estr = "THI_MAL_DIS_Q_FAULT"; break;
2499 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2500 estr, fault.func ? "VF" : "PF", fault.func,
2501 fault.address, fault.specinfo);
2504 /* Process FUM fault */
2505 if (eicr & FM10K_EICR_FUM_FAULT) {
2506 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2509 switch (fault.type) {
2511 estr = "FUM_NO_FAULT"; break;
2512 case FUM_UNMAPPED_ADDR:
2513 estr = "FUM_UNMAPPED_ADDR"; break;
2514 case FUM_POISONED_TLP:
2515 estr = "FUM_POISONED_TLP"; break;
2516 case FUM_BAD_VF_QACCESS:
2517 estr = "FUM_BAD_VF_QACCESS"; break;
2518 case FUM_ADD_DECODE_ERR:
2519 estr = "FUM_ADD_DECODE_ERR"; break;
2521 estr = "FUM_RO_ERROR"; break;
2522 case FUM_QPRC_CRC_ERROR:
2523 estr = "FUM_QPRC_CRC_ERROR"; break;
2524 case FUM_CSR_TIMEOUT:
2525 estr = "FUM_CSR_TIMEOUT"; break;
2526 case FUM_INVALID_TYPE:
2527 estr = "FUM_INVALID_TYPE"; break;
2528 case FUM_INVALID_LENGTH:
2529 estr = "FUM_INVALID_LENGTH"; break;
2530 case FUM_INVALID_BE:
2531 estr = "FUM_INVALID_BE"; break;
2532 case FUM_INVALID_ALIGN:
2533 estr = "FUM_INVALID_ALIGN"; break;
2537 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2538 estr, fault.func ? "VF" : "PF", fault.func,
2539 fault.address, fault.specinfo);
2544 PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2549 * PF interrupt handler triggered by NIC for handling specific interrupt.
2552 * Pointer to interrupt handle.
2554 * The address of parameter (struct rte_eth_dev *) regsitered before.
2560 fm10k_dev_interrupt_handler_pf(void *param)
2562 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2563 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2564 uint32_t cause, status;
2565 struct fm10k_dev_info *dev_info =
2566 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2570 if (hw->mac.type != fm10k_mac_pf)
2573 cause = FM10K_READ_REG(hw, FM10K_EICR);
2575 /* Handle PCI fault cases */
2576 if (cause & FM10K_EICR_FAULT_MASK) {
2577 PMD_INIT_LOG(ERR, "INT: find fault!");
2578 fm10k_dev_handle_fault(hw, cause);
2581 /* Handle switch up/down */
2582 if (cause & FM10K_EICR_SWITCHNOTREADY)
2583 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2585 if (cause & FM10K_EICR_SWITCHREADY) {
2586 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2587 if (dev_info->sm_down == 1) {
2590 /* For recreating logical ports */
2591 status_mbx = hw->mac.ops.update_lport_state(hw,
2592 hw->mac.dglort_map, MAX_LPORT_NUM, 1);
2593 if (status_mbx == FM10K_SUCCESS)
2595 "INT: Recreated Logical port");
2598 "INT: Logical ports weren't recreated");
2600 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2601 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2602 if (status_mbx != FM10K_SUCCESS)
2603 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2605 fm10k_mbx_unlock(hw);
2607 /* first clear the internal SW recording structure */
2608 if (!(dev->data->dev_conf.rxmode.mq_mode &
2609 ETH_MQ_RX_VMDQ_FLAG))
2610 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2613 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2614 MAIN_VSI_POOL_NUMBER);
2617 * Add default mac address and vlan for the logical
2618 * ports that have been created, leave to the
2619 * application to fully recover Rx filtering.
2621 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2622 MAIN_VSI_POOL_NUMBER);
2624 if (!(dev->data->dev_conf.rxmode.mq_mode &
2625 ETH_MQ_RX_VMDQ_FLAG))
2626 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2629 dev_info->sm_down = 0;
2630 rte_eth_dev_callback_process(dev,
2631 RTE_ETH_EVENT_INTR_LSC,
2636 /* Handle mailbox message */
2638 err = hw->mbx.ops.process(hw, &hw->mbx);
2639 fm10k_mbx_unlock(hw);
2641 if (err == FM10K_ERR_RESET_REQUESTED) {
2642 PMD_INIT_LOG(INFO, "INT: Switch is down");
2643 dev_info->sm_down = 1;
2644 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2647 /* Handle SRAM error */
2648 if (cause & FM10K_EICR_SRAMERROR) {
2649 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2651 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2652 /* Write to clear pending bits */
2653 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2655 /* Todo: print out error message after shared code updates */
2658 /* Clear these 3 events if having any */
2659 cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2660 FM10K_EICR_SWITCHREADY;
2662 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2664 /* Re-enable interrupt from device side */
2665 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2666 FM10K_ITR_MASK_CLEAR);
2667 /* Re-enable interrupt from host side */
2668 rte_intr_ack(dev->intr_handle);
2672 * VF interrupt handler triggered by NIC for handling specific interrupt.
2675 * Pointer to interrupt handle.
2677 * The address of parameter (struct rte_eth_dev *) regsitered before.
2683 fm10k_dev_interrupt_handler_vf(void *param)
2685 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2686 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2687 struct fm10k_mbx_info *mbx = &hw->mbx;
2688 struct fm10k_dev_info *dev_info =
2689 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2690 const enum fm10k_mbx_state state = mbx->state;
2693 if (hw->mac.type != fm10k_mac_vf)
2696 /* Handle mailbox message if lock is acquired */
2698 hw->mbx.ops.process(hw, &hw->mbx);
2699 fm10k_mbx_unlock(hw);
2701 if (state == FM10K_STATE_OPEN && mbx->state == FM10K_STATE_CONNECT) {
2702 PMD_INIT_LOG(INFO, "INT: Switch has gone down");
2705 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2707 fm10k_mbx_unlock(hw);
2709 /* Setting reset flag */
2710 dev_info->sm_down = 1;
2711 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2714 if (dev_info->sm_down == 1 &&
2715 hw->mac.dglort_map == FM10K_DGLORTMAP_ZERO) {
2716 PMD_INIT_LOG(INFO, "INT: Switch has gone up");
2718 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2719 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2720 if (status_mbx != FM10K_SUCCESS)
2721 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2722 fm10k_mbx_unlock(hw);
2724 /* first clear the internal SW recording structure */
2725 fm10k_vlan_filter_set(dev, hw->mac.default_vid, false);
2726 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2727 MAIN_VSI_POOL_NUMBER);
2730 * Add default mac address and vlan for the logical ports that
2731 * have been created, leave to the application to fully recover
2734 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2735 MAIN_VSI_POOL_NUMBER);
2736 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
2738 dev_info->sm_down = 0;
2739 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2742 /* Re-enable interrupt from device side */
2743 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2744 FM10K_ITR_MASK_CLEAR);
2745 /* Re-enable interrupt from host side */
2746 rte_intr_ack(dev->intr_handle);
2749 /* Mailbox message handler in VF */
2750 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2751 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2752 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2753 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2754 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2758 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2762 /* Initialize mailbox lock */
2763 fm10k_mbx_initlock(hw);
2765 /* Replace default message handler with new ones */
2766 if (hw->mac.type == fm10k_mac_vf)
2767 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2770 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2774 /* Connect to SM for PF device or PF for VF device */
2775 return hw->mbx.ops.connect(hw, &hw->mbx);
2779 fm10k_close_mbx_service(struct fm10k_hw *hw)
2781 /* Disconnect from SM for PF device or PF for VF device */
2782 hw->mbx.ops.disconnect(hw, &hw->mbx);
2786 fm10k_dev_close(struct rte_eth_dev *dev)
2788 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2790 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2793 PMD_INIT_FUNC_TRACE();
2794 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2798 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2799 MAX_LPORT_NUM, false);
2800 fm10k_mbx_unlock(hw);
2802 /* allow 100ms for device to quiesce */
2803 rte_delay_us(FM10K_SWITCH_QUIESCE_US);
2805 /* Stop mailbox service first */
2806 fm10k_close_mbx_service(hw);
2808 ret = fm10k_dev_stop(dev);
2810 fm10k_dev_queue_release(dev);
2813 /* disable uio/vfio intr */
2814 rte_intr_disable(intr_handle);
2816 /*PF/VF has different interrupt handling mechanism */
2817 if (hw->mac.type == fm10k_mac_pf) {
2818 /* disable interrupt */
2819 fm10k_dev_disable_intr_pf(dev);
2821 /* unregister callback func to eal lib */
2822 rte_intr_callback_unregister(intr_handle,
2823 fm10k_dev_interrupt_handler_pf, (void *)dev);
2825 /* disable interrupt */
2826 fm10k_dev_disable_intr_vf(dev);
2828 rte_intr_callback_unregister(intr_handle,
2829 fm10k_dev_interrupt_handler_vf, (void *)dev);
2835 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2836 .dev_configure = fm10k_dev_configure,
2837 .dev_start = fm10k_dev_start,
2838 .dev_stop = fm10k_dev_stop,
2839 .dev_close = fm10k_dev_close,
2840 .promiscuous_enable = fm10k_dev_promiscuous_enable,
2841 .promiscuous_disable = fm10k_dev_promiscuous_disable,
2842 .allmulticast_enable = fm10k_dev_allmulticast_enable,
2843 .allmulticast_disable = fm10k_dev_allmulticast_disable,
2844 .stats_get = fm10k_stats_get,
2845 .xstats_get = fm10k_xstats_get,
2846 .xstats_get_names = fm10k_xstats_get_names,
2847 .stats_reset = fm10k_stats_reset,
2848 .xstats_reset = fm10k_stats_reset,
2849 .link_update = fm10k_link_update,
2850 .dev_infos_get = fm10k_dev_infos_get,
2851 .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2852 .vlan_filter_set = fm10k_vlan_filter_set,
2853 .vlan_offload_set = fm10k_vlan_offload_set,
2854 .mac_addr_add = fm10k_macaddr_add,
2855 .mac_addr_remove = fm10k_macaddr_remove,
2856 .rx_queue_start = fm10k_dev_rx_queue_start,
2857 .rx_queue_stop = fm10k_dev_rx_queue_stop,
2858 .tx_queue_start = fm10k_dev_tx_queue_start,
2859 .tx_queue_stop = fm10k_dev_tx_queue_stop,
2860 .rx_queue_setup = fm10k_rx_queue_setup,
2861 .rx_queue_release = fm10k_rx_queue_release,
2862 .tx_queue_setup = fm10k_tx_queue_setup,
2863 .tx_queue_release = fm10k_tx_queue_release,
2864 .rx_queue_intr_enable = fm10k_dev_rx_queue_intr_enable,
2865 .rx_queue_intr_disable = fm10k_dev_rx_queue_intr_disable,
2866 .reta_update = fm10k_reta_update,
2867 .reta_query = fm10k_reta_query,
2868 .rss_hash_update = fm10k_rss_hash_update,
2869 .rss_hash_conf_get = fm10k_rss_hash_conf_get,
2872 static int ftag_check_handler(__rte_unused const char *key,
2873 const char *value, __rte_unused void *opaque)
2875 if (strcmp(value, "1"))
2882 fm10k_check_ftag(struct rte_devargs *devargs)
2884 struct rte_kvargs *kvlist;
2885 const char *ftag_key = "enable_ftag";
2887 if (devargs == NULL)
2890 kvlist = rte_kvargs_parse(devargs->args, NULL);
2894 if (!rte_kvargs_count(kvlist, ftag_key)) {
2895 rte_kvargs_free(kvlist);
2898 /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2899 if (rte_kvargs_process(kvlist, ftag_key,
2900 ftag_check_handler, NULL) < 0) {
2901 rte_kvargs_free(kvlist);
2904 rte_kvargs_free(kvlist);
2910 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
2914 struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
2919 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
2920 ret = fm10k_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
2931 static void __rte_cold
2932 fm10k_set_tx_function(struct rte_eth_dev *dev)
2934 struct fm10k_tx_queue *txq;
2937 uint16_t tx_ftag_en = 0;
2939 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2940 /* primary process has set the ftag flag and offloads */
2941 txq = dev->data->tx_queues[0];
2942 if (fm10k_tx_vec_condition_check(txq)) {
2943 dev->tx_pkt_burst = fm10k_xmit_pkts;
2944 dev->tx_pkt_prepare = fm10k_prep_pkts;
2945 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2947 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2948 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2949 dev->tx_pkt_prepare = NULL;
2954 if (fm10k_check_ftag(dev->device->devargs))
2957 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2958 txq = dev->data->tx_queues[i];
2959 txq->tx_ftag_en = tx_ftag_en;
2960 /* Check if Vector Tx is satisfied */
2961 if (fm10k_tx_vec_condition_check(txq))
2966 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2967 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2968 txq = dev->data->tx_queues[i];
2969 fm10k_txq_vec_setup(txq);
2971 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2972 dev->tx_pkt_prepare = NULL;
2974 dev->tx_pkt_burst = fm10k_xmit_pkts;
2975 dev->tx_pkt_prepare = fm10k_prep_pkts;
2976 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2980 static void __rte_cold
2981 fm10k_set_rx_function(struct rte_eth_dev *dev)
2983 struct fm10k_dev_info *dev_info =
2984 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2985 uint16_t i, rx_using_sse;
2986 uint16_t rx_ftag_en = 0;
2988 if (fm10k_check_ftag(dev->device->devargs))
2991 /* In order to allow Vector Rx there are a few configuration
2992 * conditions to be met.
2994 if (!fm10k_rx_vec_condition_check(dev) &&
2995 dev_info->rx_vec_allowed && !rx_ftag_en) {
2996 if (dev->data->scattered_rx)
2997 dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2999 dev->rx_pkt_burst = fm10k_recv_pkts_vec;
3000 } else if (dev->data->scattered_rx)
3001 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
3003 dev->rx_pkt_burst = fm10k_recv_pkts;
3006 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
3007 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
3010 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
3012 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
3014 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3017 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3018 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
3020 rxq->rx_using_sse = rx_using_sse;
3021 rxq->rx_ftag_en = rx_ftag_en;
3026 fm10k_params_init(struct rte_eth_dev *dev)
3028 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3029 struct fm10k_dev_info *info =
3030 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
3032 /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
3033 * there is no way to get link status without reading BAR4. Until this
3034 * works, assume we have maximum bandwidth.
3035 * @todo - fix bus info
3037 hw->bus_caps.speed = fm10k_bus_speed_8000;
3038 hw->bus_caps.width = fm10k_bus_width_pcie_x8;
3039 hw->bus_caps.payload = fm10k_bus_payload_512;
3040 hw->bus.speed = fm10k_bus_speed_8000;
3041 hw->bus.width = fm10k_bus_width_pcie_x8;
3042 hw->bus.payload = fm10k_bus_payload_256;
3044 info->rx_vec_allowed = true;
3045 info->sm_down = false;
3049 eth_fm10k_dev_init(struct rte_eth_dev *dev)
3051 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3052 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
3053 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3055 struct fm10k_macvlan_filter_info *macvlan;
3057 PMD_INIT_FUNC_TRACE();
3059 dev->dev_ops = &fm10k_eth_dev_ops;
3060 dev->rx_queue_count = fm10k_dev_rx_queue_count;
3061 dev->rx_descriptor_done = fm10k_dev_rx_descriptor_done;
3062 dev->rx_descriptor_status = fm10k_dev_rx_descriptor_status;
3063 dev->tx_descriptor_status = fm10k_dev_tx_descriptor_status;
3064 dev->rx_pkt_burst = &fm10k_recv_pkts;
3065 dev->tx_pkt_burst = &fm10k_xmit_pkts;
3066 dev->tx_pkt_prepare = &fm10k_prep_pkts;
3069 * Primary process does the whole initialization, for secondary
3070 * processes, we just select the same Rx and Tx function as primary.
3072 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3073 fm10k_set_rx_function(dev);
3074 fm10k_set_tx_function(dev);
3078 rte_eth_copy_pci_info(dev, pdev);
3080 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
3081 memset(macvlan, 0, sizeof(*macvlan));
3082 /* Vendor and Device ID need to be set before init of shared code */
3083 memset(hw, 0, sizeof(*hw));
3084 hw->device_id = pdev->id.device_id;
3085 hw->vendor_id = pdev->id.vendor_id;
3086 hw->subsystem_device_id = pdev->id.subsystem_device_id;
3087 hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
3088 hw->revision_id = 0;
3089 hw->hw_addr = (void *)pdev->mem_resource[0].addr;
3090 if (hw->hw_addr == NULL) {
3091 PMD_INIT_LOG(ERR, "Bad mem resource."
3092 " Try to refuse unused devices.");
3096 /* Store fm10k_adapter pointer */
3097 hw->back = dev->data->dev_private;
3099 /* Initialize the shared code */
3100 diag = fm10k_init_shared_code(hw);
3101 if (diag != FM10K_SUCCESS) {
3102 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
3106 /* Initialize parameters */
3107 fm10k_params_init(dev);
3109 /* Initialize the hw */
3110 diag = fm10k_init_hw(hw);
3111 if (diag != FM10K_SUCCESS) {
3112 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
3116 /* Initialize MAC address(es) */
3117 dev->data->mac_addrs = rte_zmalloc("fm10k",
3118 RTE_ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
3119 if (dev->data->mac_addrs == NULL) {
3120 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
3124 diag = fm10k_read_mac_addr(hw);
3126 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
3127 &dev->data->mac_addrs[0]);
3129 if (diag != FM10K_SUCCESS ||
3130 !rte_is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
3132 /* Generate a random addr */
3133 rte_eth_random_addr(hw->mac.addr);
3134 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
3135 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
3136 &dev->data->mac_addrs[0]);
3139 /* Reset the hw statistics */
3140 diag = fm10k_stats_reset(dev);
3142 PMD_INIT_LOG(ERR, "Stats reset failed: %d", diag);
3147 diag = fm10k_reset_hw(hw);
3148 if (diag != FM10K_SUCCESS) {
3149 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
3153 /* Setup mailbox service */
3154 diag = fm10k_setup_mbx_service(hw);
3155 if (diag != FM10K_SUCCESS) {
3156 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
3160 /*PF/VF has different interrupt handling mechanism */
3161 if (hw->mac.type == fm10k_mac_pf) {
3162 /* register callback func to eal lib */
3163 rte_intr_callback_register(intr_handle,
3164 fm10k_dev_interrupt_handler_pf, (void *)dev);
3166 /* enable MISC interrupt */
3167 fm10k_dev_enable_intr_pf(dev);
3169 rte_intr_callback_register(intr_handle,
3170 fm10k_dev_interrupt_handler_vf, (void *)dev);
3172 fm10k_dev_enable_intr_vf(dev);
3175 /* Enable intr after callback registered */
3176 rte_intr_enable(intr_handle);
3178 hw->mac.ops.update_int_moderator(hw);
3180 /* Make sure Switch Manager is ready before going forward. */
3181 if (hw->mac.type == fm10k_mac_pf) {
3182 bool switch_ready = false;
3184 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3186 hw->mac.ops.get_host_state(hw, &switch_ready);
3187 fm10k_mbx_unlock(hw);
3188 if (switch_ready == true)
3190 /* Delay some time to acquire async LPORT_MAP info. */
3191 rte_delay_us(WAIT_SWITCH_MSG_US);
3194 if (switch_ready == false) {
3195 PMD_INIT_LOG(ERR, "switch is not ready");
3201 * Below function will trigger operations on mailbox, acquire lock to
3202 * avoid race condition from interrupt handler. Operations on mailbox
3203 * FIFO will trigger interrupt to PF/SM, in which interrupt handler
3204 * will handle and generate an interrupt to our side. Then, FIFO in
3205 * mailbox will be touched.
3208 /* Enable port first */
3209 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
3212 /* Set unicast mode by default. App can change to other mode in other
3215 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
3216 FM10K_XCAST_MODE_NONE);
3218 fm10k_mbx_unlock(hw);
3220 /* Make sure default VID is ready before going forward. */
3221 if (hw->mac.type == fm10k_mac_pf) {
3222 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3223 if (hw->mac.default_vid)
3225 /* Delay some time to acquire async port VLAN info. */
3226 rte_delay_us(WAIT_SWITCH_MSG_US);
3229 if (!hw->mac.default_vid) {
3230 PMD_INIT_LOG(ERR, "default VID is not ready");
3235 /* Add default mac address */
3236 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3237 MAIN_VSI_POOL_NUMBER);
3243 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3245 PMD_INIT_FUNC_TRACE();
3246 fm10k_dev_close(dev);
3250 static int eth_fm10k_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3251 struct rte_pci_device *pci_dev)
3253 return rte_eth_dev_pci_generic_probe(pci_dev,
3254 sizeof(struct fm10k_adapter), eth_fm10k_dev_init);
3257 static int eth_fm10k_pci_remove(struct rte_pci_device *pci_dev)
3259 return rte_eth_dev_pci_generic_remove(pci_dev, eth_fm10k_dev_uninit);
3263 * The set of PCI devices this driver supports. This driver will enable both PF
3264 * and SRIOV-VF devices.
3266 static const struct rte_pci_id pci_id_fm10k_map[] = {
3267 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3268 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3269 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3270 { .vendor_id = 0, /* sentinel */ },
3273 static struct rte_pci_driver rte_pmd_fm10k = {
3274 .id_table = pci_id_fm10k_map,
3275 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3276 .probe = eth_fm10k_pci_probe,
3277 .remove = eth_fm10k_pci_remove,
3280 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k);
3281 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3282 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio-pci");
3283 RTE_LOG_REGISTER(fm10k_logtype_init, pmd.net.fm10k.init, NOTICE);
3284 RTE_LOG_REGISTER(fm10k_logtype_driver, pmd.net.fm10k.driver, NOTICE);
3285 #ifdef RTE_LIBRTE_FM10K_DEBUG_RX
3286 RTE_LOG_REGISTER(fm10k_logtype_rx, pmd.net.fm10k.rx, DEBUG);
3288 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX
3289 RTE_LOG_REGISTER(fm10k_logtype_tx, pmd.net.fm10k.tx, DEBUG);
3291 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX_FREE
3292 RTE_LOG_REGISTER(fm10k_logtype_tx_free, pmd.net.fm10k.tx_free, DEBUG);