1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2013-2016 Intel Corporation
5 #include <rte_ethdev_driver.h>
6 #include <rte_ethdev_pci.h>
7 #include <rte_malloc.h>
8 #include <rte_memzone.h>
9 #include <rte_string_fns.h>
11 #include <rte_spinlock.h>
12 #include <rte_kvargs.h>
15 #include "base/fm10k_api.h"
17 /* Default delay to acquire mailbox lock */
18 #define FM10K_MBXLOCK_DELAY_US 20
19 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
21 #define MAIN_VSI_POOL_NUMBER 0
23 /* Max try times to acquire switch status */
24 #define MAX_QUERY_SWITCH_STATE_TIMES 10
25 /* Wait interval to get switch status */
26 #define WAIT_SWITCH_MSG_US 100000
27 /* A period of quiescence for switch */
28 #define FM10K_SWITCH_QUIESCE_US 100000
29 /* Number of chars per uint32 type */
30 #define CHARS_PER_UINT32 (sizeof(uint32_t))
31 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
33 /* default 1:1 map from queue ID to interrupt vector ID */
34 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
36 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
37 #define MAX_LPORT_NUM 128
38 #define GLORT_FD_Q_BASE 0x40
39 #define GLORT_PF_MASK 0xFFC0
40 #define GLORT_FD_MASK GLORT_PF_MASK
41 #define GLORT_FD_INDEX GLORT_FD_Q_BASE
43 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
44 static int fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
45 static int fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
46 static int fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
47 static int fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
48 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
50 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
51 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
52 const u8 *mac, bool add, uint32_t pool);
53 static void fm10k_tx_queue_release(void *queue);
54 static void fm10k_rx_queue_release(void *queue);
55 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
56 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
57 static int fm10k_check_ftag(struct rte_devargs *devargs);
58 static int fm10k_link_update(struct rte_eth_dev *dev, int wait_to_complete);
60 static int fm10k_dev_infos_get(struct rte_eth_dev *dev,
61 struct rte_eth_dev_info *dev_info);
62 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev);
63 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev);
64 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev);
65 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev);
67 struct fm10k_xstats_name_off {
68 char name[RTE_ETH_XSTATS_NAME_SIZE];
72 static const struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
73 {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
74 {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
75 {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
76 {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
77 {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
78 {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
79 {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
80 {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
84 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
85 sizeof(fm10k_hw_stats_strings[0]))
87 static const struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
88 {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
89 {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
90 {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
93 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
94 sizeof(fm10k_hw_stats_rx_q_strings[0]))
96 static const struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
97 {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
98 {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
101 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
102 sizeof(fm10k_hw_stats_tx_q_strings[0]))
104 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
105 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
107 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
110 fm10k_mbx_initlock(struct fm10k_hw *hw)
112 rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
116 fm10k_mbx_lock(struct fm10k_hw *hw)
118 while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
119 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
123 fm10k_mbx_unlock(struct fm10k_hw *hw)
125 rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
128 /* Stubs needed for linkage when vPMD is disabled */
130 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
137 __rte_unused void *rx_queue,
138 __rte_unused struct rte_mbuf **rx_pkts,
139 __rte_unused uint16_t nb_pkts)
145 fm10k_recv_scattered_pkts_vec(
146 __rte_unused void *rx_queue,
147 __rte_unused struct rte_mbuf **rx_pkts,
148 __rte_unused uint16_t nb_pkts)
154 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
161 fm10k_rx_queue_release_mbufs_vec(
162 __rte_unused struct fm10k_rx_queue *rxq)
168 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
174 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
180 fm10k_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
181 __rte_unused struct rte_mbuf **tx_pkts,
182 __rte_unused uint16_t nb_pkts)
188 * reset queue to initial state, allocate software buffers used when starting
190 * return 0 on success
191 * return -ENOMEM if buffers cannot be allocated
192 * return -EINVAL if buffers do not satisfy alignment condition
195 rx_queue_reset(struct fm10k_rx_queue *q)
197 static const union fm10k_rx_desc zero = {{0} };
200 PMD_INIT_FUNC_TRACE();
202 diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
206 for (i = 0; i < q->nb_desc; ++i) {
207 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
208 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
209 rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
213 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
214 q->hw_ring[i].q.pkt_addr = dma_addr;
215 q->hw_ring[i].q.hdr_addr = dma_addr;
218 /* initialize extra software ring entries. Space for these extra
219 * entries is always allocated.
221 memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
222 for (i = 0; i < q->nb_fake_desc; ++i) {
223 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
224 q->hw_ring[q->nb_desc + i] = zero;
229 q->next_trigger = q->alloc_thresh - 1;
230 FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
231 q->rxrearm_start = 0;
238 * clean queue, descriptor rings, free software buffers used when stopping
242 rx_queue_clean(struct fm10k_rx_queue *q)
244 union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
246 PMD_INIT_FUNC_TRACE();
248 /* zero descriptor rings */
249 for (i = 0; i < q->nb_desc; ++i)
250 q->hw_ring[i] = zero;
252 /* zero faked descriptors */
253 for (i = 0; i < q->nb_fake_desc; ++i)
254 q->hw_ring[q->nb_desc + i] = zero;
256 /* vPMD driver has a different way of releasing mbufs. */
257 if (q->rx_using_sse) {
258 fm10k_rx_queue_release_mbufs_vec(q);
262 /* free software buffers */
263 for (i = 0; i < q->nb_desc; ++i) {
265 rte_pktmbuf_free_seg(q->sw_ring[i]);
266 q->sw_ring[i] = NULL;
272 * free all queue memory used when releasing the queue (i.e. configure)
275 rx_queue_free(struct fm10k_rx_queue *q)
277 PMD_INIT_FUNC_TRACE();
279 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
282 rte_free(q->sw_ring);
291 * disable RX queue, wait unitl HW finished necessary flush operation
294 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
298 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
299 FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
300 reg & ~FM10K_RXQCTL_ENABLE);
302 /* Wait 100us at most */
303 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
305 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
306 if (!(reg & FM10K_RXQCTL_ENABLE))
310 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
317 * reset queue to initial state, allocate software buffers used when starting
321 tx_queue_reset(struct fm10k_tx_queue *q)
323 PMD_INIT_FUNC_TRACE();
327 q->nb_free = q->nb_desc - 1;
328 fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
329 FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
333 * clean queue, descriptor rings, free software buffers used when stopping
337 tx_queue_clean(struct fm10k_tx_queue *q)
339 struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
341 PMD_INIT_FUNC_TRACE();
343 /* zero descriptor rings */
344 for (i = 0; i < q->nb_desc; ++i)
345 q->hw_ring[i] = zero;
347 /* free software buffers */
348 for (i = 0; i < q->nb_desc; ++i) {
350 rte_pktmbuf_free_seg(q->sw_ring[i]);
351 q->sw_ring[i] = NULL;
357 * free all queue memory used when releasing the queue (i.e. configure)
360 tx_queue_free(struct fm10k_tx_queue *q)
362 PMD_INIT_FUNC_TRACE();
364 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
366 if (q->rs_tracker.list) {
367 rte_free(q->rs_tracker.list);
368 q->rs_tracker.list = NULL;
371 rte_free(q->sw_ring);
380 * disable TX queue, wait unitl HW finished necessary flush operation
383 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
387 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
388 FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
389 reg & ~FM10K_TXDCTL_ENABLE);
391 /* Wait 100us at most */
392 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
394 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
395 if (!(reg & FM10K_TXDCTL_ENABLE))
399 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
406 fm10k_check_mq_mode(struct rte_eth_dev *dev)
408 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
409 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
410 struct rte_eth_vmdq_rx_conf *vmdq_conf;
411 uint16_t nb_rx_q = dev->data->nb_rx_queues;
413 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
415 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
416 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
420 if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
423 if (hw->mac.type == fm10k_mac_vf) {
424 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
428 /* Check VMDQ queue pool number */
429 if (vmdq_conf->nb_queue_pools >
430 sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
431 vmdq_conf->nb_queue_pools > nb_rx_q) {
432 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
433 vmdq_conf->nb_queue_pools);
440 static const struct fm10k_txq_ops def_txq_ops = {
441 .reset = tx_queue_reset,
445 fm10k_dev_configure(struct rte_eth_dev *dev)
449 PMD_INIT_FUNC_TRACE();
451 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
452 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
454 /* multipe queue mode checking */
455 ret = fm10k_check_mq_mode(dev);
457 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
462 dev->data->scattered_rx = 0;
468 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
470 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
471 struct rte_eth_vmdq_rx_conf *vmdq_conf;
474 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
476 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
477 if (!vmdq_conf->pool_map[i].pools)
480 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
481 fm10k_mbx_unlock(hw);
486 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
488 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
490 /* Add default mac address */
491 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
492 MAIN_VSI_POOL_NUMBER);
496 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
498 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
499 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
500 uint32_t mrqc, *key, i, reta, j;
503 #define RSS_KEY_SIZE 40
504 static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
505 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
506 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
507 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
508 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
509 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
512 if (dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
513 dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
514 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
518 /* random key is rss_intel_key (default) or user provided (rss_key) */
519 if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
520 key = (uint32_t *)rss_intel_key;
522 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
524 /* Now fill our hash function seeds, 4 bytes at a time */
525 for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
526 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
529 * Fill in redirection table
530 * The byte-swap is needed because NIC registers are in
531 * little-endian order.
534 for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
535 if (j == dev->data->nb_rx_queues)
537 reta = (reta << CHAR_BIT) | j;
539 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
544 * Generate RSS hash based on packet types, TCP/UDP
545 * port numbers and/or IPv4/v6 src and dst addresses
547 hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
549 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
550 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
551 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
552 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
553 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
554 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
555 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
556 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
557 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
560 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
565 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
569 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
571 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
574 for (i = 0; i < nb_lport_new; i++) {
575 /* Set unicast mode by default. App can change
576 * to other mode in other API func.
579 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
580 FM10K_XCAST_MODE_NONE);
581 fm10k_mbx_unlock(hw);
586 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
588 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
589 struct rte_eth_vmdq_rx_conf *vmdq_conf;
590 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
591 struct fm10k_macvlan_filter_info *macvlan;
592 uint16_t nb_queue_pools = 0; /* pool number in configuration */
593 uint16_t nb_lport_new;
595 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
596 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
598 fm10k_dev_rss_configure(dev);
600 /* only PF supports VMDQ */
601 if (hw->mac.type != fm10k_mac_pf)
604 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
605 nb_queue_pools = vmdq_conf->nb_queue_pools;
607 /* no pool number change, no need to update logic port and VLAN/MAC */
608 if (macvlan->nb_queue_pools == nb_queue_pools)
611 nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
612 fm10k_dev_logic_port_update(dev, nb_lport_new);
614 /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
615 memset(dev->data->mac_addrs, 0,
616 RTE_ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
617 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
618 &dev->data->mac_addrs[0]);
619 memset(macvlan, 0, sizeof(*macvlan));
620 macvlan->nb_queue_pools = nb_queue_pools;
623 fm10k_dev_vmdq_rx_configure(dev);
625 fm10k_dev_pf_main_vsi_reset(dev);
629 fm10k_dev_tx_init(struct rte_eth_dev *dev)
631 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
633 struct fm10k_tx_queue *txq;
637 /* Disable TXINT to avoid possible interrupt */
638 for (i = 0; i < hw->mac.max_queues; i++)
639 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
640 3 << FM10K_TXINT_TIMER_SHIFT);
643 for (i = 0; i < dev->data->nb_tx_queues; ++i) {
644 txq = dev->data->tx_queues[i];
645 base_addr = txq->hw_ring_phys_addr;
646 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
648 /* disable queue to avoid issues while updating state */
649 ret = tx_queue_disable(hw, i);
651 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
654 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
655 * register is read-only for VF.
657 if (fm10k_check_ftag(dev->device->devargs)) {
658 if (hw->mac.type == fm10k_mac_pf) {
659 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
660 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
661 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
663 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
668 /* set location and size for descriptor ring */
669 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
670 base_addr & UINT64_LOWER_32BITS_MASK);
671 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
672 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
673 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
675 /* assign default SGLORT for each TX queue by PF */
676 if (hw->mac.type == fm10k_mac_pf)
677 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
680 /* set up vector or scalar TX function as appropriate */
681 fm10k_set_tx_function(dev);
687 fm10k_dev_rx_init(struct rte_eth_dev *dev)
689 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
690 struct fm10k_macvlan_filter_info *macvlan;
691 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
692 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
694 struct fm10k_rx_queue *rxq;
697 uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
698 uint32_t logic_port = hw->mac.dglort_map;
700 uint16_t queue_stride = 0;
702 /* enable RXINT for interrupt mode */
704 if (rte_intr_dp_is_en(intr_handle)) {
705 for (; i < dev->data->nb_rx_queues; i++) {
706 FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
707 if (hw->mac.type == fm10k_mac_pf)
708 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
710 FM10K_ITR_MASK_CLEAR);
712 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
714 FM10K_ITR_MASK_CLEAR);
717 /* Disable other RXINT to avoid possible interrupt */
718 for (; i < hw->mac.max_queues; i++)
719 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
720 3 << FM10K_RXINT_TIMER_SHIFT);
722 /* Setup RX queues */
723 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
724 rxq = dev->data->rx_queues[i];
725 base_addr = rxq->hw_ring_phys_addr;
726 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
728 /* disable queue to avoid issues while updating state */
729 ret = rx_queue_disable(hw, i);
731 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
735 /* Setup the Base and Length of the Rx Descriptor Ring */
736 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
737 base_addr & UINT64_LOWER_32BITS_MASK);
738 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
739 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
740 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
742 /* Configure the Rx buffer size for one buff without split */
743 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
744 RTE_PKTMBUF_HEADROOM);
745 /* As RX buffer is aligned to 512B within mbuf, some bytes are
746 * reserved for this purpose, and the worst case could be 511B.
747 * But SRR reg assumes all buffers have the same size. In order
748 * to fill the gap, we'll have to consider the worst case and
749 * assume 512B is reserved. If we don't do so, it's possible
750 * for HW to overwrite data to next mbuf.
752 buf_size -= FM10K_RX_DATABUF_ALIGN;
754 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
755 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
756 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
758 /* It adds dual VLAN length for supporting dual VLAN */
759 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
760 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
761 rxq->offloads & DEV_RX_OFFLOAD_SCATTER) {
763 dev->data->scattered_rx = 1;
764 reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
765 reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
766 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
769 /* Enable drop on empty, it's RO for VF */
770 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
771 rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
773 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
774 FM10K_WRITE_FLUSH(hw);
777 /* Configure VMDQ/RSS if applicable */
778 fm10k_dev_mq_rx_configure(dev);
780 /* Decide the best RX function */
781 fm10k_set_rx_function(dev);
783 /* update RX_SGLORT for loopback suppress*/
784 if (hw->mac.type != fm10k_mac_pf)
786 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
787 if (macvlan->nb_queue_pools)
788 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
789 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
790 if (i && queue_stride && !(i % queue_stride))
792 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
799 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
801 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
804 struct fm10k_rx_queue *rxq;
806 PMD_INIT_FUNC_TRACE();
808 rxq = dev->data->rx_queues[rx_queue_id];
809 err = rx_queue_reset(rxq);
810 if (err == -ENOMEM) {
811 PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
813 } else if (err == -EINVAL) {
814 PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
819 /* Setup the HW Rx Head and Tail Descriptor Pointers
820 * Note: this must be done AFTER the queue is enabled on real
821 * hardware, but BEFORE the queue is enabled when using the
822 * emulation platform. Do it in both places for now and remove
823 * this comment and the following two register writes when the
824 * emulation platform is no longer being used.
826 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
827 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
829 /* Set PF ownership flag for PF devices */
830 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
831 if (hw->mac.type == fm10k_mac_pf)
832 reg |= FM10K_RXQCTL_PF;
833 reg |= FM10K_RXQCTL_ENABLE;
834 /* enable RX queue */
835 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
836 FM10K_WRITE_FLUSH(hw);
838 /* Setup the HW Rx Head and Tail Descriptor Pointers
839 * Note: this must be done AFTER the queue is enabled
841 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
842 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
843 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
849 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
851 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
853 PMD_INIT_FUNC_TRACE();
855 /* Disable RX queue */
856 rx_queue_disable(hw, rx_queue_id);
858 /* Free mbuf and clean HW ring */
859 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
860 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
866 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
868 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
869 /** @todo - this should be defined in the shared code */
870 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY 0x00010000
871 uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
872 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
874 PMD_INIT_FUNC_TRACE();
878 /* reset head and tail pointers */
879 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
880 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
882 /* enable TX queue */
883 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
884 FM10K_TXDCTL_ENABLE | txdctl);
885 FM10K_WRITE_FLUSH(hw);
886 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
892 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
894 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
896 PMD_INIT_FUNC_TRACE();
898 tx_queue_disable(hw, tx_queue_id);
899 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
900 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
905 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
907 return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
908 != FM10K_DGLORTMAP_NONE);
912 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
914 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
917 PMD_INIT_FUNC_TRACE();
919 /* Return if it didn't acquire valid glort range */
920 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
924 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
925 FM10K_XCAST_MODE_PROMISC);
926 fm10k_mbx_unlock(hw);
928 if (status != FM10K_SUCCESS) {
929 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
937 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
939 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
943 PMD_INIT_FUNC_TRACE();
945 /* Return if it didn't acquire valid glort range */
946 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
949 if (dev->data->all_multicast == 1)
950 mode = FM10K_XCAST_MODE_ALLMULTI;
952 mode = FM10K_XCAST_MODE_NONE;
955 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
957 fm10k_mbx_unlock(hw);
959 if (status != FM10K_SUCCESS) {
960 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
968 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
970 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 PMD_INIT_FUNC_TRACE();
975 /* Return if it didn't acquire valid glort range */
976 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
979 /* If promiscuous mode is enabled, it doesn't make sense to enable
980 * allmulticast and disable promiscuous since fm10k only can select
983 if (dev->data->promiscuous) {
984 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
985 "needn't enable allmulticast");
990 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
991 FM10K_XCAST_MODE_ALLMULTI);
992 fm10k_mbx_unlock(hw);
994 if (status != FM10K_SUCCESS) {
995 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1003 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1005 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1008 PMD_INIT_FUNC_TRACE();
1010 /* Return if it didn't acquire valid glort range */
1011 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1014 if (dev->data->promiscuous) {
1015 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1016 "since promisc mode is enabled");
1021 /* Change mode to unicast mode */
1022 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1023 FM10K_XCAST_MODE_NONE);
1024 fm10k_mbx_unlock(hw);
1026 if (status != FM10K_SUCCESS) {
1027 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1035 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1037 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038 uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1039 uint16_t nb_queue_pools;
1040 struct fm10k_macvlan_filter_info *macvlan;
1042 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1043 nb_queue_pools = macvlan->nb_queue_pools;
1044 pool_len = nb_queue_pools ? rte_fls_u32(nb_queue_pools - 1) : 0;
1045 rss_len = rte_fls_u32(dev->data->nb_rx_queues - 1) - pool_len;
1047 /* GLORT 0x0-0x3F are used by PF and VMDQ, 0x40-0x7F used by FD */
1048 dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1049 dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1051 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1052 /* Configure VMDQ/RSS DGlort Decoder */
1053 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1055 /* Flow Director configurations, only queue number is valid. */
1056 dglortdec = rte_fls_u32(dev->data->nb_rx_queues - 1);
1057 dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1058 (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1059 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1060 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1062 /* Invalidate all other GLORT entries */
1063 for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1064 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1065 FM10K_DGLORTMAP_NONE);
1068 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1070 fm10k_dev_start(struct rte_eth_dev *dev)
1072 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1075 PMD_INIT_FUNC_TRACE();
1077 /* stop, init, then start the hw */
1078 diag = fm10k_stop_hw(hw);
1079 if (diag != FM10K_SUCCESS) {
1080 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1084 diag = fm10k_init_hw(hw);
1085 if (diag != FM10K_SUCCESS) {
1086 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1090 diag = fm10k_start_hw(hw);
1091 if (diag != FM10K_SUCCESS) {
1092 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1096 diag = fm10k_dev_tx_init(dev);
1098 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1102 if (fm10k_dev_rxq_interrupt_setup(dev))
1105 diag = fm10k_dev_rx_init(dev);
1107 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1111 if (hw->mac.type == fm10k_mac_pf)
1112 fm10k_dev_dglort_map_configure(dev);
1114 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1115 struct fm10k_rx_queue *rxq;
1116 rxq = dev->data->rx_queues[i];
1118 if (rxq->rx_deferred_start)
1120 diag = fm10k_dev_rx_queue_start(dev, i);
1123 for (j = 0; j < i; ++j)
1124 rx_queue_clean(dev->data->rx_queues[j]);
1129 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1130 struct fm10k_tx_queue *txq;
1131 txq = dev->data->tx_queues[i];
1133 if (txq->tx_deferred_start)
1135 diag = fm10k_dev_tx_queue_start(dev, i);
1138 for (j = 0; j < i; ++j)
1139 tx_queue_clean(dev->data->tx_queues[j]);
1140 for (j = 0; j < dev->data->nb_rx_queues; ++j)
1141 rx_queue_clean(dev->data->rx_queues[j]);
1146 /* Update default vlan when not in VMDQ mode */
1147 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1148 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1150 fm10k_link_update(dev, 0);
1156 fm10k_dev_stop(struct rte_eth_dev *dev)
1158 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1160 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1163 PMD_INIT_FUNC_TRACE();
1165 if (dev->data->tx_queues)
1166 for (i = 0; i < dev->data->nb_tx_queues; i++)
1167 fm10k_dev_tx_queue_stop(dev, i);
1169 if (dev->data->rx_queues)
1170 for (i = 0; i < dev->data->nb_rx_queues; i++)
1171 fm10k_dev_rx_queue_stop(dev, i);
1173 /* Disable datapath event */
1174 if (rte_intr_dp_is_en(intr_handle)) {
1175 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1176 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1177 3 << FM10K_RXINT_TIMER_SHIFT);
1178 if (hw->mac.type == fm10k_mac_pf)
1179 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1180 FM10K_ITR_MASK_SET);
1182 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1183 FM10K_ITR_MASK_SET);
1186 /* Clean datapath event and queue/vec mapping */
1187 rte_intr_efd_disable(intr_handle);
1188 rte_free(intr_handle->intr_vec);
1189 intr_handle->intr_vec = NULL;
1193 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1197 PMD_INIT_FUNC_TRACE();
1199 if (dev->data->tx_queues) {
1200 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1201 struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1207 if (dev->data->rx_queues) {
1208 for (i = 0; i < dev->data->nb_rx_queues; i++)
1209 fm10k_rx_queue_release(dev->data->rx_queues[i]);
1214 fm10k_link_update(struct rte_eth_dev *dev,
1215 __rte_unused int wait_to_complete)
1217 struct fm10k_dev_info *dev_info =
1218 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1219 PMD_INIT_FUNC_TRACE();
1221 dev->data->dev_link.link_speed = ETH_SPEED_NUM_50G;
1222 dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1223 dev->data->dev_link.link_status =
1224 dev_info->sm_down ? ETH_LINK_DOWN : ETH_LINK_UP;
1225 dev->data->dev_link.link_autoneg = ETH_LINK_FIXED;
1230 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1231 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1236 if (xstats_names != NULL) {
1237 /* Note: limit checked in rte_eth_xstats_names() */
1240 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1241 snprintf(xstats_names[count].name,
1242 sizeof(xstats_names[count].name),
1243 "%s", fm10k_hw_stats_strings[count].name);
1247 /* PF queue stats */
1248 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1249 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1250 snprintf(xstats_names[count].name,
1251 sizeof(xstats_names[count].name),
1253 fm10k_hw_stats_rx_q_strings[i].name);
1256 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1257 snprintf(xstats_names[count].name,
1258 sizeof(xstats_names[count].name),
1260 fm10k_hw_stats_tx_q_strings[i].name);
1265 return FM10K_NB_XSTATS;
1269 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1272 struct fm10k_hw_stats *hw_stats =
1273 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1274 unsigned i, q, count = 0;
1276 if (n < FM10K_NB_XSTATS)
1277 return FM10K_NB_XSTATS;
1280 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1281 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1282 fm10k_hw_stats_strings[count].offset);
1283 xstats[count].id = count;
1287 /* PF queue stats */
1288 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1289 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1290 xstats[count].value =
1291 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1292 fm10k_hw_stats_rx_q_strings[i].offset);
1293 xstats[count].id = count;
1296 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1297 xstats[count].value =
1298 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1299 fm10k_hw_stats_tx_q_strings[i].offset);
1300 xstats[count].id = count;
1305 return FM10K_NB_XSTATS;
1309 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1311 uint64_t ipackets, opackets, ibytes, obytes, imissed;
1312 struct fm10k_hw *hw =
1313 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1314 struct fm10k_hw_stats *hw_stats =
1315 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1318 PMD_INIT_FUNC_TRACE();
1320 fm10k_update_hw_stats(hw, hw_stats);
1322 ipackets = opackets = ibytes = obytes = imissed = 0;
1323 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1324 (i < hw->mac.max_queues); ++i) {
1325 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1326 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1327 stats->q_ibytes[i] = hw_stats->q[i].rx_bytes.count;
1328 stats->q_obytes[i] = hw_stats->q[i].tx_bytes.count;
1329 stats->q_errors[i] = hw_stats->q[i].rx_drops.count;
1330 ipackets += stats->q_ipackets[i];
1331 opackets += stats->q_opackets[i];
1332 ibytes += stats->q_ibytes[i];
1333 obytes += stats->q_obytes[i];
1334 imissed += stats->q_errors[i];
1336 stats->ipackets = ipackets;
1337 stats->opackets = opackets;
1338 stats->ibytes = ibytes;
1339 stats->obytes = obytes;
1340 stats->imissed = imissed;
1345 fm10k_stats_reset(struct rte_eth_dev *dev)
1347 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348 struct fm10k_hw_stats *hw_stats =
1349 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1351 PMD_INIT_FUNC_TRACE();
1353 memset(hw_stats, 0, sizeof(*hw_stats));
1354 fm10k_rebind_hw_stats(hw, hw_stats);
1360 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1361 struct rte_eth_dev_info *dev_info)
1363 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1366 PMD_INIT_FUNC_TRACE();
1368 dev_info->min_rx_bufsize = FM10K_MIN_RX_BUF_SIZE;
1369 dev_info->max_rx_pktlen = FM10K_MAX_PKT_SIZE;
1370 dev_info->max_rx_queues = hw->mac.max_queues;
1371 dev_info->max_tx_queues = hw->mac.max_queues;
1372 dev_info->max_mac_addrs = FM10K_MAX_MACADDR_NUM;
1373 dev_info->max_hash_mac_addrs = 0;
1374 dev_info->max_vfs = pdev->max_vfs;
1375 dev_info->vmdq_pool_base = 0;
1376 dev_info->vmdq_queue_base = 0;
1377 dev_info->max_vmdq_pools = ETH_32_POOLS;
1378 dev_info->vmdq_queue_num = FM10K_MAX_QUEUES_PF;
1379 dev_info->rx_queue_offload_capa = fm10k_get_rx_queue_offloads_capa(dev);
1380 dev_info->rx_offload_capa = fm10k_get_rx_port_offloads_capa(dev) |
1381 dev_info->rx_queue_offload_capa;
1382 dev_info->tx_queue_offload_capa = fm10k_get_tx_queue_offloads_capa(dev);
1383 dev_info->tx_offload_capa = fm10k_get_tx_port_offloads_capa(dev) |
1384 dev_info->tx_queue_offload_capa;
1386 dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1387 dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1388 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1391 ETH_RSS_NONFRAG_IPV4_TCP |
1392 ETH_RSS_NONFRAG_IPV6_TCP |
1393 ETH_RSS_IPV6_TCP_EX |
1394 ETH_RSS_NONFRAG_IPV4_UDP |
1395 ETH_RSS_NONFRAG_IPV6_UDP |
1396 ETH_RSS_IPV6_UDP_EX;
1398 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1400 .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1401 .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1402 .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1404 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1409 dev_info->default_txconf = (struct rte_eth_txconf) {
1411 .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1412 .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1413 .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1415 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1416 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1420 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1421 .nb_max = FM10K_MAX_RX_DESC,
1422 .nb_min = FM10K_MIN_RX_DESC,
1423 .nb_align = FM10K_MULT_RX_DESC,
1426 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1427 .nb_max = FM10K_MAX_TX_DESC,
1428 .nb_min = FM10K_MIN_TX_DESC,
1429 .nb_align = FM10K_MULT_TX_DESC,
1430 .nb_seg_max = FM10K_TX_MAX_SEG,
1431 .nb_mtu_seg_max = FM10K_TX_MAX_MTU_SEG,
1434 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1435 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1436 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1441 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1442 static const uint32_t *
1443 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1445 if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1446 dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1447 static uint32_t ptypes[] = {
1448 /* refers to rx_desc_to_ol_flags() */
1451 RTE_PTYPE_L3_IPV4_EXT,
1453 RTE_PTYPE_L3_IPV6_EXT,
1460 } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1461 dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1462 static uint32_t ptypes_vec[] = {
1463 /* refers to fm10k_desc_to_pktype_v() */
1465 RTE_PTYPE_L3_IPV4_EXT,
1467 RTE_PTYPE_L3_IPV6_EXT,
1470 RTE_PTYPE_TUNNEL_GENEVE,
1471 RTE_PTYPE_TUNNEL_NVGRE,
1472 RTE_PTYPE_TUNNEL_VXLAN,
1473 RTE_PTYPE_TUNNEL_GRE,
1483 static const uint32_t *
1484 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1491 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1494 uint16_t mac_num = 0;
1495 uint32_t vid_idx, vid_bit, mac_index;
1496 struct fm10k_hw *hw;
1497 struct fm10k_macvlan_filter_info *macvlan;
1498 struct rte_eth_dev_data *data = dev->data;
1500 hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1501 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1503 if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1504 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1508 if (vlan_id > ETH_VLAN_ID_MAX) {
1509 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1513 vid_idx = FM10K_VFTA_IDX(vlan_id);
1514 vid_bit = FM10K_VFTA_BIT(vlan_id);
1515 /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1516 if (on && (macvlan->vfta[vid_idx] & vid_bit))
1518 /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1519 if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1520 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1521 "in the VLAN filter table");
1526 result = fm10k_update_vlan(hw, vlan_id, 0, on);
1527 fm10k_mbx_unlock(hw);
1528 if (result != FM10K_SUCCESS) {
1529 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1533 for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1534 (result == FM10K_SUCCESS); mac_index++) {
1535 if (rte_is_zero_ether_addr(&data->mac_addrs[mac_index]))
1537 if (mac_num > macvlan->mac_num - 1) {
1538 PMD_INIT_LOG(ERR, "MAC address number "
1543 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1544 data->mac_addrs[mac_index].addr_bytes,
1546 fm10k_mbx_unlock(hw);
1549 if (result != FM10K_SUCCESS) {
1550 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1555 macvlan->vlan_num++;
1556 macvlan->vfta[vid_idx] |= vid_bit;
1558 macvlan->vlan_num--;
1559 macvlan->vfta[vid_idx] &= ~vid_bit;
1565 fm10k_vlan_offload_set(struct rte_eth_dev *dev __rte_unused,
1566 int mask __rte_unused)
1571 /* Add/Remove a MAC address, and update filters to main VSI */
1572 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1573 const u8 *mac, bool add, uint32_t pool)
1575 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576 struct fm10k_macvlan_filter_info *macvlan;
1579 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1581 if (pool != MAIN_VSI_POOL_NUMBER) {
1582 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1583 "mac to pool %u", pool);
1586 for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1587 if (!macvlan->vfta[j])
1589 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1590 if (!(macvlan->vfta[j] & (1 << k)))
1592 if (i + 1 > macvlan->vlan_num) {
1593 PMD_INIT_LOG(ERR, "vlan number not match");
1597 fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1598 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1599 fm10k_mbx_unlock(hw);
1605 /* Add/Remove a MAC address, and update filters to VMDQ */
1606 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1607 const u8 *mac, bool add, uint32_t pool)
1609 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610 struct fm10k_macvlan_filter_info *macvlan;
1611 struct rte_eth_vmdq_rx_conf *vmdq_conf;
1614 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1615 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1617 if (pool > macvlan->nb_queue_pools) {
1618 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1620 pool, macvlan->nb_queue_pools);
1623 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1624 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1627 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1628 vmdq_conf->pool_map[i].vlan_id, add, 0);
1629 fm10k_mbx_unlock(hw);
1633 /* Add/Remove a MAC address, and update filters */
1634 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1635 const u8 *mac, bool add, uint32_t pool)
1637 struct fm10k_macvlan_filter_info *macvlan;
1639 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1641 if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1642 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1644 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1652 /* Add a MAC address, and update filters */
1654 fm10k_macaddr_add(struct rte_eth_dev *dev,
1655 struct rte_ether_addr *mac_addr,
1659 struct fm10k_macvlan_filter_info *macvlan;
1661 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1662 fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1663 macvlan->mac_vmdq_id[index] = pool;
1667 /* Remove a MAC address, and update filters */
1669 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1671 struct rte_eth_dev_data *data = dev->data;
1672 struct fm10k_macvlan_filter_info *macvlan;
1674 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1675 fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1676 FALSE, macvlan->mac_vmdq_id[index]);
1677 macvlan->mac_vmdq_id[index] = 0;
1681 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1683 if ((request < min) || (request > max) || ((request % mult) != 0))
1691 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1693 if ((request < min) || (request > max) || ((div % request) != 0))
1700 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1702 uint16_t rx_free_thresh;
1704 if (conf->rx_free_thresh == 0)
1705 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1707 rx_free_thresh = conf->rx_free_thresh;
1709 /* make sure the requested threshold satisfies the constraints */
1710 if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1711 FM10K_RX_FREE_THRESH_MAX(q),
1712 FM10K_RX_FREE_THRESH_DIV(q),
1714 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1715 "less than or equal to %u, "
1716 "greater than or equal to %u, "
1717 "and a divisor of %u",
1718 rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1719 FM10K_RX_FREE_THRESH_MIN(q),
1720 FM10K_RX_FREE_THRESH_DIV(q));
1724 q->alloc_thresh = rx_free_thresh;
1725 q->drop_en = conf->rx_drop_en;
1726 q->rx_deferred_start = conf->rx_deferred_start;
1732 * Hardware requires specific alignment for Rx packet buffers. At
1733 * least one of the following two conditions must be satisfied.
1734 * 1. Address is 512B aligned
1735 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
1737 * As such, the driver may need to adjust the DMA address within the
1738 * buffer by up to 512B.
1740 * return 1 if the element size is valid, otherwise return 0.
1743 mempool_element_size_valid(struct rte_mempool *mp)
1747 /* elt_size includes mbuf header and headroom */
1748 min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1749 RTE_PKTMBUF_HEADROOM;
1751 /* account for up to 512B of alignment */
1752 min_size -= FM10K_RX_DATABUF_ALIGN;
1754 /* sanity check for overflow */
1755 if (min_size > mp->elt_size)
1762 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev)
1766 return (uint64_t)(DEV_RX_OFFLOAD_SCATTER);
1769 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)
1773 return (uint64_t)(DEV_RX_OFFLOAD_VLAN_STRIP |
1774 DEV_RX_OFFLOAD_VLAN_FILTER |
1775 DEV_RX_OFFLOAD_IPV4_CKSUM |
1776 DEV_RX_OFFLOAD_UDP_CKSUM |
1777 DEV_RX_OFFLOAD_TCP_CKSUM |
1778 DEV_RX_OFFLOAD_JUMBO_FRAME |
1779 DEV_RX_OFFLOAD_HEADER_SPLIT |
1780 DEV_RX_OFFLOAD_RSS_HASH);
1784 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1785 uint16_t nb_desc, unsigned int socket_id,
1786 const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1788 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789 struct fm10k_dev_info *dev_info =
1790 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1791 struct fm10k_rx_queue *q;
1792 const struct rte_memzone *mz;
1795 PMD_INIT_FUNC_TRACE();
1797 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1799 /* make sure the mempool element size can account for alignment. */
1800 if (!mempool_element_size_valid(mp)) {
1801 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1805 /* make sure a valid number of descriptors have been requested */
1806 if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1807 FM10K_MULT_RX_DESC, nb_desc)) {
1808 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1809 "less than or equal to %"PRIu32", "
1810 "greater than or equal to %u, "
1811 "and a multiple of %u",
1812 nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1813 FM10K_MULT_RX_DESC);
1818 * if this queue existed already, free the associated memory. The
1819 * queue cannot be reused in case we need to allocate memory on
1820 * different socket than was previously used.
1822 if (dev->data->rx_queues[queue_id] != NULL) {
1823 rx_queue_free(dev->data->rx_queues[queue_id]);
1824 dev->data->rx_queues[queue_id] = NULL;
1827 /* allocate memory for the queue structure */
1828 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1831 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1837 q->nb_desc = nb_desc;
1838 q->nb_fake_desc = FM10K_MULT_RX_DESC;
1839 q->port_id = dev->data->port_id;
1840 q->queue_id = queue_id;
1841 q->tail_ptr = (volatile uint32_t *)
1842 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1843 q->offloads = offloads;
1844 if (handle_rxconf(q, conf)) {
1848 /* allocate memory for the software ring */
1849 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1850 (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1851 RTE_CACHE_LINE_SIZE, socket_id);
1852 if (q->sw_ring == NULL) {
1853 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1859 * allocate memory for the hardware descriptor ring. A memzone large
1860 * enough to hold the maximum ring size is requested to allow for
1861 * resizing in later calls to the queue setup function.
1863 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1864 FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1867 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1868 rte_free(q->sw_ring);
1872 q->hw_ring = mz->addr;
1873 q->hw_ring_phys_addr = mz->iova;
1875 /* Check if number of descs satisfied Vector requirement */
1876 if (!rte_is_power_of_2(nb_desc)) {
1877 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1878 "preconditions - canceling the feature for "
1879 "the whole port[%d]",
1880 q->queue_id, q->port_id);
1881 dev_info->rx_vec_allowed = false;
1883 fm10k_rxq_vec_setup(q);
1885 dev->data->rx_queues[queue_id] = q;
1890 fm10k_rx_queue_release(void *queue)
1892 PMD_INIT_FUNC_TRACE();
1894 rx_queue_free(queue);
1898 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1900 uint16_t tx_free_thresh;
1901 uint16_t tx_rs_thresh;
1903 /* constraint MACROs require that tx_free_thresh is configured
1904 * before tx_rs_thresh */
1905 if (conf->tx_free_thresh == 0)
1906 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1908 tx_free_thresh = conf->tx_free_thresh;
1910 /* make sure the requested threshold satisfies the constraints */
1911 if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1912 FM10K_TX_FREE_THRESH_MAX(q),
1913 FM10K_TX_FREE_THRESH_DIV(q),
1915 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1916 "less than or equal to %u, "
1917 "greater than or equal to %u, "
1918 "and a divisor of %u",
1919 tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1920 FM10K_TX_FREE_THRESH_MIN(q),
1921 FM10K_TX_FREE_THRESH_DIV(q));
1925 q->free_thresh = tx_free_thresh;
1927 if (conf->tx_rs_thresh == 0)
1928 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1930 tx_rs_thresh = conf->tx_rs_thresh;
1932 q->tx_deferred_start = conf->tx_deferred_start;
1934 /* make sure the requested threshold satisfies the constraints */
1935 if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1936 FM10K_TX_RS_THRESH_MAX(q),
1937 FM10K_TX_RS_THRESH_DIV(q),
1939 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1940 "less than or equal to %u, "
1941 "greater than or equal to %u, "
1942 "and a divisor of %u",
1943 tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1944 FM10K_TX_RS_THRESH_MIN(q),
1945 FM10K_TX_RS_THRESH_DIV(q));
1949 q->rs_thresh = tx_rs_thresh;
1954 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1961 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1965 return (uint64_t)(DEV_TX_OFFLOAD_VLAN_INSERT |
1966 DEV_TX_OFFLOAD_MULTI_SEGS |
1967 DEV_TX_OFFLOAD_IPV4_CKSUM |
1968 DEV_TX_OFFLOAD_UDP_CKSUM |
1969 DEV_TX_OFFLOAD_TCP_CKSUM |
1970 DEV_TX_OFFLOAD_TCP_TSO);
1974 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1975 uint16_t nb_desc, unsigned int socket_id,
1976 const struct rte_eth_txconf *conf)
1978 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979 struct fm10k_tx_queue *q;
1980 const struct rte_memzone *mz;
1983 PMD_INIT_FUNC_TRACE();
1985 offloads = conf->offloads | dev->data->dev_conf.txmode.offloads;
1987 /* make sure a valid number of descriptors have been requested */
1988 if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1989 FM10K_MULT_TX_DESC, nb_desc)) {
1990 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1991 "less than or equal to %"PRIu32", "
1992 "greater than or equal to %u, "
1993 "and a multiple of %u",
1994 nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1995 FM10K_MULT_TX_DESC);
2000 * if this queue existed already, free the associated memory. The
2001 * queue cannot be reused in case we need to allocate memory on
2002 * different socket than was previously used.
2004 if (dev->data->tx_queues[queue_id] != NULL) {
2005 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
2008 dev->data->tx_queues[queue_id] = NULL;
2011 /* allocate memory for the queue structure */
2012 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2015 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2020 q->nb_desc = nb_desc;
2021 q->port_id = dev->data->port_id;
2022 q->queue_id = queue_id;
2023 q->offloads = offloads;
2024 q->ops = &def_txq_ops;
2025 q->tail_ptr = (volatile uint32_t *)
2026 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2027 if (handle_txconf(q, conf))
2030 /* allocate memory for the software ring */
2031 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2032 nb_desc * sizeof(struct rte_mbuf *),
2033 RTE_CACHE_LINE_SIZE, socket_id);
2034 if (q->sw_ring == NULL) {
2035 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2041 * allocate memory for the hardware descriptor ring. A memzone large
2042 * enough to hold the maximum ring size is requested to allow for
2043 * resizing in later calls to the queue setup function.
2045 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2046 FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2049 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2050 rte_free(q->sw_ring);
2054 q->hw_ring = mz->addr;
2055 q->hw_ring_phys_addr = mz->iova;
2058 * allocate memory for the RS bit tracker. Enough slots to hold the
2059 * descriptor index for each RS bit needing to be set are required.
2061 q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2062 ((nb_desc + 1) / q->rs_thresh) *
2064 RTE_CACHE_LINE_SIZE, socket_id);
2065 if (q->rs_tracker.list == NULL) {
2066 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2067 rte_free(q->sw_ring);
2072 dev->data->tx_queues[queue_id] = q;
2077 fm10k_tx_queue_release(void *queue)
2079 struct fm10k_tx_queue *q = queue;
2080 PMD_INIT_FUNC_TRACE();
2086 fm10k_reta_update(struct rte_eth_dev *dev,
2087 struct rte_eth_rss_reta_entry64 *reta_conf,
2090 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091 uint16_t i, j, idx, shift;
2095 PMD_INIT_FUNC_TRACE();
2097 if (reta_size > FM10K_MAX_RSS_INDICES) {
2098 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2099 "(%d) doesn't match the number hardware can supported "
2100 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2105 * Update Redirection Table RETA[n], n=0..31. The redirection table has
2106 * 128-entries in 32 registers
2108 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2109 idx = i / RTE_RETA_GROUP_SIZE;
2110 shift = i % RTE_RETA_GROUP_SIZE;
2111 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2112 BIT_MASK_PER_UINT32);
2117 if (mask != BIT_MASK_PER_UINT32)
2118 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2120 for (j = 0; j < CHARS_PER_UINT32; j++) {
2121 if (mask & (0x1 << j)) {
2123 reta &= ~(UINT8_MAX << CHAR_BIT * j);
2124 reta |= reta_conf[idx].reta[shift + j] <<
2128 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2135 fm10k_reta_query(struct rte_eth_dev *dev,
2136 struct rte_eth_rss_reta_entry64 *reta_conf,
2139 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2140 uint16_t i, j, idx, shift;
2144 PMD_INIT_FUNC_TRACE();
2146 if (reta_size < FM10K_MAX_RSS_INDICES) {
2147 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2148 "(%d) doesn't match the number hardware can supported "
2149 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2154 * Read Redirection Table RETA[n], n=0..31. The redirection table has
2155 * 128-entries in 32 registers
2157 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2158 idx = i / RTE_RETA_GROUP_SIZE;
2159 shift = i % RTE_RETA_GROUP_SIZE;
2160 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2161 BIT_MASK_PER_UINT32);
2165 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2166 for (j = 0; j < CHARS_PER_UINT32; j++) {
2167 if (mask & (0x1 << j))
2168 reta_conf[idx].reta[shift + j] = ((reta >>
2169 CHAR_BIT * j) & UINT8_MAX);
2177 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2178 struct rte_eth_rss_conf *rss_conf)
2180 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2181 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2183 uint64_t hf = rss_conf->rss_hf;
2186 PMD_INIT_FUNC_TRACE();
2188 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2189 FM10K_RSSRK_ENTRIES_PER_REG))
2196 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
2197 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
2198 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
2199 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
2200 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
2201 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
2202 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
2203 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
2204 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
2206 /* If the mapping doesn't fit any supported, return */
2211 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2212 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2214 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2220 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2221 struct rte_eth_rss_conf *rss_conf)
2223 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2224 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2229 PMD_INIT_FUNC_TRACE();
2231 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2232 FM10K_RSSRK_ENTRIES_PER_REG))
2236 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2237 key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2239 mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2241 hf |= (mrqc & FM10K_MRQC_IPV4) ? ETH_RSS_IPV4 : 0;
2242 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6 : 0;
2243 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6_EX : 0;
2244 hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP : 0;
2245 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP : 0;
2246 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX : 0;
2247 hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP : 0;
2248 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP : 0;
2249 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX : 0;
2251 rss_conf->rss_hf = hf;
2257 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2259 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2262 /* Bind all local non-queue interrupt to vector 0 */
2263 int_map |= FM10K_MISC_VEC_ID;
2265 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2266 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2267 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2268 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2269 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2270 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2272 /* Enable misc causes */
2273 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2274 FM10K_EIMR_ENABLE(THI_FAULT) |
2275 FM10K_EIMR_ENABLE(FUM_FAULT) |
2276 FM10K_EIMR_ENABLE(MAILBOX) |
2277 FM10K_EIMR_ENABLE(SWITCHREADY) |
2278 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2279 FM10K_EIMR_ENABLE(SRAMERROR) |
2280 FM10K_EIMR_ENABLE(VFLR));
2283 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2284 FM10K_ITR_MASK_CLEAR);
2285 FM10K_WRITE_FLUSH(hw);
2289 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2291 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2294 int_map |= FM10K_MISC_VEC_ID;
2296 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2297 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2298 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2299 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2300 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2301 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2303 /* Disable misc causes */
2304 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2305 FM10K_EIMR_DISABLE(THI_FAULT) |
2306 FM10K_EIMR_DISABLE(FUM_FAULT) |
2307 FM10K_EIMR_DISABLE(MAILBOX) |
2308 FM10K_EIMR_DISABLE(SWITCHREADY) |
2309 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2310 FM10K_EIMR_DISABLE(SRAMERROR) |
2311 FM10K_EIMR_DISABLE(VFLR));
2314 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2315 FM10K_WRITE_FLUSH(hw);
2319 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2321 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2324 /* Bind all local non-queue interrupt to vector 0 */
2325 int_map |= FM10K_MISC_VEC_ID;
2327 /* Only INT 0 available, other 15 are reserved. */
2328 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2331 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2332 FM10K_ITR_MASK_CLEAR);
2333 FM10K_WRITE_FLUSH(hw);
2337 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2339 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2342 int_map |= FM10K_MISC_VEC_ID;
2344 /* Only INT 0 available, other 15 are reserved. */
2345 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2348 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2349 FM10K_WRITE_FLUSH(hw);
2353 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2355 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2359 if (hw->mac.type == fm10k_mac_pf)
2360 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2361 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2363 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2364 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2365 rte_intr_ack(&pdev->intr_handle);
2370 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2372 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2376 if (hw->mac.type == fm10k_mac_pf)
2377 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2378 FM10K_ITR_MASK_SET);
2380 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2381 FM10K_ITR_MASK_SET);
2386 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2388 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2390 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2391 uint32_t intr_vector, vec;
2395 /* fm10k needs one separate interrupt for mailbox,
2396 * so only drivers which support multiple interrupt vectors
2397 * e.g. vfio-pci can work for fm10k interrupt mode
2399 if (!rte_intr_cap_multiple(intr_handle) ||
2400 dev->data->dev_conf.intr_conf.rxq == 0)
2403 intr_vector = dev->data->nb_rx_queues;
2405 /* disable interrupt first */
2406 rte_intr_disable(intr_handle);
2407 if (hw->mac.type == fm10k_mac_pf)
2408 fm10k_dev_disable_intr_pf(dev);
2410 fm10k_dev_disable_intr_vf(dev);
2412 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2413 PMD_INIT_LOG(ERR, "Failed to init event fd");
2417 if (rte_intr_dp_is_en(intr_handle) && !result) {
2418 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2419 dev->data->nb_rx_queues * sizeof(int), 0);
2420 if (intr_handle->intr_vec) {
2421 for (queue_id = 0, vec = FM10K_RX_VEC_START;
2422 queue_id < dev->data->nb_rx_queues;
2424 intr_handle->intr_vec[queue_id] = vec;
2425 if (vec < intr_handle->nb_efd - 1
2426 + FM10K_RX_VEC_START)
2430 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2431 " intr_vec", dev->data->nb_rx_queues);
2432 rte_intr_efd_disable(intr_handle);
2437 if (hw->mac.type == fm10k_mac_pf)
2438 fm10k_dev_enable_intr_pf(dev);
2440 fm10k_dev_enable_intr_vf(dev);
2441 rte_intr_enable(intr_handle);
2442 hw->mac.ops.update_int_moderator(hw);
2447 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2449 struct fm10k_fault fault;
2451 const char *estr = "Unknown error";
2453 /* Process PCA fault */
2454 if (eicr & FM10K_EICR_PCA_FAULT) {
2455 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2458 switch (fault.type) {
2460 estr = "PCA_NO_FAULT"; break;
2461 case PCA_UNMAPPED_ADDR:
2462 estr = "PCA_UNMAPPED_ADDR"; break;
2463 case PCA_BAD_QACCESS_PF:
2464 estr = "PCA_BAD_QACCESS_PF"; break;
2465 case PCA_BAD_QACCESS_VF:
2466 estr = "PCA_BAD_QACCESS_VF"; break;
2467 case PCA_MALICIOUS_REQ:
2468 estr = "PCA_MALICIOUS_REQ"; break;
2469 case PCA_POISONED_TLP:
2470 estr = "PCA_POISONED_TLP"; break;
2472 estr = "PCA_TLP_ABORT"; break;
2476 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2477 estr, fault.func ? "VF" : "PF", fault.func,
2478 fault.address, fault.specinfo);
2481 /* Process THI fault */
2482 if (eicr & FM10K_EICR_THI_FAULT) {
2483 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2486 switch (fault.type) {
2488 estr = "THI_NO_FAULT"; break;
2489 case THI_MAL_DIS_Q_FAULT:
2490 estr = "THI_MAL_DIS_Q_FAULT"; break;
2494 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2495 estr, fault.func ? "VF" : "PF", fault.func,
2496 fault.address, fault.specinfo);
2499 /* Process FUM fault */
2500 if (eicr & FM10K_EICR_FUM_FAULT) {
2501 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2504 switch (fault.type) {
2506 estr = "FUM_NO_FAULT"; break;
2507 case FUM_UNMAPPED_ADDR:
2508 estr = "FUM_UNMAPPED_ADDR"; break;
2509 case FUM_POISONED_TLP:
2510 estr = "FUM_POISONED_TLP"; break;
2511 case FUM_BAD_VF_QACCESS:
2512 estr = "FUM_BAD_VF_QACCESS"; break;
2513 case FUM_ADD_DECODE_ERR:
2514 estr = "FUM_ADD_DECODE_ERR"; break;
2516 estr = "FUM_RO_ERROR"; break;
2517 case FUM_QPRC_CRC_ERROR:
2518 estr = "FUM_QPRC_CRC_ERROR"; break;
2519 case FUM_CSR_TIMEOUT:
2520 estr = "FUM_CSR_TIMEOUT"; break;
2521 case FUM_INVALID_TYPE:
2522 estr = "FUM_INVALID_TYPE"; break;
2523 case FUM_INVALID_LENGTH:
2524 estr = "FUM_INVALID_LENGTH"; break;
2525 case FUM_INVALID_BE:
2526 estr = "FUM_INVALID_BE"; break;
2527 case FUM_INVALID_ALIGN:
2528 estr = "FUM_INVALID_ALIGN"; break;
2532 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2533 estr, fault.func ? "VF" : "PF", fault.func,
2534 fault.address, fault.specinfo);
2539 PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2544 * PF interrupt handler triggered by NIC for handling specific interrupt.
2547 * Pointer to interrupt handle.
2549 * The address of parameter (struct rte_eth_dev *) regsitered before.
2555 fm10k_dev_interrupt_handler_pf(void *param)
2557 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2558 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559 uint32_t cause, status;
2560 struct fm10k_dev_info *dev_info =
2561 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2565 if (hw->mac.type != fm10k_mac_pf)
2568 cause = FM10K_READ_REG(hw, FM10K_EICR);
2570 /* Handle PCI fault cases */
2571 if (cause & FM10K_EICR_FAULT_MASK) {
2572 PMD_INIT_LOG(ERR, "INT: find fault!");
2573 fm10k_dev_handle_fault(hw, cause);
2576 /* Handle switch up/down */
2577 if (cause & FM10K_EICR_SWITCHNOTREADY)
2578 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2580 if (cause & FM10K_EICR_SWITCHREADY) {
2581 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2582 if (dev_info->sm_down == 1) {
2585 /* For recreating logical ports */
2586 status_mbx = hw->mac.ops.update_lport_state(hw,
2587 hw->mac.dglort_map, MAX_LPORT_NUM, 1);
2588 if (status_mbx == FM10K_SUCCESS)
2590 "INT: Recreated Logical port");
2593 "INT: Logical ports weren't recreated");
2595 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2596 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2597 if (status_mbx != FM10K_SUCCESS)
2598 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2600 fm10k_mbx_unlock(hw);
2602 /* first clear the internal SW recording structure */
2603 if (!(dev->data->dev_conf.rxmode.mq_mode &
2604 ETH_MQ_RX_VMDQ_FLAG))
2605 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2608 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2609 MAIN_VSI_POOL_NUMBER);
2612 * Add default mac address and vlan for the logical
2613 * ports that have been created, leave to the
2614 * application to fully recover Rx filtering.
2616 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2617 MAIN_VSI_POOL_NUMBER);
2619 if (!(dev->data->dev_conf.rxmode.mq_mode &
2620 ETH_MQ_RX_VMDQ_FLAG))
2621 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2624 dev_info->sm_down = 0;
2625 rte_eth_dev_callback_process(dev,
2626 RTE_ETH_EVENT_INTR_LSC,
2631 /* Handle mailbox message */
2633 err = hw->mbx.ops.process(hw, &hw->mbx);
2634 fm10k_mbx_unlock(hw);
2636 if (err == FM10K_ERR_RESET_REQUESTED) {
2637 PMD_INIT_LOG(INFO, "INT: Switch is down");
2638 dev_info->sm_down = 1;
2639 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2642 /* Handle SRAM error */
2643 if (cause & FM10K_EICR_SRAMERROR) {
2644 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2646 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2647 /* Write to clear pending bits */
2648 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2650 /* Todo: print out error message after shared code updates */
2653 /* Clear these 3 events if having any */
2654 cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2655 FM10K_EICR_SWITCHREADY;
2657 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2659 /* Re-enable interrupt from device side */
2660 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2661 FM10K_ITR_MASK_CLEAR);
2662 /* Re-enable interrupt from host side */
2663 rte_intr_ack(dev->intr_handle);
2667 * VF interrupt handler triggered by NIC for handling specific interrupt.
2670 * Pointer to interrupt handle.
2672 * The address of parameter (struct rte_eth_dev *) regsitered before.
2678 fm10k_dev_interrupt_handler_vf(void *param)
2680 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2681 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2682 struct fm10k_mbx_info *mbx = &hw->mbx;
2683 struct fm10k_dev_info *dev_info =
2684 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2685 const enum fm10k_mbx_state state = mbx->state;
2688 if (hw->mac.type != fm10k_mac_vf)
2691 /* Handle mailbox message if lock is acquired */
2693 hw->mbx.ops.process(hw, &hw->mbx);
2694 fm10k_mbx_unlock(hw);
2696 if (state == FM10K_STATE_OPEN && mbx->state == FM10K_STATE_CONNECT) {
2697 PMD_INIT_LOG(INFO, "INT: Switch has gone down");
2700 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2702 fm10k_mbx_unlock(hw);
2704 /* Setting reset flag */
2705 dev_info->sm_down = 1;
2706 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2709 if (dev_info->sm_down == 1 &&
2710 hw->mac.dglort_map == FM10K_DGLORTMAP_ZERO) {
2711 PMD_INIT_LOG(INFO, "INT: Switch has gone up");
2713 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2714 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2715 if (status_mbx != FM10K_SUCCESS)
2716 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2717 fm10k_mbx_unlock(hw);
2719 /* first clear the internal SW recording structure */
2720 fm10k_vlan_filter_set(dev, hw->mac.default_vid, false);
2721 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2722 MAIN_VSI_POOL_NUMBER);
2725 * Add default mac address and vlan for the logical ports that
2726 * have been created, leave to the application to fully recover
2729 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2730 MAIN_VSI_POOL_NUMBER);
2731 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
2733 dev_info->sm_down = 0;
2734 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2737 /* Re-enable interrupt from device side */
2738 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2739 FM10K_ITR_MASK_CLEAR);
2740 /* Re-enable interrupt from host side */
2741 rte_intr_ack(dev->intr_handle);
2744 /* Mailbox message handler in VF */
2745 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2746 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2747 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2748 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2749 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2753 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2757 /* Initialize mailbox lock */
2758 fm10k_mbx_initlock(hw);
2760 /* Replace default message handler with new ones */
2761 if (hw->mac.type == fm10k_mac_vf)
2762 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2765 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2769 /* Connect to SM for PF device or PF for VF device */
2770 return hw->mbx.ops.connect(hw, &hw->mbx);
2774 fm10k_close_mbx_service(struct fm10k_hw *hw)
2776 /* Disconnect from SM for PF device or PF for VF device */
2777 hw->mbx.ops.disconnect(hw, &hw->mbx);
2781 fm10k_dev_close(struct rte_eth_dev *dev)
2783 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2785 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2787 PMD_INIT_FUNC_TRACE();
2790 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2791 MAX_LPORT_NUM, false);
2792 fm10k_mbx_unlock(hw);
2794 /* allow 100ms for device to quiesce */
2795 rte_delay_us(FM10K_SWITCH_QUIESCE_US);
2797 /* Stop mailbox service first */
2798 fm10k_close_mbx_service(hw);
2799 fm10k_dev_stop(dev);
2800 fm10k_dev_queue_release(dev);
2803 dev->dev_ops = NULL;
2804 dev->rx_pkt_burst = NULL;
2805 dev->tx_pkt_burst = NULL;
2807 /* disable uio/vfio intr */
2808 rte_intr_disable(intr_handle);
2810 /*PF/VF has different interrupt handling mechanism */
2811 if (hw->mac.type == fm10k_mac_pf) {
2812 /* disable interrupt */
2813 fm10k_dev_disable_intr_pf(dev);
2815 /* unregister callback func to eal lib */
2816 rte_intr_callback_unregister(intr_handle,
2817 fm10k_dev_interrupt_handler_pf, (void *)dev);
2819 /* disable interrupt */
2820 fm10k_dev_disable_intr_vf(dev);
2822 rte_intr_callback_unregister(intr_handle,
2823 fm10k_dev_interrupt_handler_vf, (void *)dev);
2827 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2828 .dev_configure = fm10k_dev_configure,
2829 .dev_start = fm10k_dev_start,
2830 .dev_stop = fm10k_dev_stop,
2831 .dev_close = fm10k_dev_close,
2832 .promiscuous_enable = fm10k_dev_promiscuous_enable,
2833 .promiscuous_disable = fm10k_dev_promiscuous_disable,
2834 .allmulticast_enable = fm10k_dev_allmulticast_enable,
2835 .allmulticast_disable = fm10k_dev_allmulticast_disable,
2836 .stats_get = fm10k_stats_get,
2837 .xstats_get = fm10k_xstats_get,
2838 .xstats_get_names = fm10k_xstats_get_names,
2839 .stats_reset = fm10k_stats_reset,
2840 .xstats_reset = fm10k_stats_reset,
2841 .link_update = fm10k_link_update,
2842 .dev_infos_get = fm10k_dev_infos_get,
2843 .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2844 .vlan_filter_set = fm10k_vlan_filter_set,
2845 .vlan_offload_set = fm10k_vlan_offload_set,
2846 .mac_addr_add = fm10k_macaddr_add,
2847 .mac_addr_remove = fm10k_macaddr_remove,
2848 .rx_queue_start = fm10k_dev_rx_queue_start,
2849 .rx_queue_stop = fm10k_dev_rx_queue_stop,
2850 .tx_queue_start = fm10k_dev_tx_queue_start,
2851 .tx_queue_stop = fm10k_dev_tx_queue_stop,
2852 .rx_queue_setup = fm10k_rx_queue_setup,
2853 .rx_queue_release = fm10k_rx_queue_release,
2854 .tx_queue_setup = fm10k_tx_queue_setup,
2855 .tx_queue_release = fm10k_tx_queue_release,
2856 .rx_queue_intr_enable = fm10k_dev_rx_queue_intr_enable,
2857 .rx_queue_intr_disable = fm10k_dev_rx_queue_intr_disable,
2858 .reta_update = fm10k_reta_update,
2859 .reta_query = fm10k_reta_query,
2860 .rss_hash_update = fm10k_rss_hash_update,
2861 .rss_hash_conf_get = fm10k_rss_hash_conf_get,
2864 static int ftag_check_handler(__rte_unused const char *key,
2865 const char *value, __rte_unused void *opaque)
2867 if (strcmp(value, "1"))
2874 fm10k_check_ftag(struct rte_devargs *devargs)
2876 struct rte_kvargs *kvlist;
2877 const char *ftag_key = "enable_ftag";
2879 if (devargs == NULL)
2882 kvlist = rte_kvargs_parse(devargs->args, NULL);
2886 if (!rte_kvargs_count(kvlist, ftag_key)) {
2887 rte_kvargs_free(kvlist);
2890 /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2891 if (rte_kvargs_process(kvlist, ftag_key,
2892 ftag_check_handler, NULL) < 0) {
2893 rte_kvargs_free(kvlist);
2896 rte_kvargs_free(kvlist);
2902 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
2906 struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
2911 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
2912 ret = fm10k_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
2923 static void __rte_cold
2924 fm10k_set_tx_function(struct rte_eth_dev *dev)
2926 struct fm10k_tx_queue *txq;
2929 uint16_t tx_ftag_en = 0;
2931 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2932 /* primary process has set the ftag flag and offloads */
2933 txq = dev->data->tx_queues[0];
2934 if (fm10k_tx_vec_condition_check(txq)) {
2935 dev->tx_pkt_burst = fm10k_xmit_pkts;
2936 dev->tx_pkt_prepare = fm10k_prep_pkts;
2937 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2939 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2940 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2941 dev->tx_pkt_prepare = NULL;
2946 if (fm10k_check_ftag(dev->device->devargs))
2949 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2950 txq = dev->data->tx_queues[i];
2951 txq->tx_ftag_en = tx_ftag_en;
2952 /* Check if Vector Tx is satisfied */
2953 if (fm10k_tx_vec_condition_check(txq))
2958 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2959 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2960 txq = dev->data->tx_queues[i];
2961 fm10k_txq_vec_setup(txq);
2963 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2964 dev->tx_pkt_prepare = NULL;
2966 dev->tx_pkt_burst = fm10k_xmit_pkts;
2967 dev->tx_pkt_prepare = fm10k_prep_pkts;
2968 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2972 static void __rte_cold
2973 fm10k_set_rx_function(struct rte_eth_dev *dev)
2975 struct fm10k_dev_info *dev_info =
2976 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2977 uint16_t i, rx_using_sse;
2978 uint16_t rx_ftag_en = 0;
2980 if (fm10k_check_ftag(dev->device->devargs))
2983 /* In order to allow Vector Rx there are a few configuration
2984 * conditions to be met.
2986 if (!fm10k_rx_vec_condition_check(dev) &&
2987 dev_info->rx_vec_allowed && !rx_ftag_en) {
2988 if (dev->data->scattered_rx)
2989 dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2991 dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2992 } else if (dev->data->scattered_rx)
2993 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2995 dev->rx_pkt_burst = fm10k_recv_pkts;
2998 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2999 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
3002 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
3004 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
3006 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3009 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3010 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
3012 rxq->rx_using_sse = rx_using_sse;
3013 rxq->rx_ftag_en = rx_ftag_en;
3018 fm10k_params_init(struct rte_eth_dev *dev)
3020 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3021 struct fm10k_dev_info *info =
3022 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
3024 /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
3025 * there is no way to get link status without reading BAR4. Until this
3026 * works, assume we have maximum bandwidth.
3027 * @todo - fix bus info
3029 hw->bus_caps.speed = fm10k_bus_speed_8000;
3030 hw->bus_caps.width = fm10k_bus_width_pcie_x8;
3031 hw->bus_caps.payload = fm10k_bus_payload_512;
3032 hw->bus.speed = fm10k_bus_speed_8000;
3033 hw->bus.width = fm10k_bus_width_pcie_x8;
3034 hw->bus.payload = fm10k_bus_payload_256;
3036 info->rx_vec_allowed = true;
3037 info->sm_down = false;
3041 eth_fm10k_dev_init(struct rte_eth_dev *dev)
3043 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3044 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
3045 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3047 struct fm10k_macvlan_filter_info *macvlan;
3049 PMD_INIT_FUNC_TRACE();
3051 dev->dev_ops = &fm10k_eth_dev_ops;
3052 dev->rx_queue_count = fm10k_dev_rx_queue_count;
3053 dev->rx_descriptor_done = fm10k_dev_rx_descriptor_done;
3054 dev->rx_descriptor_status = fm10k_dev_rx_descriptor_status;
3055 dev->tx_descriptor_status = fm10k_dev_tx_descriptor_status;
3056 dev->rx_pkt_burst = &fm10k_recv_pkts;
3057 dev->tx_pkt_burst = &fm10k_xmit_pkts;
3058 dev->tx_pkt_prepare = &fm10k_prep_pkts;
3061 * Primary process does the whole initialization, for secondary
3062 * processes, we just select the same Rx and Tx function as primary.
3064 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3065 fm10k_set_rx_function(dev);
3066 fm10k_set_tx_function(dev);
3070 rte_eth_copy_pci_info(dev, pdev);
3072 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
3073 memset(macvlan, 0, sizeof(*macvlan));
3074 /* Vendor and Device ID need to be set before init of shared code */
3075 memset(hw, 0, sizeof(*hw));
3076 hw->device_id = pdev->id.device_id;
3077 hw->vendor_id = pdev->id.vendor_id;
3078 hw->subsystem_device_id = pdev->id.subsystem_device_id;
3079 hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
3080 hw->revision_id = 0;
3081 hw->hw_addr = (void *)pdev->mem_resource[0].addr;
3082 if (hw->hw_addr == NULL) {
3083 PMD_INIT_LOG(ERR, "Bad mem resource."
3084 " Try to refuse unused devices.");
3088 /* Store fm10k_adapter pointer */
3089 hw->back = dev->data->dev_private;
3091 /* Initialize the shared code */
3092 diag = fm10k_init_shared_code(hw);
3093 if (diag != FM10K_SUCCESS) {
3094 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
3098 /* Initialize parameters */
3099 fm10k_params_init(dev);
3101 /* Initialize the hw */
3102 diag = fm10k_init_hw(hw);
3103 if (diag != FM10K_SUCCESS) {
3104 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
3108 /* Initialize MAC address(es) */
3109 dev->data->mac_addrs = rte_zmalloc("fm10k",
3110 RTE_ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
3111 if (dev->data->mac_addrs == NULL) {
3112 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
3116 diag = fm10k_read_mac_addr(hw);
3118 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
3119 &dev->data->mac_addrs[0]);
3121 if (diag != FM10K_SUCCESS ||
3122 !rte_is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
3124 /* Generate a random addr */
3125 rte_eth_random_addr(hw->mac.addr);
3126 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
3127 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
3128 &dev->data->mac_addrs[0]);
3131 /* Pass the information to the rte_eth_dev_close() that it should also
3132 * release the private port resources.
3134 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
3136 /* Reset the hw statistics */
3137 diag = fm10k_stats_reset(dev);
3139 PMD_INIT_LOG(ERR, "Stats reset failed: %d", diag);
3144 diag = fm10k_reset_hw(hw);
3145 if (diag != FM10K_SUCCESS) {
3146 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
3150 /* Setup mailbox service */
3151 diag = fm10k_setup_mbx_service(hw);
3152 if (diag != FM10K_SUCCESS) {
3153 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
3157 /*PF/VF has different interrupt handling mechanism */
3158 if (hw->mac.type == fm10k_mac_pf) {
3159 /* register callback func to eal lib */
3160 rte_intr_callback_register(intr_handle,
3161 fm10k_dev_interrupt_handler_pf, (void *)dev);
3163 /* enable MISC interrupt */
3164 fm10k_dev_enable_intr_pf(dev);
3166 rte_intr_callback_register(intr_handle,
3167 fm10k_dev_interrupt_handler_vf, (void *)dev);
3169 fm10k_dev_enable_intr_vf(dev);
3172 /* Enable intr after callback registered */
3173 rte_intr_enable(intr_handle);
3175 hw->mac.ops.update_int_moderator(hw);
3177 /* Make sure Switch Manager is ready before going forward. */
3178 if (hw->mac.type == fm10k_mac_pf) {
3179 bool switch_ready = false;
3181 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3183 hw->mac.ops.get_host_state(hw, &switch_ready);
3184 fm10k_mbx_unlock(hw);
3185 if (switch_ready == true)
3187 /* Delay some time to acquire async LPORT_MAP info. */
3188 rte_delay_us(WAIT_SWITCH_MSG_US);
3191 if (switch_ready == false) {
3192 PMD_INIT_LOG(ERR, "switch is not ready");
3198 * Below function will trigger operations on mailbox, acquire lock to
3199 * avoid race condition from interrupt handler. Operations on mailbox
3200 * FIFO will trigger interrupt to PF/SM, in which interrupt handler
3201 * will handle and generate an interrupt to our side. Then, FIFO in
3202 * mailbox will be touched.
3205 /* Enable port first */
3206 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
3209 /* Set unicast mode by default. App can change to other mode in other
3212 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
3213 FM10K_XCAST_MODE_NONE);
3215 fm10k_mbx_unlock(hw);
3217 /* Make sure default VID is ready before going forward. */
3218 if (hw->mac.type == fm10k_mac_pf) {
3219 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3220 if (hw->mac.default_vid)
3222 /* Delay some time to acquire async port VLAN info. */
3223 rte_delay_us(WAIT_SWITCH_MSG_US);
3226 if (!hw->mac.default_vid) {
3227 PMD_INIT_LOG(ERR, "default VID is not ready");
3232 /* Add default mac address */
3233 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3234 MAIN_VSI_POOL_NUMBER);
3240 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3242 PMD_INIT_FUNC_TRACE();
3244 /* only uninitialize in the primary process */
3245 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3248 /* safe to close dev here */
3249 fm10k_dev_close(dev);
3254 static int eth_fm10k_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3255 struct rte_pci_device *pci_dev)
3257 return rte_eth_dev_pci_generic_probe(pci_dev,
3258 sizeof(struct fm10k_adapter), eth_fm10k_dev_init);
3261 static int eth_fm10k_pci_remove(struct rte_pci_device *pci_dev)
3263 return rte_eth_dev_pci_generic_remove(pci_dev, eth_fm10k_dev_uninit);
3267 * The set of PCI devices this driver supports. This driver will enable both PF
3268 * and SRIOV-VF devices.
3270 static const struct rte_pci_id pci_id_fm10k_map[] = {
3271 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3272 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3273 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3274 { .vendor_id = 0, /* sentinel */ },
3277 static struct rte_pci_driver rte_pmd_fm10k = {
3278 .id_table = pci_id_fm10k_map,
3279 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3280 .probe = eth_fm10k_pci_probe,
3281 .remove = eth_fm10k_pci_remove,
3284 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k);
3285 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3286 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio-pci");
3287 RTE_LOG_REGISTER(fm10k_logtype_init, pmd.net.fm10k.init, NOTICE);
3288 RTE_LOG_REGISTER(fm10k_logtype_driver, pmd.net.fm10k.driver, NOTICE);
3289 #ifdef RTE_LIBRTE_FM10K_DEBUG_RX
3290 RTE_LOG_REGISTER(fm10k_logtype_rx, pmd.net.fm10k.rx, DEBUG);
3292 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX
3293 RTE_LOG_REGISTER(fm10k_logtype_tx, pmd.net.fm10k.tx, DEBUG);
3295 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX_FREE
3296 RTE_LOG_REGISTER(fm10k_logtype_tx_free, pmd.net.fm10k.tx_free, DEBUG);