drivers/net/fm10k/fm10k_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2013-2016 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_ethdev_pci.h>
   7 #include <rte_malloc.h>
   8 #include <rte_memzone.h>
   9 #include <rte_string_fns.h>
  10 #include <rte_dev.h>
  11 #include <rte_spinlock.h>
  12 #include <rte_kvargs.h>
  13
  14 #include "fm10k.h"
  15 #include "base/fm10k_api.h"
  16
  17 /* Default delay to acquire mailbox lock */
  18 #define FM10K_MBXLOCK_DELAY_US 20
  19 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  20
  21 #define MAIN_VSI_POOL_NUMBER 0
  22
  23 /* Max try times to acquire switch status */
  24 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  25 /* Wait interval to get switch status */
  26 #define WAIT_SWITCH_MSG_US    100000
  27 /* A period of quiescence for switch */
  28 #define FM10K_SWITCH_QUIESCE_US 100000
  29 /* Number of chars per uint32 type */
  30 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  31 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  32
  33 /* default 1:1 map from queue ID to interrupt vector ID */
  34 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
  35
  36 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  37 #define MAX_LPORT_NUM    128
  38 #define GLORT_FD_Q_BASE  0x40
  39 #define GLORT_PF_MASK    0xFFC0
  40 #define GLORT_FD_MASK    GLORT_PF_MASK
  41 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  42
  43 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  44 static int fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  45 static int fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  46 static int fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  47 static int fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  48 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  49 static int
  50 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  51 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  52         const u8 *mac, bool add, uint32_t pool);
  53 static void fm10k_tx_queue_release(void *queue);
  54 static void fm10k_rx_queue_release(void *queue);
  55 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  56 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  57 static int fm10k_check_ftag(struct rte_devargs *devargs);
  58 static int fm10k_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  59
  60 static int fm10k_dev_infos_get(struct rte_eth_dev *dev,
  61                                struct rte_eth_dev_info *dev_info);
  62 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev);
  63 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev);
  64 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev);
  65 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev);
  66
  67 struct fm10k_xstats_name_off {
  68         char name[RTE_ETH_XSTATS_NAME_SIZE];
  69         unsigned offset;
  70 };
  71
  72 static const struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  73         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  74         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  75         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  76         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  77         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  78         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
  79         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
  80         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
  81                 nodesc_drop)},
  82 };
  83
  84 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
  85                 sizeof(fm10k_hw_stats_strings[0]))
  86
  87 static const struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
  88         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
  89         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
  90         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
  91 };
  92
  93 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
  94                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
  95
  96 static const struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
  97         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
  98         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
  99 };
 100
 101 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 102                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 103
 104 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 105                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 106 static int
 107 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 108
 109 static void
 110 fm10k_mbx_initlock(struct fm10k_hw *hw)
 111 {
 112         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 113 }
 114
 115 static void
 116 fm10k_mbx_lock(struct fm10k_hw *hw)
 117 {
 118         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 119                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 120 }
 121
 122 static void
 123 fm10k_mbx_unlock(struct fm10k_hw *hw)
 124 {
 125         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 126 }
 127
 128 /* Stubs needed for linkage when vPMD is disabled */
 129 __rte_weak int
 130 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 131 {
 132         return -1;
 133 }
 134
 135 __rte_weak uint16_t
 136 fm10k_recv_pkts_vec(
 137         __rte_unused void *rx_queue,
 138         __rte_unused struct rte_mbuf **rx_pkts,
 139         __rte_unused uint16_t nb_pkts)
 140 {
 141         return 0;
 142 }
 143
 144 __rte_weak uint16_t
 145 fm10k_recv_scattered_pkts_vec(
 146                 __rte_unused void *rx_queue,
 147                 __rte_unused struct rte_mbuf **rx_pkts,
 148                 __rte_unused uint16_t nb_pkts)
 149 {
 150         return 0;
 151 }
 152
 153 __rte_weak int
 154 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 155
 156 {
 157         return -1;
 158 }
 159
 160 __rte_weak void
 161 fm10k_rx_queue_release_mbufs_vec(
 162                 __rte_unused struct fm10k_rx_queue *rxq)
 163 {
 164         return;
 165 }
 166
 167 __rte_weak void
 168 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 169 {
 170         return;
 171 }
 172
 173 __rte_weak int
 174 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 175 {
 176         return -1;
 177 }
 178
 179 __rte_weak uint16_t
 180 fm10k_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
 181                            __rte_unused struct rte_mbuf **tx_pkts,
 182                            __rte_unused uint16_t nb_pkts)
 183 {
 184         return 0;
 185 }
 186
 187 /*
 188  * reset queue to initial state, allocate software buffers used when starting
 189  * device.
 190  * return 0 on success
 191  * return -ENOMEM if buffers cannot be allocated
 192  * return -EINVAL if buffers do not satisfy alignment condition
 193  */
 194 static inline int
 195 rx_queue_reset(struct fm10k_rx_queue *q)
 196 {
 197         static const union fm10k_rx_desc zero = {{0} };
 198         uint64_t dma_addr;
 199         int i, diag;
 200         PMD_INIT_FUNC_TRACE();
 201
 202         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 203         if (diag != 0)
 204                 return -ENOMEM;
 205
 206         for (i = 0; i < q->nb_desc; ++i) {
 207                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 208                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 209                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 210                                                 q->nb_desc);
 211                         return -EINVAL;
 212                 }
 213                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 214                 q->hw_ring[i].q.pkt_addr = dma_addr;
 215                 q->hw_ring[i].q.hdr_addr = dma_addr;
 216         }
 217
 218         /* initialize extra software ring entries. Space for these extra
 219          * entries is always allocated.
 220          */
 221         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 222         for (i = 0; i < q->nb_fake_desc; ++i) {
 223                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 224                 q->hw_ring[q->nb_desc + i] = zero;
 225         }
 226
 227         q->next_dd = 0;
 228         q->next_alloc = 0;
 229         q->next_trigger = q->alloc_thresh - 1;
 230         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 231         q->rxrearm_start = 0;
 232         q->rxrearm_nb = 0;
 233
 234         return 0;
 235 }
 236
 237 /*
 238  * clean queue, descriptor rings, free software buffers used when stopping
 239  * device.
 240  */
 241 static inline void
 242 rx_queue_clean(struct fm10k_rx_queue *q)
 243 {
 244         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 245         uint32_t i;
 246         PMD_INIT_FUNC_TRACE();
 247
 248         /* zero descriptor rings */
 249         for (i = 0; i < q->nb_desc; ++i)
 250                 q->hw_ring[i] = zero;
 251
 252         /* zero faked descriptors */
 253         for (i = 0; i < q->nb_fake_desc; ++i)
 254                 q->hw_ring[q->nb_desc + i] = zero;
 255
 256         /* vPMD driver has a different way of releasing mbufs. */
 257         if (q->rx_using_sse) {
 258                 fm10k_rx_queue_release_mbufs_vec(q);
 259                 return;
 260         }
 261
 262         /* free software buffers */
 263         for (i = 0; i < q->nb_desc; ++i) {
 264                 if (q->sw_ring[i]) {
 265                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 266                         q->sw_ring[i] = NULL;
 267                 }
 268         }
 269 }
 270
 271 /*
 272  * free all queue memory used when releasing the queue (i.e. configure)
 273  */
 274 static inline void
 275 rx_queue_free(struct fm10k_rx_queue *q)
 276 {
 277         PMD_INIT_FUNC_TRACE();
 278         if (q) {
 279                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 280                 rx_queue_clean(q);
 281                 if (q->sw_ring) {
 282                         rte_free(q->sw_ring);
 283                         q->sw_ring = NULL;
 284                 }
 285                 rte_free(q);
 286                 q = NULL;
 287         }
 288 }
 289
 290 /*
 291  * disable RX queue, wait unitl HW finished necessary flush operation
 292  */
 293 static inline int
 294 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 295 {
 296         uint32_t reg, i;
 297
 298         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 299         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 300                         reg & ~FM10K_RXQCTL_ENABLE);
 301
 302         /* Wait 100us at most */
 303         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 304                 rte_delay_us(1);
 305                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 306                 if (!(reg & FM10K_RXQCTL_ENABLE))
 307                         break;
 308         }
 309
 310         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 311                 return -1;
 312
 313         return 0;
 314 }
 315
 316 /*
 317  * reset queue to initial state, allocate software buffers used when starting
 318  * device
 319  */
 320 static inline void
 321 tx_queue_reset(struct fm10k_tx_queue *q)
 322 {
 323         PMD_INIT_FUNC_TRACE();
 324         q->last_free = 0;
 325         q->next_free = 0;
 326         q->nb_used = 0;
 327         q->nb_free = q->nb_desc - 1;
 328         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 329         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 330 }
 331
 332 /*
 333  * clean queue, descriptor rings, free software buffers used when stopping
 334  * device
 335  */
 336 static inline void
 337 tx_queue_clean(struct fm10k_tx_queue *q)
 338 {
 339         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 340         uint32_t i;
 341         PMD_INIT_FUNC_TRACE();
 342
 343         /* zero descriptor rings */
 344         for (i = 0; i < q->nb_desc; ++i)
 345                 q->hw_ring[i] = zero;
 346
 347         /* free software buffers */
 348         for (i = 0; i < q->nb_desc; ++i) {
 349                 if (q->sw_ring[i]) {
 350                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 351                         q->sw_ring[i] = NULL;
 352                 }
 353         }
 354 }
 355
 356 /*
 357  * free all queue memory used when releasing the queue (i.e. configure)
 358  */
 359 static inline void
 360 tx_queue_free(struct fm10k_tx_queue *q)
 361 {
 362         PMD_INIT_FUNC_TRACE();
 363         if (q) {
 364                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 365                 tx_queue_clean(q);
 366                 if (q->rs_tracker.list) {
 367                         rte_free(q->rs_tracker.list);
 368                         q->rs_tracker.list = NULL;
 369                 }
 370                 if (q->sw_ring) {
 371                         rte_free(q->sw_ring);
 372                         q->sw_ring = NULL;
 373                 }
 374                 rte_free(q);
 375                 q = NULL;
 376         }
 377 }
 378
 379 /*
 380  * disable TX queue, wait unitl HW finished necessary flush operation
 381  */
 382 static inline int
 383 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 384 {
 385         uint32_t reg, i;
 386
 387         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 388         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 389                         reg & ~FM10K_TXDCTL_ENABLE);
 390
 391         /* Wait 100us at most */
 392         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 393                 rte_delay_us(1);
 394                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 395                 if (!(reg & FM10K_TXDCTL_ENABLE))
 396                         break;
 397         }
 398
 399         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 400                 return -1;
 401
 402         return 0;
 403 }
 404
 405 static int
 406 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 407 {
 408         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 409         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 410         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 411         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 412
 413         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 414
 415         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 416                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 417                 return -EINVAL;
 418         }
 419
 420         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 421                 return 0;
 422
 423         if (hw->mac.type == fm10k_mac_vf) {
 424                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 425                 return -EINVAL;
 426         }
 427
 428         /* Check VMDQ queue pool number */
 429         if (vmdq_conf->nb_queue_pools >
 430                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 431                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 432                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 433                         vmdq_conf->nb_queue_pools);
 434                 return -EINVAL;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static const struct fm10k_txq_ops def_txq_ops = {
 441         .reset = tx_queue_reset,
 442 };
 443
 444 static int
 445 fm10k_dev_configure(struct rte_eth_dev *dev)
 446 {
 447         int ret;
 448
 449         PMD_INIT_FUNC_TRACE();
 450
 451         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 452                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 453
 454         /* multipe queue mode checking */
 455         ret  = fm10k_check_mq_mode(dev);
 456         if (ret != 0) {
 457                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 458                             ret);
 459                 return ret;
 460         }
 461
 462         dev->data->scattered_rx = 0;
 463
 464         return 0;
 465 }
 466
 467 static void
 468 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 469 {
 470         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 471         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 472         uint32_t i;
 473
 474         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 475
 476         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 477                 if (!vmdq_conf->pool_map[i].pools)
 478                         continue;
 479                 fm10k_mbx_lock(hw);
 480                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 481                 fm10k_mbx_unlock(hw);
 482         }
 483 }
 484
 485 static void
 486 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 487 {
 488         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 489
 490         /* Add default mac address */
 491         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 492                 MAIN_VSI_POOL_NUMBER);
 493 }
 494
 495 static void
 496 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 497 {
 498         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 499         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 500         uint32_t mrqc, *key, i, reta, j;
 501         uint64_t hf;
 502
 503 #define RSS_KEY_SIZE 40
 504         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 505                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 506                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 507                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 508                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 509                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 510         };
 511
 512         if (dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 513                 dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 514                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 515                 return;
 516         }
 517
 518         /* random key is rss_intel_key (default) or user provided (rss_key) */
 519         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 520                 key = (uint32_t *)rss_intel_key;
 521         else
 522                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 523
 524         /* Now fill our hash function seeds, 4 bytes at a time */
 525         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 526                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 527
 528         /*
 529          * Fill in redirection table
 530          * The byte-swap is needed because NIC registers are in
 531          * little-endian order.
 532          */
 533         reta = 0;
 534         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 535                 if (j == dev->data->nb_rx_queues)
 536                         j = 0;
 537                 reta = (reta << CHAR_BIT) | j;
 538                 if ((i & 3) == 3)
 539                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 540                                         rte_bswap32(reta));
 541         }
 542
 543         /*
 544          * Generate RSS hash based on packet types, TCP/UDP
 545          * port numbers and/or IPv4/v6 src and dst addresses
 546          */
 547         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 548         mrqc = 0;
 549         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 550         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 551         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 552         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 553         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 554         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 555         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 556         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 557         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 558
 559         if (mrqc == 0) {
 560                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 561                         "supported", hf);
 562                 return;
 563         }
 564
 565         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 566 }
 567
 568 static void
 569 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 570 {
 571         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 572         uint32_t i;
 573
 574         for (i = 0; i < nb_lport_new; i++) {
 575                 /* Set unicast mode by default. App can change
 576                  * to other mode in other API func.
 577                  */
 578                 fm10k_mbx_lock(hw);
 579                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 580                         FM10K_XCAST_MODE_NONE);
 581                 fm10k_mbx_unlock(hw);
 582         }
 583 }
 584
 585 static void
 586 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 587 {
 588         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 589         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 590         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 591         struct fm10k_macvlan_filter_info *macvlan;
 592         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 593         uint16_t nb_lport_new;
 594
 595         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 596         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 597
 598         fm10k_dev_rss_configure(dev);
 599
 600         /* only PF supports VMDQ */
 601         if (hw->mac.type != fm10k_mac_pf)
 602                 return;
 603
 604         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 605                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 606
 607         /* no pool number change, no need to update logic port and VLAN/MAC */
 608         if (macvlan->nb_queue_pools == nb_queue_pools)
 609                 return;
 610
 611         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 612         fm10k_dev_logic_port_update(dev, nb_lport_new);
 613
 614         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 615         memset(dev->data->mac_addrs, 0,
 616                 RTE_ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 617         rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
 618                 &dev->data->mac_addrs[0]);
 619         memset(macvlan, 0, sizeof(*macvlan));
 620         macvlan->nb_queue_pools = nb_queue_pools;
 621
 622         if (nb_queue_pools)
 623                 fm10k_dev_vmdq_rx_configure(dev);
 624         else
 625                 fm10k_dev_pf_main_vsi_reset(dev);
 626 }
 627
 628 static int
 629 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 630 {
 631         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 632         int i, ret;
 633         struct fm10k_tx_queue *txq;
 634         uint64_t base_addr;
 635         uint32_t size;
 636
 637         /* Disable TXINT to avoid possible interrupt */
 638         for (i = 0; i < hw->mac.max_queues; i++)
 639                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 640                                 3 << FM10K_TXINT_TIMER_SHIFT);
 641
 642         /* Setup TX queue */
 643         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 644                 txq = dev->data->tx_queues[i];
 645                 base_addr = txq->hw_ring_phys_addr;
 646                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 647
 648                 /* disable queue to avoid issues while updating state */
 649                 ret = tx_queue_disable(hw, i);
 650                 if (ret) {
 651                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 652                         return -1;
 653                 }
 654                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 655                  * register is read-only for VF.
 656                  */
 657                 if (fm10k_check_ftag(dev->device->devargs)) {
 658                         if (hw->mac.type == fm10k_mac_pf) {
 659                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 660                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 661                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 662                         } else {
 663                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 664                                 return -ENOTSUP;
 665                         }
 666                 }
 667
 668                 /* set location and size for descriptor ring */
 669                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 670                                 base_addr & UINT64_LOWER_32BITS_MASK);
 671                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 672                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 673                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 674
 675                 /* assign default SGLORT for each TX queue by PF */
 676                 if (hw->mac.type == fm10k_mac_pf)
 677                         FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 678         }
 679
 680         /* set up vector or scalar TX function as appropriate */
 681         fm10k_set_tx_function(dev);
 682
 683         return 0;
 684 }
 685
 686 static int
 687 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 688 {
 689         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 690         struct fm10k_macvlan_filter_info *macvlan;
 691         struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
 692         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
 693         int i, ret;
 694         struct fm10k_rx_queue *rxq;
 695         uint64_t base_addr;
 696         uint32_t size;
 697         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 698         uint32_t logic_port = hw->mac.dglort_map;
 699         uint16_t buf_size;
 700         uint16_t queue_stride = 0;
 701
 702         /* enable RXINT for interrupt mode */
 703         i = 0;
 704         if (rte_intr_dp_is_en(intr_handle)) {
 705                 for (; i < dev->data->nb_rx_queues; i++) {
 706                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
 707                         if (hw->mac.type == fm10k_mac_pf)
 708                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
 709                                         FM10K_ITR_AUTOMASK |
 710                                         FM10K_ITR_MASK_CLEAR);
 711                         else
 712                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
 713                                         FM10K_ITR_AUTOMASK |
 714                                         FM10K_ITR_MASK_CLEAR);
 715                 }
 716         }
 717         /* Disable other RXINT to avoid possible interrupt */
 718         for (; i < hw->mac.max_queues; i++)
 719                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 720                         3 << FM10K_RXINT_TIMER_SHIFT);
 721
 722         /* Setup RX queues */
 723         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 724                 rxq = dev->data->rx_queues[i];
 725                 base_addr = rxq->hw_ring_phys_addr;
 726                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 727
 728                 /* disable queue to avoid issues while updating state */
 729                 ret = rx_queue_disable(hw, i);
 730                 if (ret) {
 731                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 732                         return -1;
 733                 }
 734
 735                 /* Setup the Base and Length of the Rx Descriptor Ring */
 736                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 737                                 base_addr & UINT64_LOWER_32BITS_MASK);
 738                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 739                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 740                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 741
 742                 /* Configure the Rx buffer size for one buff without split */
 743                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 744                         RTE_PKTMBUF_HEADROOM);
 745                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 746                  * reserved for this purpose, and the worst case could be 511B.
 747                  * But SRR reg assumes all buffers have the same size. In order
 748                  * to fill the gap, we'll have to consider the worst case and
 749                  * assume 512B is reserved. If we don't do so, it's possible
 750                  * for HW to overwrite data to next mbuf.
 751                  */
 752                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 753
 754                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 755                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 756                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 757
 758                 /* It adds dual VLAN length for supporting dual VLAN */
 759                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 760                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 761                         rxq->offloads & DEV_RX_OFFLOAD_SCATTER) {
 762                         uint32_t reg;
 763                         dev->data->scattered_rx = 1;
 764                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 765                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 766                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 767                 }
 768
 769                 /* Enable drop on empty, it's RO for VF */
 770                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 771                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 772
 773                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 774                 FM10K_WRITE_FLUSH(hw);
 775         }
 776
 777         /* Configure VMDQ/RSS if applicable */
 778         fm10k_dev_mq_rx_configure(dev);
 779
 780         /* Decide the best RX function */
 781         fm10k_set_rx_function(dev);
 782
 783         /* update RX_SGLORT for loopback suppress*/
 784         if (hw->mac.type != fm10k_mac_pf)
 785                 return 0;
 786         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 787         if (macvlan->nb_queue_pools)
 788                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 789         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 790                 if (i && queue_stride && !(i % queue_stride))
 791                         logic_port++;
 792                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int
 799 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 800 {
 801         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 802         int err;
 803         uint32_t reg;
 804         struct fm10k_rx_queue *rxq;
 805
 806         PMD_INIT_FUNC_TRACE();
 807
 808         rxq = dev->data->rx_queues[rx_queue_id];
 809         err = rx_queue_reset(rxq);
 810         if (err == -ENOMEM) {
 811                 PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 812                 return err;
 813         } else if (err == -EINVAL) {
 814                 PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 815                         " %d", err);
 816                 return err;
 817         }
 818
 819         /* Setup the HW Rx Head and Tail Descriptor Pointers
 820          * Note: this must be done AFTER the queue is enabled on real
 821          * hardware, but BEFORE the queue is enabled when using the
 822          * emulation platform. Do it in both places for now and remove
 823          * this comment and the following two register writes when the
 824          * emulation platform is no longer being used.
 825          */
 826         FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 827         FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 828
 829         /* Set PF ownership flag for PF devices */
 830         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 831         if (hw->mac.type == fm10k_mac_pf)
 832                 reg |= FM10K_RXQCTL_PF;
 833         reg |= FM10K_RXQCTL_ENABLE;
 834         /* enable RX queue */
 835         FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 836         FM10K_WRITE_FLUSH(hw);
 837
 838         /* Setup the HW Rx Head and Tail Descriptor Pointers
 839          * Note: this must be done AFTER the queue is enabled
 840          */
 841         FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 842         FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 843         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 844
 845         return 0;
 846 }
 847
 848 static int
 849 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 850 {
 851         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 852
 853         PMD_INIT_FUNC_TRACE();
 854
 855         /* Disable RX queue */
 856         rx_queue_disable(hw, rx_queue_id);
 857
 858         /* Free mbuf and clean HW ring */
 859         rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 860         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 861
 862         return 0;
 863 }
 864
 865 static int
 866 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 867 {
 868         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 869         /** @todo - this should be defined in the shared code */
 870 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 871         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 872         struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 873
 874         PMD_INIT_FUNC_TRACE();
 875
 876         q->ops->reset(q);
 877
 878         /* reset head and tail pointers */
 879         FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 880         FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 881
 882         /* enable TX queue */
 883         FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 884                                 FM10K_TXDCTL_ENABLE | txdctl);
 885         FM10K_WRITE_FLUSH(hw);
 886         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 887
 888         return 0;
 889 }
 890
 891 static int
 892 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 893 {
 894         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 895
 896         PMD_INIT_FUNC_TRACE();
 897
 898         tx_queue_disable(hw, tx_queue_id);
 899         tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 900         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 901
 902         return 0;
 903 }
 904
 905 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 906 {
 907         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 908                 != FM10K_DGLORTMAP_NONE);
 909 }
 910
 911 static int
 912 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 913 {
 914         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 915         int status;
 916
 917         PMD_INIT_FUNC_TRACE();
 918
 919         /* Return if it didn't acquire valid glort range */
 920         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 921                 return 0;
 922
 923         fm10k_mbx_lock(hw);
 924         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 925                                 FM10K_XCAST_MODE_PROMISC);
 926         fm10k_mbx_unlock(hw);
 927
 928         if (status != FM10K_SUCCESS) {
 929                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 930                 return -EAGAIN;
 931         }
 932
 933         return 0;
 934 }
 935
 936 static int
 937 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 938 {
 939         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 940         uint8_t mode;
 941         int status;
 942
 943         PMD_INIT_FUNC_TRACE();
 944
 945         /* Return if it didn't acquire valid glort range */
 946         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 947                 return 0;
 948
 949         if (dev->data->all_multicast == 1)
 950                 mode = FM10K_XCAST_MODE_ALLMULTI;
 951         else
 952                 mode = FM10K_XCAST_MODE_NONE;
 953
 954         fm10k_mbx_lock(hw);
 955         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 956                                 mode);
 957         fm10k_mbx_unlock(hw);
 958
 959         if (status != FM10K_SUCCESS) {
 960                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 961                 return -EAGAIN;
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int
 968 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 969 {
 970         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971         int status;
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         /* Return if it didn't acquire valid glort range */
 976         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 977                 return 0;
 978
 979         /* If promiscuous mode is enabled, it doesn't make sense to enable
 980          * allmulticast and disable promiscuous since fm10k only can select
 981          * one of the modes.
 982          */
 983         if (dev->data->promiscuous) {
 984                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
 985                         "needn't enable allmulticast");
 986                 return 0;
 987         }
 988
 989         fm10k_mbx_lock(hw);
 990         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 991                                 FM10K_XCAST_MODE_ALLMULTI);
 992         fm10k_mbx_unlock(hw);
 993
 994         if (status != FM10K_SUCCESS) {
 995                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
 996                 return -EAGAIN;
 997         }
 998
 999         return 0;
1000 }
1001
1002 static int
1003 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1004 {
1005         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         int status;
1007
1008         PMD_INIT_FUNC_TRACE();
1009
1010         /* Return if it didn't acquire valid glort range */
1011         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1012                 return 0;
1013
1014         if (dev->data->promiscuous) {
1015                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1016                         "since promisc mode is enabled");
1017                 return -EINVAL;
1018         }
1019
1020         fm10k_mbx_lock(hw);
1021         /* Change mode to unicast mode */
1022         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1023                                 FM10K_XCAST_MODE_NONE);
1024         fm10k_mbx_unlock(hw);
1025
1026         if (status != FM10K_SUCCESS) {
1027                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1028                 return -EAGAIN;
1029         }
1030
1031         return 0;
1032 }
1033
1034 static void
1035 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1036 {
1037         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1039         uint16_t nb_queue_pools;
1040         struct fm10k_macvlan_filter_info *macvlan;
1041
1042         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1043         nb_queue_pools = macvlan->nb_queue_pools;
1044         pool_len = nb_queue_pools ? rte_fls_u32(nb_queue_pools - 1) : 0;
1045         rss_len = rte_fls_u32(dev->data->nb_rx_queues - 1) - pool_len;
1046
1047         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1048         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1049         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1050                         hw->mac.dglort_map;
1051         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1052         /* Configure VMDQ/RSS DGlort Decoder */
1053         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1054
1055         /* Flow Director configurations, only queue number is valid. */
1056         dglortdec = rte_fls_u32(dev->data->nb_rx_queues - 1);
1057         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1058                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1059         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1060         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1061
1062         /* Invalidate all other GLORT entries */
1063         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1064                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1065                                 FM10K_DGLORTMAP_NONE);
1066 }
1067
1068 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1069 static int
1070 fm10k_dev_start(struct rte_eth_dev *dev)
1071 {
1072         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1073         int i, diag;
1074
1075         PMD_INIT_FUNC_TRACE();
1076
1077         /* stop, init, then start the hw */
1078         diag = fm10k_stop_hw(hw);
1079         if (diag != FM10K_SUCCESS) {
1080                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1081                 return -EIO;
1082         }
1083
1084         diag = fm10k_init_hw(hw);
1085         if (diag != FM10K_SUCCESS) {
1086                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1087                 return -EIO;
1088         }
1089
1090         diag = fm10k_start_hw(hw);
1091         if (diag != FM10K_SUCCESS) {
1092                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1093                 return -EIO;
1094         }
1095
1096         diag = fm10k_dev_tx_init(dev);
1097         if (diag) {
1098                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1099                 return diag;
1100         }
1101
1102         if (fm10k_dev_rxq_interrupt_setup(dev))
1103                 return -EIO;
1104
1105         diag = fm10k_dev_rx_init(dev);
1106         if (diag) {
1107                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1108                 return diag;
1109         }
1110
1111         if (hw->mac.type == fm10k_mac_pf)
1112                 fm10k_dev_dglort_map_configure(dev);
1113
1114         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1115                 struct fm10k_rx_queue *rxq;
1116                 rxq = dev->data->rx_queues[i];
1117
1118                 if (rxq->rx_deferred_start)
1119                         continue;
1120                 diag = fm10k_dev_rx_queue_start(dev, i);
1121                 if (diag != 0) {
1122                         int j;
1123                         for (j = 0; j < i; ++j)
1124                                 rx_queue_clean(dev->data->rx_queues[j]);
1125                         return diag;
1126                 }
1127         }
1128
1129         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1130                 struct fm10k_tx_queue *txq;
1131                 txq = dev->data->tx_queues[i];
1132
1133                 if (txq->tx_deferred_start)
1134                         continue;
1135                 diag = fm10k_dev_tx_queue_start(dev, i);
1136                 if (diag != 0) {
1137                         int j;
1138                         for (j = 0; j < i; ++j)
1139                                 tx_queue_clean(dev->data->tx_queues[j]);
1140                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1141                                 rx_queue_clean(dev->data->rx_queues[j]);
1142                         return diag;
1143                 }
1144         }
1145
1146         /* Update default vlan when not in VMDQ mode */
1147         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1148                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1149
1150         fm10k_link_update(dev, 0);
1151
1152         return 0;
1153 }
1154
1155 static void
1156 fm10k_dev_stop(struct rte_eth_dev *dev)
1157 {
1158         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1159         struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1160         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1161         int i;
1162
1163         PMD_INIT_FUNC_TRACE();
1164
1165         if (dev->data->tx_queues)
1166                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1167                         fm10k_dev_tx_queue_stop(dev, i);
1168
1169         if (dev->data->rx_queues)
1170                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1171                         fm10k_dev_rx_queue_stop(dev, i);
1172
1173         /* Disable datapath event */
1174         if (rte_intr_dp_is_en(intr_handle)) {
1175                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1176                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1177                                 3 << FM10K_RXINT_TIMER_SHIFT);
1178                         if (hw->mac.type == fm10k_mac_pf)
1179                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1180                                         FM10K_ITR_MASK_SET);
1181                         else
1182                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1183                                         FM10K_ITR_MASK_SET);
1184                 }
1185         }
1186         /* Clean datapath event and queue/vec mapping */
1187         rte_intr_efd_disable(intr_handle);
1188         rte_free(intr_handle->intr_vec);
1189         intr_handle->intr_vec = NULL;
1190 }
1191
1192 static void
1193 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1194 {
1195         int i;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         if (dev->data->tx_queues) {
1200                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1201                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1202
1203                         tx_queue_free(txq);
1204                 }
1205         }
1206
1207         if (dev->data->rx_queues) {
1208                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1209                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1210         }
1211 }
1212
1213 static int
1214 fm10k_link_update(struct rte_eth_dev *dev,
1215         __rte_unused int wait_to_complete)
1216 {
1217         struct fm10k_dev_info *dev_info =
1218                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1219         PMD_INIT_FUNC_TRACE();
1220
1221         dev->data->dev_link.link_speed  = ETH_SPEED_NUM_50G;
1222         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1223         dev->data->dev_link.link_status =
1224                 dev_info->sm_down ? ETH_LINK_DOWN : ETH_LINK_UP;
1225         dev->data->dev_link.link_autoneg = ETH_LINK_FIXED;
1226
1227         return 0;
1228 }
1229
1230 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1231         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1232 {
1233         unsigned i, q;
1234         unsigned count = 0;
1235
1236         if (xstats_names != NULL) {
1237                 /* Note: limit checked in rte_eth_xstats_names() */
1238
1239                 /* Global stats */
1240                 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1241                         snprintf(xstats_names[count].name,
1242                                 sizeof(xstats_names[count].name),
1243                                 "%s", fm10k_hw_stats_strings[count].name);
1244                         count++;
1245                 }
1246
1247                 /* PF queue stats */
1248                 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1249                         for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1250                                 snprintf(xstats_names[count].name,
1251                                         sizeof(xstats_names[count].name),
1252                                         "rx_q%u_%s", q,
1253                                         fm10k_hw_stats_rx_q_strings[i].name);
1254                                 count++;
1255                         }
1256                         for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1257                                 snprintf(xstats_names[count].name,
1258                                         sizeof(xstats_names[count].name),
1259                                         "tx_q%u_%s", q,
1260                                         fm10k_hw_stats_tx_q_strings[i].name);
1261                                 count++;
1262                         }
1263                 }
1264         }
1265         return FM10K_NB_XSTATS;
1266 }
1267
1268 static int
1269 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1270                  unsigned n)
1271 {
1272         struct fm10k_hw_stats *hw_stats =
1273                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1274         unsigned i, q, count = 0;
1275
1276         if (n < FM10K_NB_XSTATS)
1277                 return FM10K_NB_XSTATS;
1278
1279         /* Global stats */
1280         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1281                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1282                         fm10k_hw_stats_strings[count].offset);
1283                 xstats[count].id = count;
1284                 count++;
1285         }
1286
1287         /* PF queue stats */
1288         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1289                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1290                         xstats[count].value =
1291                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1292                                 fm10k_hw_stats_rx_q_strings[i].offset);
1293                         xstats[count].id = count;
1294                         count++;
1295                 }
1296                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1297                         xstats[count].value =
1298                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1299                                 fm10k_hw_stats_tx_q_strings[i].offset);
1300                         xstats[count].id = count;
1301                         count++;
1302                 }
1303         }
1304
1305         return FM10K_NB_XSTATS;
1306 }
1307
1308 static int
1309 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1310 {
1311         uint64_t ipackets, opackets, ibytes, obytes, imissed;
1312         struct fm10k_hw *hw =
1313                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1314         struct fm10k_hw_stats *hw_stats =
1315                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1316         int i;
1317
1318         PMD_INIT_FUNC_TRACE();
1319
1320         fm10k_update_hw_stats(hw, hw_stats);
1321
1322         ipackets = opackets = ibytes = obytes = imissed = 0;
1323         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1324                 (i < hw->mac.max_queues); ++i) {
1325                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1326                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1327                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1328                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1329                 stats->q_errors[i]   = hw_stats->q[i].rx_drops.count;
1330                 ipackets += stats->q_ipackets[i];
1331                 opackets += stats->q_opackets[i];
1332                 ibytes   += stats->q_ibytes[i];
1333                 obytes   += stats->q_obytes[i];
1334                 imissed  += stats->q_errors[i];
1335         }
1336         stats->ipackets = ipackets;
1337         stats->opackets = opackets;
1338         stats->ibytes = ibytes;
1339         stats->obytes = obytes;
1340         stats->imissed = imissed;
1341         return 0;
1342 }
1343
1344 static int
1345 fm10k_stats_reset(struct rte_eth_dev *dev)
1346 {
1347         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         struct fm10k_hw_stats *hw_stats =
1349                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1350
1351         PMD_INIT_FUNC_TRACE();
1352
1353         memset(hw_stats, 0, sizeof(*hw_stats));
1354         fm10k_rebind_hw_stats(hw, hw_stats);
1355
1356         return 0;
1357 }
1358
1359 static int
1360 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1361         struct rte_eth_dev_info *dev_info)
1362 {
1363         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364         struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1365
1366         PMD_INIT_FUNC_TRACE();
1367
1368         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1369         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1370         dev_info->max_rx_queues      = hw->mac.max_queues;
1371         dev_info->max_tx_queues      = hw->mac.max_queues;
1372         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1373         dev_info->max_hash_mac_addrs = 0;
1374         dev_info->max_vfs            = pdev->max_vfs;
1375         dev_info->vmdq_pool_base     = 0;
1376         dev_info->vmdq_queue_base    = 0;
1377         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1378         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1379         dev_info->rx_queue_offload_capa = fm10k_get_rx_queue_offloads_capa(dev);
1380         dev_info->rx_offload_capa = fm10k_get_rx_port_offloads_capa(dev) |
1381                                     dev_info->rx_queue_offload_capa;
1382         dev_info->tx_queue_offload_capa = fm10k_get_tx_queue_offloads_capa(dev);
1383         dev_info->tx_offload_capa = fm10k_get_tx_port_offloads_capa(dev) |
1384                                     dev_info->tx_queue_offload_capa;
1385
1386         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1387         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1388         dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1389                                         ETH_RSS_IPV6 |
1390                                         ETH_RSS_IPV6_EX |
1391                                         ETH_RSS_NONFRAG_IPV4_TCP |
1392                                         ETH_RSS_NONFRAG_IPV6_TCP |
1393                                         ETH_RSS_IPV6_TCP_EX |
1394                                         ETH_RSS_NONFRAG_IPV4_UDP |
1395                                         ETH_RSS_NONFRAG_IPV6_UDP |
1396                                         ETH_RSS_IPV6_UDP_EX;
1397
1398         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1399                 .rx_thresh = {
1400                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1401                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1402                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1403                 },
1404                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1405                 .rx_drop_en = 0,
1406                 .offloads = 0,
1407         };
1408
1409         dev_info->default_txconf = (struct rte_eth_txconf) {
1410                 .tx_thresh = {
1411                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1412                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1413                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1414                 },
1415                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1416                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1417                 .offloads = 0,
1418         };
1419
1420         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1421                 .nb_max = FM10K_MAX_RX_DESC,
1422                 .nb_min = FM10K_MIN_RX_DESC,
1423                 .nb_align = FM10K_MULT_RX_DESC,
1424         };
1425
1426         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1427                 .nb_max = FM10K_MAX_TX_DESC,
1428                 .nb_min = FM10K_MIN_TX_DESC,
1429                 .nb_align = FM10K_MULT_TX_DESC,
1430                 .nb_seg_max = FM10K_TX_MAX_SEG,
1431                 .nb_mtu_seg_max = FM10K_TX_MAX_MTU_SEG,
1432         };
1433
1434         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1435                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1436                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1437
1438         return 0;
1439 }
1440
1441 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1442 static const uint32_t *
1443 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1444 {
1445         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1446             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1447                 static uint32_t ptypes[] = {
1448                         /* refers to rx_desc_to_ol_flags() */
1449                         RTE_PTYPE_L2_ETHER,
1450                         RTE_PTYPE_L3_IPV4,
1451                         RTE_PTYPE_L3_IPV4_EXT,
1452                         RTE_PTYPE_L3_IPV6,
1453                         RTE_PTYPE_L3_IPV6_EXT,
1454                         RTE_PTYPE_L4_TCP,
1455                         RTE_PTYPE_L4_UDP,
1456                         RTE_PTYPE_UNKNOWN
1457                 };
1458
1459                 return ptypes;
1460         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1461                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1462                 static uint32_t ptypes_vec[] = {
1463                         /* refers to fm10k_desc_to_pktype_v() */
1464                         RTE_PTYPE_L3_IPV4,
1465                         RTE_PTYPE_L3_IPV4_EXT,
1466                         RTE_PTYPE_L3_IPV6,
1467                         RTE_PTYPE_L3_IPV6_EXT,
1468                         RTE_PTYPE_L4_TCP,
1469                         RTE_PTYPE_L4_UDP,
1470                         RTE_PTYPE_TUNNEL_GENEVE,
1471                         RTE_PTYPE_TUNNEL_NVGRE,
1472                         RTE_PTYPE_TUNNEL_VXLAN,
1473                         RTE_PTYPE_TUNNEL_GRE,
1474                         RTE_PTYPE_UNKNOWN
1475                 };
1476
1477                 return ptypes_vec;
1478         }
1479
1480         return NULL;
1481 }
1482 #else
1483 static const uint32_t *
1484 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1485 {
1486         return NULL;
1487 }
1488 #endif
1489
1490 static int
1491 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1492 {
1493         s32 result;
1494         uint16_t mac_num = 0;
1495         uint32_t vid_idx, vid_bit, mac_index;
1496         struct fm10k_hw *hw;
1497         struct fm10k_macvlan_filter_info *macvlan;
1498         struct rte_eth_dev_data *data = dev->data;
1499
1500         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1501         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1502
1503         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1504                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1505                 return -EINVAL;
1506         }
1507
1508         if (vlan_id > ETH_VLAN_ID_MAX) {
1509                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1510                 return -EINVAL;
1511         }
1512
1513         vid_idx = FM10K_VFTA_IDX(vlan_id);
1514         vid_bit = FM10K_VFTA_BIT(vlan_id);
1515         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1516         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1517                 return 0;
1518         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1519         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1520                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1521                         "in the VLAN filter table");
1522                 return -EINVAL;
1523         }
1524
1525         fm10k_mbx_lock(hw);
1526         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1527         fm10k_mbx_unlock(hw);
1528         if (result != FM10K_SUCCESS) {
1529                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1530                 return -EIO;
1531         }
1532
1533         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1534                         (result == FM10K_SUCCESS); mac_index++) {
1535                 if (rte_is_zero_ether_addr(&data->mac_addrs[mac_index]))
1536                         continue;
1537                 if (mac_num > macvlan->mac_num - 1) {
1538                         PMD_INIT_LOG(ERR, "MAC address number "
1539                                         "not match");
1540                         break;
1541                 }
1542                 fm10k_mbx_lock(hw);
1543                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1544                         data->mac_addrs[mac_index].addr_bytes,
1545                         vlan_id, on, 0);
1546                 fm10k_mbx_unlock(hw);
1547                 mac_num++;
1548         }
1549         if (result != FM10K_SUCCESS) {
1550                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1551                 return -EIO;
1552         }
1553
1554         if (on) {
1555                 macvlan->vlan_num++;
1556                 macvlan->vfta[vid_idx] |= vid_bit;
1557         } else {
1558                 macvlan->vlan_num--;
1559                 macvlan->vfta[vid_idx] &= ~vid_bit;
1560         }
1561         return 0;
1562 }
1563
1564 static int
1565 fm10k_vlan_offload_set(struct rte_eth_dev *dev __rte_unused,
1566                        int mask __rte_unused)
1567 {
1568         return 0;
1569 }
1570
1571 /* Add/Remove a MAC address, and update filters to main VSI */
1572 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1573                 const u8 *mac, bool add, uint32_t pool)
1574 {
1575         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576         struct fm10k_macvlan_filter_info *macvlan;
1577         uint32_t i, j, k;
1578
1579         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1580
1581         if (pool != MAIN_VSI_POOL_NUMBER) {
1582                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1583                         "mac to pool %u", pool);
1584                 return;
1585         }
1586         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1587                 if (!macvlan->vfta[j])
1588                         continue;
1589                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1590                         if (!(macvlan->vfta[j] & (1 << k)))
1591                                 continue;
1592                         if (i + 1 > macvlan->vlan_num) {
1593                                 PMD_INIT_LOG(ERR, "vlan number not match");
1594                                 return;
1595                         }
1596                         fm10k_mbx_lock(hw);
1597                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1598                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1599                         fm10k_mbx_unlock(hw);
1600                         i++;
1601                 }
1602         }
1603 }
1604
1605 /* Add/Remove a MAC address, and update filters to VMDQ */
1606 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1607                 const u8 *mac, bool add, uint32_t pool)
1608 {
1609         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         struct fm10k_macvlan_filter_info *macvlan;
1611         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1612         uint32_t i;
1613
1614         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1615         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1616
1617         if (pool > macvlan->nb_queue_pools) {
1618                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1619                         " Max pool is %u",
1620                         pool, macvlan->nb_queue_pools);
1621                 return;
1622         }
1623         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1624                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1625                         continue;
1626                 fm10k_mbx_lock(hw);
1627                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1628                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1629                 fm10k_mbx_unlock(hw);
1630         }
1631 }
1632
1633 /* Add/Remove a MAC address, and update filters */
1634 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1635                 const u8 *mac, bool add, uint32_t pool)
1636 {
1637         struct fm10k_macvlan_filter_info *macvlan;
1638
1639         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1640
1641         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1642                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1643         else
1644                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1645
1646         if (add)
1647                 macvlan->mac_num++;
1648         else
1649                 macvlan->mac_num--;
1650 }
1651
1652 /* Add a MAC address, and update filters */
1653 static int
1654 fm10k_macaddr_add(struct rte_eth_dev *dev,
1655                 struct rte_ether_addr *mac_addr,
1656                 uint32_t index,
1657                 uint32_t pool)
1658 {
1659         struct fm10k_macvlan_filter_info *macvlan;
1660
1661         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1662         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1663         macvlan->mac_vmdq_id[index] = pool;
1664         return 0;
1665 }
1666
1667 /* Remove a MAC address, and update filters */
1668 static void
1669 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1670 {
1671         struct rte_eth_dev_data *data = dev->data;
1672         struct fm10k_macvlan_filter_info *macvlan;
1673
1674         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1675         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1676                         FALSE, macvlan->mac_vmdq_id[index]);
1677         macvlan->mac_vmdq_id[index] = 0;
1678 }
1679
1680 static inline int
1681 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1682 {
1683         if ((request < min) || (request > max) || ((request % mult) != 0))
1684                 return -1;
1685         else
1686                 return 0;
1687 }
1688
1689
1690 static inline int
1691 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1692 {
1693         if ((request < min) || (request > max) || ((div % request) != 0))
1694                 return -1;
1695         else
1696                 return 0;
1697 }
1698
1699 static inline int
1700 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1701 {
1702         uint16_t rx_free_thresh;
1703
1704         if (conf->rx_free_thresh == 0)
1705                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1706         else
1707                 rx_free_thresh = conf->rx_free_thresh;
1708
1709         /* make sure the requested threshold satisfies the constraints */
1710         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1711                         FM10K_RX_FREE_THRESH_MAX(q),
1712                         FM10K_RX_FREE_THRESH_DIV(q),
1713                         rx_free_thresh)) {
1714                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1715                         "less than or equal to %u, "
1716                         "greater than or equal to %u, "
1717                         "and a divisor of %u",
1718                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1719                         FM10K_RX_FREE_THRESH_MIN(q),
1720                         FM10K_RX_FREE_THRESH_DIV(q));
1721                 return -EINVAL;
1722         }
1723
1724         q->alloc_thresh = rx_free_thresh;
1725         q->drop_en = conf->rx_drop_en;
1726         q->rx_deferred_start = conf->rx_deferred_start;
1727
1728         return 0;
1729 }
1730
1731 /*
1732  * Hardware requires specific alignment for Rx packet buffers. At
1733  * least one of the following two conditions must be satisfied.
1734  *  1. Address is 512B aligned
1735  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1736  *
1737  * As such, the driver may need to adjust the DMA address within the
1738  * buffer by up to 512B.
1739  *
1740  * return 1 if the element size is valid, otherwise return 0.
1741  */
1742 static int
1743 mempool_element_size_valid(struct rte_mempool *mp)
1744 {
1745         uint32_t min_size;
1746
1747         /* elt_size includes mbuf header and headroom */
1748         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1749                         RTE_PKTMBUF_HEADROOM;
1750
1751         /* account for up to 512B of alignment */
1752         min_size -= FM10K_RX_DATABUF_ALIGN;
1753
1754         /* sanity check for overflow */
1755         if (min_size > mp->elt_size)
1756                 return 0;
1757
1758         /* size is valid */
1759         return 1;
1760 }
1761
1762 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev)
1763 {
1764         RTE_SET_USED(dev);
1765
1766         return (uint64_t)(DEV_RX_OFFLOAD_SCATTER);
1767 }
1768
1769 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)
1770 {
1771         RTE_SET_USED(dev);
1772
1773         return  (uint64_t)(DEV_RX_OFFLOAD_VLAN_STRIP  |
1774                            DEV_RX_OFFLOAD_VLAN_FILTER |
1775                            DEV_RX_OFFLOAD_IPV4_CKSUM  |
1776                            DEV_RX_OFFLOAD_UDP_CKSUM   |
1777                            DEV_RX_OFFLOAD_TCP_CKSUM   |
1778                            DEV_RX_OFFLOAD_JUMBO_FRAME |
1779                            DEV_RX_OFFLOAD_HEADER_SPLIT |
1780                            DEV_RX_OFFLOAD_RSS_HASH);
1781 }
1782
1783 static int
1784 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1785         uint16_t nb_desc, unsigned int socket_id,
1786         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1787 {
1788         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789         struct fm10k_dev_info *dev_info =
1790                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1791         struct fm10k_rx_queue *q;
1792         const struct rte_memzone *mz;
1793         uint64_t offloads;
1794
1795         PMD_INIT_FUNC_TRACE();
1796
1797         offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1798
1799         /* make sure the mempool element size can account for alignment. */
1800         if (!mempool_element_size_valid(mp)) {
1801                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1802                 return -EINVAL;
1803         }
1804
1805         /* make sure a valid number of descriptors have been requested */
1806         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1807                                 FM10K_MULT_RX_DESC, nb_desc)) {
1808                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1809                         "less than or equal to %"PRIu32", "
1810                         "greater than or equal to %u, "
1811                         "and a multiple of %u",
1812                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1813                         FM10K_MULT_RX_DESC);
1814                 return -EINVAL;
1815         }
1816
1817         /*
1818          * if this queue existed already, free the associated memory. The
1819          * queue cannot be reused in case we need to allocate memory on
1820          * different socket than was previously used.
1821          */
1822         if (dev->data->rx_queues[queue_id] != NULL) {
1823                 rx_queue_free(dev->data->rx_queues[queue_id]);
1824                 dev->data->rx_queues[queue_id] = NULL;
1825         }
1826
1827         /* allocate memory for the queue structure */
1828         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1829                                 socket_id);
1830         if (q == NULL) {
1831                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1832                 return -ENOMEM;
1833         }
1834
1835         /* setup queue */
1836         q->mp = mp;
1837         q->nb_desc = nb_desc;
1838         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1839         q->port_id = dev->data->port_id;
1840         q->queue_id = queue_id;
1841         q->tail_ptr = (volatile uint32_t *)
1842                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1843         q->offloads = offloads;
1844         if (handle_rxconf(q, conf)) {
1845                 rte_free(q);
1846                 return -EINVAL;
1847         }
1848         /* allocate memory for the software ring */
1849         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1850                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1851                         RTE_CACHE_LINE_SIZE, socket_id);
1852         if (q->sw_ring == NULL) {
1853                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1854                 rte_free(q);
1855                 return -ENOMEM;
1856         }
1857
1858         /*
1859          * allocate memory for the hardware descriptor ring. A memzone large
1860          * enough to hold the maximum ring size is requested to allow for
1861          * resizing in later calls to the queue setup function.
1862          */
1863         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1864                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1865                                       socket_id);
1866         if (mz == NULL) {
1867                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1868                 rte_free(q->sw_ring);
1869                 rte_free(q);
1870                 return -ENOMEM;
1871         }
1872         q->hw_ring = mz->addr;
1873         q->hw_ring_phys_addr = mz->iova;
1874
1875         /* Check if number of descs satisfied Vector requirement */
1876         if (!rte_is_power_of_2(nb_desc)) {
1877                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1878                                     "preconditions - canceling the feature for "
1879                                     "the whole port[%d]",
1880                              q->queue_id, q->port_id);
1881                 dev_info->rx_vec_allowed = false;
1882         } else
1883                 fm10k_rxq_vec_setup(q);
1884
1885         dev->data->rx_queues[queue_id] = q;
1886         return 0;
1887 }
1888
1889 static void
1890 fm10k_rx_queue_release(void *queue)
1891 {
1892         PMD_INIT_FUNC_TRACE();
1893
1894         rx_queue_free(queue);
1895 }
1896
1897 static inline int
1898 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1899 {
1900         uint16_t tx_free_thresh;
1901         uint16_t tx_rs_thresh;
1902
1903         /* constraint MACROs require that tx_free_thresh is configured
1904          * before tx_rs_thresh */
1905         if (conf->tx_free_thresh == 0)
1906                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1907         else
1908                 tx_free_thresh = conf->tx_free_thresh;
1909
1910         /* make sure the requested threshold satisfies the constraints */
1911         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1912                         FM10K_TX_FREE_THRESH_MAX(q),
1913                         FM10K_TX_FREE_THRESH_DIV(q),
1914                         tx_free_thresh)) {
1915                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1916                         "less than or equal to %u, "
1917                         "greater than or equal to %u, "
1918                         "and a divisor of %u",
1919                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1920                         FM10K_TX_FREE_THRESH_MIN(q),
1921                         FM10K_TX_FREE_THRESH_DIV(q));
1922                 return -EINVAL;
1923         }
1924
1925         q->free_thresh = tx_free_thresh;
1926
1927         if (conf->tx_rs_thresh == 0)
1928                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1929         else
1930                 tx_rs_thresh = conf->tx_rs_thresh;
1931
1932         q->tx_deferred_start = conf->tx_deferred_start;
1933
1934         /* make sure the requested threshold satisfies the constraints */
1935         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1936                         FM10K_TX_RS_THRESH_MAX(q),
1937                         FM10K_TX_RS_THRESH_DIV(q),
1938                         tx_rs_thresh)) {
1939                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1940                         "less than or equal to %u, "
1941                         "greater than or equal to %u, "
1942                         "and a divisor of %u",
1943                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1944                         FM10K_TX_RS_THRESH_MIN(q),
1945                         FM10K_TX_RS_THRESH_DIV(q));
1946                 return -EINVAL;
1947         }
1948
1949         q->rs_thresh = tx_rs_thresh;
1950
1951         return 0;
1952 }
1953
1954 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1955 {
1956         RTE_SET_USED(dev);
1957
1958         return 0;
1959 }
1960
1961 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1962 {
1963         RTE_SET_USED(dev);
1964
1965         return (uint64_t)(DEV_TX_OFFLOAD_VLAN_INSERT |
1966                           DEV_TX_OFFLOAD_MULTI_SEGS  |
1967                           DEV_TX_OFFLOAD_IPV4_CKSUM  |
1968                           DEV_TX_OFFLOAD_UDP_CKSUM   |
1969                           DEV_TX_OFFLOAD_TCP_CKSUM   |
1970                           DEV_TX_OFFLOAD_TCP_TSO);
1971 }
1972
1973 static int
1974 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1975         uint16_t nb_desc, unsigned int socket_id,
1976         const struct rte_eth_txconf *conf)
1977 {
1978         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979         struct fm10k_tx_queue *q;
1980         const struct rte_memzone *mz;
1981         uint64_t offloads;
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         offloads = conf->offloads | dev->data->dev_conf.txmode.offloads;
1986
1987         /* make sure a valid number of descriptors have been requested */
1988         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1989                                 FM10K_MULT_TX_DESC, nb_desc)) {
1990                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1991                         "less than or equal to %"PRIu32", "
1992                         "greater than or equal to %u, "
1993                         "and a multiple of %u",
1994                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1995                         FM10K_MULT_TX_DESC);
1996                 return -EINVAL;
1997         }
1998
1999         /*
2000          * if this queue existed already, free the associated memory. The
2001          * queue cannot be reused in case we need to allocate memory on
2002          * different socket than was previously used.
2003          */
2004         if (dev->data->tx_queues[queue_id] != NULL) {
2005                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
2006
2007                 tx_queue_free(txq);
2008                 dev->data->tx_queues[queue_id] = NULL;
2009         }
2010
2011         /* allocate memory for the queue structure */
2012         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2013                                 socket_id);
2014         if (q == NULL) {
2015                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2016                 return -ENOMEM;
2017         }
2018
2019         /* setup queue */
2020         q->nb_desc = nb_desc;
2021         q->port_id = dev->data->port_id;
2022         q->queue_id = queue_id;
2023         q->offloads = offloads;
2024         q->ops = &def_txq_ops;
2025         q->tail_ptr = (volatile uint32_t *)
2026                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2027         if (handle_txconf(q, conf)) {
2028                 rte_free(q);
2029                 return -EINVAL;
2030         }
2031
2032         /* allocate memory for the software ring */
2033         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2034                                         nb_desc * sizeof(struct rte_mbuf *),
2035                                         RTE_CACHE_LINE_SIZE, socket_id);
2036         if (q->sw_ring == NULL) {
2037                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2038                 rte_free(q);
2039                 return -ENOMEM;
2040         }
2041
2042         /*
2043          * allocate memory for the hardware descriptor ring. A memzone large
2044          * enough to hold the maximum ring size is requested to allow for
2045          * resizing in later calls to the queue setup function.
2046          */
2047         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2048                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2049                                       socket_id);
2050         if (mz == NULL) {
2051                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2052                 rte_free(q->sw_ring);
2053                 rte_free(q);
2054                 return -ENOMEM;
2055         }
2056         q->hw_ring = mz->addr;
2057         q->hw_ring_phys_addr = mz->iova;
2058
2059         /*
2060          * allocate memory for the RS bit tracker. Enough slots to hold the
2061          * descriptor index for each RS bit needing to be set are required.
2062          */
2063         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2064                                 ((nb_desc + 1) / q->rs_thresh) *
2065                                 sizeof(uint16_t),
2066                                 RTE_CACHE_LINE_SIZE, socket_id);
2067         if (q->rs_tracker.list == NULL) {
2068                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2069                 rte_free(q->sw_ring);
2070                 rte_free(q);
2071                 return -ENOMEM;
2072         }
2073
2074         dev->data->tx_queues[queue_id] = q;
2075         return 0;
2076 }
2077
2078 static void
2079 fm10k_tx_queue_release(void *queue)
2080 {
2081         struct fm10k_tx_queue *q = queue;
2082         PMD_INIT_FUNC_TRACE();
2083
2084         tx_queue_free(q);
2085 }
2086
2087 static int
2088 fm10k_reta_update(struct rte_eth_dev *dev,
2089                         struct rte_eth_rss_reta_entry64 *reta_conf,
2090                         uint16_t reta_size)
2091 {
2092         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093         uint16_t i, j, idx, shift;
2094         uint8_t mask;
2095         uint32_t reta;
2096
2097         PMD_INIT_FUNC_TRACE();
2098
2099         if (reta_size > FM10K_MAX_RSS_INDICES) {
2100                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2101                         "(%d) doesn't match the number hardware can supported "
2102                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2103                 return -EINVAL;
2104         }
2105
2106         /*
2107          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2108          * 128-entries in 32 registers
2109          */
2110         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2111                 idx = i / RTE_RETA_GROUP_SIZE;
2112                 shift = i % RTE_RETA_GROUP_SIZE;
2113                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2114                                 BIT_MASK_PER_UINT32);
2115                 if (mask == 0)
2116                         continue;
2117
2118                 reta = 0;
2119                 if (mask != BIT_MASK_PER_UINT32)
2120                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2121
2122                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2123                         if (mask & (0x1 << j)) {
2124                                 if (mask != 0xF)
2125                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2126                                 reta |= reta_conf[idx].reta[shift + j] <<
2127                                                 (CHAR_BIT * j);
2128                         }
2129                 }
2130                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2131         }
2132
2133         return 0;
2134 }
2135
2136 static int
2137 fm10k_reta_query(struct rte_eth_dev *dev,
2138                         struct rte_eth_rss_reta_entry64 *reta_conf,
2139                         uint16_t reta_size)
2140 {
2141         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         uint16_t i, j, idx, shift;
2143         uint8_t mask;
2144         uint32_t reta;
2145
2146         PMD_INIT_FUNC_TRACE();
2147
2148         if (reta_size < FM10K_MAX_RSS_INDICES) {
2149                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2150                         "(%d) doesn't match the number hardware can supported "
2151                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2152                 return -EINVAL;
2153         }
2154
2155         /*
2156          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2157          * 128-entries in 32 registers
2158          */
2159         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2160                 idx = i / RTE_RETA_GROUP_SIZE;
2161                 shift = i % RTE_RETA_GROUP_SIZE;
2162                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2163                                 BIT_MASK_PER_UINT32);
2164                 if (mask == 0)
2165                         continue;
2166
2167                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2168                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2169                         if (mask & (0x1 << j))
2170                                 reta_conf[idx].reta[shift + j] = ((reta >>
2171                                         CHAR_BIT * j) & UINT8_MAX);
2172                 }
2173         }
2174
2175         return 0;
2176 }
2177
2178 static int
2179 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2180         struct rte_eth_rss_conf *rss_conf)
2181 {
2182         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2184         uint32_t mrqc;
2185         uint64_t hf = rss_conf->rss_hf;
2186         int i;
2187
2188         PMD_INIT_FUNC_TRACE();
2189
2190         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2191                                 FM10K_RSSRK_ENTRIES_PER_REG))
2192                 return -EINVAL;
2193
2194         if (hf == 0)
2195                 return -EINVAL;
2196
2197         mrqc = 0;
2198         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2199         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2200         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2201         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2202         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2203         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2204         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2205         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2206         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2207
2208         /* If the mapping doesn't fit any supported, return */
2209         if (mrqc == 0)
2210                 return -EINVAL;
2211
2212         if (key != NULL)
2213                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2214                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2215
2216         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2217
2218         return 0;
2219 }
2220
2221 static int
2222 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2223         struct rte_eth_rss_conf *rss_conf)
2224 {
2225         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2227         uint32_t mrqc;
2228         uint64_t hf;
2229         int i;
2230
2231         PMD_INIT_FUNC_TRACE();
2232
2233         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2234                                 FM10K_RSSRK_ENTRIES_PER_REG))
2235                 return -EINVAL;
2236
2237         if (key != NULL)
2238                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2239                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2240
2241         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2242         hf = 0;
2243         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2244         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2245         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2246         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2247         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2248         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2249         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2250         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2251         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2252
2253         rss_conf->rss_hf = hf;
2254
2255         return 0;
2256 }
2257
2258 static void
2259 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2260 {
2261         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2263
2264         /* Bind all local non-queue interrupt to vector 0 */
2265         int_map |= FM10K_MISC_VEC_ID;
2266
2267         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2268         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2269         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2270         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2271         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2272         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2273
2274         /* Enable misc causes */
2275         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2276                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2277                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2278                                 FM10K_EIMR_ENABLE(MAILBOX) |
2279                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2280                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2281                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2282                                 FM10K_EIMR_ENABLE(VFLR));
2283
2284         /* Enable ITR 0 */
2285         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2286                                         FM10K_ITR_MASK_CLEAR);
2287         FM10K_WRITE_FLUSH(hw);
2288 }
2289
2290 static void
2291 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2292 {
2293         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2294         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2295
2296         int_map |= FM10K_MISC_VEC_ID;
2297
2298         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2299         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2300         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2301         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2302         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2303         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2304
2305         /* Disable misc causes */
2306         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2307                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2308                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2309                                 FM10K_EIMR_DISABLE(MAILBOX) |
2310                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2311                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2312                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2313                                 FM10K_EIMR_DISABLE(VFLR));
2314
2315         /* Disable ITR 0 */
2316         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2317         FM10K_WRITE_FLUSH(hw);
2318 }
2319
2320 static void
2321 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2322 {
2323         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2324         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2325
2326         /* Bind all local non-queue interrupt to vector 0 */
2327         int_map |= FM10K_MISC_VEC_ID;
2328
2329         /* Only INT 0 available, other 15 are reserved. */
2330         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2331
2332         /* Enable ITR 0 */
2333         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2334                                         FM10K_ITR_MASK_CLEAR);
2335         FM10K_WRITE_FLUSH(hw);
2336 }
2337
2338 static void
2339 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2340 {
2341         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2343
2344         int_map |= FM10K_MISC_VEC_ID;
2345
2346         /* Only INT 0 available, other 15 are reserved. */
2347         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2348
2349         /* Disable ITR 0 */
2350         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2351         FM10K_WRITE_FLUSH(hw);
2352 }
2353
2354 static int
2355 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2356 {
2357         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358         struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2359
2360         /* Enable ITR */
2361         if (hw->mac.type == fm10k_mac_pf)
2362                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2363                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2364         else
2365                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2366                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2367         rte_intr_ack(&pdev->intr_handle);
2368         return 0;
2369 }
2370
2371 static int
2372 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2373 {
2374         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375         struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2376
2377         /* Disable ITR */
2378         if (hw->mac.type == fm10k_mac_pf)
2379                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2380                         FM10K_ITR_MASK_SET);
2381         else
2382                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2383                         FM10K_ITR_MASK_SET);
2384         return 0;
2385 }
2386
2387 static int
2388 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2389 {
2390         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2392         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2393         uint32_t intr_vector, vec;
2394         uint16_t queue_id;
2395         int result = 0;
2396
2397         /* fm10k needs one separate interrupt for mailbox,
2398          * so only drivers which support multiple interrupt vectors
2399          * e.g. vfio-pci can work for fm10k interrupt mode
2400          */
2401         if (!rte_intr_cap_multiple(intr_handle) ||
2402                         dev->data->dev_conf.intr_conf.rxq == 0)
2403                 return result;
2404
2405         intr_vector = dev->data->nb_rx_queues;
2406
2407         /* disable interrupt first */
2408         rte_intr_disable(intr_handle);
2409         if (hw->mac.type == fm10k_mac_pf)
2410                 fm10k_dev_disable_intr_pf(dev);
2411         else
2412                 fm10k_dev_disable_intr_vf(dev);
2413
2414         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2415                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2416                 result = -EIO;
2417         }
2418
2419         if (rte_intr_dp_is_en(intr_handle) && !result) {
2420                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2421                         dev->data->nb_rx_queues * sizeof(int), 0);
2422                 if (intr_handle->intr_vec) {
2423                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2424                                         queue_id < dev->data->nb_rx_queues;
2425                                         queue_id++) {
2426                                 intr_handle->intr_vec[queue_id] = vec;
2427                                 if (vec < intr_handle->nb_efd - 1
2428                                                 + FM10K_RX_VEC_START)
2429                                         vec++;
2430                         }
2431                 } else {
2432                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2433                                 " intr_vec", dev->data->nb_rx_queues);
2434                         rte_intr_efd_disable(intr_handle);
2435                         result = -ENOMEM;
2436                 }
2437         }
2438
2439         if (hw->mac.type == fm10k_mac_pf)
2440                 fm10k_dev_enable_intr_pf(dev);
2441         else
2442                 fm10k_dev_enable_intr_vf(dev);
2443         rte_intr_enable(intr_handle);
2444         hw->mac.ops.update_int_moderator(hw);
2445         return result;
2446 }
2447
2448 static int
2449 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2450 {
2451         struct fm10k_fault fault;
2452         int err;
2453         const char *estr = "Unknown error";
2454
2455         /* Process PCA fault */
2456         if (eicr & FM10K_EICR_PCA_FAULT) {
2457                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2458                 if (err)
2459                         goto error;
2460                 switch (fault.type) {
2461                 case PCA_NO_FAULT:
2462                         estr = "PCA_NO_FAULT"; break;
2463                 case PCA_UNMAPPED_ADDR:
2464                         estr = "PCA_UNMAPPED_ADDR"; break;
2465                 case PCA_BAD_QACCESS_PF:
2466                         estr = "PCA_BAD_QACCESS_PF"; break;
2467                 case PCA_BAD_QACCESS_VF:
2468                         estr = "PCA_BAD_QACCESS_VF"; break;
2469                 case PCA_MALICIOUS_REQ:
2470                         estr = "PCA_MALICIOUS_REQ"; break;
2471                 case PCA_POISONED_TLP:
2472                         estr = "PCA_POISONED_TLP"; break;
2473                 case PCA_TLP_ABORT:
2474                         estr = "PCA_TLP_ABORT"; break;
2475                 default:
2476                         goto error;
2477                 }
2478                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2479                         estr, fault.func ? "VF" : "PF", fault.func,
2480                         fault.address, fault.specinfo);
2481         }
2482
2483         /* Process THI fault */
2484         if (eicr & FM10K_EICR_THI_FAULT) {
2485                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2486                 if (err)
2487                         goto error;
2488                 switch (fault.type) {
2489                 case THI_NO_FAULT:
2490                         estr = "THI_NO_FAULT"; break;
2491                 case THI_MAL_DIS_Q_FAULT:
2492                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2493                 default:
2494                         goto error;
2495                 }
2496                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2497                         estr, fault.func ? "VF" : "PF", fault.func,
2498                         fault.address, fault.specinfo);
2499         }
2500
2501         /* Process FUM fault */
2502         if (eicr & FM10K_EICR_FUM_FAULT) {
2503                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2504                 if (err)
2505                         goto error;
2506                 switch (fault.type) {
2507                 case FUM_NO_FAULT:
2508                         estr = "FUM_NO_FAULT"; break;
2509                 case FUM_UNMAPPED_ADDR:
2510                         estr = "FUM_UNMAPPED_ADDR"; break;
2511                 case FUM_POISONED_TLP:
2512                         estr = "FUM_POISONED_TLP"; break;
2513                 case FUM_BAD_VF_QACCESS:
2514                         estr = "FUM_BAD_VF_QACCESS"; break;
2515                 case FUM_ADD_DECODE_ERR:
2516                         estr = "FUM_ADD_DECODE_ERR"; break;
2517                 case FUM_RO_ERROR:
2518                         estr = "FUM_RO_ERROR"; break;
2519                 case FUM_QPRC_CRC_ERROR:
2520                         estr = "FUM_QPRC_CRC_ERROR"; break;
2521                 case FUM_CSR_TIMEOUT:
2522                         estr = "FUM_CSR_TIMEOUT"; break;
2523                 case FUM_INVALID_TYPE:
2524                         estr = "FUM_INVALID_TYPE"; break;
2525                 case FUM_INVALID_LENGTH:
2526                         estr = "FUM_INVALID_LENGTH"; break;
2527                 case FUM_INVALID_BE:
2528                         estr = "FUM_INVALID_BE"; break;
2529                 case FUM_INVALID_ALIGN:
2530                         estr = "FUM_INVALID_ALIGN"; break;
2531                 default:
2532                         goto error;
2533                 }
2534                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2535                         estr, fault.func ? "VF" : "PF", fault.func,
2536                         fault.address, fault.specinfo);
2537         }
2538
2539         return 0;
2540 error:
2541         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2542         return err;
2543 }
2544
2545 /**
2546  * PF interrupt handler triggered by NIC for handling specific interrupt.
2547  *
2548  * @param handle
2549  *  Pointer to interrupt handle.
2550  * @param param
2551  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2552  *
2553  * @return
2554  *  void
2555  */
2556 static void
2557 fm10k_dev_interrupt_handler_pf(void *param)
2558 {
2559         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2560         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2561         uint32_t cause, status;
2562         struct fm10k_dev_info *dev_info =
2563                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2564         int status_mbx;
2565         s32 err;
2566
2567         if (hw->mac.type != fm10k_mac_pf)
2568                 return;
2569
2570         cause = FM10K_READ_REG(hw, FM10K_EICR);
2571
2572         /* Handle PCI fault cases */
2573         if (cause & FM10K_EICR_FAULT_MASK) {
2574                 PMD_INIT_LOG(ERR, "INT: find fault!");
2575                 fm10k_dev_handle_fault(hw, cause);
2576         }
2577
2578         /* Handle switch up/down */
2579         if (cause & FM10K_EICR_SWITCHNOTREADY)
2580                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2581
2582         if (cause & FM10K_EICR_SWITCHREADY) {
2583                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2584                 if (dev_info->sm_down == 1) {
2585                         fm10k_mbx_lock(hw);
2586
2587                         /* For recreating logical ports */
2588                         status_mbx = hw->mac.ops.update_lport_state(hw,
2589                                         hw->mac.dglort_map, MAX_LPORT_NUM, 1);
2590                         if (status_mbx == FM10K_SUCCESS)
2591                                 PMD_INIT_LOG(INFO,
2592                                         "INT: Recreated Logical port");
2593                         else
2594                                 PMD_INIT_LOG(INFO,
2595                                         "INT: Logical ports weren't recreated");
2596
2597                         status_mbx = hw->mac.ops.update_xcast_mode(hw,
2598                                 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2599                         if (status_mbx != FM10K_SUCCESS)
2600                                 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2601
2602                         fm10k_mbx_unlock(hw);
2603
2604                         /* first clear the internal SW recording structure */
2605                         if (!(dev->data->dev_conf.rxmode.mq_mode &
2606                                                 ETH_MQ_RX_VMDQ_FLAG))
2607                                 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2608                                         false);
2609
2610                         fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2611                                         MAIN_VSI_POOL_NUMBER);
2612
2613                         /*
2614                          * Add default mac address and vlan for the logical
2615                          * ports that have been created, leave to the
2616                          * application to fully recover Rx filtering.
2617                          */
2618                         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2619                                         MAIN_VSI_POOL_NUMBER);
2620
2621                         if (!(dev->data->dev_conf.rxmode.mq_mode &
2622                                                 ETH_MQ_RX_VMDQ_FLAG))
2623                                 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2624                                         true);
2625
2626                         dev_info->sm_down = 0;
2627                         rte_eth_dev_callback_process(dev,
2628                                         RTE_ETH_EVENT_INTR_LSC,
2629                                         NULL);
2630                 }
2631         }
2632
2633         /* Handle mailbox message */
2634         fm10k_mbx_lock(hw);
2635         err = hw->mbx.ops.process(hw, &hw->mbx);
2636         fm10k_mbx_unlock(hw);
2637
2638         if (err == FM10K_ERR_RESET_REQUESTED) {
2639                 PMD_INIT_LOG(INFO, "INT: Switch is down");
2640                 dev_info->sm_down = 1;
2641                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2642         }
2643
2644         /* Handle SRAM error */
2645         if (cause & FM10K_EICR_SRAMERROR) {
2646                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2647
2648                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2649                 /* Write to clear pending bits */
2650                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2651
2652                 /* Todo: print out error message after shared code  updates */
2653         }
2654
2655         /* Clear these 3 events if having any */
2656         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2657                  FM10K_EICR_SWITCHREADY;
2658         if (cause)
2659                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2660
2661         /* Re-enable interrupt from device side */
2662         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2663                                         FM10K_ITR_MASK_CLEAR);
2664         /* Re-enable interrupt from host side */
2665         rte_intr_ack(dev->intr_handle);
2666 }
2667
2668 /**
2669  * VF interrupt handler triggered by NIC for handling specific interrupt.
2670  *
2671  * @param handle
2672  *  Pointer to interrupt handle.
2673  * @param param
2674  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2675  *
2676  * @return
2677  *  void
2678  */
2679 static void
2680 fm10k_dev_interrupt_handler_vf(void *param)
2681 {
2682         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2683         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684         struct fm10k_mbx_info *mbx = &hw->mbx;
2685         struct fm10k_dev_info *dev_info =
2686                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2687         const enum fm10k_mbx_state state = mbx->state;
2688         int status_mbx;
2689
2690         if (hw->mac.type != fm10k_mac_vf)
2691                 return;
2692
2693         /* Handle mailbox message if lock is acquired */
2694         fm10k_mbx_lock(hw);
2695         hw->mbx.ops.process(hw, &hw->mbx);
2696         fm10k_mbx_unlock(hw);
2697
2698         if (state == FM10K_STATE_OPEN && mbx->state == FM10K_STATE_CONNECT) {
2699                 PMD_INIT_LOG(INFO, "INT: Switch has gone down");
2700
2701                 fm10k_mbx_lock(hw);
2702                 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2703                                 MAX_LPORT_NUM, 1);
2704                 fm10k_mbx_unlock(hw);
2705
2706                 /* Setting reset flag */
2707                 dev_info->sm_down = 1;
2708                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2709         }
2710
2711         if (dev_info->sm_down == 1 &&
2712                         hw->mac.dglort_map == FM10K_DGLORTMAP_ZERO) {
2713                 PMD_INIT_LOG(INFO, "INT: Switch has gone up");
2714                 fm10k_mbx_lock(hw);
2715                 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2716                                 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2717                 if (status_mbx != FM10K_SUCCESS)
2718                         PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2719                 fm10k_mbx_unlock(hw);
2720
2721                 /* first clear the internal SW recording structure */
2722                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, false);
2723                 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2724                                 MAIN_VSI_POOL_NUMBER);
2725
2726                 /*
2727                  * Add default mac address and vlan for the logical ports that
2728                  * have been created, leave to the application to fully recover
2729                  * Rx filtering.
2730                  */
2731                 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2732                                 MAIN_VSI_POOL_NUMBER);
2733                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
2734
2735                 dev_info->sm_down = 0;
2736                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2737         }
2738
2739         /* Re-enable interrupt from device side */
2740         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2741                                         FM10K_ITR_MASK_CLEAR);
2742         /* Re-enable interrupt from host side */
2743         rte_intr_ack(dev->intr_handle);
2744 }
2745
2746 /* Mailbox message handler in VF */
2747 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2748         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2749         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2750         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2751         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2752 };
2753
2754 static int
2755 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2756 {
2757         int err = 0;
2758
2759         /* Initialize mailbox lock */
2760         fm10k_mbx_initlock(hw);
2761
2762         /* Replace default message handler with new ones */
2763         if (hw->mac.type == fm10k_mac_vf)
2764                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2765
2766         if (err) {
2767                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2768                                 err);
2769                 return err;
2770         }
2771         /* Connect to SM for PF device or PF for VF device */
2772         return hw->mbx.ops.connect(hw, &hw->mbx);
2773 }
2774
2775 static void
2776 fm10k_close_mbx_service(struct fm10k_hw *hw)
2777 {
2778         /* Disconnect from SM for PF device or PF for VF device */
2779         hw->mbx.ops.disconnect(hw, &hw->mbx);
2780 }
2781
2782 static int
2783 fm10k_dev_close(struct rte_eth_dev *dev)
2784 {
2785         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786         struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2787         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2788
2789         PMD_INIT_FUNC_TRACE();
2790         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2791                 return 0;
2792
2793         fm10k_mbx_lock(hw);
2794         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2795                 MAX_LPORT_NUM, false);
2796         fm10k_mbx_unlock(hw);
2797
2798         /* allow 100ms for device to quiesce */
2799         rte_delay_us(FM10K_SWITCH_QUIESCE_US);
2800
2801         /* Stop mailbox service first */
2802         fm10k_close_mbx_service(hw);
2803         fm10k_dev_stop(dev);
2804         fm10k_dev_queue_release(dev);
2805         fm10k_stop_hw(hw);
2806
2807         dev->dev_ops = NULL;
2808         dev->rx_pkt_burst = NULL;
2809         dev->tx_pkt_burst = NULL;
2810
2811         /* disable uio/vfio intr */
2812         rte_intr_disable(intr_handle);
2813
2814         /*PF/VF has different interrupt handling mechanism */
2815         if (hw->mac.type == fm10k_mac_pf) {
2816                 /* disable interrupt */
2817                 fm10k_dev_disable_intr_pf(dev);
2818
2819                 /* unregister callback func to eal lib */
2820                 rte_intr_callback_unregister(intr_handle,
2821                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2822         } else {
2823                 /* disable interrupt */
2824                 fm10k_dev_disable_intr_vf(dev);
2825
2826                 rte_intr_callback_unregister(intr_handle,
2827                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2828         }
2829
2830         return 0;
2831 }
2832
2833 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2834         .dev_configure          = fm10k_dev_configure,
2835         .dev_start              = fm10k_dev_start,
2836         .dev_stop               = fm10k_dev_stop,
2837         .dev_close              = fm10k_dev_close,
2838         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2839         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2840         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2841         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2842         .stats_get              = fm10k_stats_get,
2843         .xstats_get             = fm10k_xstats_get,
2844         .xstats_get_names       = fm10k_xstats_get_names,
2845         .stats_reset            = fm10k_stats_reset,
2846         .xstats_reset           = fm10k_stats_reset,
2847         .link_update            = fm10k_link_update,
2848         .dev_infos_get          = fm10k_dev_infos_get,
2849         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2850         .vlan_filter_set        = fm10k_vlan_filter_set,
2851         .vlan_offload_set       = fm10k_vlan_offload_set,
2852         .mac_addr_add           = fm10k_macaddr_add,
2853         .mac_addr_remove        = fm10k_macaddr_remove,
2854         .rx_queue_start         = fm10k_dev_rx_queue_start,
2855         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2856         .tx_queue_start         = fm10k_dev_tx_queue_start,
2857         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2858         .rx_queue_setup         = fm10k_rx_queue_setup,
2859         .rx_queue_release       = fm10k_rx_queue_release,
2860         .tx_queue_setup         = fm10k_tx_queue_setup,
2861         .tx_queue_release       = fm10k_tx_queue_release,
2862         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2863         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2864         .reta_update            = fm10k_reta_update,
2865         .reta_query             = fm10k_reta_query,
2866         .rss_hash_update        = fm10k_rss_hash_update,
2867         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2868 };
2869
2870 static int ftag_check_handler(__rte_unused const char *key,
2871                 const char *value, __rte_unused void *opaque)
2872 {
2873         if (strcmp(value, "1"))
2874                 return -1;
2875
2876         return 0;
2877 }
2878
2879 static int
2880 fm10k_check_ftag(struct rte_devargs *devargs)
2881 {
2882         struct rte_kvargs *kvlist;
2883         const char *ftag_key = "enable_ftag";
2884
2885         if (devargs == NULL)
2886                 return 0;
2887
2888         kvlist = rte_kvargs_parse(devargs->args, NULL);
2889         if (kvlist == NULL)
2890                 return 0;
2891
2892         if (!rte_kvargs_count(kvlist, ftag_key)) {
2893                 rte_kvargs_free(kvlist);
2894                 return 0;
2895         }
2896         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2897         if (rte_kvargs_process(kvlist, ftag_key,
2898                                 ftag_check_handler, NULL) < 0) {
2899                 rte_kvargs_free(kvlist);
2900                 return 0;
2901         }
2902         rte_kvargs_free(kvlist);
2903
2904         return 1;
2905 }
2906
2907 static uint16_t
2908 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
2909                     uint16_t nb_pkts)
2910 {
2911         uint16_t nb_tx = 0;
2912         struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
2913
2914         while (nb_pkts) {
2915                 uint16_t ret, num;
2916
2917                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
2918                 ret = fm10k_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
2919                                                  num);
2920                 nb_tx += ret;
2921                 nb_pkts -= ret;
2922                 if (ret < num)
2923                         break;
2924         }
2925
2926         return nb_tx;
2927 }
2928
2929 static void __rte_cold
2930 fm10k_set_tx_function(struct rte_eth_dev *dev)
2931 {
2932         struct fm10k_tx_queue *txq;
2933         int i;
2934         int use_sse = 1;
2935         uint16_t tx_ftag_en = 0;
2936
2937         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2938                 /* primary process has set the ftag flag and offloads */
2939                 txq = dev->data->tx_queues[0];
2940                 if (fm10k_tx_vec_condition_check(txq)) {
2941                         dev->tx_pkt_burst = fm10k_xmit_pkts;
2942                         dev->tx_pkt_prepare = fm10k_prep_pkts;
2943                         PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2944                 } else {
2945                         PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2946                         dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2947                         dev->tx_pkt_prepare = NULL;
2948                 }
2949                 return;
2950         }
2951
2952         if (fm10k_check_ftag(dev->device->devargs))
2953                 tx_ftag_en = 1;
2954
2955         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2956                 txq = dev->data->tx_queues[i];
2957                 txq->tx_ftag_en = tx_ftag_en;
2958                 /* Check if Vector Tx is satisfied */
2959                 if (fm10k_tx_vec_condition_check(txq))
2960                         use_sse = 0;
2961         }
2962
2963         if (use_sse) {
2964                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2965                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2966                         txq = dev->data->tx_queues[i];
2967                         fm10k_txq_vec_setup(txq);
2968                 }
2969                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2970                 dev->tx_pkt_prepare = NULL;
2971         } else {
2972                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2973                 dev->tx_pkt_prepare = fm10k_prep_pkts;
2974                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2975         }
2976 }
2977
2978 static void __rte_cold
2979 fm10k_set_rx_function(struct rte_eth_dev *dev)
2980 {
2981         struct fm10k_dev_info *dev_info =
2982                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2983         uint16_t i, rx_using_sse;
2984         uint16_t rx_ftag_en = 0;
2985
2986         if (fm10k_check_ftag(dev->device->devargs))
2987                 rx_ftag_en = 1;
2988
2989         /* In order to allow Vector Rx there are a few configuration
2990          * conditions to be met.
2991          */
2992         if (!fm10k_rx_vec_condition_check(dev) &&
2993                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2994                 if (dev->data->scattered_rx)
2995                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2996                 else
2997                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2998         } else if (dev->data->scattered_rx)
2999                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
3000         else
3001                 dev->rx_pkt_burst = fm10k_recv_pkts;
3002
3003         rx_using_sse =
3004                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
3005                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
3006
3007         if (rx_using_sse)
3008                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
3009         else
3010                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
3011
3012         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3013                 return;
3014
3015         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3016                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
3017
3018                 rxq->rx_using_sse = rx_using_sse;
3019                 rxq->rx_ftag_en = rx_ftag_en;
3020         }
3021 }
3022
3023 static void
3024 fm10k_params_init(struct rte_eth_dev *dev)
3025 {
3026         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027         struct fm10k_dev_info *info =
3028                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
3029
3030         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
3031          * there is no way to get link status without reading BAR4.  Until this
3032          * works, assume we have maximum bandwidth.
3033          * @todo - fix bus info
3034          */
3035         hw->bus_caps.speed = fm10k_bus_speed_8000;
3036         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
3037         hw->bus_caps.payload = fm10k_bus_payload_512;
3038         hw->bus.speed = fm10k_bus_speed_8000;
3039         hw->bus.width = fm10k_bus_width_pcie_x8;
3040         hw->bus.payload = fm10k_bus_payload_256;
3041
3042         info->rx_vec_allowed = true;
3043         info->sm_down = false;
3044 }
3045
3046 static int
3047 eth_fm10k_dev_init(struct rte_eth_dev *dev)
3048 {
3049         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3050         struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
3051         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3052         int diag, i;
3053         struct fm10k_macvlan_filter_info *macvlan;
3054
3055         PMD_INIT_FUNC_TRACE();
3056
3057         dev->dev_ops = &fm10k_eth_dev_ops;
3058         dev->rx_queue_count = fm10k_dev_rx_queue_count;
3059         dev->rx_descriptor_done = fm10k_dev_rx_descriptor_done;
3060         dev->rx_descriptor_status = fm10k_dev_rx_descriptor_status;
3061         dev->tx_descriptor_status = fm10k_dev_tx_descriptor_status;
3062         dev->rx_pkt_burst = &fm10k_recv_pkts;
3063         dev->tx_pkt_burst = &fm10k_xmit_pkts;
3064         dev->tx_pkt_prepare = &fm10k_prep_pkts;
3065
3066         /*
3067          * Primary process does the whole initialization, for secondary
3068          * processes, we just select the same Rx and Tx function as primary.
3069          */
3070         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3071                 fm10k_set_rx_function(dev);
3072                 fm10k_set_tx_function(dev);
3073                 return 0;
3074         }
3075
3076         rte_eth_copy_pci_info(dev, pdev);
3077
3078         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
3079         memset(macvlan, 0, sizeof(*macvlan));
3080         /* Vendor and Device ID need to be set before init of shared code */
3081         memset(hw, 0, sizeof(*hw));
3082         hw->device_id = pdev->id.device_id;
3083         hw->vendor_id = pdev->id.vendor_id;
3084         hw->subsystem_device_id = pdev->id.subsystem_device_id;
3085         hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
3086         hw->revision_id = 0;
3087         hw->hw_addr = (void *)pdev->mem_resource[0].addr;
3088         if (hw->hw_addr == NULL) {
3089                 PMD_INIT_LOG(ERR, "Bad mem resource."
3090                         " Try to refuse unused devices.");
3091                 return -EIO;
3092         }
3093
3094         /* Store fm10k_adapter pointer */
3095         hw->back = dev->data->dev_private;
3096
3097         /* Initialize the shared code */
3098         diag = fm10k_init_shared_code(hw);
3099         if (diag != FM10K_SUCCESS) {
3100                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
3101                 return -EIO;
3102         }
3103
3104         /* Initialize parameters */
3105         fm10k_params_init(dev);
3106
3107         /* Initialize the hw */
3108         diag = fm10k_init_hw(hw);
3109         if (diag != FM10K_SUCCESS) {
3110                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
3111                 return -EIO;
3112         }
3113
3114         /* Initialize MAC address(es) */
3115         dev->data->mac_addrs = rte_zmalloc("fm10k",
3116                         RTE_ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
3117         if (dev->data->mac_addrs == NULL) {
3118                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
3119                 return -ENOMEM;
3120         }
3121
3122         diag = fm10k_read_mac_addr(hw);
3123
3124         rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
3125                         &dev->data->mac_addrs[0]);
3126
3127         if (diag != FM10K_SUCCESS ||
3128                 !rte_is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
3129
3130                 /* Generate a random addr */
3131                 rte_eth_random_addr(hw->mac.addr);
3132                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
3133                 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
3134                 &dev->data->mac_addrs[0]);
3135         }
3136
3137         /* Reset the hw statistics */
3138         diag = fm10k_stats_reset(dev);
3139         if (diag != 0) {
3140                 PMD_INIT_LOG(ERR, "Stats reset failed: %d", diag);
3141                 return diag;
3142         }
3143
3144         /* Reset the hw */
3145         diag = fm10k_reset_hw(hw);
3146         if (diag != FM10K_SUCCESS) {
3147                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
3148                 return -EIO;
3149         }
3150
3151         /* Setup mailbox service */
3152         diag = fm10k_setup_mbx_service(hw);
3153         if (diag != FM10K_SUCCESS) {
3154                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
3155                 return -EIO;
3156         }
3157
3158         /*PF/VF has different interrupt handling mechanism */
3159         if (hw->mac.type == fm10k_mac_pf) {
3160                 /* register callback func to eal lib */
3161                 rte_intr_callback_register(intr_handle,
3162                         fm10k_dev_interrupt_handler_pf, (void *)dev);
3163
3164                 /* enable MISC interrupt */
3165                 fm10k_dev_enable_intr_pf(dev);
3166         } else { /* VF */
3167                 rte_intr_callback_register(intr_handle,
3168                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3169
3170                 fm10k_dev_enable_intr_vf(dev);
3171         }
3172
3173         /* Enable intr after callback registered */
3174         rte_intr_enable(intr_handle);
3175
3176         hw->mac.ops.update_int_moderator(hw);
3177
3178         /* Make sure Switch Manager is ready before going forward. */
3179         if (hw->mac.type == fm10k_mac_pf) {
3180                 bool switch_ready = false;
3181
3182                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3183                         fm10k_mbx_lock(hw);
3184                         hw->mac.ops.get_host_state(hw, &switch_ready);
3185                         fm10k_mbx_unlock(hw);
3186                         if (switch_ready == true)
3187                                 break;
3188                         /* Delay some time to acquire async LPORT_MAP info. */
3189                         rte_delay_us(WAIT_SWITCH_MSG_US);
3190                 }
3191
3192                 if (switch_ready == false) {
3193                         PMD_INIT_LOG(ERR, "switch is not ready");
3194                         return -1;
3195                 }
3196         }
3197
3198         /*
3199          * Below function will trigger operations on mailbox, acquire lock to
3200          * avoid race condition from interrupt handler. Operations on mailbox
3201          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
3202          * will handle and generate an interrupt to our side. Then,  FIFO in
3203          * mailbox will be touched.
3204          */
3205         fm10k_mbx_lock(hw);
3206         /* Enable port first */
3207         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
3208                                         MAX_LPORT_NUM, 1);
3209
3210         /* Set unicast mode by default. App can change to other mode in other
3211          * API func.
3212          */
3213         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
3214                                         FM10K_XCAST_MODE_NONE);
3215
3216         fm10k_mbx_unlock(hw);
3217
3218         /* Make sure default VID is ready before going forward. */
3219         if (hw->mac.type == fm10k_mac_pf) {
3220                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3221                         if (hw->mac.default_vid)
3222                                 break;
3223                         /* Delay some time to acquire async port VLAN info. */
3224                         rte_delay_us(WAIT_SWITCH_MSG_US);
3225                 }
3226
3227                 if (!hw->mac.default_vid) {
3228                         PMD_INIT_LOG(ERR, "default VID is not ready");
3229                         return -1;
3230                 }
3231         }
3232
3233         /* Add default mac address */
3234         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3235                 MAIN_VSI_POOL_NUMBER);
3236
3237         return 0;
3238 }
3239
3240 static int
3241 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3242 {
3243         PMD_INIT_FUNC_TRACE();
3244         fm10k_dev_close(dev);
3245         return 0;
3246 }
3247
3248 static int eth_fm10k_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3249         struct rte_pci_device *pci_dev)
3250 {
3251         return rte_eth_dev_pci_generic_probe(pci_dev,
3252                 sizeof(struct fm10k_adapter), eth_fm10k_dev_init);
3253 }
3254
3255 static int eth_fm10k_pci_remove(struct rte_pci_device *pci_dev)
3256 {
3257         return rte_eth_dev_pci_generic_remove(pci_dev, eth_fm10k_dev_uninit);
3258 }
3259
3260 /*
3261  * The set of PCI devices this driver supports. This driver will enable both PF
3262  * and SRIOV-VF devices.
3263  */
3264 static const struct rte_pci_id pci_id_fm10k_map[] = {
3265         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3266         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3267         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3268         { .vendor_id = 0, /* sentinel */ },
3269 };
3270
3271 static struct rte_pci_driver rte_pmd_fm10k = {
3272         .id_table = pci_id_fm10k_map,
3273         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3274         .probe = eth_fm10k_pci_probe,
3275         .remove = eth_fm10k_pci_remove,
3276 };
3277
3278 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k);
3279 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3280 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio-pci");
3281 RTE_LOG_REGISTER(fm10k_logtype_init, pmd.net.fm10k.init, NOTICE);
3282 RTE_LOG_REGISTER(fm10k_logtype_driver, pmd.net.fm10k.driver, NOTICE);
3283 #ifdef RTE_LIBRTE_FM10K_DEBUG_RX
3284 RTE_LOG_REGISTER(fm10k_logtype_rx, pmd.net.fm10k.rx, DEBUG);
3285 #endif
3286 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX
3287 RTE_LOG_REGISTER(fm10k_logtype_tx, pmd.net.fm10k.tx, DEBUG);
3288 #endif
3289 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX_FREE
3290 RTE_LOG_REGISTER(fm10k_logtype_tx_free, pmd.net.fm10k.tx_free, DEBUG);
3291 #endif