1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2013-2016 Intel Corporation
5 #include <rte_ethdev_driver.h>
6 #include <rte_ethdev_pci.h>
7 #include <rte_malloc.h>
8 #include <rte_memzone.h>
9 #include <rte_string_fns.h>
11 #include <rte_spinlock.h>
12 #include <rte_kvargs.h>
15 #include "base/fm10k_api.h"
17 /* Default delay to acquire mailbox lock */
18 #define FM10K_MBXLOCK_DELAY_US 20
19 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
21 #define MAIN_VSI_POOL_NUMBER 0
23 /* Max try times to acquire switch status */
24 #define MAX_QUERY_SWITCH_STATE_TIMES 10
25 /* Wait interval to get switch status */
26 #define WAIT_SWITCH_MSG_US 100000
27 /* A period of quiescence for switch */
28 #define FM10K_SWITCH_QUIESCE_US 100000
29 /* Number of chars per uint32 type */
30 #define CHARS_PER_UINT32 (sizeof(uint32_t))
31 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
33 /* default 1:1 map from queue ID to interrupt vector ID */
34 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
36 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
37 #define MAX_LPORT_NUM 128
38 #define GLORT_FD_Q_BASE 0x40
39 #define GLORT_PF_MASK 0xFFC0
40 #define GLORT_FD_MASK GLORT_PF_MASK
41 #define GLORT_FD_INDEX GLORT_FD_Q_BASE
43 int fm10k_logtype_init;
44 int fm10k_logtype_driver;
46 #ifdef RTE_LIBRTE_FM10K_DEBUG_RX
49 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX
52 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX_FREE
53 int fm10k_logtype_tx_free;
56 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
57 static int fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
58 static int fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
59 static int fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
60 static int fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
61 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
63 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
64 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
65 const u8 *mac, bool add, uint32_t pool);
66 static void fm10k_tx_queue_release(void *queue);
67 static void fm10k_rx_queue_release(void *queue);
68 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
69 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
70 static int fm10k_check_ftag(struct rte_devargs *devargs);
71 static int fm10k_link_update(struct rte_eth_dev *dev, int wait_to_complete);
73 static int fm10k_dev_infos_get(struct rte_eth_dev *dev,
74 struct rte_eth_dev_info *dev_info);
75 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev);
76 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev);
77 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev);
78 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev);
80 struct fm10k_xstats_name_off {
81 char name[RTE_ETH_XSTATS_NAME_SIZE];
85 static const struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
86 {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
87 {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
88 {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
89 {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
90 {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
91 {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
92 {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
93 {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
97 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
98 sizeof(fm10k_hw_stats_strings[0]))
100 static const struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
101 {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
102 {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
103 {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
106 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
107 sizeof(fm10k_hw_stats_rx_q_strings[0]))
109 static const struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
110 {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
111 {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
114 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
115 sizeof(fm10k_hw_stats_tx_q_strings[0]))
117 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
118 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
120 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
123 fm10k_mbx_initlock(struct fm10k_hw *hw)
125 rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
129 fm10k_mbx_lock(struct fm10k_hw *hw)
131 while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
132 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
136 fm10k_mbx_unlock(struct fm10k_hw *hw)
138 rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
141 /* Stubs needed for linkage when vPMD is disabled */
143 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
150 __rte_unused void *rx_queue,
151 __rte_unused struct rte_mbuf **rx_pkts,
152 __rte_unused uint16_t nb_pkts)
158 fm10k_recv_scattered_pkts_vec(
159 __rte_unused void *rx_queue,
160 __rte_unused struct rte_mbuf **rx_pkts,
161 __rte_unused uint16_t nb_pkts)
167 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
174 fm10k_rx_queue_release_mbufs_vec(
175 __rte_unused struct fm10k_rx_queue *rxq)
181 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
187 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
193 fm10k_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
194 __rte_unused struct rte_mbuf **tx_pkts,
195 __rte_unused uint16_t nb_pkts)
201 * reset queue to initial state, allocate software buffers used when starting
203 * return 0 on success
204 * return -ENOMEM if buffers cannot be allocated
205 * return -EINVAL if buffers do not satisfy alignment condition
208 rx_queue_reset(struct fm10k_rx_queue *q)
210 static const union fm10k_rx_desc zero = {{0} };
213 PMD_INIT_FUNC_TRACE();
215 diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
219 for (i = 0; i < q->nb_desc; ++i) {
220 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
221 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
222 rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
226 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
227 q->hw_ring[i].q.pkt_addr = dma_addr;
228 q->hw_ring[i].q.hdr_addr = dma_addr;
231 /* initialize extra software ring entries. Space for these extra
232 * entries is always allocated.
234 memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
235 for (i = 0; i < q->nb_fake_desc; ++i) {
236 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
237 q->hw_ring[q->nb_desc + i] = zero;
242 q->next_trigger = q->alloc_thresh - 1;
243 FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
244 q->rxrearm_start = 0;
251 * clean queue, descriptor rings, free software buffers used when stopping
255 rx_queue_clean(struct fm10k_rx_queue *q)
257 union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
259 PMD_INIT_FUNC_TRACE();
261 /* zero descriptor rings */
262 for (i = 0; i < q->nb_desc; ++i)
263 q->hw_ring[i] = zero;
265 /* zero faked descriptors */
266 for (i = 0; i < q->nb_fake_desc; ++i)
267 q->hw_ring[q->nb_desc + i] = zero;
269 /* vPMD driver has a different way of releasing mbufs. */
270 if (q->rx_using_sse) {
271 fm10k_rx_queue_release_mbufs_vec(q);
275 /* free software buffers */
276 for (i = 0; i < q->nb_desc; ++i) {
278 rte_pktmbuf_free_seg(q->sw_ring[i]);
279 q->sw_ring[i] = NULL;
285 * free all queue memory used when releasing the queue (i.e. configure)
288 rx_queue_free(struct fm10k_rx_queue *q)
290 PMD_INIT_FUNC_TRACE();
292 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
295 rte_free(q->sw_ring);
304 * disable RX queue, wait unitl HW finished necessary flush operation
307 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
311 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
312 FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
313 reg & ~FM10K_RXQCTL_ENABLE);
315 /* Wait 100us at most */
316 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
318 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
319 if (!(reg & FM10K_RXQCTL_ENABLE))
323 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
330 * reset queue to initial state, allocate software buffers used when starting
334 tx_queue_reset(struct fm10k_tx_queue *q)
336 PMD_INIT_FUNC_TRACE();
340 q->nb_free = q->nb_desc - 1;
341 fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
342 FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
346 * clean queue, descriptor rings, free software buffers used when stopping
350 tx_queue_clean(struct fm10k_tx_queue *q)
352 struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
354 PMD_INIT_FUNC_TRACE();
356 /* zero descriptor rings */
357 for (i = 0; i < q->nb_desc; ++i)
358 q->hw_ring[i] = zero;
360 /* free software buffers */
361 for (i = 0; i < q->nb_desc; ++i) {
363 rte_pktmbuf_free_seg(q->sw_ring[i]);
364 q->sw_ring[i] = NULL;
370 * free all queue memory used when releasing the queue (i.e. configure)
373 tx_queue_free(struct fm10k_tx_queue *q)
375 PMD_INIT_FUNC_TRACE();
377 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
379 if (q->rs_tracker.list) {
380 rte_free(q->rs_tracker.list);
381 q->rs_tracker.list = NULL;
384 rte_free(q->sw_ring);
393 * disable TX queue, wait unitl HW finished necessary flush operation
396 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
400 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
401 FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
402 reg & ~FM10K_TXDCTL_ENABLE);
404 /* Wait 100us at most */
405 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
407 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
408 if (!(reg & FM10K_TXDCTL_ENABLE))
412 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
419 fm10k_check_mq_mode(struct rte_eth_dev *dev)
421 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
422 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
423 struct rte_eth_vmdq_rx_conf *vmdq_conf;
424 uint16_t nb_rx_q = dev->data->nb_rx_queues;
426 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
428 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
429 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
433 if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
436 if (hw->mac.type == fm10k_mac_vf) {
437 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
441 /* Check VMDQ queue pool number */
442 if (vmdq_conf->nb_queue_pools >
443 sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
444 vmdq_conf->nb_queue_pools > nb_rx_q) {
445 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
446 vmdq_conf->nb_queue_pools);
453 static const struct fm10k_txq_ops def_txq_ops = {
454 .reset = tx_queue_reset,
458 fm10k_dev_configure(struct rte_eth_dev *dev)
462 PMD_INIT_FUNC_TRACE();
464 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
465 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
467 /* multipe queue mode checking */
468 ret = fm10k_check_mq_mode(dev);
470 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
475 dev->data->scattered_rx = 0;
481 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
483 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
484 struct rte_eth_vmdq_rx_conf *vmdq_conf;
487 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
489 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
490 if (!vmdq_conf->pool_map[i].pools)
493 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
494 fm10k_mbx_unlock(hw);
499 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
501 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
503 /* Add default mac address */
504 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
505 MAIN_VSI_POOL_NUMBER);
509 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
511 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
512 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
513 uint32_t mrqc, *key, i, reta, j;
516 #define RSS_KEY_SIZE 40
517 static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
518 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
519 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
520 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
521 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
522 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
525 if (dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
526 dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
527 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
531 /* random key is rss_intel_key (default) or user provided (rss_key) */
532 if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
533 key = (uint32_t *)rss_intel_key;
535 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
537 /* Now fill our hash function seeds, 4 bytes at a time */
538 for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
539 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
542 * Fill in redirection table
543 * The byte-swap is needed because NIC registers are in
544 * little-endian order.
547 for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
548 if (j == dev->data->nb_rx_queues)
550 reta = (reta << CHAR_BIT) | j;
552 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
557 * Generate RSS hash based on packet types, TCP/UDP
558 * port numbers and/or IPv4/v6 src and dst addresses
560 hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
562 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
563 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
564 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
565 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
566 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
567 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
568 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
569 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
570 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
573 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
578 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
582 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
584 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
587 for (i = 0; i < nb_lport_new; i++) {
588 /* Set unicast mode by default. App can change
589 * to other mode in other API func.
592 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
593 FM10K_XCAST_MODE_NONE);
594 fm10k_mbx_unlock(hw);
599 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
601 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
602 struct rte_eth_vmdq_rx_conf *vmdq_conf;
603 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
604 struct fm10k_macvlan_filter_info *macvlan;
605 uint16_t nb_queue_pools = 0; /* pool number in configuration */
606 uint16_t nb_lport_new;
608 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
609 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
611 fm10k_dev_rss_configure(dev);
613 /* only PF supports VMDQ */
614 if (hw->mac.type != fm10k_mac_pf)
617 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
618 nb_queue_pools = vmdq_conf->nb_queue_pools;
620 /* no pool number change, no need to update logic port and VLAN/MAC */
621 if (macvlan->nb_queue_pools == nb_queue_pools)
624 nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
625 fm10k_dev_logic_port_update(dev, nb_lport_new);
627 /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
628 memset(dev->data->mac_addrs, 0,
629 RTE_ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
630 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
631 &dev->data->mac_addrs[0]);
632 memset(macvlan, 0, sizeof(*macvlan));
633 macvlan->nb_queue_pools = nb_queue_pools;
636 fm10k_dev_vmdq_rx_configure(dev);
638 fm10k_dev_pf_main_vsi_reset(dev);
642 fm10k_dev_tx_init(struct rte_eth_dev *dev)
644 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
646 struct fm10k_tx_queue *txq;
650 /* Disable TXINT to avoid possible interrupt */
651 for (i = 0; i < hw->mac.max_queues; i++)
652 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
653 3 << FM10K_TXINT_TIMER_SHIFT);
656 for (i = 0; i < dev->data->nb_tx_queues; ++i) {
657 txq = dev->data->tx_queues[i];
658 base_addr = txq->hw_ring_phys_addr;
659 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
661 /* disable queue to avoid issues while updating state */
662 ret = tx_queue_disable(hw, i);
664 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
667 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
668 * register is read-only for VF.
670 if (fm10k_check_ftag(dev->device->devargs)) {
671 if (hw->mac.type == fm10k_mac_pf) {
672 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
673 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
674 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
676 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
681 /* set location and size for descriptor ring */
682 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
683 base_addr & UINT64_LOWER_32BITS_MASK);
684 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
685 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
686 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
688 /* assign default SGLORT for each TX queue by PF */
689 if (hw->mac.type == fm10k_mac_pf)
690 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
693 /* set up vector or scalar TX function as appropriate */
694 fm10k_set_tx_function(dev);
700 fm10k_dev_rx_init(struct rte_eth_dev *dev)
702 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
703 struct fm10k_macvlan_filter_info *macvlan;
704 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
705 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
707 struct fm10k_rx_queue *rxq;
710 uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
711 uint32_t logic_port = hw->mac.dglort_map;
713 uint16_t queue_stride = 0;
715 /* enable RXINT for interrupt mode */
717 if (rte_intr_dp_is_en(intr_handle)) {
718 for (; i < dev->data->nb_rx_queues; i++) {
719 FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
720 if (hw->mac.type == fm10k_mac_pf)
721 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
723 FM10K_ITR_MASK_CLEAR);
725 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
727 FM10K_ITR_MASK_CLEAR);
730 /* Disable other RXINT to avoid possible interrupt */
731 for (; i < hw->mac.max_queues; i++)
732 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
733 3 << FM10K_RXINT_TIMER_SHIFT);
735 /* Setup RX queues */
736 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
737 rxq = dev->data->rx_queues[i];
738 base_addr = rxq->hw_ring_phys_addr;
739 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
741 /* disable queue to avoid issues while updating state */
742 ret = rx_queue_disable(hw, i);
744 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
748 /* Setup the Base and Length of the Rx Descriptor Ring */
749 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
750 base_addr & UINT64_LOWER_32BITS_MASK);
751 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
752 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
753 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
755 /* Configure the Rx buffer size for one buff without split */
756 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
757 RTE_PKTMBUF_HEADROOM);
758 /* As RX buffer is aligned to 512B within mbuf, some bytes are
759 * reserved for this purpose, and the worst case could be 511B.
760 * But SRR reg assumes all buffers have the same size. In order
761 * to fill the gap, we'll have to consider the worst case and
762 * assume 512B is reserved. If we don't do so, it's possible
763 * for HW to overwrite data to next mbuf.
765 buf_size -= FM10K_RX_DATABUF_ALIGN;
767 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
768 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
769 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
771 /* It adds dual VLAN length for supporting dual VLAN */
772 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
773 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
774 rxq->offloads & DEV_RX_OFFLOAD_SCATTER) {
776 dev->data->scattered_rx = 1;
777 reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
778 reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
779 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
782 /* Enable drop on empty, it's RO for VF */
783 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
784 rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
786 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
787 FM10K_WRITE_FLUSH(hw);
790 /* Configure VMDQ/RSS if applicable */
791 fm10k_dev_mq_rx_configure(dev);
793 /* Decide the best RX function */
794 fm10k_set_rx_function(dev);
796 /* update RX_SGLORT for loopback suppress*/
797 if (hw->mac.type != fm10k_mac_pf)
799 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
800 if (macvlan->nb_queue_pools)
801 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
802 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
803 if (i && queue_stride && !(i % queue_stride))
805 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
812 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
814 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
817 struct fm10k_rx_queue *rxq;
819 PMD_INIT_FUNC_TRACE();
821 rxq = dev->data->rx_queues[rx_queue_id];
822 err = rx_queue_reset(rxq);
823 if (err == -ENOMEM) {
824 PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
826 } else if (err == -EINVAL) {
827 PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
832 /* Setup the HW Rx Head and Tail Descriptor Pointers
833 * Note: this must be done AFTER the queue is enabled on real
834 * hardware, but BEFORE the queue is enabled when using the
835 * emulation platform. Do it in both places for now and remove
836 * this comment and the following two register writes when the
837 * emulation platform is no longer being used.
839 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
840 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
842 /* Set PF ownership flag for PF devices */
843 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
844 if (hw->mac.type == fm10k_mac_pf)
845 reg |= FM10K_RXQCTL_PF;
846 reg |= FM10K_RXQCTL_ENABLE;
847 /* enable RX queue */
848 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
849 FM10K_WRITE_FLUSH(hw);
851 /* Setup the HW Rx Head and Tail Descriptor Pointers
852 * Note: this must be done AFTER the queue is enabled
854 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
855 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
856 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
862 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
864 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
866 PMD_INIT_FUNC_TRACE();
868 /* Disable RX queue */
869 rx_queue_disable(hw, rx_queue_id);
871 /* Free mbuf and clean HW ring */
872 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
873 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
879 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
881 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
882 /** @todo - this should be defined in the shared code */
883 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY 0x00010000
884 uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
885 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
887 PMD_INIT_FUNC_TRACE();
891 /* reset head and tail pointers */
892 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
893 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
895 /* enable TX queue */
896 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
897 FM10K_TXDCTL_ENABLE | txdctl);
898 FM10K_WRITE_FLUSH(hw);
899 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
905 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
907 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
909 PMD_INIT_FUNC_TRACE();
911 tx_queue_disable(hw, tx_queue_id);
912 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
913 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
918 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
920 return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
921 != FM10K_DGLORTMAP_NONE);
925 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
927 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
930 PMD_INIT_FUNC_TRACE();
932 /* Return if it didn't acquire valid glort range */
933 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
937 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
938 FM10K_XCAST_MODE_PROMISC);
939 fm10k_mbx_unlock(hw);
941 if (status != FM10K_SUCCESS) {
942 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
950 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
952 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
956 PMD_INIT_FUNC_TRACE();
958 /* Return if it didn't acquire valid glort range */
959 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
962 if (dev->data->all_multicast == 1)
963 mode = FM10K_XCAST_MODE_ALLMULTI;
965 mode = FM10K_XCAST_MODE_NONE;
968 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
970 fm10k_mbx_unlock(hw);
972 if (status != FM10K_SUCCESS) {
973 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
981 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
983 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
986 PMD_INIT_FUNC_TRACE();
988 /* Return if it didn't acquire valid glort range */
989 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
992 /* If promiscuous mode is enabled, it doesn't make sense to enable
993 * allmulticast and disable promiscuous since fm10k only can select
996 if (dev->data->promiscuous) {
997 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
998 "needn't enable allmulticast");
1003 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1004 FM10K_XCAST_MODE_ALLMULTI);
1005 fm10k_mbx_unlock(hw);
1007 if (status != FM10K_SUCCESS) {
1008 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1016 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1018 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1021 PMD_INIT_FUNC_TRACE();
1023 /* Return if it didn't acquire valid glort range */
1024 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1027 if (dev->data->promiscuous) {
1028 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1029 "since promisc mode is enabled");
1034 /* Change mode to unicast mode */
1035 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1036 FM10K_XCAST_MODE_NONE);
1037 fm10k_mbx_unlock(hw);
1039 if (status != FM10K_SUCCESS) {
1040 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1048 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1050 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051 uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1052 uint16_t nb_queue_pools;
1053 struct fm10k_macvlan_filter_info *macvlan;
1055 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1056 nb_queue_pools = macvlan->nb_queue_pools;
1057 pool_len = nb_queue_pools ? rte_fls_u32(nb_queue_pools - 1) : 0;
1058 rss_len = rte_fls_u32(dev->data->nb_rx_queues - 1) - pool_len;
1060 /* GLORT 0x0-0x3F are used by PF and VMDQ, 0x40-0x7F used by FD */
1061 dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1062 dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1064 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1065 /* Configure VMDQ/RSS DGlort Decoder */
1066 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1068 /* Flow Director configurations, only queue number is valid. */
1069 dglortdec = rte_fls_u32(dev->data->nb_rx_queues - 1);
1070 dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1071 (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1072 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1073 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1075 /* Invalidate all other GLORT entries */
1076 for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1077 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1078 FM10K_DGLORTMAP_NONE);
1081 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1083 fm10k_dev_start(struct rte_eth_dev *dev)
1085 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1088 PMD_INIT_FUNC_TRACE();
1090 /* stop, init, then start the hw */
1091 diag = fm10k_stop_hw(hw);
1092 if (diag != FM10K_SUCCESS) {
1093 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1097 diag = fm10k_init_hw(hw);
1098 if (diag != FM10K_SUCCESS) {
1099 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1103 diag = fm10k_start_hw(hw);
1104 if (diag != FM10K_SUCCESS) {
1105 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1109 diag = fm10k_dev_tx_init(dev);
1111 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1115 if (fm10k_dev_rxq_interrupt_setup(dev))
1118 diag = fm10k_dev_rx_init(dev);
1120 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1124 if (hw->mac.type == fm10k_mac_pf)
1125 fm10k_dev_dglort_map_configure(dev);
1127 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1128 struct fm10k_rx_queue *rxq;
1129 rxq = dev->data->rx_queues[i];
1131 if (rxq->rx_deferred_start)
1133 diag = fm10k_dev_rx_queue_start(dev, i);
1136 for (j = 0; j < i; ++j)
1137 rx_queue_clean(dev->data->rx_queues[j]);
1142 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1143 struct fm10k_tx_queue *txq;
1144 txq = dev->data->tx_queues[i];
1146 if (txq->tx_deferred_start)
1148 diag = fm10k_dev_tx_queue_start(dev, i);
1151 for (j = 0; j < i; ++j)
1152 tx_queue_clean(dev->data->tx_queues[j]);
1153 for (j = 0; j < dev->data->nb_rx_queues; ++j)
1154 rx_queue_clean(dev->data->rx_queues[j]);
1159 /* Update default vlan when not in VMDQ mode */
1160 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1161 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1163 fm10k_link_update(dev, 0);
1169 fm10k_dev_stop(struct rte_eth_dev *dev)
1171 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1172 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1173 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1176 PMD_INIT_FUNC_TRACE();
1178 if (dev->data->tx_queues)
1179 for (i = 0; i < dev->data->nb_tx_queues; i++)
1180 fm10k_dev_tx_queue_stop(dev, i);
1182 if (dev->data->rx_queues)
1183 for (i = 0; i < dev->data->nb_rx_queues; i++)
1184 fm10k_dev_rx_queue_stop(dev, i);
1186 /* Disable datapath event */
1187 if (rte_intr_dp_is_en(intr_handle)) {
1188 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1189 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1190 3 << FM10K_RXINT_TIMER_SHIFT);
1191 if (hw->mac.type == fm10k_mac_pf)
1192 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1193 FM10K_ITR_MASK_SET);
1195 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1196 FM10K_ITR_MASK_SET);
1199 /* Clean datapath event and queue/vec mapping */
1200 rte_intr_efd_disable(intr_handle);
1201 rte_free(intr_handle->intr_vec);
1202 intr_handle->intr_vec = NULL;
1206 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1210 PMD_INIT_FUNC_TRACE();
1212 if (dev->data->tx_queues) {
1213 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1214 struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1220 if (dev->data->rx_queues) {
1221 for (i = 0; i < dev->data->nb_rx_queues; i++)
1222 fm10k_rx_queue_release(dev->data->rx_queues[i]);
1227 fm10k_link_update(struct rte_eth_dev *dev,
1228 __rte_unused int wait_to_complete)
1230 struct fm10k_dev_info *dev_info =
1231 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1232 PMD_INIT_FUNC_TRACE();
1234 dev->data->dev_link.link_speed = ETH_SPEED_NUM_50G;
1235 dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1236 dev->data->dev_link.link_status =
1237 dev_info->sm_down ? ETH_LINK_DOWN : ETH_LINK_UP;
1238 dev->data->dev_link.link_autoneg = ETH_LINK_FIXED;
1243 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1244 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1249 if (xstats_names != NULL) {
1250 /* Note: limit checked in rte_eth_xstats_names() */
1253 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1254 snprintf(xstats_names[count].name,
1255 sizeof(xstats_names[count].name),
1256 "%s", fm10k_hw_stats_strings[count].name);
1260 /* PF queue stats */
1261 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1262 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1263 snprintf(xstats_names[count].name,
1264 sizeof(xstats_names[count].name),
1266 fm10k_hw_stats_rx_q_strings[i].name);
1269 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1270 snprintf(xstats_names[count].name,
1271 sizeof(xstats_names[count].name),
1273 fm10k_hw_stats_tx_q_strings[i].name);
1278 return FM10K_NB_XSTATS;
1282 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1285 struct fm10k_hw_stats *hw_stats =
1286 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1287 unsigned i, q, count = 0;
1289 if (n < FM10K_NB_XSTATS)
1290 return FM10K_NB_XSTATS;
1293 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1294 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1295 fm10k_hw_stats_strings[count].offset);
1296 xstats[count].id = count;
1300 /* PF queue stats */
1301 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1302 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1303 xstats[count].value =
1304 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1305 fm10k_hw_stats_rx_q_strings[i].offset);
1306 xstats[count].id = count;
1309 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1310 xstats[count].value =
1311 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1312 fm10k_hw_stats_tx_q_strings[i].offset);
1313 xstats[count].id = count;
1318 return FM10K_NB_XSTATS;
1322 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1324 uint64_t ipackets, opackets, ibytes, obytes, imissed;
1325 struct fm10k_hw *hw =
1326 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327 struct fm10k_hw_stats *hw_stats =
1328 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1331 PMD_INIT_FUNC_TRACE();
1333 fm10k_update_hw_stats(hw, hw_stats);
1335 ipackets = opackets = ibytes = obytes = imissed = 0;
1336 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1337 (i < hw->mac.max_queues); ++i) {
1338 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1339 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1340 stats->q_ibytes[i] = hw_stats->q[i].rx_bytes.count;
1341 stats->q_obytes[i] = hw_stats->q[i].tx_bytes.count;
1342 stats->q_errors[i] = hw_stats->q[i].rx_drops.count;
1343 ipackets += stats->q_ipackets[i];
1344 opackets += stats->q_opackets[i];
1345 ibytes += stats->q_ibytes[i];
1346 obytes += stats->q_obytes[i];
1347 imissed += stats->q_errors[i];
1349 stats->ipackets = ipackets;
1350 stats->opackets = opackets;
1351 stats->ibytes = ibytes;
1352 stats->obytes = obytes;
1353 stats->imissed = imissed;
1358 fm10k_stats_reset(struct rte_eth_dev *dev)
1360 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361 struct fm10k_hw_stats *hw_stats =
1362 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1364 PMD_INIT_FUNC_TRACE();
1366 memset(hw_stats, 0, sizeof(*hw_stats));
1367 fm10k_rebind_hw_stats(hw, hw_stats);
1373 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1374 struct rte_eth_dev_info *dev_info)
1376 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1377 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1379 PMD_INIT_FUNC_TRACE();
1381 dev_info->min_rx_bufsize = FM10K_MIN_RX_BUF_SIZE;
1382 dev_info->max_rx_pktlen = FM10K_MAX_PKT_SIZE;
1383 dev_info->max_rx_queues = hw->mac.max_queues;
1384 dev_info->max_tx_queues = hw->mac.max_queues;
1385 dev_info->max_mac_addrs = FM10K_MAX_MACADDR_NUM;
1386 dev_info->max_hash_mac_addrs = 0;
1387 dev_info->max_vfs = pdev->max_vfs;
1388 dev_info->vmdq_pool_base = 0;
1389 dev_info->vmdq_queue_base = 0;
1390 dev_info->max_vmdq_pools = ETH_32_POOLS;
1391 dev_info->vmdq_queue_num = FM10K_MAX_QUEUES_PF;
1392 dev_info->rx_queue_offload_capa = fm10k_get_rx_queue_offloads_capa(dev);
1393 dev_info->rx_offload_capa = fm10k_get_rx_port_offloads_capa(dev) |
1394 dev_info->rx_queue_offload_capa;
1395 dev_info->tx_queue_offload_capa = fm10k_get_tx_queue_offloads_capa(dev);
1396 dev_info->tx_offload_capa = fm10k_get_tx_port_offloads_capa(dev) |
1397 dev_info->tx_queue_offload_capa;
1399 dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1400 dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1401 dev_info->flow_type_rss_offloads = ETH_RSS_IPV4 |
1404 ETH_RSS_NONFRAG_IPV4_TCP |
1405 ETH_RSS_NONFRAG_IPV6_TCP |
1406 ETH_RSS_IPV6_TCP_EX |
1407 ETH_RSS_NONFRAG_IPV4_UDP |
1408 ETH_RSS_NONFRAG_IPV6_UDP |
1409 ETH_RSS_IPV6_UDP_EX;
1411 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1413 .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1414 .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1415 .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1417 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1422 dev_info->default_txconf = (struct rte_eth_txconf) {
1424 .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1425 .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1426 .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1428 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1429 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1433 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1434 .nb_max = FM10K_MAX_RX_DESC,
1435 .nb_min = FM10K_MIN_RX_DESC,
1436 .nb_align = FM10K_MULT_RX_DESC,
1439 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1440 .nb_max = FM10K_MAX_TX_DESC,
1441 .nb_min = FM10K_MIN_TX_DESC,
1442 .nb_align = FM10K_MULT_TX_DESC,
1443 .nb_seg_max = FM10K_TX_MAX_SEG,
1444 .nb_mtu_seg_max = FM10K_TX_MAX_MTU_SEG,
1447 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1448 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1449 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1454 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1455 static const uint32_t *
1456 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1458 if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1459 dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1460 static uint32_t ptypes[] = {
1461 /* refers to rx_desc_to_ol_flags() */
1464 RTE_PTYPE_L3_IPV4_EXT,
1466 RTE_PTYPE_L3_IPV6_EXT,
1473 } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1474 dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1475 static uint32_t ptypes_vec[] = {
1476 /* refers to fm10k_desc_to_pktype_v() */
1478 RTE_PTYPE_L3_IPV4_EXT,
1480 RTE_PTYPE_L3_IPV6_EXT,
1483 RTE_PTYPE_TUNNEL_GENEVE,
1484 RTE_PTYPE_TUNNEL_NVGRE,
1485 RTE_PTYPE_TUNNEL_VXLAN,
1486 RTE_PTYPE_TUNNEL_GRE,
1496 static const uint32_t *
1497 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1504 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1507 uint16_t mac_num = 0;
1508 uint32_t vid_idx, vid_bit, mac_index;
1509 struct fm10k_hw *hw;
1510 struct fm10k_macvlan_filter_info *macvlan;
1511 struct rte_eth_dev_data *data = dev->data;
1513 hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1514 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1516 if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1517 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1521 if (vlan_id > ETH_VLAN_ID_MAX) {
1522 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1526 vid_idx = FM10K_VFTA_IDX(vlan_id);
1527 vid_bit = FM10K_VFTA_BIT(vlan_id);
1528 /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1529 if (on && (macvlan->vfta[vid_idx] & vid_bit))
1531 /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1532 if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1533 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1534 "in the VLAN filter table");
1539 result = fm10k_update_vlan(hw, vlan_id, 0, on);
1540 fm10k_mbx_unlock(hw);
1541 if (result != FM10K_SUCCESS) {
1542 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1546 for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1547 (result == FM10K_SUCCESS); mac_index++) {
1548 if (rte_is_zero_ether_addr(&data->mac_addrs[mac_index]))
1550 if (mac_num > macvlan->mac_num - 1) {
1551 PMD_INIT_LOG(ERR, "MAC address number "
1556 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1557 data->mac_addrs[mac_index].addr_bytes,
1559 fm10k_mbx_unlock(hw);
1562 if (result != FM10K_SUCCESS) {
1563 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1568 macvlan->vlan_num++;
1569 macvlan->vfta[vid_idx] |= vid_bit;
1571 macvlan->vlan_num--;
1572 macvlan->vfta[vid_idx] &= ~vid_bit;
1578 fm10k_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1580 if (mask & ETH_VLAN_STRIP_MASK) {
1581 if (!(dev->data->dev_conf.rxmode.offloads &
1582 DEV_RX_OFFLOAD_VLAN_STRIP))
1583 PMD_INIT_LOG(ERR, "VLAN stripping is "
1584 "always on in fm10k");
1587 if (mask & ETH_VLAN_EXTEND_MASK) {
1588 if (dev->data->dev_conf.rxmode.offloads &
1589 DEV_RX_OFFLOAD_VLAN_EXTEND)
1590 PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1591 "supported in fm10k");
1594 if (mask & ETH_VLAN_FILTER_MASK) {
1595 if (!(dev->data->dev_conf.rxmode.offloads &
1596 DEV_RX_OFFLOAD_VLAN_FILTER))
1597 PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1603 /* Add/Remove a MAC address, and update filters to main VSI */
1604 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1605 const u8 *mac, bool add, uint32_t pool)
1607 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608 struct fm10k_macvlan_filter_info *macvlan;
1611 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1613 if (pool != MAIN_VSI_POOL_NUMBER) {
1614 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1615 "mac to pool %u", pool);
1618 for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1619 if (!macvlan->vfta[j])
1621 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1622 if (!(macvlan->vfta[j] & (1 << k)))
1624 if (i + 1 > macvlan->vlan_num) {
1625 PMD_INIT_LOG(ERR, "vlan number not match");
1629 fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1630 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1631 fm10k_mbx_unlock(hw);
1637 /* Add/Remove a MAC address, and update filters to VMDQ */
1638 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1639 const u8 *mac, bool add, uint32_t pool)
1641 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642 struct fm10k_macvlan_filter_info *macvlan;
1643 struct rte_eth_vmdq_rx_conf *vmdq_conf;
1646 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1647 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1649 if (pool > macvlan->nb_queue_pools) {
1650 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1652 pool, macvlan->nb_queue_pools);
1655 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1656 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1659 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1660 vmdq_conf->pool_map[i].vlan_id, add, 0);
1661 fm10k_mbx_unlock(hw);
1665 /* Add/Remove a MAC address, and update filters */
1666 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1667 const u8 *mac, bool add, uint32_t pool)
1669 struct fm10k_macvlan_filter_info *macvlan;
1671 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1673 if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1674 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1676 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1684 /* Add a MAC address, and update filters */
1686 fm10k_macaddr_add(struct rte_eth_dev *dev,
1687 struct rte_ether_addr *mac_addr,
1691 struct fm10k_macvlan_filter_info *macvlan;
1693 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1694 fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1695 macvlan->mac_vmdq_id[index] = pool;
1699 /* Remove a MAC address, and update filters */
1701 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1703 struct rte_eth_dev_data *data = dev->data;
1704 struct fm10k_macvlan_filter_info *macvlan;
1706 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1707 fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1708 FALSE, macvlan->mac_vmdq_id[index]);
1709 macvlan->mac_vmdq_id[index] = 0;
1713 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1715 if ((request < min) || (request > max) || ((request % mult) != 0))
1723 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1725 if ((request < min) || (request > max) || ((div % request) != 0))
1732 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1734 uint16_t rx_free_thresh;
1736 if (conf->rx_free_thresh == 0)
1737 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1739 rx_free_thresh = conf->rx_free_thresh;
1741 /* make sure the requested threshold satisfies the constraints */
1742 if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1743 FM10K_RX_FREE_THRESH_MAX(q),
1744 FM10K_RX_FREE_THRESH_DIV(q),
1746 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1747 "less than or equal to %u, "
1748 "greater than or equal to %u, "
1749 "and a divisor of %u",
1750 rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1751 FM10K_RX_FREE_THRESH_MIN(q),
1752 FM10K_RX_FREE_THRESH_DIV(q));
1756 q->alloc_thresh = rx_free_thresh;
1757 q->drop_en = conf->rx_drop_en;
1758 q->rx_deferred_start = conf->rx_deferred_start;
1764 * Hardware requires specific alignment for Rx packet buffers. At
1765 * least one of the following two conditions must be satisfied.
1766 * 1. Address is 512B aligned
1767 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
1769 * As such, the driver may need to adjust the DMA address within the
1770 * buffer by up to 512B.
1772 * return 1 if the element size is valid, otherwise return 0.
1775 mempool_element_size_valid(struct rte_mempool *mp)
1779 /* elt_size includes mbuf header and headroom */
1780 min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1781 RTE_PKTMBUF_HEADROOM;
1783 /* account for up to 512B of alignment */
1784 min_size -= FM10K_RX_DATABUF_ALIGN;
1786 /* sanity check for overflow */
1787 if (min_size > mp->elt_size)
1794 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev)
1798 return (uint64_t)(DEV_RX_OFFLOAD_SCATTER);
1801 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)
1805 return (uint64_t)(DEV_RX_OFFLOAD_VLAN_STRIP |
1806 DEV_RX_OFFLOAD_VLAN_FILTER |
1807 DEV_RX_OFFLOAD_IPV4_CKSUM |
1808 DEV_RX_OFFLOAD_UDP_CKSUM |
1809 DEV_RX_OFFLOAD_TCP_CKSUM |
1810 DEV_RX_OFFLOAD_JUMBO_FRAME |
1811 DEV_RX_OFFLOAD_HEADER_SPLIT |
1812 DEV_RX_OFFLOAD_RSS_HASH);
1816 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1817 uint16_t nb_desc, unsigned int socket_id,
1818 const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1820 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821 struct fm10k_dev_info *dev_info =
1822 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1823 struct fm10k_rx_queue *q;
1824 const struct rte_memzone *mz;
1827 PMD_INIT_FUNC_TRACE();
1829 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1831 /* make sure the mempool element size can account for alignment. */
1832 if (!mempool_element_size_valid(mp)) {
1833 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1837 /* make sure a valid number of descriptors have been requested */
1838 if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1839 FM10K_MULT_RX_DESC, nb_desc)) {
1840 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1841 "less than or equal to %"PRIu32", "
1842 "greater than or equal to %u, "
1843 "and a multiple of %u",
1844 nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1845 FM10K_MULT_RX_DESC);
1850 * if this queue existed already, free the associated memory. The
1851 * queue cannot be reused in case we need to allocate memory on
1852 * different socket than was previously used.
1854 if (dev->data->rx_queues[queue_id] != NULL) {
1855 rx_queue_free(dev->data->rx_queues[queue_id]);
1856 dev->data->rx_queues[queue_id] = NULL;
1859 /* allocate memory for the queue structure */
1860 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1863 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1869 q->nb_desc = nb_desc;
1870 q->nb_fake_desc = FM10K_MULT_RX_DESC;
1871 q->port_id = dev->data->port_id;
1872 q->queue_id = queue_id;
1873 q->tail_ptr = (volatile uint32_t *)
1874 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1875 q->offloads = offloads;
1876 if (handle_rxconf(q, conf))
1879 /* allocate memory for the software ring */
1880 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1881 (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1882 RTE_CACHE_LINE_SIZE, socket_id);
1883 if (q->sw_ring == NULL) {
1884 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1890 * allocate memory for the hardware descriptor ring. A memzone large
1891 * enough to hold the maximum ring size is requested to allow for
1892 * resizing in later calls to the queue setup function.
1894 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1895 FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1898 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1899 rte_free(q->sw_ring);
1903 q->hw_ring = mz->addr;
1904 q->hw_ring_phys_addr = mz->iova;
1906 /* Check if number of descs satisfied Vector requirement */
1907 if (!rte_is_power_of_2(nb_desc)) {
1908 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1909 "preconditions - canceling the feature for "
1910 "the whole port[%d]",
1911 q->queue_id, q->port_id);
1912 dev_info->rx_vec_allowed = false;
1914 fm10k_rxq_vec_setup(q);
1916 dev->data->rx_queues[queue_id] = q;
1921 fm10k_rx_queue_release(void *queue)
1923 PMD_INIT_FUNC_TRACE();
1925 rx_queue_free(queue);
1929 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1931 uint16_t tx_free_thresh;
1932 uint16_t tx_rs_thresh;
1934 /* constraint MACROs require that tx_free_thresh is configured
1935 * before tx_rs_thresh */
1936 if (conf->tx_free_thresh == 0)
1937 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1939 tx_free_thresh = conf->tx_free_thresh;
1941 /* make sure the requested threshold satisfies the constraints */
1942 if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1943 FM10K_TX_FREE_THRESH_MAX(q),
1944 FM10K_TX_FREE_THRESH_DIV(q),
1946 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1947 "less than or equal to %u, "
1948 "greater than or equal to %u, "
1949 "and a divisor of %u",
1950 tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1951 FM10K_TX_FREE_THRESH_MIN(q),
1952 FM10K_TX_FREE_THRESH_DIV(q));
1956 q->free_thresh = tx_free_thresh;
1958 if (conf->tx_rs_thresh == 0)
1959 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1961 tx_rs_thresh = conf->tx_rs_thresh;
1963 q->tx_deferred_start = conf->tx_deferred_start;
1965 /* make sure the requested threshold satisfies the constraints */
1966 if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1967 FM10K_TX_RS_THRESH_MAX(q),
1968 FM10K_TX_RS_THRESH_DIV(q),
1970 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1971 "less than or equal to %u, "
1972 "greater than or equal to %u, "
1973 "and a divisor of %u",
1974 tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1975 FM10K_TX_RS_THRESH_MIN(q),
1976 FM10K_TX_RS_THRESH_DIV(q));
1980 q->rs_thresh = tx_rs_thresh;
1985 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1992 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1996 return (uint64_t)(DEV_TX_OFFLOAD_VLAN_INSERT |
1997 DEV_TX_OFFLOAD_MULTI_SEGS |
1998 DEV_TX_OFFLOAD_IPV4_CKSUM |
1999 DEV_TX_OFFLOAD_UDP_CKSUM |
2000 DEV_TX_OFFLOAD_TCP_CKSUM |
2001 DEV_TX_OFFLOAD_TCP_TSO);
2005 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
2006 uint16_t nb_desc, unsigned int socket_id,
2007 const struct rte_eth_txconf *conf)
2009 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010 struct fm10k_tx_queue *q;
2011 const struct rte_memzone *mz;
2014 PMD_INIT_FUNC_TRACE();
2016 offloads = conf->offloads | dev->data->dev_conf.txmode.offloads;
2018 /* make sure a valid number of descriptors have been requested */
2019 if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
2020 FM10K_MULT_TX_DESC, nb_desc)) {
2021 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
2022 "less than or equal to %"PRIu32", "
2023 "greater than or equal to %u, "
2024 "and a multiple of %u",
2025 nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
2026 FM10K_MULT_TX_DESC);
2031 * if this queue existed already, free the associated memory. The
2032 * queue cannot be reused in case we need to allocate memory on
2033 * different socket than was previously used.
2035 if (dev->data->tx_queues[queue_id] != NULL) {
2036 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
2039 dev->data->tx_queues[queue_id] = NULL;
2042 /* allocate memory for the queue structure */
2043 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2046 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2051 q->nb_desc = nb_desc;
2052 q->port_id = dev->data->port_id;
2053 q->queue_id = queue_id;
2054 q->offloads = offloads;
2055 q->ops = &def_txq_ops;
2056 q->tail_ptr = (volatile uint32_t *)
2057 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2058 if (handle_txconf(q, conf))
2061 /* allocate memory for the software ring */
2062 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2063 nb_desc * sizeof(struct rte_mbuf *),
2064 RTE_CACHE_LINE_SIZE, socket_id);
2065 if (q->sw_ring == NULL) {
2066 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2072 * allocate memory for the hardware descriptor ring. A memzone large
2073 * enough to hold the maximum ring size is requested to allow for
2074 * resizing in later calls to the queue setup function.
2076 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2077 FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2080 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2081 rte_free(q->sw_ring);
2085 q->hw_ring = mz->addr;
2086 q->hw_ring_phys_addr = mz->iova;
2089 * allocate memory for the RS bit tracker. Enough slots to hold the
2090 * descriptor index for each RS bit needing to be set are required.
2092 q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2093 ((nb_desc + 1) / q->rs_thresh) *
2095 RTE_CACHE_LINE_SIZE, socket_id);
2096 if (q->rs_tracker.list == NULL) {
2097 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2098 rte_free(q->sw_ring);
2103 dev->data->tx_queues[queue_id] = q;
2108 fm10k_tx_queue_release(void *queue)
2110 struct fm10k_tx_queue *q = queue;
2111 PMD_INIT_FUNC_TRACE();
2117 fm10k_reta_update(struct rte_eth_dev *dev,
2118 struct rte_eth_rss_reta_entry64 *reta_conf,
2121 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2122 uint16_t i, j, idx, shift;
2126 PMD_INIT_FUNC_TRACE();
2128 if (reta_size > FM10K_MAX_RSS_INDICES) {
2129 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2130 "(%d) doesn't match the number hardware can supported "
2131 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2136 * Update Redirection Table RETA[n], n=0..31. The redirection table has
2137 * 128-entries in 32 registers
2139 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2140 idx = i / RTE_RETA_GROUP_SIZE;
2141 shift = i % RTE_RETA_GROUP_SIZE;
2142 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2143 BIT_MASK_PER_UINT32);
2148 if (mask != BIT_MASK_PER_UINT32)
2149 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2151 for (j = 0; j < CHARS_PER_UINT32; j++) {
2152 if (mask & (0x1 << j)) {
2154 reta &= ~(UINT8_MAX << CHAR_BIT * j);
2155 reta |= reta_conf[idx].reta[shift + j] <<
2159 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2166 fm10k_reta_query(struct rte_eth_dev *dev,
2167 struct rte_eth_rss_reta_entry64 *reta_conf,
2170 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2171 uint16_t i, j, idx, shift;
2175 PMD_INIT_FUNC_TRACE();
2177 if (reta_size < FM10K_MAX_RSS_INDICES) {
2178 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2179 "(%d) doesn't match the number hardware can supported "
2180 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2185 * Read Redirection Table RETA[n], n=0..31. The redirection table has
2186 * 128-entries in 32 registers
2188 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2189 idx = i / RTE_RETA_GROUP_SIZE;
2190 shift = i % RTE_RETA_GROUP_SIZE;
2191 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2192 BIT_MASK_PER_UINT32);
2196 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2197 for (j = 0; j < CHARS_PER_UINT32; j++) {
2198 if (mask & (0x1 << j))
2199 reta_conf[idx].reta[shift + j] = ((reta >>
2200 CHAR_BIT * j) & UINT8_MAX);
2208 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2209 struct rte_eth_rss_conf *rss_conf)
2211 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2214 uint64_t hf = rss_conf->rss_hf;
2217 PMD_INIT_FUNC_TRACE();
2219 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2220 FM10K_RSSRK_ENTRIES_PER_REG))
2227 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
2228 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
2229 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
2230 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
2231 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
2232 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
2233 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
2234 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
2235 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
2237 /* If the mapping doesn't fit any supported, return */
2242 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2243 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2245 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2251 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2252 struct rte_eth_rss_conf *rss_conf)
2254 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2255 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2260 PMD_INIT_FUNC_TRACE();
2262 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2263 FM10K_RSSRK_ENTRIES_PER_REG))
2267 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2268 key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2270 mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2272 hf |= (mrqc & FM10K_MRQC_IPV4) ? ETH_RSS_IPV4 : 0;
2273 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6 : 0;
2274 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6_EX : 0;
2275 hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP : 0;
2276 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP : 0;
2277 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX : 0;
2278 hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP : 0;
2279 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP : 0;
2280 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX : 0;
2282 rss_conf->rss_hf = hf;
2288 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2290 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2293 /* Bind all local non-queue interrupt to vector 0 */
2294 int_map |= FM10K_MISC_VEC_ID;
2296 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2297 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2298 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2299 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2300 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2301 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2303 /* Enable misc causes */
2304 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2305 FM10K_EIMR_ENABLE(THI_FAULT) |
2306 FM10K_EIMR_ENABLE(FUM_FAULT) |
2307 FM10K_EIMR_ENABLE(MAILBOX) |
2308 FM10K_EIMR_ENABLE(SWITCHREADY) |
2309 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2310 FM10K_EIMR_ENABLE(SRAMERROR) |
2311 FM10K_EIMR_ENABLE(VFLR));
2314 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2315 FM10K_ITR_MASK_CLEAR);
2316 FM10K_WRITE_FLUSH(hw);
2320 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2322 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2325 int_map |= FM10K_MISC_VEC_ID;
2327 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2328 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2329 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2330 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2331 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2332 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2334 /* Disable misc causes */
2335 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2336 FM10K_EIMR_DISABLE(THI_FAULT) |
2337 FM10K_EIMR_DISABLE(FUM_FAULT) |
2338 FM10K_EIMR_DISABLE(MAILBOX) |
2339 FM10K_EIMR_DISABLE(SWITCHREADY) |
2340 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2341 FM10K_EIMR_DISABLE(SRAMERROR) |
2342 FM10K_EIMR_DISABLE(VFLR));
2345 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2346 FM10K_WRITE_FLUSH(hw);
2350 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2352 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2355 /* Bind all local non-queue interrupt to vector 0 */
2356 int_map |= FM10K_MISC_VEC_ID;
2358 /* Only INT 0 available, other 15 are reserved. */
2359 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2362 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2363 FM10K_ITR_MASK_CLEAR);
2364 FM10K_WRITE_FLUSH(hw);
2368 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2370 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2373 int_map |= FM10K_MISC_VEC_ID;
2375 /* Only INT 0 available, other 15 are reserved. */
2376 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2379 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2380 FM10K_WRITE_FLUSH(hw);
2384 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2386 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2390 if (hw->mac.type == fm10k_mac_pf)
2391 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2392 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2394 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2395 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2396 rte_intr_ack(&pdev->intr_handle);
2401 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2403 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2407 if (hw->mac.type == fm10k_mac_pf)
2408 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2409 FM10K_ITR_MASK_SET);
2411 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2412 FM10K_ITR_MASK_SET);
2417 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2419 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2421 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2422 uint32_t intr_vector, vec;
2426 /* fm10k needs one separate interrupt for mailbox,
2427 * so only drivers which support multiple interrupt vectors
2428 * e.g. vfio-pci can work for fm10k interrupt mode
2430 if (!rte_intr_cap_multiple(intr_handle) ||
2431 dev->data->dev_conf.intr_conf.rxq == 0)
2434 intr_vector = dev->data->nb_rx_queues;
2436 /* disable interrupt first */
2437 rte_intr_disable(intr_handle);
2438 if (hw->mac.type == fm10k_mac_pf)
2439 fm10k_dev_disable_intr_pf(dev);
2441 fm10k_dev_disable_intr_vf(dev);
2443 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2444 PMD_INIT_LOG(ERR, "Failed to init event fd");
2448 if (rte_intr_dp_is_en(intr_handle) && !result) {
2449 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2450 dev->data->nb_rx_queues * sizeof(int), 0);
2451 if (intr_handle->intr_vec) {
2452 for (queue_id = 0, vec = FM10K_RX_VEC_START;
2453 queue_id < dev->data->nb_rx_queues;
2455 intr_handle->intr_vec[queue_id] = vec;
2456 if (vec < intr_handle->nb_efd - 1
2457 + FM10K_RX_VEC_START)
2461 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2462 " intr_vec", dev->data->nb_rx_queues);
2463 rte_intr_efd_disable(intr_handle);
2468 if (hw->mac.type == fm10k_mac_pf)
2469 fm10k_dev_enable_intr_pf(dev);
2471 fm10k_dev_enable_intr_vf(dev);
2472 rte_intr_enable(intr_handle);
2473 hw->mac.ops.update_int_moderator(hw);
2478 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2480 struct fm10k_fault fault;
2482 const char *estr = "Unknown error";
2484 /* Process PCA fault */
2485 if (eicr & FM10K_EICR_PCA_FAULT) {
2486 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2489 switch (fault.type) {
2491 estr = "PCA_NO_FAULT"; break;
2492 case PCA_UNMAPPED_ADDR:
2493 estr = "PCA_UNMAPPED_ADDR"; break;
2494 case PCA_BAD_QACCESS_PF:
2495 estr = "PCA_BAD_QACCESS_PF"; break;
2496 case PCA_BAD_QACCESS_VF:
2497 estr = "PCA_BAD_QACCESS_VF"; break;
2498 case PCA_MALICIOUS_REQ:
2499 estr = "PCA_MALICIOUS_REQ"; break;
2500 case PCA_POISONED_TLP:
2501 estr = "PCA_POISONED_TLP"; break;
2503 estr = "PCA_TLP_ABORT"; break;
2507 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2508 estr, fault.func ? "VF" : "PF", fault.func,
2509 fault.address, fault.specinfo);
2512 /* Process THI fault */
2513 if (eicr & FM10K_EICR_THI_FAULT) {
2514 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2517 switch (fault.type) {
2519 estr = "THI_NO_FAULT"; break;
2520 case THI_MAL_DIS_Q_FAULT:
2521 estr = "THI_MAL_DIS_Q_FAULT"; break;
2525 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2526 estr, fault.func ? "VF" : "PF", fault.func,
2527 fault.address, fault.specinfo);
2530 /* Process FUM fault */
2531 if (eicr & FM10K_EICR_FUM_FAULT) {
2532 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2535 switch (fault.type) {
2537 estr = "FUM_NO_FAULT"; break;
2538 case FUM_UNMAPPED_ADDR:
2539 estr = "FUM_UNMAPPED_ADDR"; break;
2540 case FUM_POISONED_TLP:
2541 estr = "FUM_POISONED_TLP"; break;
2542 case FUM_BAD_VF_QACCESS:
2543 estr = "FUM_BAD_VF_QACCESS"; break;
2544 case FUM_ADD_DECODE_ERR:
2545 estr = "FUM_ADD_DECODE_ERR"; break;
2547 estr = "FUM_RO_ERROR"; break;
2548 case FUM_QPRC_CRC_ERROR:
2549 estr = "FUM_QPRC_CRC_ERROR"; break;
2550 case FUM_CSR_TIMEOUT:
2551 estr = "FUM_CSR_TIMEOUT"; break;
2552 case FUM_INVALID_TYPE:
2553 estr = "FUM_INVALID_TYPE"; break;
2554 case FUM_INVALID_LENGTH:
2555 estr = "FUM_INVALID_LENGTH"; break;
2556 case FUM_INVALID_BE:
2557 estr = "FUM_INVALID_BE"; break;
2558 case FUM_INVALID_ALIGN:
2559 estr = "FUM_INVALID_ALIGN"; break;
2563 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2564 estr, fault.func ? "VF" : "PF", fault.func,
2565 fault.address, fault.specinfo);
2570 PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2575 * PF interrupt handler triggered by NIC for handling specific interrupt.
2578 * Pointer to interrupt handle.
2580 * The address of parameter (struct rte_eth_dev *) regsitered before.
2586 fm10k_dev_interrupt_handler_pf(void *param)
2588 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2589 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590 uint32_t cause, status;
2591 struct fm10k_dev_info *dev_info =
2592 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2596 if (hw->mac.type != fm10k_mac_pf)
2599 cause = FM10K_READ_REG(hw, FM10K_EICR);
2601 /* Handle PCI fault cases */
2602 if (cause & FM10K_EICR_FAULT_MASK) {
2603 PMD_INIT_LOG(ERR, "INT: find fault!");
2604 fm10k_dev_handle_fault(hw, cause);
2607 /* Handle switch up/down */
2608 if (cause & FM10K_EICR_SWITCHNOTREADY)
2609 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2611 if (cause & FM10K_EICR_SWITCHREADY) {
2612 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2613 if (dev_info->sm_down == 1) {
2616 /* For recreating logical ports */
2617 status_mbx = hw->mac.ops.update_lport_state(hw,
2618 hw->mac.dglort_map, MAX_LPORT_NUM, 1);
2619 if (status_mbx == FM10K_SUCCESS)
2621 "INT: Recreated Logical port");
2624 "INT: Logical ports weren't recreated");
2626 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2627 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2628 if (status_mbx != FM10K_SUCCESS)
2629 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2631 fm10k_mbx_unlock(hw);
2633 /* first clear the internal SW recording structure */
2634 if (!(dev->data->dev_conf.rxmode.mq_mode &
2635 ETH_MQ_RX_VMDQ_FLAG))
2636 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2639 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2640 MAIN_VSI_POOL_NUMBER);
2643 * Add default mac address and vlan for the logical
2644 * ports that have been created, leave to the
2645 * application to fully recover Rx filtering.
2647 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2648 MAIN_VSI_POOL_NUMBER);
2650 if (!(dev->data->dev_conf.rxmode.mq_mode &
2651 ETH_MQ_RX_VMDQ_FLAG))
2652 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2655 dev_info->sm_down = 0;
2656 _rte_eth_dev_callback_process(dev,
2657 RTE_ETH_EVENT_INTR_LSC,
2662 /* Handle mailbox message */
2664 err = hw->mbx.ops.process(hw, &hw->mbx);
2665 fm10k_mbx_unlock(hw);
2667 if (err == FM10K_ERR_RESET_REQUESTED) {
2668 PMD_INIT_LOG(INFO, "INT: Switch is down");
2669 dev_info->sm_down = 1;
2670 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2674 /* Handle SRAM error */
2675 if (cause & FM10K_EICR_SRAMERROR) {
2676 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2678 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2679 /* Write to clear pending bits */
2680 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2682 /* Todo: print out error message after shared code updates */
2685 /* Clear these 3 events if having any */
2686 cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2687 FM10K_EICR_SWITCHREADY;
2689 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2691 /* Re-enable interrupt from device side */
2692 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2693 FM10K_ITR_MASK_CLEAR);
2694 /* Re-enable interrupt from host side */
2695 rte_intr_ack(dev->intr_handle);
2699 * VF interrupt handler triggered by NIC for handling specific interrupt.
2702 * Pointer to interrupt handle.
2704 * The address of parameter (struct rte_eth_dev *) regsitered before.
2710 fm10k_dev_interrupt_handler_vf(void *param)
2712 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2713 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2714 struct fm10k_mbx_info *mbx = &hw->mbx;
2715 struct fm10k_dev_info *dev_info =
2716 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2717 const enum fm10k_mbx_state state = mbx->state;
2720 if (hw->mac.type != fm10k_mac_vf)
2723 /* Handle mailbox message if lock is acquired */
2725 hw->mbx.ops.process(hw, &hw->mbx);
2726 fm10k_mbx_unlock(hw);
2728 if (state == FM10K_STATE_OPEN && mbx->state == FM10K_STATE_CONNECT) {
2729 PMD_INIT_LOG(INFO, "INT: Switch has gone down");
2732 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2734 fm10k_mbx_unlock(hw);
2736 /* Setting reset flag */
2737 dev_info->sm_down = 1;
2738 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2742 if (dev_info->sm_down == 1 &&
2743 hw->mac.dglort_map == FM10K_DGLORTMAP_ZERO) {
2744 PMD_INIT_LOG(INFO, "INT: Switch has gone up");
2746 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2747 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2748 if (status_mbx != FM10K_SUCCESS)
2749 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2750 fm10k_mbx_unlock(hw);
2752 /* first clear the internal SW recording structure */
2753 fm10k_vlan_filter_set(dev, hw->mac.default_vid, false);
2754 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2755 MAIN_VSI_POOL_NUMBER);
2758 * Add default mac address and vlan for the logical ports that
2759 * have been created, leave to the application to fully recover
2762 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2763 MAIN_VSI_POOL_NUMBER);
2764 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
2766 dev_info->sm_down = 0;
2767 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2771 /* Re-enable interrupt from device side */
2772 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2773 FM10K_ITR_MASK_CLEAR);
2774 /* Re-enable interrupt from host side */
2775 rte_intr_ack(dev->intr_handle);
2778 /* Mailbox message handler in VF */
2779 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2780 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2781 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2782 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2783 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2787 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2791 /* Initialize mailbox lock */
2792 fm10k_mbx_initlock(hw);
2794 /* Replace default message handler with new ones */
2795 if (hw->mac.type == fm10k_mac_vf)
2796 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2799 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2803 /* Connect to SM for PF device or PF for VF device */
2804 return hw->mbx.ops.connect(hw, &hw->mbx);
2808 fm10k_close_mbx_service(struct fm10k_hw *hw)
2810 /* Disconnect from SM for PF device or PF for VF device */
2811 hw->mbx.ops.disconnect(hw, &hw->mbx);
2815 fm10k_dev_close(struct rte_eth_dev *dev)
2817 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2819 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2821 PMD_INIT_FUNC_TRACE();
2824 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2825 MAX_LPORT_NUM, false);
2826 fm10k_mbx_unlock(hw);
2828 /* allow 100ms for device to quiesce */
2829 rte_delay_us(FM10K_SWITCH_QUIESCE_US);
2831 /* Stop mailbox service first */
2832 fm10k_close_mbx_service(hw);
2833 fm10k_dev_stop(dev);
2834 fm10k_dev_queue_release(dev);
2837 dev->dev_ops = NULL;
2838 dev->rx_pkt_burst = NULL;
2839 dev->tx_pkt_burst = NULL;
2841 /* disable uio/vfio intr */
2842 rte_intr_disable(intr_handle);
2844 /*PF/VF has different interrupt handling mechanism */
2845 if (hw->mac.type == fm10k_mac_pf) {
2846 /* disable interrupt */
2847 fm10k_dev_disable_intr_pf(dev);
2849 /* unregister callback func to eal lib */
2850 rte_intr_callback_unregister(intr_handle,
2851 fm10k_dev_interrupt_handler_pf, (void *)dev);
2853 /* disable interrupt */
2854 fm10k_dev_disable_intr_vf(dev);
2856 rte_intr_callback_unregister(intr_handle,
2857 fm10k_dev_interrupt_handler_vf, (void *)dev);
2861 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2862 .dev_configure = fm10k_dev_configure,
2863 .dev_start = fm10k_dev_start,
2864 .dev_stop = fm10k_dev_stop,
2865 .dev_close = fm10k_dev_close,
2866 .promiscuous_enable = fm10k_dev_promiscuous_enable,
2867 .promiscuous_disable = fm10k_dev_promiscuous_disable,
2868 .allmulticast_enable = fm10k_dev_allmulticast_enable,
2869 .allmulticast_disable = fm10k_dev_allmulticast_disable,
2870 .stats_get = fm10k_stats_get,
2871 .xstats_get = fm10k_xstats_get,
2872 .xstats_get_names = fm10k_xstats_get_names,
2873 .stats_reset = fm10k_stats_reset,
2874 .xstats_reset = fm10k_stats_reset,
2875 .link_update = fm10k_link_update,
2876 .dev_infos_get = fm10k_dev_infos_get,
2877 .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2878 .vlan_filter_set = fm10k_vlan_filter_set,
2879 .vlan_offload_set = fm10k_vlan_offload_set,
2880 .mac_addr_add = fm10k_macaddr_add,
2881 .mac_addr_remove = fm10k_macaddr_remove,
2882 .rx_queue_start = fm10k_dev_rx_queue_start,
2883 .rx_queue_stop = fm10k_dev_rx_queue_stop,
2884 .tx_queue_start = fm10k_dev_tx_queue_start,
2885 .tx_queue_stop = fm10k_dev_tx_queue_stop,
2886 .rx_queue_setup = fm10k_rx_queue_setup,
2887 .rx_queue_release = fm10k_rx_queue_release,
2888 .tx_queue_setup = fm10k_tx_queue_setup,
2889 .tx_queue_release = fm10k_tx_queue_release,
2890 .rx_queue_count = fm10k_dev_rx_queue_count,
2891 .rx_descriptor_done = fm10k_dev_rx_descriptor_done,
2892 .rx_descriptor_status = fm10k_dev_rx_descriptor_status,
2893 .tx_descriptor_status = fm10k_dev_tx_descriptor_status,
2894 .rx_queue_intr_enable = fm10k_dev_rx_queue_intr_enable,
2895 .rx_queue_intr_disable = fm10k_dev_rx_queue_intr_disable,
2896 .reta_update = fm10k_reta_update,
2897 .reta_query = fm10k_reta_query,
2898 .rss_hash_update = fm10k_rss_hash_update,
2899 .rss_hash_conf_get = fm10k_rss_hash_conf_get,
2902 static int ftag_check_handler(__rte_unused const char *key,
2903 const char *value, __rte_unused void *opaque)
2905 if (strcmp(value, "1"))
2912 fm10k_check_ftag(struct rte_devargs *devargs)
2914 struct rte_kvargs *kvlist;
2915 const char *ftag_key = "enable_ftag";
2917 if (devargs == NULL)
2920 kvlist = rte_kvargs_parse(devargs->args, NULL);
2924 if (!rte_kvargs_count(kvlist, ftag_key)) {
2925 rte_kvargs_free(kvlist);
2928 /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2929 if (rte_kvargs_process(kvlist, ftag_key,
2930 ftag_check_handler, NULL) < 0) {
2931 rte_kvargs_free(kvlist);
2934 rte_kvargs_free(kvlist);
2940 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
2944 struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
2949 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
2950 ret = fm10k_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
2961 static void __rte_cold
2962 fm10k_set_tx_function(struct rte_eth_dev *dev)
2964 struct fm10k_tx_queue *txq;
2967 uint16_t tx_ftag_en = 0;
2969 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2970 /* primary process has set the ftag flag and offloads */
2971 txq = dev->data->tx_queues[0];
2972 if (fm10k_tx_vec_condition_check(txq)) {
2973 dev->tx_pkt_burst = fm10k_xmit_pkts;
2974 dev->tx_pkt_prepare = fm10k_prep_pkts;
2975 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2977 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2978 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2979 dev->tx_pkt_prepare = NULL;
2984 if (fm10k_check_ftag(dev->device->devargs))
2987 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2988 txq = dev->data->tx_queues[i];
2989 txq->tx_ftag_en = tx_ftag_en;
2990 /* Check if Vector Tx is satisfied */
2991 if (fm10k_tx_vec_condition_check(txq))
2996 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2997 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2998 txq = dev->data->tx_queues[i];
2999 fm10k_txq_vec_setup(txq);
3001 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
3002 dev->tx_pkt_prepare = NULL;
3004 dev->tx_pkt_burst = fm10k_xmit_pkts;
3005 dev->tx_pkt_prepare = fm10k_prep_pkts;
3006 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
3010 static void __rte_cold
3011 fm10k_set_rx_function(struct rte_eth_dev *dev)
3013 struct fm10k_dev_info *dev_info =
3014 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
3015 uint16_t i, rx_using_sse;
3016 uint16_t rx_ftag_en = 0;
3018 if (fm10k_check_ftag(dev->device->devargs))
3021 /* In order to allow Vector Rx there are a few configuration
3022 * conditions to be met.
3024 if (!fm10k_rx_vec_condition_check(dev) &&
3025 dev_info->rx_vec_allowed && !rx_ftag_en) {
3026 if (dev->data->scattered_rx)
3027 dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
3029 dev->rx_pkt_burst = fm10k_recv_pkts_vec;
3030 } else if (dev->data->scattered_rx)
3031 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
3033 dev->rx_pkt_burst = fm10k_recv_pkts;
3036 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
3037 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
3040 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
3042 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
3044 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3047 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3048 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
3050 rxq->rx_using_sse = rx_using_sse;
3051 rxq->rx_ftag_en = rx_ftag_en;
3056 fm10k_params_init(struct rte_eth_dev *dev)
3058 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3059 struct fm10k_dev_info *info =
3060 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
3062 /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
3063 * there is no way to get link status without reading BAR4. Until this
3064 * works, assume we have maximum bandwidth.
3065 * @todo - fix bus info
3067 hw->bus_caps.speed = fm10k_bus_speed_8000;
3068 hw->bus_caps.width = fm10k_bus_width_pcie_x8;
3069 hw->bus_caps.payload = fm10k_bus_payload_512;
3070 hw->bus.speed = fm10k_bus_speed_8000;
3071 hw->bus.width = fm10k_bus_width_pcie_x8;
3072 hw->bus.payload = fm10k_bus_payload_256;
3074 info->rx_vec_allowed = true;
3075 info->sm_down = false;
3079 eth_fm10k_dev_init(struct rte_eth_dev *dev)
3081 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3082 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
3083 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3085 struct fm10k_macvlan_filter_info *macvlan;
3087 PMD_INIT_FUNC_TRACE();
3089 dev->dev_ops = &fm10k_eth_dev_ops;
3090 dev->rx_pkt_burst = &fm10k_recv_pkts;
3091 dev->tx_pkt_burst = &fm10k_xmit_pkts;
3092 dev->tx_pkt_prepare = &fm10k_prep_pkts;
3095 * Primary process does the whole initialization, for secondary
3096 * processes, we just select the same Rx and Tx function as primary.
3098 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3099 fm10k_set_rx_function(dev);
3100 fm10k_set_tx_function(dev);
3104 rte_eth_copy_pci_info(dev, pdev);
3106 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
3107 memset(macvlan, 0, sizeof(*macvlan));
3108 /* Vendor and Device ID need to be set before init of shared code */
3109 memset(hw, 0, sizeof(*hw));
3110 hw->device_id = pdev->id.device_id;
3111 hw->vendor_id = pdev->id.vendor_id;
3112 hw->subsystem_device_id = pdev->id.subsystem_device_id;
3113 hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
3114 hw->revision_id = 0;
3115 hw->hw_addr = (void *)pdev->mem_resource[0].addr;
3116 if (hw->hw_addr == NULL) {
3117 PMD_INIT_LOG(ERR, "Bad mem resource."
3118 " Try to blacklist unused devices.");
3122 /* Store fm10k_adapter pointer */
3123 hw->back = dev->data->dev_private;
3125 /* Initialize the shared code */
3126 diag = fm10k_init_shared_code(hw);
3127 if (diag != FM10K_SUCCESS) {
3128 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
3132 /* Initialize parameters */
3133 fm10k_params_init(dev);
3135 /* Initialize the hw */
3136 diag = fm10k_init_hw(hw);
3137 if (diag != FM10K_SUCCESS) {
3138 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
3142 /* Initialize MAC address(es) */
3143 dev->data->mac_addrs = rte_zmalloc("fm10k",
3144 RTE_ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
3145 if (dev->data->mac_addrs == NULL) {
3146 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
3150 diag = fm10k_read_mac_addr(hw);
3152 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
3153 &dev->data->mac_addrs[0]);
3155 if (diag != FM10K_SUCCESS ||
3156 !rte_is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
3158 /* Generate a random addr */
3159 rte_eth_random_addr(hw->mac.addr);
3160 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
3161 rte_ether_addr_copy((const struct rte_ether_addr *)hw->mac.addr,
3162 &dev->data->mac_addrs[0]);
3165 /* Pass the information to the rte_eth_dev_close() that it should also
3166 * release the private port resources.
3168 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
3170 /* Reset the hw statistics */
3171 diag = fm10k_stats_reset(dev);
3173 PMD_INIT_LOG(ERR, "Stats reset failed: %d", diag);
3178 diag = fm10k_reset_hw(hw);
3179 if (diag != FM10K_SUCCESS) {
3180 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
3184 /* Setup mailbox service */
3185 diag = fm10k_setup_mbx_service(hw);
3186 if (diag != FM10K_SUCCESS) {
3187 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
3191 /*PF/VF has different interrupt handling mechanism */
3192 if (hw->mac.type == fm10k_mac_pf) {
3193 /* register callback func to eal lib */
3194 rte_intr_callback_register(intr_handle,
3195 fm10k_dev_interrupt_handler_pf, (void *)dev);
3197 /* enable MISC interrupt */
3198 fm10k_dev_enable_intr_pf(dev);
3200 rte_intr_callback_register(intr_handle,
3201 fm10k_dev_interrupt_handler_vf, (void *)dev);
3203 fm10k_dev_enable_intr_vf(dev);
3206 /* Enable intr after callback registered */
3207 rte_intr_enable(intr_handle);
3209 hw->mac.ops.update_int_moderator(hw);
3211 /* Make sure Switch Manager is ready before going forward. */
3212 if (hw->mac.type == fm10k_mac_pf) {
3213 bool switch_ready = false;
3215 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3217 hw->mac.ops.get_host_state(hw, &switch_ready);
3218 fm10k_mbx_unlock(hw);
3219 if (switch_ready == true)
3221 /* Delay some time to acquire async LPORT_MAP info. */
3222 rte_delay_us(WAIT_SWITCH_MSG_US);
3225 if (switch_ready == false) {
3226 PMD_INIT_LOG(ERR, "switch is not ready");
3232 * Below function will trigger operations on mailbox, acquire lock to
3233 * avoid race condition from interrupt handler. Operations on mailbox
3234 * FIFO will trigger interrupt to PF/SM, in which interrupt handler
3235 * will handle and generate an interrupt to our side. Then, FIFO in
3236 * mailbox will be touched.
3239 /* Enable port first */
3240 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
3243 /* Set unicast mode by default. App can change to other mode in other
3246 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
3247 FM10K_XCAST_MODE_NONE);
3249 fm10k_mbx_unlock(hw);
3251 /* Make sure default VID is ready before going forward. */
3252 if (hw->mac.type == fm10k_mac_pf) {
3253 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3254 if (hw->mac.default_vid)
3256 /* Delay some time to acquire async port VLAN info. */
3257 rte_delay_us(WAIT_SWITCH_MSG_US);
3260 if (!hw->mac.default_vid) {
3261 PMD_INIT_LOG(ERR, "default VID is not ready");
3266 /* Add default mac address */
3267 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3268 MAIN_VSI_POOL_NUMBER);
3274 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3276 PMD_INIT_FUNC_TRACE();
3278 /* only uninitialize in the primary process */
3279 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3282 /* safe to close dev here */
3283 fm10k_dev_close(dev);
3288 static int eth_fm10k_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3289 struct rte_pci_device *pci_dev)
3291 return rte_eth_dev_pci_generic_probe(pci_dev,
3292 sizeof(struct fm10k_adapter), eth_fm10k_dev_init);
3295 static int eth_fm10k_pci_remove(struct rte_pci_device *pci_dev)
3297 return rte_eth_dev_pci_generic_remove(pci_dev, eth_fm10k_dev_uninit);
3301 * The set of PCI devices this driver supports. This driver will enable both PF
3302 * and SRIOV-VF devices.
3304 static const struct rte_pci_id pci_id_fm10k_map[] = {
3305 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3306 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3307 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3308 { .vendor_id = 0, /* sentinel */ },
3311 static struct rte_pci_driver rte_pmd_fm10k = {
3312 .id_table = pci_id_fm10k_map,
3313 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3314 .probe = eth_fm10k_pci_probe,
3315 .remove = eth_fm10k_pci_remove,
3318 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k);
3319 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3320 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio-pci");
3322 RTE_INIT(fm10k_init_log)
3324 fm10k_logtype_init = rte_log_register("pmd.net.fm10k.init");
3325 if (fm10k_logtype_init >= 0)
3326 rte_log_set_level(fm10k_logtype_init, RTE_LOG_NOTICE);
3327 fm10k_logtype_driver = rte_log_register("pmd.net.fm10k.driver");
3328 if (fm10k_logtype_driver >= 0)
3329 rte_log_set_level(fm10k_logtype_driver, RTE_LOG_NOTICE);
3331 #ifdef RTE_LIBRTE_FM10K_DEBUG_RX
3332 fm10k_logtype_rx = rte_log_register("pmd.net.fm10k.rx");
3333 if (fm10k_logtype_rx >= 0)
3334 rte_log_set_level(fm10k_logtype_rx, RTE_LOG_DEBUG);
3337 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX
3338 fm10k_logtype_tx = rte_log_register("pmd.net.fm10k.tx");
3339 if (fm10k_logtype_tx >= 0)
3340 rte_log_set_level(fm10k_logtype_tx, RTE_LOG_DEBUG);
3343 #ifdef RTE_LIBRTE_FM10K_DEBUG_TX_FREE
3344 fm10k_logtype_tx_free = rte_log_register("pmd.net.fm10k.tx_free");
3345 if (fm10k_logtype_tx_free >= 0)
3346 rte_log_set_level(fm10k_logtype_tx_free, RTE_LOG_DEBUG);