1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2013-2016 Intel Corporation
5 #include <rte_ethdev_driver.h>
6 #include <rte_ethdev_pci.h>
7 #include <rte_malloc.h>
8 #include <rte_memzone.h>
9 #include <rte_string_fns.h>
11 #include <rte_spinlock.h>
12 #include <rte_kvargs.h>
15 #include "base/fm10k_api.h"
17 /* Default delay to acquire mailbox lock */
18 #define FM10K_MBXLOCK_DELAY_US 20
19 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
21 #define MAIN_VSI_POOL_NUMBER 0
23 /* Max try times to acquire switch status */
24 #define MAX_QUERY_SWITCH_STATE_TIMES 10
25 /* Wait interval to get switch status */
26 #define WAIT_SWITCH_MSG_US 100000
27 /* A period of quiescence for switch */
28 #define FM10K_SWITCH_QUIESCE_US 100000
29 /* Number of chars per uint32 type */
30 #define CHARS_PER_UINT32 (sizeof(uint32_t))
31 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
33 /* default 1:1 map from queue ID to interrupt vector ID */
34 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
36 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
37 #define MAX_LPORT_NUM 128
38 #define GLORT_FD_Q_BASE 0x40
39 #define GLORT_PF_MASK 0xFFC0
40 #define GLORT_FD_MASK GLORT_PF_MASK
41 #define GLORT_FD_INDEX GLORT_FD_Q_BASE
43 int fm10k_logtype_init;
44 int fm10k_logtype_driver;
46 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
47 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
48 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
49 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
50 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
51 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
53 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
54 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
55 const u8 *mac, bool add, uint32_t pool);
56 static void fm10k_tx_queue_release(void *queue);
57 static void fm10k_rx_queue_release(void *queue);
58 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
59 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
60 static int fm10k_check_ftag(struct rte_devargs *devargs);
61 static int fm10k_link_update(struct rte_eth_dev *dev, int wait_to_complete);
63 static void fm10k_dev_infos_get(struct rte_eth_dev *dev,
64 struct rte_eth_dev_info *dev_info);
65 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev);
66 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev);
67 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev);
68 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev);
70 struct fm10k_xstats_name_off {
71 char name[RTE_ETH_XSTATS_NAME_SIZE];
75 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
76 {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
77 {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
78 {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
79 {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
80 {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
81 {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
82 {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
83 {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
87 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
88 sizeof(fm10k_hw_stats_strings[0]))
90 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
91 {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
92 {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
93 {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
96 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
97 sizeof(fm10k_hw_stats_rx_q_strings[0]))
99 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
100 {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
101 {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
104 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
105 sizeof(fm10k_hw_stats_tx_q_strings[0]))
107 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
108 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
110 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
113 fm10k_mbx_initlock(struct fm10k_hw *hw)
115 rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
119 fm10k_mbx_lock(struct fm10k_hw *hw)
121 while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
122 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
126 fm10k_mbx_unlock(struct fm10k_hw *hw)
128 rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
131 /* Stubs needed for linkage when vPMD is disabled */
132 int __attribute__((weak))
133 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
138 uint16_t __attribute__((weak))
140 __rte_unused void *rx_queue,
141 __rte_unused struct rte_mbuf **rx_pkts,
142 __rte_unused uint16_t nb_pkts)
147 uint16_t __attribute__((weak))
148 fm10k_recv_scattered_pkts_vec(
149 __rte_unused void *rx_queue,
150 __rte_unused struct rte_mbuf **rx_pkts,
151 __rte_unused uint16_t nb_pkts)
156 int __attribute__((weak))
157 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
163 void __attribute__((weak))
164 fm10k_rx_queue_release_mbufs_vec(
165 __rte_unused struct fm10k_rx_queue *rxq)
170 void __attribute__((weak))
171 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
176 int __attribute__((weak))
177 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
182 uint16_t __attribute__((weak))
183 fm10k_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
184 __rte_unused struct rte_mbuf **tx_pkts,
185 __rte_unused uint16_t nb_pkts)
191 * reset queue to initial state, allocate software buffers used when starting
193 * return 0 on success
194 * return -ENOMEM if buffers cannot be allocated
195 * return -EINVAL if buffers do not satisfy alignment condition
198 rx_queue_reset(struct fm10k_rx_queue *q)
200 static const union fm10k_rx_desc zero = {{0} };
203 PMD_INIT_FUNC_TRACE();
205 diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
209 for (i = 0; i < q->nb_desc; ++i) {
210 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
211 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
212 rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
216 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
217 q->hw_ring[i].q.pkt_addr = dma_addr;
218 q->hw_ring[i].q.hdr_addr = dma_addr;
221 /* initialize extra software ring entries. Space for these extra
222 * entries is always allocated.
224 memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
225 for (i = 0; i < q->nb_fake_desc; ++i) {
226 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
227 q->hw_ring[q->nb_desc + i] = zero;
232 q->next_trigger = q->alloc_thresh - 1;
233 FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
234 q->rxrearm_start = 0;
241 * clean queue, descriptor rings, free software buffers used when stopping
245 rx_queue_clean(struct fm10k_rx_queue *q)
247 union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
249 PMD_INIT_FUNC_TRACE();
251 /* zero descriptor rings */
252 for (i = 0; i < q->nb_desc; ++i)
253 q->hw_ring[i] = zero;
255 /* zero faked descriptors */
256 for (i = 0; i < q->nb_fake_desc; ++i)
257 q->hw_ring[q->nb_desc + i] = zero;
259 /* vPMD driver has a different way of releasing mbufs. */
260 if (q->rx_using_sse) {
261 fm10k_rx_queue_release_mbufs_vec(q);
265 /* free software buffers */
266 for (i = 0; i < q->nb_desc; ++i) {
268 rte_pktmbuf_free_seg(q->sw_ring[i]);
269 q->sw_ring[i] = NULL;
275 * free all queue memory used when releasing the queue (i.e. configure)
278 rx_queue_free(struct fm10k_rx_queue *q)
280 PMD_INIT_FUNC_TRACE();
282 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
285 rte_free(q->sw_ring);
294 * disable RX queue, wait unitl HW finished necessary flush operation
297 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
301 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
302 FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
303 reg & ~FM10K_RXQCTL_ENABLE);
305 /* Wait 100us at most */
306 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
308 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
309 if (!(reg & FM10K_RXQCTL_ENABLE))
313 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
320 * reset queue to initial state, allocate software buffers used when starting
324 tx_queue_reset(struct fm10k_tx_queue *q)
326 PMD_INIT_FUNC_TRACE();
330 q->nb_free = q->nb_desc - 1;
331 fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
332 FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
336 * clean queue, descriptor rings, free software buffers used when stopping
340 tx_queue_clean(struct fm10k_tx_queue *q)
342 struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
344 PMD_INIT_FUNC_TRACE();
346 /* zero descriptor rings */
347 for (i = 0; i < q->nb_desc; ++i)
348 q->hw_ring[i] = zero;
350 /* free software buffers */
351 for (i = 0; i < q->nb_desc; ++i) {
353 rte_pktmbuf_free_seg(q->sw_ring[i]);
354 q->sw_ring[i] = NULL;
360 * free all queue memory used when releasing the queue (i.e. configure)
363 tx_queue_free(struct fm10k_tx_queue *q)
365 PMD_INIT_FUNC_TRACE();
367 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
369 if (q->rs_tracker.list) {
370 rte_free(q->rs_tracker.list);
371 q->rs_tracker.list = NULL;
374 rte_free(q->sw_ring);
383 * disable TX queue, wait unitl HW finished necessary flush operation
386 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
390 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
391 FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
392 reg & ~FM10K_TXDCTL_ENABLE);
394 /* Wait 100us at most */
395 for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
397 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
398 if (!(reg & FM10K_TXDCTL_ENABLE))
402 if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
409 fm10k_check_mq_mode(struct rte_eth_dev *dev)
411 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
412 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
413 struct rte_eth_vmdq_rx_conf *vmdq_conf;
414 uint16_t nb_rx_q = dev->data->nb_rx_queues;
416 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
418 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
419 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
423 if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
426 if (hw->mac.type == fm10k_mac_vf) {
427 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
431 /* Check VMDQ queue pool number */
432 if (vmdq_conf->nb_queue_pools >
433 sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
434 vmdq_conf->nb_queue_pools > nb_rx_q) {
435 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
436 vmdq_conf->nb_queue_pools);
443 static const struct fm10k_txq_ops def_txq_ops = {
444 .reset = tx_queue_reset,
448 fm10k_dev_configure(struct rte_eth_dev *dev)
452 PMD_INIT_FUNC_TRACE();
454 /* KEEP_CRC offload flag is not supported by PMD
455 * can remove the below block when DEV_RX_OFFLOAD_CRC_STRIP removed
457 if (rte_eth_dev_must_keep_crc(dev->data->dev_conf.rxmode.offloads))
458 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
460 /* multipe queue mode checking */
461 ret = fm10k_check_mq_mode(dev);
463 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
468 dev->data->scattered_rx = 0;
473 /* fls = find last set bit = 32 minus the number of leading zeros */
475 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
479 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
481 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
482 struct rte_eth_vmdq_rx_conf *vmdq_conf;
485 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
487 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
488 if (!vmdq_conf->pool_map[i].pools)
491 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
492 fm10k_mbx_unlock(hw);
497 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
499 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
501 /* Add default mac address */
502 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
503 MAIN_VSI_POOL_NUMBER);
507 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
509 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
510 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
511 uint32_t mrqc, *key, i, reta, j;
514 #define RSS_KEY_SIZE 40
515 static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
516 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
517 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
518 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
519 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
520 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
523 if (dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
524 dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
525 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
529 /* random key is rss_intel_key (default) or user provided (rss_key) */
530 if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
531 key = (uint32_t *)rss_intel_key;
533 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
535 /* Now fill our hash function seeds, 4 bytes at a time */
536 for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
537 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
540 * Fill in redirection table
541 * The byte-swap is needed because NIC registers are in
542 * little-endian order.
545 for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
546 if (j == dev->data->nb_rx_queues)
548 reta = (reta << CHAR_BIT) | j;
550 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
555 * Generate RSS hash based on packet types, TCP/UDP
556 * port numbers and/or IPv4/v6 src and dst addresses
558 hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
560 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
561 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
562 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
563 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
564 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
565 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
566 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
567 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
568 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
571 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
576 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
580 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
582 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
585 for (i = 0; i < nb_lport_new; i++) {
586 /* Set unicast mode by default. App can change
587 * to other mode in other API func.
590 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
591 FM10K_XCAST_MODE_NONE);
592 fm10k_mbx_unlock(hw);
597 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
599 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
600 struct rte_eth_vmdq_rx_conf *vmdq_conf;
601 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
602 struct fm10k_macvlan_filter_info *macvlan;
603 uint16_t nb_queue_pools = 0; /* pool number in configuration */
604 uint16_t nb_lport_new;
606 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
607 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
609 fm10k_dev_rss_configure(dev);
611 /* only PF supports VMDQ */
612 if (hw->mac.type != fm10k_mac_pf)
615 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
616 nb_queue_pools = vmdq_conf->nb_queue_pools;
618 /* no pool number change, no need to update logic port and VLAN/MAC */
619 if (macvlan->nb_queue_pools == nb_queue_pools)
622 nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
623 fm10k_dev_logic_port_update(dev, nb_lport_new);
625 /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
626 memset(dev->data->mac_addrs, 0,
627 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
628 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
629 &dev->data->mac_addrs[0]);
630 memset(macvlan, 0, sizeof(*macvlan));
631 macvlan->nb_queue_pools = nb_queue_pools;
634 fm10k_dev_vmdq_rx_configure(dev);
636 fm10k_dev_pf_main_vsi_reset(dev);
640 fm10k_dev_tx_init(struct rte_eth_dev *dev)
642 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
644 struct fm10k_tx_queue *txq;
648 /* Disable TXINT to avoid possible interrupt */
649 for (i = 0; i < hw->mac.max_queues; i++)
650 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
651 3 << FM10K_TXINT_TIMER_SHIFT);
654 for (i = 0; i < dev->data->nb_tx_queues; ++i) {
655 txq = dev->data->tx_queues[i];
656 base_addr = txq->hw_ring_phys_addr;
657 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
659 /* disable queue to avoid issues while updating state */
660 ret = tx_queue_disable(hw, i);
662 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
665 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
666 * register is read-only for VF.
668 if (fm10k_check_ftag(dev->device->devargs)) {
669 if (hw->mac.type == fm10k_mac_pf) {
670 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
671 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
672 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
674 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
679 /* set location and size for descriptor ring */
680 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
681 base_addr & UINT64_LOWER_32BITS_MASK);
682 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
683 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
684 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
686 /* assign default SGLORT for each TX queue by PF */
687 if (hw->mac.type == fm10k_mac_pf)
688 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
691 /* set up vector or scalar TX function as appropriate */
692 fm10k_set_tx_function(dev);
698 fm10k_dev_rx_init(struct rte_eth_dev *dev)
700 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
701 struct fm10k_macvlan_filter_info *macvlan;
702 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
703 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
705 struct fm10k_rx_queue *rxq;
708 uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
709 uint32_t logic_port = hw->mac.dglort_map;
711 uint16_t queue_stride = 0;
713 /* enable RXINT for interrupt mode */
715 if (rte_intr_dp_is_en(intr_handle)) {
716 for (; i < dev->data->nb_rx_queues; i++) {
717 FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
718 if (hw->mac.type == fm10k_mac_pf)
719 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
721 FM10K_ITR_MASK_CLEAR);
723 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
725 FM10K_ITR_MASK_CLEAR);
728 /* Disable other RXINT to avoid possible interrupt */
729 for (; i < hw->mac.max_queues; i++)
730 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
731 3 << FM10K_RXINT_TIMER_SHIFT);
733 /* Setup RX queues */
734 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
735 rxq = dev->data->rx_queues[i];
736 base_addr = rxq->hw_ring_phys_addr;
737 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
739 /* disable queue to avoid issues while updating state */
740 ret = rx_queue_disable(hw, i);
742 PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
746 /* Setup the Base and Length of the Rx Descriptor Ring */
747 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
748 base_addr & UINT64_LOWER_32BITS_MASK);
749 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
750 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
751 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
753 /* Configure the Rx buffer size for one buff without split */
754 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
755 RTE_PKTMBUF_HEADROOM);
756 /* As RX buffer is aligned to 512B within mbuf, some bytes are
757 * reserved for this purpose, and the worst case could be 511B.
758 * But SRR reg assumes all buffers have the same size. In order
759 * to fill the gap, we'll have to consider the worst case and
760 * assume 512B is reserved. If we don't do so, it's possible
761 * for HW to overwrite data to next mbuf.
763 buf_size -= FM10K_RX_DATABUF_ALIGN;
765 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
766 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
767 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
769 /* It adds dual VLAN length for supporting dual VLAN */
770 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
771 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
772 rxq->offloads & DEV_RX_OFFLOAD_SCATTER) {
774 dev->data->scattered_rx = 1;
775 reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
776 reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
777 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
780 /* Enable drop on empty, it's RO for VF */
781 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
782 rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
784 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
785 FM10K_WRITE_FLUSH(hw);
788 /* Configure VMDQ/RSS if applicable */
789 fm10k_dev_mq_rx_configure(dev);
791 /* Decide the best RX function */
792 fm10k_set_rx_function(dev);
794 /* update RX_SGLORT for loopback suppress*/
795 if (hw->mac.type != fm10k_mac_pf)
797 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
798 if (macvlan->nb_queue_pools)
799 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
800 for (i = 0; i < dev->data->nb_rx_queues; ++i) {
801 if (i && queue_stride && !(i % queue_stride))
803 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
810 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
812 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
815 struct fm10k_rx_queue *rxq;
817 PMD_INIT_FUNC_TRACE();
819 if (rx_queue_id < dev->data->nb_rx_queues) {
820 rxq = dev->data->rx_queues[rx_queue_id];
821 err = rx_queue_reset(rxq);
822 if (err == -ENOMEM) {
823 PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
825 } else if (err == -EINVAL) {
826 PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
831 /* Setup the HW Rx Head and Tail Descriptor Pointers
832 * Note: this must be done AFTER the queue is enabled on real
833 * hardware, but BEFORE the queue is enabled when using the
834 * emulation platform. Do it in both places for now and remove
835 * this comment and the following two register writes when the
836 * emulation platform is no longer being used.
838 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
839 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
841 /* Set PF ownership flag for PF devices */
842 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
843 if (hw->mac.type == fm10k_mac_pf)
844 reg |= FM10K_RXQCTL_PF;
845 reg |= FM10K_RXQCTL_ENABLE;
846 /* enable RX queue */
847 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
848 FM10K_WRITE_FLUSH(hw);
850 /* Setup the HW Rx Head and Tail Descriptor Pointers
851 * Note: this must be done AFTER the queue is enabled
853 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
854 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
855 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
862 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
864 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
866 PMD_INIT_FUNC_TRACE();
868 if (rx_queue_id < dev->data->nb_rx_queues) {
869 /* Disable RX queue */
870 rx_queue_disable(hw, rx_queue_id);
872 /* Free mbuf and clean HW ring */
873 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
874 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
881 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
883 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
884 /** @todo - this should be defined in the shared code */
885 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY 0x00010000
886 uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
889 PMD_INIT_FUNC_TRACE();
891 if (tx_queue_id < dev->data->nb_tx_queues) {
892 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
896 /* reset head and tail pointers */
897 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
898 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
900 /* enable TX queue */
901 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
902 FM10K_TXDCTL_ENABLE | txdctl);
903 FM10K_WRITE_FLUSH(hw);
904 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
912 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
914 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
916 PMD_INIT_FUNC_TRACE();
918 if (tx_queue_id < dev->data->nb_tx_queues) {
919 tx_queue_disable(hw, tx_queue_id);
920 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
921 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
927 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
929 return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
930 != FM10K_DGLORTMAP_NONE);
934 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
936 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
939 PMD_INIT_FUNC_TRACE();
941 /* Return if it didn't acquire valid glort range */
942 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
946 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
947 FM10K_XCAST_MODE_PROMISC);
948 fm10k_mbx_unlock(hw);
950 if (status != FM10K_SUCCESS)
951 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
955 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
957 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
961 PMD_INIT_FUNC_TRACE();
963 /* Return if it didn't acquire valid glort range */
964 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
967 if (dev->data->all_multicast == 1)
968 mode = FM10K_XCAST_MODE_ALLMULTI;
970 mode = FM10K_XCAST_MODE_NONE;
973 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
975 fm10k_mbx_unlock(hw);
977 if (status != FM10K_SUCCESS)
978 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
982 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
984 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
987 PMD_INIT_FUNC_TRACE();
989 /* Return if it didn't acquire valid glort range */
990 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
993 /* If promiscuous mode is enabled, it doesn't make sense to enable
994 * allmulticast and disable promiscuous since fm10k only can select
997 if (dev->data->promiscuous) {
998 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
999 "needn't enable allmulticast");
1004 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1005 FM10K_XCAST_MODE_ALLMULTI);
1006 fm10k_mbx_unlock(hw);
1008 if (status != FM10K_SUCCESS)
1009 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1013 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1015 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1018 PMD_INIT_FUNC_TRACE();
1020 /* Return if it didn't acquire valid glort range */
1021 if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1024 if (dev->data->promiscuous) {
1025 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1026 "since promisc mode is enabled");
1031 /* Change mode to unicast mode */
1032 status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1033 FM10K_XCAST_MODE_NONE);
1034 fm10k_mbx_unlock(hw);
1036 if (status != FM10K_SUCCESS)
1037 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1041 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1043 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044 uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1045 uint16_t nb_queue_pools;
1046 struct fm10k_macvlan_filter_info *macvlan;
1048 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1049 nb_queue_pools = macvlan->nb_queue_pools;
1050 pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1051 rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1053 /* GLORT 0x0-0x3F are used by PF and VMDQ, 0x40-0x7F used by FD */
1054 dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1055 dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1057 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1058 /* Configure VMDQ/RSS DGlort Decoder */
1059 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1061 /* Flow Director configurations, only queue number is valid. */
1062 dglortdec = fls(dev->data->nb_rx_queues - 1);
1063 dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1064 (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1065 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1066 FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1068 /* Invalidate all other GLORT entries */
1069 for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1070 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1071 FM10K_DGLORTMAP_NONE);
1074 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1076 fm10k_dev_start(struct rte_eth_dev *dev)
1078 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1081 PMD_INIT_FUNC_TRACE();
1083 /* stop, init, then start the hw */
1084 diag = fm10k_stop_hw(hw);
1085 if (diag != FM10K_SUCCESS) {
1086 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1090 diag = fm10k_init_hw(hw);
1091 if (diag != FM10K_SUCCESS) {
1092 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1096 diag = fm10k_start_hw(hw);
1097 if (diag != FM10K_SUCCESS) {
1098 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1102 diag = fm10k_dev_tx_init(dev);
1104 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1108 if (fm10k_dev_rxq_interrupt_setup(dev))
1111 diag = fm10k_dev_rx_init(dev);
1113 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1117 if (hw->mac.type == fm10k_mac_pf)
1118 fm10k_dev_dglort_map_configure(dev);
1120 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1121 struct fm10k_rx_queue *rxq;
1122 rxq = dev->data->rx_queues[i];
1124 if (rxq->rx_deferred_start)
1126 diag = fm10k_dev_rx_queue_start(dev, i);
1129 for (j = 0; j < i; ++j)
1130 rx_queue_clean(dev->data->rx_queues[j]);
1135 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1136 struct fm10k_tx_queue *txq;
1137 txq = dev->data->tx_queues[i];
1139 if (txq->tx_deferred_start)
1141 diag = fm10k_dev_tx_queue_start(dev, i);
1144 for (j = 0; j < i; ++j)
1145 tx_queue_clean(dev->data->tx_queues[j]);
1146 for (j = 0; j < dev->data->nb_rx_queues; ++j)
1147 rx_queue_clean(dev->data->rx_queues[j]);
1152 /* Update default vlan when not in VMDQ mode */
1153 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1154 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1156 fm10k_link_update(dev, 0);
1162 fm10k_dev_stop(struct rte_eth_dev *dev)
1164 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1165 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1166 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1169 PMD_INIT_FUNC_TRACE();
1171 if (dev->data->tx_queues)
1172 for (i = 0; i < dev->data->nb_tx_queues; i++)
1173 fm10k_dev_tx_queue_stop(dev, i);
1175 if (dev->data->rx_queues)
1176 for (i = 0; i < dev->data->nb_rx_queues; i++)
1177 fm10k_dev_rx_queue_stop(dev, i);
1179 /* Disable datapath event */
1180 if (rte_intr_dp_is_en(intr_handle)) {
1181 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1182 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1183 3 << FM10K_RXINT_TIMER_SHIFT);
1184 if (hw->mac.type == fm10k_mac_pf)
1185 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1186 FM10K_ITR_MASK_SET);
1188 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1189 FM10K_ITR_MASK_SET);
1192 /* Clean datapath event and queue/vec mapping */
1193 rte_intr_efd_disable(intr_handle);
1194 rte_free(intr_handle->intr_vec);
1195 intr_handle->intr_vec = NULL;
1199 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1203 PMD_INIT_FUNC_TRACE();
1205 if (dev->data->tx_queues) {
1206 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1207 struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1213 if (dev->data->rx_queues) {
1214 for (i = 0; i < dev->data->nb_rx_queues; i++)
1215 fm10k_rx_queue_release(dev->data->rx_queues[i]);
1220 fm10k_dev_close(struct rte_eth_dev *dev)
1222 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224 PMD_INIT_FUNC_TRACE();
1227 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1228 MAX_LPORT_NUM, false);
1229 fm10k_mbx_unlock(hw);
1231 /* allow 100ms for device to quiesce */
1232 rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1234 /* Stop mailbox service first */
1235 fm10k_close_mbx_service(hw);
1236 fm10k_dev_stop(dev);
1237 fm10k_dev_queue_release(dev);
1242 fm10k_link_update(struct rte_eth_dev *dev,
1243 __rte_unused int wait_to_complete)
1245 struct fm10k_dev_info *dev_info =
1246 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1247 PMD_INIT_FUNC_TRACE();
1249 dev->data->dev_link.link_speed = ETH_SPEED_NUM_50G;
1250 dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1251 dev->data->dev_link.link_status =
1252 dev_info->sm_down ? ETH_LINK_DOWN : ETH_LINK_UP;
1253 dev->data->dev_link.link_autoneg = ETH_LINK_FIXED;
1258 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1259 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1264 if (xstats_names != NULL) {
1265 /* Note: limit checked in rte_eth_xstats_names() */
1268 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1269 snprintf(xstats_names[count].name,
1270 sizeof(xstats_names[count].name),
1271 "%s", fm10k_hw_stats_strings[count].name);
1275 /* PF queue stats */
1276 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1277 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1278 snprintf(xstats_names[count].name,
1279 sizeof(xstats_names[count].name),
1281 fm10k_hw_stats_rx_q_strings[i].name);
1284 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1285 snprintf(xstats_names[count].name,
1286 sizeof(xstats_names[count].name),
1288 fm10k_hw_stats_tx_q_strings[i].name);
1293 return FM10K_NB_XSTATS;
1297 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1300 struct fm10k_hw_stats *hw_stats =
1301 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1302 unsigned i, q, count = 0;
1304 if (n < FM10K_NB_XSTATS)
1305 return FM10K_NB_XSTATS;
1308 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1309 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1310 fm10k_hw_stats_strings[count].offset);
1311 xstats[count].id = count;
1315 /* PF queue stats */
1316 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1317 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1318 xstats[count].value =
1319 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1320 fm10k_hw_stats_rx_q_strings[i].offset);
1321 xstats[count].id = count;
1324 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1325 xstats[count].value =
1326 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1327 fm10k_hw_stats_tx_q_strings[i].offset);
1328 xstats[count].id = count;
1333 return FM10K_NB_XSTATS;
1337 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1339 uint64_t ipackets, opackets, ibytes, obytes;
1340 struct fm10k_hw *hw =
1341 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342 struct fm10k_hw_stats *hw_stats =
1343 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1346 PMD_INIT_FUNC_TRACE();
1348 fm10k_update_hw_stats(hw, hw_stats);
1350 ipackets = opackets = ibytes = obytes = 0;
1351 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1352 (i < hw->mac.max_queues); ++i) {
1353 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1354 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1355 stats->q_ibytes[i] = hw_stats->q[i].rx_bytes.count;
1356 stats->q_obytes[i] = hw_stats->q[i].tx_bytes.count;
1357 ipackets += stats->q_ipackets[i];
1358 opackets += stats->q_opackets[i];
1359 ibytes += stats->q_ibytes[i];
1360 obytes += stats->q_obytes[i];
1362 stats->ipackets = ipackets;
1363 stats->opackets = opackets;
1364 stats->ibytes = ibytes;
1365 stats->obytes = obytes;
1370 fm10k_stats_reset(struct rte_eth_dev *dev)
1372 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1373 struct fm10k_hw_stats *hw_stats =
1374 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1376 PMD_INIT_FUNC_TRACE();
1378 memset(hw_stats, 0, sizeof(*hw_stats));
1379 fm10k_rebind_hw_stats(hw, hw_stats);
1383 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1384 struct rte_eth_dev_info *dev_info)
1386 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1387 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
1389 PMD_INIT_FUNC_TRACE();
1391 dev_info->min_rx_bufsize = FM10K_MIN_RX_BUF_SIZE;
1392 dev_info->max_rx_pktlen = FM10K_MAX_PKT_SIZE;
1393 dev_info->max_rx_queues = hw->mac.max_queues;
1394 dev_info->max_tx_queues = hw->mac.max_queues;
1395 dev_info->max_mac_addrs = FM10K_MAX_MACADDR_NUM;
1396 dev_info->max_hash_mac_addrs = 0;
1397 dev_info->max_vfs = pdev->max_vfs;
1398 dev_info->vmdq_pool_base = 0;
1399 dev_info->vmdq_queue_base = 0;
1400 dev_info->max_vmdq_pools = ETH_32_POOLS;
1401 dev_info->vmdq_queue_num = FM10K_MAX_QUEUES_PF;
1402 dev_info->rx_queue_offload_capa = fm10k_get_rx_queue_offloads_capa(dev);
1403 dev_info->rx_offload_capa = fm10k_get_rx_port_offloads_capa(dev) |
1404 dev_info->rx_queue_offload_capa;
1405 dev_info->tx_queue_offload_capa = fm10k_get_tx_queue_offloads_capa(dev);
1406 dev_info->tx_offload_capa = fm10k_get_tx_port_offloads_capa(dev) |
1407 dev_info->tx_queue_offload_capa;
1409 dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1410 dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1412 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1414 .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1415 .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1416 .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1418 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1423 dev_info->default_txconf = (struct rte_eth_txconf) {
1425 .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1426 .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1427 .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1429 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1430 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1434 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1435 .nb_max = FM10K_MAX_RX_DESC,
1436 .nb_min = FM10K_MIN_RX_DESC,
1437 .nb_align = FM10K_MULT_RX_DESC,
1440 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1441 .nb_max = FM10K_MAX_TX_DESC,
1442 .nb_min = FM10K_MIN_TX_DESC,
1443 .nb_align = FM10K_MULT_TX_DESC,
1444 .nb_seg_max = FM10K_TX_MAX_SEG,
1445 .nb_mtu_seg_max = FM10K_TX_MAX_MTU_SEG,
1448 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1449 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1450 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1453 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1454 static const uint32_t *
1455 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1457 if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1458 dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1459 static uint32_t ptypes[] = {
1460 /* refers to rx_desc_to_ol_flags() */
1463 RTE_PTYPE_L3_IPV4_EXT,
1465 RTE_PTYPE_L3_IPV6_EXT,
1472 } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1473 dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1474 static uint32_t ptypes_vec[] = {
1475 /* refers to fm10k_desc_to_pktype_v() */
1477 RTE_PTYPE_L3_IPV4_EXT,
1479 RTE_PTYPE_L3_IPV6_EXT,
1482 RTE_PTYPE_TUNNEL_GENEVE,
1483 RTE_PTYPE_TUNNEL_NVGRE,
1484 RTE_PTYPE_TUNNEL_VXLAN,
1485 RTE_PTYPE_TUNNEL_GRE,
1495 static const uint32_t *
1496 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1503 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1506 uint16_t mac_num = 0;
1507 uint32_t vid_idx, vid_bit, mac_index;
1508 struct fm10k_hw *hw;
1509 struct fm10k_macvlan_filter_info *macvlan;
1510 struct rte_eth_dev_data *data = dev->data;
1512 hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1513 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1515 if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1516 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1520 if (vlan_id > ETH_VLAN_ID_MAX) {
1521 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1525 vid_idx = FM10K_VFTA_IDX(vlan_id);
1526 vid_bit = FM10K_VFTA_BIT(vlan_id);
1527 /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1528 if (on && (macvlan->vfta[vid_idx] & vid_bit))
1530 /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1531 if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1532 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1533 "in the VLAN filter table");
1538 result = fm10k_update_vlan(hw, vlan_id, 0, on);
1539 fm10k_mbx_unlock(hw);
1540 if (result != FM10K_SUCCESS) {
1541 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1545 for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1546 (result == FM10K_SUCCESS); mac_index++) {
1547 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1549 if (mac_num > macvlan->mac_num - 1) {
1550 PMD_INIT_LOG(ERR, "MAC address number "
1555 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1556 data->mac_addrs[mac_index].addr_bytes,
1558 fm10k_mbx_unlock(hw);
1561 if (result != FM10K_SUCCESS) {
1562 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1567 macvlan->vlan_num++;
1568 macvlan->vfta[vid_idx] |= vid_bit;
1570 macvlan->vlan_num--;
1571 macvlan->vfta[vid_idx] &= ~vid_bit;
1577 fm10k_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1579 if (mask & ETH_VLAN_STRIP_MASK) {
1580 if (!(dev->data->dev_conf.rxmode.offloads &
1581 DEV_RX_OFFLOAD_VLAN_STRIP))
1582 PMD_INIT_LOG(ERR, "VLAN stripping is "
1583 "always on in fm10k");
1586 if (mask & ETH_VLAN_EXTEND_MASK) {
1587 if (dev->data->dev_conf.rxmode.offloads &
1588 DEV_RX_OFFLOAD_VLAN_EXTEND)
1589 PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1590 "supported in fm10k");
1593 if (mask & ETH_VLAN_FILTER_MASK) {
1594 if (!(dev->data->dev_conf.rxmode.offloads &
1595 DEV_RX_OFFLOAD_VLAN_FILTER))
1596 PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1602 /* Add/Remove a MAC address, and update filters to main VSI */
1603 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1604 const u8 *mac, bool add, uint32_t pool)
1606 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607 struct fm10k_macvlan_filter_info *macvlan;
1610 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1612 if (pool != MAIN_VSI_POOL_NUMBER) {
1613 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1614 "mac to pool %u", pool);
1617 for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1618 if (!macvlan->vfta[j])
1620 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1621 if (!(macvlan->vfta[j] & (1 << k)))
1623 if (i + 1 > macvlan->vlan_num) {
1624 PMD_INIT_LOG(ERR, "vlan number not match");
1628 fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1629 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1630 fm10k_mbx_unlock(hw);
1636 /* Add/Remove a MAC address, and update filters to VMDQ */
1637 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1638 const u8 *mac, bool add, uint32_t pool)
1640 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1641 struct fm10k_macvlan_filter_info *macvlan;
1642 struct rte_eth_vmdq_rx_conf *vmdq_conf;
1645 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1646 vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1648 if (pool > macvlan->nb_queue_pools) {
1649 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1651 pool, macvlan->nb_queue_pools);
1654 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1655 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1658 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1659 vmdq_conf->pool_map[i].vlan_id, add, 0);
1660 fm10k_mbx_unlock(hw);
1664 /* Add/Remove a MAC address, and update filters */
1665 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1666 const u8 *mac, bool add, uint32_t pool)
1668 struct fm10k_macvlan_filter_info *macvlan;
1670 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1672 if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1673 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1675 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1683 /* Add a MAC address, and update filters */
1685 fm10k_macaddr_add(struct rte_eth_dev *dev,
1686 struct ether_addr *mac_addr,
1690 struct fm10k_macvlan_filter_info *macvlan;
1692 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1693 fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1694 macvlan->mac_vmdq_id[index] = pool;
1698 /* Remove a MAC address, and update filters */
1700 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1702 struct rte_eth_dev_data *data = dev->data;
1703 struct fm10k_macvlan_filter_info *macvlan;
1705 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1706 fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1707 FALSE, macvlan->mac_vmdq_id[index]);
1708 macvlan->mac_vmdq_id[index] = 0;
1712 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1714 if ((request < min) || (request > max) || ((request % mult) != 0))
1722 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1724 if ((request < min) || (request > max) || ((div % request) != 0))
1731 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1733 uint16_t rx_free_thresh;
1735 if (conf->rx_free_thresh == 0)
1736 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1738 rx_free_thresh = conf->rx_free_thresh;
1740 /* make sure the requested threshold satisfies the constraints */
1741 if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1742 FM10K_RX_FREE_THRESH_MAX(q),
1743 FM10K_RX_FREE_THRESH_DIV(q),
1745 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1746 "less than or equal to %u, "
1747 "greater than or equal to %u, "
1748 "and a divisor of %u",
1749 rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1750 FM10K_RX_FREE_THRESH_MIN(q),
1751 FM10K_RX_FREE_THRESH_DIV(q));
1755 q->alloc_thresh = rx_free_thresh;
1756 q->drop_en = conf->rx_drop_en;
1757 q->rx_deferred_start = conf->rx_deferred_start;
1763 * Hardware requires specific alignment for Rx packet buffers. At
1764 * least one of the following two conditions must be satisfied.
1765 * 1. Address is 512B aligned
1766 * 2. Address is 8B aligned and buffer does not cross 4K boundary.
1768 * As such, the driver may need to adjust the DMA address within the
1769 * buffer by up to 512B.
1771 * return 1 if the element size is valid, otherwise return 0.
1774 mempool_element_size_valid(struct rte_mempool *mp)
1778 /* elt_size includes mbuf header and headroom */
1779 min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1780 RTE_PKTMBUF_HEADROOM;
1782 /* account for up to 512B of alignment */
1783 min_size -= FM10K_RX_DATABUF_ALIGN;
1785 /* sanity check for overflow */
1786 if (min_size > mp->elt_size)
1793 static uint64_t fm10k_get_rx_queue_offloads_capa(struct rte_eth_dev *dev)
1797 return (uint64_t)(DEV_RX_OFFLOAD_SCATTER);
1800 static uint64_t fm10k_get_rx_port_offloads_capa(struct rte_eth_dev *dev)
1804 return (uint64_t)(DEV_RX_OFFLOAD_VLAN_STRIP |
1805 DEV_RX_OFFLOAD_VLAN_FILTER |
1806 DEV_RX_OFFLOAD_IPV4_CKSUM |
1807 DEV_RX_OFFLOAD_UDP_CKSUM |
1808 DEV_RX_OFFLOAD_TCP_CKSUM |
1809 DEV_RX_OFFLOAD_JUMBO_FRAME |
1810 DEV_RX_OFFLOAD_CRC_STRIP |
1811 DEV_RX_OFFLOAD_HEADER_SPLIT);
1815 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1816 uint16_t nb_desc, unsigned int socket_id,
1817 const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1819 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820 struct fm10k_dev_info *dev_info =
1821 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1822 struct fm10k_rx_queue *q;
1823 const struct rte_memzone *mz;
1826 PMD_INIT_FUNC_TRACE();
1828 offloads = conf->offloads | dev->data->dev_conf.rxmode.offloads;
1830 /* make sure the mempool element size can account for alignment. */
1831 if (!mempool_element_size_valid(mp)) {
1832 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1836 /* make sure a valid number of descriptors have been requested */
1837 if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1838 FM10K_MULT_RX_DESC, nb_desc)) {
1839 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1840 "less than or equal to %"PRIu32", "
1841 "greater than or equal to %u, "
1842 "and a multiple of %u",
1843 nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1844 FM10K_MULT_RX_DESC);
1849 * if this queue existed already, free the associated memory. The
1850 * queue cannot be reused in case we need to allocate memory on
1851 * different socket than was previously used.
1853 if (dev->data->rx_queues[queue_id] != NULL) {
1854 rx_queue_free(dev->data->rx_queues[queue_id]);
1855 dev->data->rx_queues[queue_id] = NULL;
1858 /* allocate memory for the queue structure */
1859 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1862 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1868 q->nb_desc = nb_desc;
1869 q->nb_fake_desc = FM10K_MULT_RX_DESC;
1870 q->port_id = dev->data->port_id;
1871 q->queue_id = queue_id;
1872 q->tail_ptr = (volatile uint32_t *)
1873 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1874 q->offloads = offloads;
1875 if (handle_rxconf(q, conf))
1878 /* allocate memory for the software ring */
1879 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1880 (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1881 RTE_CACHE_LINE_SIZE, socket_id);
1882 if (q->sw_ring == NULL) {
1883 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1889 * allocate memory for the hardware descriptor ring. A memzone large
1890 * enough to hold the maximum ring size is requested to allow for
1891 * resizing in later calls to the queue setup function.
1893 mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1894 FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1897 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1898 rte_free(q->sw_ring);
1902 q->hw_ring = mz->addr;
1903 q->hw_ring_phys_addr = mz->iova;
1905 /* Check if number of descs satisfied Vector requirement */
1906 if (!rte_is_power_of_2(nb_desc)) {
1907 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1908 "preconditions - canceling the feature for "
1909 "the whole port[%d]",
1910 q->queue_id, q->port_id);
1911 dev_info->rx_vec_allowed = false;
1913 fm10k_rxq_vec_setup(q);
1915 dev->data->rx_queues[queue_id] = q;
1920 fm10k_rx_queue_release(void *queue)
1922 PMD_INIT_FUNC_TRACE();
1924 rx_queue_free(queue);
1928 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1930 uint16_t tx_free_thresh;
1931 uint16_t tx_rs_thresh;
1933 /* constraint MACROs require that tx_free_thresh is configured
1934 * before tx_rs_thresh */
1935 if (conf->tx_free_thresh == 0)
1936 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1938 tx_free_thresh = conf->tx_free_thresh;
1940 /* make sure the requested threshold satisfies the constraints */
1941 if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1942 FM10K_TX_FREE_THRESH_MAX(q),
1943 FM10K_TX_FREE_THRESH_DIV(q),
1945 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1946 "less than or equal to %u, "
1947 "greater than or equal to %u, "
1948 "and a divisor of %u",
1949 tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1950 FM10K_TX_FREE_THRESH_MIN(q),
1951 FM10K_TX_FREE_THRESH_DIV(q));
1955 q->free_thresh = tx_free_thresh;
1957 if (conf->tx_rs_thresh == 0)
1958 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1960 tx_rs_thresh = conf->tx_rs_thresh;
1962 q->tx_deferred_start = conf->tx_deferred_start;
1964 /* make sure the requested threshold satisfies the constraints */
1965 if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1966 FM10K_TX_RS_THRESH_MAX(q),
1967 FM10K_TX_RS_THRESH_DIV(q),
1969 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1970 "less than or equal to %u, "
1971 "greater than or equal to %u, "
1972 "and a divisor of %u",
1973 tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1974 FM10K_TX_RS_THRESH_MIN(q),
1975 FM10K_TX_RS_THRESH_DIV(q));
1979 q->rs_thresh = tx_rs_thresh;
1984 static uint64_t fm10k_get_tx_queue_offloads_capa(struct rte_eth_dev *dev)
1991 static uint64_t fm10k_get_tx_port_offloads_capa(struct rte_eth_dev *dev)
1995 return (uint64_t)(DEV_TX_OFFLOAD_VLAN_INSERT |
1996 DEV_TX_OFFLOAD_IPV4_CKSUM |
1997 DEV_TX_OFFLOAD_UDP_CKSUM |
1998 DEV_TX_OFFLOAD_TCP_CKSUM |
1999 DEV_TX_OFFLOAD_TCP_TSO);
2003 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
2004 uint16_t nb_desc, unsigned int socket_id,
2005 const struct rte_eth_txconf *conf)
2007 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008 struct fm10k_tx_queue *q;
2009 const struct rte_memzone *mz;
2012 PMD_INIT_FUNC_TRACE();
2014 offloads = conf->offloads | dev->data->dev_conf.txmode.offloads;
2016 /* make sure a valid number of descriptors have been requested */
2017 if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
2018 FM10K_MULT_TX_DESC, nb_desc)) {
2019 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
2020 "less than or equal to %"PRIu32", "
2021 "greater than or equal to %u, "
2022 "and a multiple of %u",
2023 nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
2024 FM10K_MULT_TX_DESC);
2029 * if this queue existed already, free the associated memory. The
2030 * queue cannot be reused in case we need to allocate memory on
2031 * different socket than was previously used.
2033 if (dev->data->tx_queues[queue_id] != NULL) {
2034 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
2037 dev->data->tx_queues[queue_id] = NULL;
2040 /* allocate memory for the queue structure */
2041 q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2044 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2049 q->nb_desc = nb_desc;
2050 q->port_id = dev->data->port_id;
2051 q->queue_id = queue_id;
2052 q->offloads = offloads;
2053 q->ops = &def_txq_ops;
2054 q->tail_ptr = (volatile uint32_t *)
2055 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2056 if (handle_txconf(q, conf))
2059 /* allocate memory for the software ring */
2060 q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2061 nb_desc * sizeof(struct rte_mbuf *),
2062 RTE_CACHE_LINE_SIZE, socket_id);
2063 if (q->sw_ring == NULL) {
2064 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2070 * allocate memory for the hardware descriptor ring. A memzone large
2071 * enough to hold the maximum ring size is requested to allow for
2072 * resizing in later calls to the queue setup function.
2074 mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2075 FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2078 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2079 rte_free(q->sw_ring);
2083 q->hw_ring = mz->addr;
2084 q->hw_ring_phys_addr = mz->iova;
2087 * allocate memory for the RS bit tracker. Enough slots to hold the
2088 * descriptor index for each RS bit needing to be set are required.
2090 q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2091 ((nb_desc + 1) / q->rs_thresh) *
2093 RTE_CACHE_LINE_SIZE, socket_id);
2094 if (q->rs_tracker.list == NULL) {
2095 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2096 rte_free(q->sw_ring);
2101 dev->data->tx_queues[queue_id] = q;
2106 fm10k_tx_queue_release(void *queue)
2108 struct fm10k_tx_queue *q = queue;
2109 PMD_INIT_FUNC_TRACE();
2115 fm10k_reta_update(struct rte_eth_dev *dev,
2116 struct rte_eth_rss_reta_entry64 *reta_conf,
2119 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120 uint16_t i, j, idx, shift;
2124 PMD_INIT_FUNC_TRACE();
2126 if (reta_size > FM10K_MAX_RSS_INDICES) {
2127 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2128 "(%d) doesn't match the number hardware can supported "
2129 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2134 * Update Redirection Table RETA[n], n=0..31. The redirection table has
2135 * 128-entries in 32 registers
2137 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2138 idx = i / RTE_RETA_GROUP_SIZE;
2139 shift = i % RTE_RETA_GROUP_SIZE;
2140 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2141 BIT_MASK_PER_UINT32);
2146 if (mask != BIT_MASK_PER_UINT32)
2147 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2149 for (j = 0; j < CHARS_PER_UINT32; j++) {
2150 if (mask & (0x1 << j)) {
2152 reta &= ~(UINT8_MAX << CHAR_BIT * j);
2153 reta |= reta_conf[idx].reta[shift + j] <<
2157 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2164 fm10k_reta_query(struct rte_eth_dev *dev,
2165 struct rte_eth_rss_reta_entry64 *reta_conf,
2168 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169 uint16_t i, j, idx, shift;
2173 PMD_INIT_FUNC_TRACE();
2175 if (reta_size < FM10K_MAX_RSS_INDICES) {
2176 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2177 "(%d) doesn't match the number hardware can supported "
2178 "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2183 * Read Redirection Table RETA[n], n=0..31. The redirection table has
2184 * 128-entries in 32 registers
2186 for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2187 idx = i / RTE_RETA_GROUP_SIZE;
2188 shift = i % RTE_RETA_GROUP_SIZE;
2189 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2190 BIT_MASK_PER_UINT32);
2194 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2195 for (j = 0; j < CHARS_PER_UINT32; j++) {
2196 if (mask & (0x1 << j))
2197 reta_conf[idx].reta[shift + j] = ((reta >>
2198 CHAR_BIT * j) & UINT8_MAX);
2206 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2207 struct rte_eth_rss_conf *rss_conf)
2209 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2212 uint64_t hf = rss_conf->rss_hf;
2215 PMD_INIT_FUNC_TRACE();
2217 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2218 FM10K_RSSRK_ENTRIES_PER_REG))
2225 mrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;
2226 mrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;
2227 mrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;
2228 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;
2229 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;
2230 mrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;
2231 mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;
2232 mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;
2233 mrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;
2235 /* If the mapping doesn't fit any supported, return */
2240 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2241 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2243 FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2249 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2250 struct rte_eth_rss_conf *rss_conf)
2252 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253 uint32_t *key = (uint32_t *)rss_conf->rss_key;
2258 PMD_INIT_FUNC_TRACE();
2260 if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2261 FM10K_RSSRK_ENTRIES_PER_REG))
2265 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2266 key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2268 mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2270 hf |= (mrqc & FM10K_MRQC_IPV4) ? ETH_RSS_IPV4 : 0;
2271 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6 : 0;
2272 hf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6_EX : 0;
2273 hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP : 0;
2274 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP : 0;
2275 hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX : 0;
2276 hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP : 0;
2277 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP : 0;
2278 hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX : 0;
2280 rss_conf->rss_hf = hf;
2286 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2288 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2291 /* Bind all local non-queue interrupt to vector 0 */
2292 int_map |= FM10K_MISC_VEC_ID;
2294 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2295 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2296 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2297 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2298 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2299 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2301 /* Enable misc causes */
2302 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2303 FM10K_EIMR_ENABLE(THI_FAULT) |
2304 FM10K_EIMR_ENABLE(FUM_FAULT) |
2305 FM10K_EIMR_ENABLE(MAILBOX) |
2306 FM10K_EIMR_ENABLE(SWITCHREADY) |
2307 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2308 FM10K_EIMR_ENABLE(SRAMERROR) |
2309 FM10K_EIMR_ENABLE(VFLR));
2312 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2313 FM10K_ITR_MASK_CLEAR);
2314 FM10K_WRITE_FLUSH(hw);
2318 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2320 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2321 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2323 int_map |= FM10K_MISC_VEC_ID;
2325 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2326 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2327 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2328 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2329 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2330 FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2332 /* Disable misc causes */
2333 FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2334 FM10K_EIMR_DISABLE(THI_FAULT) |
2335 FM10K_EIMR_DISABLE(FUM_FAULT) |
2336 FM10K_EIMR_DISABLE(MAILBOX) |
2337 FM10K_EIMR_DISABLE(SWITCHREADY) |
2338 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2339 FM10K_EIMR_DISABLE(SRAMERROR) |
2340 FM10K_EIMR_DISABLE(VFLR));
2343 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2344 FM10K_WRITE_FLUSH(hw);
2348 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2350 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351 uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2353 /* Bind all local non-queue interrupt to vector 0 */
2354 int_map |= FM10K_MISC_VEC_ID;
2356 /* Only INT 0 available, other 15 are reserved. */
2357 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2360 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2361 FM10K_ITR_MASK_CLEAR);
2362 FM10K_WRITE_FLUSH(hw);
2366 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2368 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369 uint32_t int_map = FM10K_INT_MAP_DISABLE;
2371 int_map |= FM10K_MISC_VEC_ID;
2373 /* Only INT 0 available, other 15 are reserved. */
2374 FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2377 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2378 FM10K_WRITE_FLUSH(hw);
2382 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2384 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2385 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2388 if (hw->mac.type == fm10k_mac_pf)
2389 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2390 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2392 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2393 FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2394 rte_intr_enable(&pdev->intr_handle);
2399 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2401 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2402 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2405 if (hw->mac.type == fm10k_mac_pf)
2406 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2407 FM10K_ITR_MASK_SET);
2409 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2410 FM10K_ITR_MASK_SET);
2415 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2417 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2418 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
2419 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2420 uint32_t intr_vector, vec;
2424 /* fm10k needs one separate interrupt for mailbox,
2425 * so only drivers which support multiple interrupt vectors
2426 * e.g. vfio-pci can work for fm10k interrupt mode
2428 if (!rte_intr_cap_multiple(intr_handle) ||
2429 dev->data->dev_conf.intr_conf.rxq == 0)
2432 intr_vector = dev->data->nb_rx_queues;
2434 /* disable interrupt first */
2435 rte_intr_disable(intr_handle);
2436 if (hw->mac.type == fm10k_mac_pf)
2437 fm10k_dev_disable_intr_pf(dev);
2439 fm10k_dev_disable_intr_vf(dev);
2441 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2442 PMD_INIT_LOG(ERR, "Failed to init event fd");
2446 if (rte_intr_dp_is_en(intr_handle) && !result) {
2447 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2448 dev->data->nb_rx_queues * sizeof(int), 0);
2449 if (intr_handle->intr_vec) {
2450 for (queue_id = 0, vec = FM10K_RX_VEC_START;
2451 queue_id < dev->data->nb_rx_queues;
2453 intr_handle->intr_vec[queue_id] = vec;
2454 if (vec < intr_handle->nb_efd - 1
2455 + FM10K_RX_VEC_START)
2459 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2460 " intr_vec", dev->data->nb_rx_queues);
2461 rte_intr_efd_disable(intr_handle);
2466 if (hw->mac.type == fm10k_mac_pf)
2467 fm10k_dev_enable_intr_pf(dev);
2469 fm10k_dev_enable_intr_vf(dev);
2470 rte_intr_enable(intr_handle);
2471 hw->mac.ops.update_int_moderator(hw);
2476 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2478 struct fm10k_fault fault;
2480 const char *estr = "Unknown error";
2482 /* Process PCA fault */
2483 if (eicr & FM10K_EICR_PCA_FAULT) {
2484 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2487 switch (fault.type) {
2489 estr = "PCA_NO_FAULT"; break;
2490 case PCA_UNMAPPED_ADDR:
2491 estr = "PCA_UNMAPPED_ADDR"; break;
2492 case PCA_BAD_QACCESS_PF:
2493 estr = "PCA_BAD_QACCESS_PF"; break;
2494 case PCA_BAD_QACCESS_VF:
2495 estr = "PCA_BAD_QACCESS_VF"; break;
2496 case PCA_MALICIOUS_REQ:
2497 estr = "PCA_MALICIOUS_REQ"; break;
2498 case PCA_POISONED_TLP:
2499 estr = "PCA_POISONED_TLP"; break;
2501 estr = "PCA_TLP_ABORT"; break;
2505 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2506 estr, fault.func ? "VF" : "PF", fault.func,
2507 fault.address, fault.specinfo);
2510 /* Process THI fault */
2511 if (eicr & FM10K_EICR_THI_FAULT) {
2512 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2515 switch (fault.type) {
2517 estr = "THI_NO_FAULT"; break;
2518 case THI_MAL_DIS_Q_FAULT:
2519 estr = "THI_MAL_DIS_Q_FAULT"; break;
2523 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2524 estr, fault.func ? "VF" : "PF", fault.func,
2525 fault.address, fault.specinfo);
2528 /* Process FUM fault */
2529 if (eicr & FM10K_EICR_FUM_FAULT) {
2530 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2533 switch (fault.type) {
2535 estr = "FUM_NO_FAULT"; break;
2536 case FUM_UNMAPPED_ADDR:
2537 estr = "FUM_UNMAPPED_ADDR"; break;
2538 case FUM_POISONED_TLP:
2539 estr = "FUM_POISONED_TLP"; break;
2540 case FUM_BAD_VF_QACCESS:
2541 estr = "FUM_BAD_VF_QACCESS"; break;
2542 case FUM_ADD_DECODE_ERR:
2543 estr = "FUM_ADD_DECODE_ERR"; break;
2545 estr = "FUM_RO_ERROR"; break;
2546 case FUM_QPRC_CRC_ERROR:
2547 estr = "FUM_QPRC_CRC_ERROR"; break;
2548 case FUM_CSR_TIMEOUT:
2549 estr = "FUM_CSR_TIMEOUT"; break;
2550 case FUM_INVALID_TYPE:
2551 estr = "FUM_INVALID_TYPE"; break;
2552 case FUM_INVALID_LENGTH:
2553 estr = "FUM_INVALID_LENGTH"; break;
2554 case FUM_INVALID_BE:
2555 estr = "FUM_INVALID_BE"; break;
2556 case FUM_INVALID_ALIGN:
2557 estr = "FUM_INVALID_ALIGN"; break;
2561 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2562 estr, fault.func ? "VF" : "PF", fault.func,
2563 fault.address, fault.specinfo);
2568 PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2573 * PF interrupt handler triggered by NIC for handling specific interrupt.
2576 * Pointer to interrupt handle.
2578 * The address of parameter (struct rte_eth_dev *) regsitered before.
2584 fm10k_dev_interrupt_handler_pf(void *param)
2586 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2587 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2588 uint32_t cause, status;
2589 struct fm10k_dev_info *dev_info =
2590 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2594 if (hw->mac.type != fm10k_mac_pf)
2597 cause = FM10K_READ_REG(hw, FM10K_EICR);
2599 /* Handle PCI fault cases */
2600 if (cause & FM10K_EICR_FAULT_MASK) {
2601 PMD_INIT_LOG(ERR, "INT: find fault!");
2602 fm10k_dev_handle_fault(hw, cause);
2605 /* Handle switch up/down */
2606 if (cause & FM10K_EICR_SWITCHNOTREADY)
2607 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2609 if (cause & FM10K_EICR_SWITCHREADY) {
2610 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2611 if (dev_info->sm_down == 1) {
2614 /* For recreating logical ports */
2615 status_mbx = hw->mac.ops.update_lport_state(hw,
2616 hw->mac.dglort_map, MAX_LPORT_NUM, 1);
2617 if (status_mbx == FM10K_SUCCESS)
2619 "INT: Recreated Logical port");
2622 "INT: Logical ports weren't recreated");
2624 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2625 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2626 if (status_mbx != FM10K_SUCCESS)
2627 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2629 fm10k_mbx_unlock(hw);
2631 /* first clear the internal SW recording structure */
2632 if (!(dev->data->dev_conf.rxmode.mq_mode &
2633 ETH_MQ_RX_VMDQ_FLAG))
2634 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2637 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2638 MAIN_VSI_POOL_NUMBER);
2641 * Add default mac address and vlan for the logical
2642 * ports that have been created, leave to the
2643 * application to fully recover Rx filtering.
2645 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2646 MAIN_VSI_POOL_NUMBER);
2648 if (!(dev->data->dev_conf.rxmode.mq_mode &
2649 ETH_MQ_RX_VMDQ_FLAG))
2650 fm10k_vlan_filter_set(dev, hw->mac.default_vid,
2653 dev_info->sm_down = 0;
2654 _rte_eth_dev_callback_process(dev,
2655 RTE_ETH_EVENT_INTR_LSC,
2660 /* Handle mailbox message */
2662 err = hw->mbx.ops.process(hw, &hw->mbx);
2663 fm10k_mbx_unlock(hw);
2665 if (err == FM10K_ERR_RESET_REQUESTED) {
2666 PMD_INIT_LOG(INFO, "INT: Switch is down");
2667 dev_info->sm_down = 1;
2668 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2672 /* Handle SRAM error */
2673 if (cause & FM10K_EICR_SRAMERROR) {
2674 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2676 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2677 /* Write to clear pending bits */
2678 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2680 /* Todo: print out error message after shared code updates */
2683 /* Clear these 3 events if having any */
2684 cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2685 FM10K_EICR_SWITCHREADY;
2687 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2689 /* Re-enable interrupt from device side */
2690 FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2691 FM10K_ITR_MASK_CLEAR);
2692 /* Re-enable interrupt from host side */
2693 rte_intr_enable(dev->intr_handle);
2697 * VF interrupt handler triggered by NIC for handling specific interrupt.
2700 * Pointer to interrupt handle.
2702 * The address of parameter (struct rte_eth_dev *) regsitered before.
2708 fm10k_dev_interrupt_handler_vf(void *param)
2710 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2711 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712 struct fm10k_mbx_info *mbx = &hw->mbx;
2713 struct fm10k_dev_info *dev_info =
2714 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2715 const enum fm10k_mbx_state state = mbx->state;
2718 if (hw->mac.type != fm10k_mac_vf)
2721 /* Handle mailbox message if lock is acquired */
2723 hw->mbx.ops.process(hw, &hw->mbx);
2724 fm10k_mbx_unlock(hw);
2726 if (state == FM10K_STATE_OPEN && mbx->state == FM10K_STATE_CONNECT) {
2727 PMD_INIT_LOG(INFO, "INT: Switch has gone down");
2730 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2732 fm10k_mbx_unlock(hw);
2734 /* Setting reset flag */
2735 dev_info->sm_down = 1;
2736 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2740 if (dev_info->sm_down == 1 &&
2741 hw->mac.dglort_map == FM10K_DGLORTMAP_ZERO) {
2742 PMD_INIT_LOG(INFO, "INT: Switch has gone up");
2744 status_mbx = hw->mac.ops.update_xcast_mode(hw,
2745 hw->mac.dglort_map, FM10K_XCAST_MODE_NONE);
2746 if (status_mbx != FM10K_SUCCESS)
2747 PMD_INIT_LOG(ERR, "Failed to set XCAST mode");
2748 fm10k_mbx_unlock(hw);
2750 /* first clear the internal SW recording structure */
2751 fm10k_vlan_filter_set(dev, hw->mac.default_vid, false);
2752 fm10k_MAC_filter_set(dev, hw->mac.addr, false,
2753 MAIN_VSI_POOL_NUMBER);
2756 * Add default mac address and vlan for the logical ports that
2757 * have been created, leave to the application to fully recover
2760 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2761 MAIN_VSI_POOL_NUMBER);
2762 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
2764 dev_info->sm_down = 0;
2765 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2769 /* Re-enable interrupt from device side */
2770 FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2771 FM10K_ITR_MASK_CLEAR);
2772 /* Re-enable interrupt from host side */
2773 rte_intr_enable(dev->intr_handle);
2776 /* Mailbox message handler in VF */
2777 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2778 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2779 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2780 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2781 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2785 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2789 /* Initialize mailbox lock */
2790 fm10k_mbx_initlock(hw);
2792 /* Replace default message handler with new ones */
2793 if (hw->mac.type == fm10k_mac_vf)
2794 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2797 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2801 /* Connect to SM for PF device or PF for VF device */
2802 return hw->mbx.ops.connect(hw, &hw->mbx);
2806 fm10k_close_mbx_service(struct fm10k_hw *hw)
2808 /* Disconnect from SM for PF device or PF for VF device */
2809 hw->mbx.ops.disconnect(hw, &hw->mbx);
2812 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2813 .dev_configure = fm10k_dev_configure,
2814 .dev_start = fm10k_dev_start,
2815 .dev_stop = fm10k_dev_stop,
2816 .dev_close = fm10k_dev_close,
2817 .promiscuous_enable = fm10k_dev_promiscuous_enable,
2818 .promiscuous_disable = fm10k_dev_promiscuous_disable,
2819 .allmulticast_enable = fm10k_dev_allmulticast_enable,
2820 .allmulticast_disable = fm10k_dev_allmulticast_disable,
2821 .stats_get = fm10k_stats_get,
2822 .xstats_get = fm10k_xstats_get,
2823 .xstats_get_names = fm10k_xstats_get_names,
2824 .stats_reset = fm10k_stats_reset,
2825 .xstats_reset = fm10k_stats_reset,
2826 .link_update = fm10k_link_update,
2827 .dev_infos_get = fm10k_dev_infos_get,
2828 .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2829 .vlan_filter_set = fm10k_vlan_filter_set,
2830 .vlan_offload_set = fm10k_vlan_offload_set,
2831 .mac_addr_add = fm10k_macaddr_add,
2832 .mac_addr_remove = fm10k_macaddr_remove,
2833 .rx_queue_start = fm10k_dev_rx_queue_start,
2834 .rx_queue_stop = fm10k_dev_rx_queue_stop,
2835 .tx_queue_start = fm10k_dev_tx_queue_start,
2836 .tx_queue_stop = fm10k_dev_tx_queue_stop,
2837 .rx_queue_setup = fm10k_rx_queue_setup,
2838 .rx_queue_release = fm10k_rx_queue_release,
2839 .tx_queue_setup = fm10k_tx_queue_setup,
2840 .tx_queue_release = fm10k_tx_queue_release,
2841 .rx_descriptor_done = fm10k_dev_rx_descriptor_done,
2842 .rx_descriptor_status = fm10k_dev_rx_descriptor_status,
2843 .tx_descriptor_status = fm10k_dev_tx_descriptor_status,
2844 .rx_queue_intr_enable = fm10k_dev_rx_queue_intr_enable,
2845 .rx_queue_intr_disable = fm10k_dev_rx_queue_intr_disable,
2846 .reta_update = fm10k_reta_update,
2847 .reta_query = fm10k_reta_query,
2848 .rss_hash_update = fm10k_rss_hash_update,
2849 .rss_hash_conf_get = fm10k_rss_hash_conf_get,
2852 static int ftag_check_handler(__rte_unused const char *key,
2853 const char *value, __rte_unused void *opaque)
2855 if (strcmp(value, "1"))
2862 fm10k_check_ftag(struct rte_devargs *devargs)
2864 struct rte_kvargs *kvlist;
2865 const char *ftag_key = "enable_ftag";
2867 if (devargs == NULL)
2870 kvlist = rte_kvargs_parse(devargs->args, NULL);
2874 if (!rte_kvargs_count(kvlist, ftag_key)) {
2875 rte_kvargs_free(kvlist);
2878 /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2879 if (rte_kvargs_process(kvlist, ftag_key,
2880 ftag_check_handler, NULL) < 0) {
2881 rte_kvargs_free(kvlist);
2884 rte_kvargs_free(kvlist);
2890 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
2894 struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
2899 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
2900 ret = fm10k_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
2911 static void __attribute__((cold))
2912 fm10k_set_tx_function(struct rte_eth_dev *dev)
2914 struct fm10k_tx_queue *txq;
2917 uint16_t tx_ftag_en = 0;
2919 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2920 /* primary process has set the ftag flag and offloads */
2921 txq = dev->data->tx_queues[0];
2922 if (fm10k_tx_vec_condition_check(txq)) {
2923 dev->tx_pkt_burst = fm10k_xmit_pkts;
2924 dev->tx_pkt_prepare = fm10k_prep_pkts;
2925 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2927 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2928 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2929 dev->tx_pkt_prepare = NULL;
2934 if (fm10k_check_ftag(dev->device->devargs))
2937 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2938 txq = dev->data->tx_queues[i];
2939 txq->tx_ftag_en = tx_ftag_en;
2940 /* Check if Vector Tx is satisfied */
2941 if (fm10k_tx_vec_condition_check(txq))
2946 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2947 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2948 txq = dev->data->tx_queues[i];
2949 fm10k_txq_vec_setup(txq);
2951 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2952 dev->tx_pkt_prepare = NULL;
2954 dev->tx_pkt_burst = fm10k_xmit_pkts;
2955 dev->tx_pkt_prepare = fm10k_prep_pkts;
2956 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2960 static void __attribute__((cold))
2961 fm10k_set_rx_function(struct rte_eth_dev *dev)
2963 struct fm10k_dev_info *dev_info =
2964 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2965 uint16_t i, rx_using_sse;
2966 uint16_t rx_ftag_en = 0;
2968 if (fm10k_check_ftag(dev->device->devargs))
2971 /* In order to allow Vector Rx there are a few configuration
2972 * conditions to be met.
2974 if (!fm10k_rx_vec_condition_check(dev) &&
2975 dev_info->rx_vec_allowed && !rx_ftag_en) {
2976 if (dev->data->scattered_rx)
2977 dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2979 dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2980 } else if (dev->data->scattered_rx)
2981 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2983 dev->rx_pkt_burst = fm10k_recv_pkts;
2986 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2987 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2990 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2992 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2994 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2997 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2998 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
3000 rxq->rx_using_sse = rx_using_sse;
3001 rxq->rx_ftag_en = rx_ftag_en;
3006 fm10k_params_init(struct rte_eth_dev *dev)
3008 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009 struct fm10k_dev_info *info =
3010 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
3012 /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
3013 * there is no way to get link status without reading BAR4. Until this
3014 * works, assume we have maximum bandwidth.
3015 * @todo - fix bus info
3017 hw->bus_caps.speed = fm10k_bus_speed_8000;
3018 hw->bus_caps.width = fm10k_bus_width_pcie_x8;
3019 hw->bus_caps.payload = fm10k_bus_payload_512;
3020 hw->bus.speed = fm10k_bus_speed_8000;
3021 hw->bus.width = fm10k_bus_width_pcie_x8;
3022 hw->bus.payload = fm10k_bus_payload_256;
3024 info->rx_vec_allowed = true;
3028 eth_fm10k_dev_init(struct rte_eth_dev *dev)
3030 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3031 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
3032 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3034 struct fm10k_macvlan_filter_info *macvlan;
3036 PMD_INIT_FUNC_TRACE();
3038 dev->dev_ops = &fm10k_eth_dev_ops;
3039 dev->rx_pkt_burst = &fm10k_recv_pkts;
3040 dev->tx_pkt_burst = &fm10k_xmit_pkts;
3041 dev->tx_pkt_prepare = &fm10k_prep_pkts;
3044 * Primary process does the whole initialization, for secondary
3045 * processes, we just select the same Rx and Tx function as primary.
3047 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3048 fm10k_set_rx_function(dev);
3049 fm10k_set_tx_function(dev);
3053 rte_eth_copy_pci_info(dev, pdev);
3055 macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
3056 memset(macvlan, 0, sizeof(*macvlan));
3057 /* Vendor and Device ID need to be set before init of shared code */
3058 memset(hw, 0, sizeof(*hw));
3059 hw->device_id = pdev->id.device_id;
3060 hw->vendor_id = pdev->id.vendor_id;
3061 hw->subsystem_device_id = pdev->id.subsystem_device_id;
3062 hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
3063 hw->revision_id = 0;
3064 hw->hw_addr = (void *)pdev->mem_resource[0].addr;
3065 if (hw->hw_addr == NULL) {
3066 PMD_INIT_LOG(ERR, "Bad mem resource."
3067 " Try to blacklist unused devices.");
3071 /* Store fm10k_adapter pointer */
3072 hw->back = dev->data->dev_private;
3074 /* Initialize the shared code */
3075 diag = fm10k_init_shared_code(hw);
3076 if (diag != FM10K_SUCCESS) {
3077 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
3081 /* Initialize parameters */
3082 fm10k_params_init(dev);
3084 /* Initialize the hw */
3085 diag = fm10k_init_hw(hw);
3086 if (diag != FM10K_SUCCESS) {
3087 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
3091 /* Initialize MAC address(es) */
3092 dev->data->mac_addrs = rte_zmalloc("fm10k",
3093 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
3094 if (dev->data->mac_addrs == NULL) {
3095 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
3099 diag = fm10k_read_mac_addr(hw);
3101 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
3102 &dev->data->mac_addrs[0]);
3104 if (diag != FM10K_SUCCESS ||
3105 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
3107 /* Generate a random addr */
3108 eth_random_addr(hw->mac.addr);
3109 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
3110 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
3111 &dev->data->mac_addrs[0]);
3114 /* Reset the hw statistics */
3115 fm10k_stats_reset(dev);
3118 diag = fm10k_reset_hw(hw);
3119 if (diag != FM10K_SUCCESS) {
3120 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
3124 /* Setup mailbox service */
3125 diag = fm10k_setup_mbx_service(hw);
3126 if (diag != FM10K_SUCCESS) {
3127 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
3131 /*PF/VF has different interrupt handling mechanism */
3132 if (hw->mac.type == fm10k_mac_pf) {
3133 /* register callback func to eal lib */
3134 rte_intr_callback_register(intr_handle,
3135 fm10k_dev_interrupt_handler_pf, (void *)dev);
3137 /* enable MISC interrupt */
3138 fm10k_dev_enable_intr_pf(dev);
3140 rte_intr_callback_register(intr_handle,
3141 fm10k_dev_interrupt_handler_vf, (void *)dev);
3143 fm10k_dev_enable_intr_vf(dev);
3146 /* Enable intr after callback registered */
3147 rte_intr_enable(intr_handle);
3149 hw->mac.ops.update_int_moderator(hw);
3151 /* Make sure Switch Manager is ready before going forward. */
3152 if (hw->mac.type == fm10k_mac_pf) {
3153 int switch_ready = 0;
3155 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3157 hw->mac.ops.get_host_state(hw, &switch_ready);
3158 fm10k_mbx_unlock(hw);
3161 /* Delay some time to acquire async LPORT_MAP info. */
3162 rte_delay_us(WAIT_SWITCH_MSG_US);
3165 if (switch_ready == 0) {
3166 PMD_INIT_LOG(ERR, "switch is not ready");
3172 * Below function will trigger operations on mailbox, acquire lock to
3173 * avoid race condition from interrupt handler. Operations on mailbox
3174 * FIFO will trigger interrupt to PF/SM, in which interrupt handler
3175 * will handle and generate an interrupt to our side. Then, FIFO in
3176 * mailbox will be touched.
3179 /* Enable port first */
3180 hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
3183 /* Set unicast mode by default. App can change to other mode in other
3186 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
3187 FM10K_XCAST_MODE_NONE);
3189 fm10k_mbx_unlock(hw);
3191 /* Make sure default VID is ready before going forward. */
3192 if (hw->mac.type == fm10k_mac_pf) {
3193 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
3194 if (hw->mac.default_vid)
3196 /* Delay some time to acquire async port VLAN info. */
3197 rte_delay_us(WAIT_SWITCH_MSG_US);
3200 if (!hw->mac.default_vid) {
3201 PMD_INIT_LOG(ERR, "default VID is not ready");
3206 /* Add default mac address */
3207 fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3208 MAIN_VSI_POOL_NUMBER);
3214 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3216 struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3217 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(dev);
3218 struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3219 PMD_INIT_FUNC_TRACE();
3221 /* only uninitialize in the primary process */
3222 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3225 /* safe to close dev here */
3226 fm10k_dev_close(dev);
3228 dev->dev_ops = NULL;
3229 dev->rx_pkt_burst = NULL;
3230 dev->tx_pkt_burst = NULL;
3232 /* disable uio/vfio intr */
3233 rte_intr_disable(intr_handle);
3235 /*PF/VF has different interrupt handling mechanism */
3236 if (hw->mac.type == fm10k_mac_pf) {
3237 /* disable interrupt */
3238 fm10k_dev_disable_intr_pf(dev);
3240 /* unregister callback func to eal lib */
3241 rte_intr_callback_unregister(intr_handle,
3242 fm10k_dev_interrupt_handler_pf, (void *)dev);
3244 /* disable interrupt */
3245 fm10k_dev_disable_intr_vf(dev);
3247 rte_intr_callback_unregister(intr_handle,
3248 fm10k_dev_interrupt_handler_vf, (void *)dev);
3251 /* free mac memory */
3252 if (dev->data->mac_addrs) {
3253 rte_free(dev->data->mac_addrs);
3254 dev->data->mac_addrs = NULL;
3257 memset(hw, 0, sizeof(*hw));
3262 static int eth_fm10k_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3263 struct rte_pci_device *pci_dev)
3265 return rte_eth_dev_pci_generic_probe(pci_dev,
3266 sizeof(struct fm10k_adapter), eth_fm10k_dev_init);
3269 static int eth_fm10k_pci_remove(struct rte_pci_device *pci_dev)
3271 return rte_eth_dev_pci_generic_remove(pci_dev, eth_fm10k_dev_uninit);
3275 * The set of PCI devices this driver supports. This driver will enable both PF
3276 * and SRIOV-VF devices.
3278 static const struct rte_pci_id pci_id_fm10k_map[] = {
3279 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3280 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3281 { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3282 { .vendor_id = 0, /* sentinel */ },
3285 static struct rte_pci_driver rte_pmd_fm10k = {
3286 .id_table = pci_id_fm10k_map,
3287 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3288 RTE_PCI_DRV_IOVA_AS_VA,
3289 .probe = eth_fm10k_pci_probe,
3290 .remove = eth_fm10k_pci_remove,
3293 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k);
3294 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3295 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio-pci");
3297 RTE_INIT(fm10k_init_log)
3299 fm10k_logtype_init = rte_log_register("pmd.net.fm10k.init");
3300 if (fm10k_logtype_init >= 0)
3301 rte_log_set_level(fm10k_logtype_init, RTE_LOG_NOTICE);
3302 fm10k_logtype_driver = rte_log_register("pmd.net.fm10k.driver");
3303 if (fm10k_logtype_driver >= 0)
3304 rte_log_set_level(fm10k_logtype_driver, RTE_LOG_NOTICE);