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36 #include <rte_ethdev.h>
37 #include <rte_common.h>
39 #include "base/fm10k_type.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq);
50 /* Handling the offload flags (olflags) field takes computation
51 * time when receiving packets. Therefore we provide a flag to disable
52 * the processing of the olflags field when they are not needed. This
53 * gives improved performance, at the cost of losing the offload info
54 * in the received packet
56 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
58 /* Vlan present flag shift */
61 #define L3TYPE_SHIFT (4)
63 #define L4TYPE_SHIFT (7)
66 fm10k_desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
68 __m128i ptype0, ptype1, vtag0, vtag1;
74 const __m128i pkttype_msk = _mm_set_epi16(
75 0x0000, 0x0000, 0x0000, 0x0000,
76 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT,
77 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);
79 /* mask everything except rss type */
80 const __m128i rsstype_msk = _mm_set_epi16(
81 0x0000, 0x0000, 0x0000, 0x0000,
82 0x000F, 0x000F, 0x000F, 0x000F);
84 /* map rss type to rss hash flag */
85 const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
86 0, 0, 0, PKT_RX_RSS_HASH,
87 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
88 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
90 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
91 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
92 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
93 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
95 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
96 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
97 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
99 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
100 vtag1 = _mm_srli_epi16(vtag1, VP_SHIFT);
101 vtag1 = _mm_and_si128(vtag1, pkttype_msk);
103 vtag1 = _mm_or_si128(ptype0, vtag1);
104 vol.dword = _mm_cvtsi128_si64(vtag1);
106 rx_pkts[0]->ol_flags = vol.e[0];
107 rx_pkts[1]->ol_flags = vol.e[1];
108 rx_pkts[2]->ol_flags = vol.e[2];
109 rx_pkts[3]->ol_flags = vol.e[3];
113 fm10k_desc_to_pktype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
115 __m128i l3l4type0, l3l4type1, l3type, l4type;
121 /* L3 pkt type mask Bit4 to Bit6 */
122 const __m128i l3type_msk = _mm_set_epi16(
123 0x0000, 0x0000, 0x0000, 0x0000,
124 0x0070, 0x0070, 0x0070, 0x0070);
126 /* L4 pkt type mask Bit7 to Bit9 */
127 const __m128i l4type_msk = _mm_set_epi16(
128 0x0000, 0x0000, 0x0000, 0x0000,
129 0x0380, 0x0380, 0x0380, 0x0380);
131 /* convert RRC l3 type to mbuf format */
132 const __m128i l3type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
133 0, 0, 0, RTE_PTYPE_L3_IPV6_EXT,
134 RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV4_EXT,
135 RTE_PTYPE_L3_IPV4, 0);
137 /* Convert RRC l4 type to mbuf format l4type_flags shift-left 8 bits
138 * to fill into8 bits length.
140 const __m128i l4type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
141 RTE_PTYPE_TUNNEL_GENEVE >> 8,
142 RTE_PTYPE_TUNNEL_NVGRE >> 8,
143 RTE_PTYPE_TUNNEL_VXLAN >> 8,
144 RTE_PTYPE_TUNNEL_GRE >> 8,
145 RTE_PTYPE_L4_UDP >> 8,
146 RTE_PTYPE_L4_TCP >> 8,
149 l3l4type0 = _mm_unpacklo_epi16(descs[0], descs[1]);
150 l3l4type1 = _mm_unpacklo_epi16(descs[2], descs[3]);
151 l3l4type0 = _mm_unpacklo_epi32(l3l4type0, l3l4type1);
153 l3type = _mm_and_si128(l3l4type0, l3type_msk);
154 l4type = _mm_and_si128(l3l4type0, l4type_msk);
156 l3type = _mm_srli_epi16(l3type, L3TYPE_SHIFT);
157 l4type = _mm_srli_epi16(l4type, L4TYPE_SHIFT);
159 l3type = _mm_shuffle_epi8(l3type_flags, l3type);
160 /* l4type_flags shift-left for 8 bits, need shift-right back */
161 l4type = _mm_shuffle_epi8(l4type_flags, l4type);
163 l4type = _mm_slli_epi16(l4type, 8);
164 l3l4type0 = _mm_or_si128(l3type, l4type);
165 vol.dword = _mm_cvtsi128_si64(l3l4type0);
167 rx_pkts[0]->packet_type = vol.e[0];
168 rx_pkts[1]->packet_type = vol.e[1];
169 rx_pkts[2]->packet_type = vol.e[2];
170 rx_pkts[3]->packet_type = vol.e[3];
173 #define fm10k_desc_to_olflags_v(desc, rx_pkts) do {} while (0)
174 #define fm10k_desc_to_pktype_v(desc, rx_pkts) do {} while (0)
177 int __attribute__((cold))
178 fm10k_rx_vec_condition_check(struct rte_eth_dev *dev)
180 #ifndef RTE_LIBRTE_IEEE1588
181 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
182 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
184 #ifndef RTE_FM10K_RX_OLFLAGS_ENABLE
185 /* whithout rx ol_flags, no VP flag report */
186 if (rxmode->hw_vlan_extend != 0)
190 /* no fdir support */
191 if (fconf->mode != RTE_FDIR_MODE_NONE)
194 /* - no csum error report support
195 * - no header split support
197 if (rxmode->hw_ip_checksum == 1 ||
198 rxmode->header_split == 1)
208 int __attribute__((cold))
209 fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)
212 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
215 /* data_off will be ajusted after new mbuf allocated for 512-byte
218 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
219 mb_def.port = rxq->port_id;
220 rte_mbuf_refcnt_set(&mb_def, 1);
222 /* prevent compiler reordering: rearm_data covers previous fields */
223 rte_compiler_barrier();
224 p = (uintptr_t)&mb_def.rearm_data;
225 rxq->mbuf_initializer = *(uint64_t *)p;
230 fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)
234 volatile union fm10k_rx_desc *rxdp;
235 struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];
236 struct rte_mbuf *mb0, *mb1;
237 __m128i head_off = _mm_set_epi64x(
238 RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,
239 RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);
240 __m128i dma_addr0, dma_addr1;
241 /* Rx buffer need to be aligned with 512 byte */
242 const __m128i hba_msk = _mm_set_epi64x(0,
243 UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);
245 rxdp = rxq->hw_ring + rxq->rxrearm_start;
247 /* Pull 'n' more MBUFs into the software ring */
248 if (rte_mempool_get_bulk(rxq->mp,
250 RTE_FM10K_RXQ_REARM_THRESH) < 0) {
251 dma_addr0 = _mm_setzero_si128();
252 /* Clean up all the HW/SW ring content */
253 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) {
254 mb_alloc[i] = &rxq->fake_mbuf;
255 _mm_store_si128((__m128i *)&rxdp[i].q,
259 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
260 RTE_FM10K_RXQ_REARM_THRESH;
264 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
265 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {
266 __m128i vaddr0, vaddr1;
272 /* Flush mbuf with pkt template.
273 * Data to be rearmed is 6 bytes long.
274 * Though, RX will overwrite ol_flags that are coming next
275 * anyway. So overwrite whole 8 bytes with one load:
276 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
278 p0 = (uintptr_t)&mb0->rearm_data;
279 *(uint64_t *)p0 = rxq->mbuf_initializer;
280 p1 = (uintptr_t)&mb1->rearm_data;
281 *(uint64_t *)p1 = rxq->mbuf_initializer;
283 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
284 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
285 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
287 /* convert pa to dma_addr hdr/data */
288 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
289 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
291 /* add headroom to pa values */
292 dma_addr0 = _mm_add_epi64(dma_addr0, head_off);
293 dma_addr1 = _mm_add_epi64(dma_addr1, head_off);
295 /* Do 512 byte alignment to satisfy HW requirement, in the
296 * meanwhile, set Header Buffer Address to zero.
298 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
299 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
301 /* flush desc with pa dma_addr */
302 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);
303 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);
305 /* enforce 512B alignment on default Rx virtual addresses */
306 mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr
307 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
308 - (char *)mb0->buf_addr);
309 mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr
310 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
311 - (char *)mb1->buf_addr);
314 rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;
315 if (rxq->rxrearm_start >= rxq->nb_desc)
316 rxq->rxrearm_start = 0;
318 rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;
320 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
321 (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));
323 /* Update the tail pointer on the NIC */
324 FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);
327 void __attribute__((cold))
328 fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq)
330 const unsigned mask = rxq->nb_desc - 1;
333 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_desc)
336 /* free all mbufs that are valid in the ring */
337 for (i = rxq->next_dd; i != rxq->rxrearm_start; i = (i + 1) & mask)
338 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
339 rxq->rxrearm_nb = rxq->nb_desc;
341 /* set all entries to NULL */
342 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_desc);
345 static inline uint16_t
346 fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
347 uint16_t nb_pkts, uint8_t *split_packet)
349 volatile union fm10k_rx_desc *rxdp;
350 struct rte_mbuf **mbufp;
351 uint16_t nb_pkts_recd;
353 struct fm10k_rx_queue *rxq = rx_queue;
356 __m128i dd_check, eop_check;
359 next_dd = rxq->next_dd;
361 /* Just the act of getting into the function from the application is
362 * going to cost about 7 cycles
364 rxdp = rxq->hw_ring + next_dd;
366 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
368 /* See if we need to rearm the RX queue - gives the prefetch a bit
371 if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH)
372 fm10k_rxq_rearm(rxq);
374 /* Before we start moving massive data around, check to see if
375 * there is actually a packet available
377 if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD))
380 /* Vecotr RX will process 4 packets at a time, strip the unaligned
381 * tails in case it's not multiple of 4.
383 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP);
385 /* 4 packets DD mask */
386 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
388 /* 4 packets EOP mask */
389 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
391 /* mask to shuffle from desc. to mbuf */
392 shuf_msk = _mm_set_epi8(
393 7, 6, 5, 4, /* octet 4~7, 32bits rss */
394 15, 14, /* octet 14~15, low 16 bits vlan_macip */
395 13, 12, /* octet 12~13, 16 bits data_len */
396 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
397 13, 12, /* octet 12~13, low 16 bits pkt_len */
398 0xFF, 0xFF, /* skip high 16 bits pkt_type */
399 0xFF, 0xFF /* Skip pkt_type field in shuffle operation */
402 /* Cache is empty -> need to scan the buffer rings, but first move
403 * the next 'n' mbufs into the cache
405 mbufp = &rxq->sw_ring[next_dd];
407 /* A. load 4 packet in one loop
408 * [A*. mask out 4 unused dirty field in desc]
409 * B. copy 4 mbuf point from swring to rx_pkts
410 * C. calc the number of DD bits among the 4 packets
411 * [C*. extract the end-of-packet bit, if requested]
412 * D. fill info. from desc to mbuf
414 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
415 pos += RTE_FM10K_DESCS_PER_LOOP,
416 rxdp += RTE_FM10K_DESCS_PER_LOOP) {
417 __m128i descs0[RTE_FM10K_DESCS_PER_LOOP];
418 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
419 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
420 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
422 /* B.1 load 1 mbuf point */
423 mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]);
425 /* Read desc statuses backwards to avoid race condition */
426 /* A.1 load 4 pkts desc */
427 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
429 /* B.2 copy 2 mbuf point into rx_pkts */
430 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
432 /* B.1 load 1 mbuf point */
433 mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]);
435 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
436 /* B.1 load 2 mbuf point */
437 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
438 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
440 /* B.2 copy 2 mbuf point into rx_pkts */
441 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
443 /* avoid compiler reorder optimization */
444 rte_compiler_barrier();
447 rte_prefetch0(&rx_pkts[pos]->cacheline1);
448 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
449 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
450 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
453 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
454 pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk);
455 pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk);
457 /* C.1 4=>2 filter staterr info only */
458 sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]);
459 /* C.1 4=>2 filter staterr info only */
460 sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]);
462 /* set ol_flags with vlan packet type */
463 fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]);
465 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
466 pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk);
467 pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk);
469 /* C.2 get 4 pkts staterr value */
470 zero = _mm_xor_si128(dd_check, dd_check);
471 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
473 /* D.3 copy final 3,4 data to rx_pkts */
474 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
476 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
479 /* C* extract and record EOP bit */
481 __m128i eop_shuf_mask = _mm_set_epi8(
482 0xFF, 0xFF, 0xFF, 0xFF,
483 0xFF, 0xFF, 0xFF, 0xFF,
484 0xFF, 0xFF, 0xFF, 0xFF,
485 0x04, 0x0C, 0x00, 0x08
488 /* and with mask to extract bits, flipping 1-0 */
489 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
490 /* the staterr values are not in order, as the count
491 * count of dd bits doesn't care. However, for end of
492 * packet tracking, we do care, so shuffle. This also
493 * compresses the 32-bit values to 8-bit
495 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
496 /* store the resulting 32-bit value */
497 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
498 split_packet += RTE_FM10K_DESCS_PER_LOOP;
500 /* zero-out next pointers */
501 rx_pkts[pos]->next = NULL;
502 rx_pkts[pos + 1]->next = NULL;
503 rx_pkts[pos + 2]->next = NULL;
504 rx_pkts[pos + 3]->next = NULL;
507 /* C.3 calc available number of desc */
508 staterr = _mm_and_si128(staterr, dd_check);
509 staterr = _mm_packs_epi32(staterr, zero);
511 /* D.3 copy final 1,2 data to rx_pkts */
512 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
514 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
517 fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]);
519 /* C.4 calc avaialbe number of desc */
520 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
522 if (likely(var != RTE_FM10K_DESCS_PER_LOOP))
526 /* Update our internal tail pointer */
527 rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd);
528 rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1));
529 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
534 /* vPMD receive routine
537 * - don't support ol_flags for rss and csum err
540 fm10k_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
543 return fm10k_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
546 static inline uint16_t
547 fm10k_reassemble_packets(struct fm10k_rx_queue *rxq,
548 struct rte_mbuf **rx_bufs,
549 uint16_t nb_bufs, uint8_t *split_flags)
551 struct rte_mbuf *pkts[RTE_FM10K_MAX_RX_BURST]; /*finished pkts*/
552 struct rte_mbuf *start = rxq->pkt_first_seg;
553 struct rte_mbuf *end = rxq->pkt_last_seg;
554 unsigned pkt_idx, buf_idx;
556 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
558 /* processing a split packet */
559 end->next = rx_bufs[buf_idx];
561 start->pkt_len += rx_bufs[buf_idx]->data_len;
564 if (!split_flags[buf_idx]) {
565 /* it's the last packet of the set */
566 start->hash = end->hash;
567 start->ol_flags = end->ol_flags;
568 pkts[pkt_idx++] = start;
572 /* not processing a split packet */
573 if (!split_flags[buf_idx]) {
574 /* not a split packet, save and skip */
575 pkts[pkt_idx++] = rx_bufs[buf_idx];
578 end = start = rx_bufs[buf_idx];
582 /* save the partial packet for next time */
583 rxq->pkt_first_seg = start;
584 rxq->pkt_last_seg = end;
585 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
590 * vPMD receive routine that reassembles scattered packets
593 * - don't support ol_flags for rss and csum err
594 * - nb_pkts > RTE_FM10K_MAX_RX_BURST, only scan RTE_FM10K_MAX_RX_BURST
598 fm10k_recv_scattered_pkts_vec(void *rx_queue,
599 struct rte_mbuf **rx_pkts,
602 struct fm10k_rx_queue *rxq = rx_queue;
603 uint8_t split_flags[RTE_FM10K_MAX_RX_BURST] = {0};
606 /* Split_flags only can support max of RTE_FM10K_MAX_RX_BURST */
607 nb_pkts = RTE_MIN(nb_pkts, RTE_FM10K_MAX_RX_BURST);
608 /* get some new buffers */
609 uint16_t nb_bufs = fm10k_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
614 /* happy day case, full burst + no packets to be joined */
615 const uint64_t *split_fl64 = (uint64_t *)split_flags;
617 if (rxq->pkt_first_seg == NULL &&
618 split_fl64[0] == 0 && split_fl64[1] == 0 &&
619 split_fl64[2] == 0 && split_fl64[3] == 0)
622 /* reassemble any packets that need reassembly*/
623 if (rxq->pkt_first_seg == NULL) {
624 /* find the first split flag, and only reassemble then*/
625 while (i < nb_bufs && !split_flags[i])
630 return i + fm10k_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
634 static const struct fm10k_txq_ops vec_txq_ops = {
635 .reset = fm10k_reset_tx_queue,
638 void __attribute__((cold))
639 fm10k_txq_vec_setup(struct fm10k_tx_queue *txq)
641 txq->ops = &vec_txq_ops;
644 int __attribute__((cold))
645 fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq)
647 /* Vector TX can't offload any features yet */
648 if ((txq->txq_flags & FM10K_SIMPLE_TX_FLAG) != FM10K_SIMPLE_TX_FLAG)
655 vtx1(volatile struct fm10k_tx_desc *txdp,
656 struct rte_mbuf *pkt, uint64_t flags)
658 __m128i descriptor = _mm_set_epi64x(flags << 56 |
659 pkt->vlan_tci << 16 | pkt->data_len,
661 _mm_store_si128((__m128i *)txdp, descriptor);
665 vtx(volatile struct fm10k_tx_desc *txdp,
666 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
670 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
671 vtx1(txdp, *pkt, flags);
674 static inline int __attribute__((always_inline))
675 fm10k_tx_free_bufs(struct fm10k_tx_queue *txq)
677 struct rte_mbuf **txep;
682 struct rte_mbuf *m, *free[RTE_FM10K_TX_MAX_FREE_BUF_SZ];
684 /* check DD bit on threshold descriptor */
685 flags = txq->hw_ring[txq->next_dd].flags;
686 if (!(flags & FM10K_TXD_FLAG_DONE))
691 /* First buffer to free from S/W ring is at index
692 * next_dd - (rs_thresh-1)
694 txep = &txq->sw_ring[txq->next_dd - (n - 1)];
695 m = __rte_pktmbuf_prefree_seg(txep[0]);
696 if (likely(m != NULL)) {
699 for (i = 1; i < n; i++) {
700 m = __rte_pktmbuf_prefree_seg(txep[i]);
701 if (likely(m != NULL)) {
702 if (likely(m->pool == free[0]->pool))
705 rte_mempool_put_bulk(free[0]->pool,
706 (void *)free, nb_free);
712 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
714 for (i = 1; i < n; i++) {
715 m = __rte_pktmbuf_prefree_seg(txep[i]);
717 rte_mempool_put(m->pool, m);
721 /* buffers were freed, update counters */
722 txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
723 txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
724 if (txq->next_dd >= txq->nb_desc)
725 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
727 return txq->rs_thresh;
730 static inline void __attribute__((always_inline))
731 tx_backlog_entry(struct rte_mbuf **txep,
732 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
736 for (i = 0; i < (int)nb_pkts; ++i)
737 txep[i] = tx_pkts[i];
741 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
744 struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
745 volatile struct fm10k_tx_desc *txdp;
746 struct rte_mbuf **txep;
747 uint16_t n, nb_commit, tx_id;
748 uint64_t flags = FM10K_TXD_FLAG_LAST;
749 uint64_t rs = FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_LAST;
752 /* cross rx_thresh boundary is not allowed */
753 nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
755 if (txq->nb_free < txq->free_thresh)
756 fm10k_tx_free_bufs(txq);
758 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
759 if (unlikely(nb_pkts == 0))
762 tx_id = txq->next_free;
763 txdp = &txq->hw_ring[tx_id];
764 txep = &txq->sw_ring[tx_id];
766 txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
768 n = (uint16_t)(txq->nb_desc - tx_id);
769 if (nb_commit >= n) {
770 tx_backlog_entry(txep, tx_pkts, n);
772 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
773 vtx1(txdp, *tx_pkts, flags);
775 vtx1(txdp, *tx_pkts++, rs);
777 nb_commit = (uint16_t)(nb_commit - n);
780 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
782 /* avoid reach the end of ring */
783 txdp = &(txq->hw_ring[tx_id]);
784 txep = &txq->sw_ring[tx_id];
787 tx_backlog_entry(txep, tx_pkts, nb_commit);
789 vtx(txdp, tx_pkts, nb_commit, flags);
791 tx_id = (uint16_t)(tx_id + nb_commit);
792 if (tx_id > txq->next_rs) {
793 txq->hw_ring[txq->next_rs].flags |= FM10K_TXD_FLAG_RS;
794 txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh);
797 txq->next_free = tx_id;
799 FM10K_PCI_REG_WRITE(txq->tail_ptr, txq->next_free);
804 static void __attribute__((cold))
805 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
807 static const struct fm10k_tx_desc zeroed_desc = {0};
808 struct rte_mbuf **txe = txq->sw_ring;
811 /* Zero out HW ring memory */
812 for (i = 0; i < txq->nb_desc; i++)
813 txq->hw_ring[i] = zeroed_desc;
815 /* Initialize SW ring entries */
816 for (i = 0; i < txq->nb_desc; i++)
819 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
820 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
824 /* Always allow 1 descriptor to be un-allocated to avoid
825 * a H/W race condition
827 txq->nb_free = (uint16_t)(txq->nb_desc - 1);
828 FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);