net/i40e: fix Rx packet statistics
[dpdk.git] / drivers / net / fm10k / fm10k_rxtx_vec.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2013-2015 Intel Corporation
3  */
4
5 #include <inttypes.h>
6
7 #include <ethdev_driver.h>
8 #include <rte_common.h>
9 #include "fm10k.h"
10 #include "base/fm10k_type.h"
11
12 #include <tmmintrin.h>
13
14 #ifndef __INTEL_COMPILER
15 #pragma GCC diagnostic ignored "-Wcast-qual"
16 #endif
17
18 static void
19 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq);
20
21 /* Handling the offload flags (olflags) field takes computation
22  * time when receiving packets. Therefore we provide a flag to disable
23  * the processing of the olflags field when they are not needed. This
24  * gives improved performance, at the cost of losing the offload info
25  * in the received packet
26  */
27 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
28
29 /* Vlan present flag shift */
30 #define VP_SHIFT     (2)
31 /* L3 type shift */
32 #define L3TYPE_SHIFT     (4)
33 /* L4 type shift */
34 #define L4TYPE_SHIFT     (7)
35 /* HBO flag shift */
36 #define HBOFLAG_SHIFT     (10)
37 /* RXE flag shift */
38 #define RXEFLAG_SHIFT     (13)
39 /* IPE/L4E flag shift */
40 #define L3L4EFLAG_SHIFT     (14)
41 /* shift PKT_RX_L4_CKSUM_GOOD into one byte by 1 bit */
42 #define CKSUM_SHIFT     (1)
43
44 static inline void
45 fm10k_desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
46 {
47         __m128i ptype0, ptype1, vtag0, vtag1, eflag0, eflag1, cksumflag;
48         union {
49                 uint16_t e[4];
50                 uint64_t dword;
51         } vol;
52
53         const __m128i pkttype_msk = _mm_set_epi16(
54                         0x0000, 0x0000, 0x0000, 0x0000,
55                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
56                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
57                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
58                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
59
60         /* mask everything except rss type */
61         const __m128i rsstype_msk = _mm_set_epi16(
62                         0x0000, 0x0000, 0x0000, 0x0000,
63                         0x000F, 0x000F, 0x000F, 0x000F);
64
65         /* mask for HBO and RXE flag flags */
66         const __m128i rxe_msk = _mm_set_epi16(
67                         0x0000, 0x0000, 0x0000, 0x0000,
68                         0x0001, 0x0001, 0x0001, 0x0001);
69
70         /* mask the lower byte of ol_flags */
71         const __m128i ol_flags_msk = _mm_set_epi16(
72                         0x0000, 0x0000, 0x0000, 0x0000,
73                         0x00FF, 0x00FF, 0x00FF, 0x00FF);
74
75         const __m128i l3l4cksum_flag = _mm_set_epi8(0, 0, 0, 0,
76                         0, 0, 0, 0,
77                         0, 0, 0, 0,
78                         (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
79                         (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT,
80                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
81                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT);
82
83         const __m128i rxe_flag = _mm_set_epi8(0, 0, 0, 0,
84                         0, 0, 0, 0,
85                         0, 0, 0, 0,
86                         0, 0, 0, 0);
87
88         /* map rss type to rss hash flag */
89         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
90                         0, 0, 0, PKT_RX_RSS_HASH,
91                         PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
92                         PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
93
94         /* Calculate RSS_hash and Vlan fields */
95         ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
96         ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
97         vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
98         vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
99
100         ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
101         ptype0 = _mm_and_si128(ptype0, rsstype_msk);
102         ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
103
104         vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
105         eflag0 = vtag1;
106         cksumflag = vtag1;
107         vtag1 = _mm_srli_epi16(vtag1, VP_SHIFT);
108         vtag1 = _mm_and_si128(vtag1, pkttype_msk);
109
110         vtag1 = _mm_or_si128(ptype0, vtag1);
111
112         /* Process err flags, simply set RECIP_ERR bit if HBO/IXE is set */
113         eflag1 = _mm_srli_epi16(eflag0, RXEFLAG_SHIFT);
114         eflag0 = _mm_srli_epi16(eflag0, HBOFLAG_SHIFT);
115         eflag0 = _mm_or_si128(eflag0, eflag1);
116         eflag0 = _mm_and_si128(eflag0, rxe_msk);
117         eflag0 = _mm_shuffle_epi8(rxe_flag, eflag0);
118
119         vtag1 = _mm_or_si128(eflag0, vtag1);
120
121         /* Process L4/L3 checksum error flags */
122         cksumflag = _mm_srli_epi16(cksumflag, L3L4EFLAG_SHIFT);
123         cksumflag = _mm_shuffle_epi8(l3l4cksum_flag, cksumflag);
124
125         /* clean the higher byte and shift back the flag bits */
126         cksumflag = _mm_and_si128(cksumflag, ol_flags_msk);
127         cksumflag = _mm_slli_epi16(cksumflag, CKSUM_SHIFT);
128         vtag1 = _mm_or_si128(cksumflag, vtag1);
129
130         vol.dword = _mm_cvtsi128_si64(vtag1);
131
132         rx_pkts[0]->ol_flags = vol.e[0];
133         rx_pkts[1]->ol_flags = vol.e[1];
134         rx_pkts[2]->ol_flags = vol.e[2];
135         rx_pkts[3]->ol_flags = vol.e[3];
136 }
137
138 /* @note: When this function is changed, make corresponding change to
139  * fm10k_dev_supported_ptypes_get().
140  */
141 static inline void
142 fm10k_desc_to_pktype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
143 {
144         __m128i l3l4type0, l3l4type1, l3type, l4type;
145         union {
146                 uint16_t e[4];
147                 uint64_t dword;
148         } vol;
149
150         /* L3 pkt type mask  Bit4 to Bit6 */
151         const __m128i l3type_msk = _mm_set_epi16(
152                         0x0000, 0x0000, 0x0000, 0x0000,
153                         0x0070, 0x0070, 0x0070, 0x0070);
154
155         /* L4 pkt type mask  Bit7 to Bit9 */
156         const __m128i l4type_msk = _mm_set_epi16(
157                         0x0000, 0x0000, 0x0000, 0x0000,
158                         0x0380, 0x0380, 0x0380, 0x0380);
159
160         /* convert RRC l3 type to mbuf format */
161         const __m128i l3type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
162                         0, 0, 0, RTE_PTYPE_L3_IPV6_EXT,
163                         RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV4_EXT,
164                         RTE_PTYPE_L3_IPV4, 0);
165
166         /* Convert RRC l4 type to mbuf format l4type_flags shift-left 8 bits
167          * to fill into8 bits length.
168          */
169         const __m128i l4type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
170                         RTE_PTYPE_TUNNEL_GENEVE >> 8,
171                         RTE_PTYPE_TUNNEL_NVGRE >> 8,
172                         RTE_PTYPE_TUNNEL_VXLAN >> 8,
173                         RTE_PTYPE_TUNNEL_GRE >> 8,
174                         RTE_PTYPE_L4_UDP >> 8,
175                         RTE_PTYPE_L4_TCP >> 8,
176                         0);
177
178         l3l4type0 = _mm_unpacklo_epi16(descs[0], descs[1]);
179         l3l4type1 = _mm_unpacklo_epi16(descs[2], descs[3]);
180         l3l4type0 = _mm_unpacklo_epi32(l3l4type0, l3l4type1);
181
182         l3type = _mm_and_si128(l3l4type0, l3type_msk);
183         l4type = _mm_and_si128(l3l4type0, l4type_msk);
184
185         l3type = _mm_srli_epi16(l3type, L3TYPE_SHIFT);
186         l4type = _mm_srli_epi16(l4type, L4TYPE_SHIFT);
187
188         l3type = _mm_shuffle_epi8(l3type_flags, l3type);
189         /* l4type_flags shift-left for 8 bits, need shift-right back */
190         l4type = _mm_shuffle_epi8(l4type_flags, l4type);
191
192         l4type = _mm_slli_epi16(l4type, 8);
193         l3l4type0 = _mm_or_si128(l3type, l4type);
194         vol.dword = _mm_cvtsi128_si64(l3l4type0);
195
196         rx_pkts[0]->packet_type = vol.e[0];
197         rx_pkts[1]->packet_type = vol.e[1];
198         rx_pkts[2]->packet_type = vol.e[2];
199         rx_pkts[3]->packet_type = vol.e[3];
200 }
201 #else
202 #define fm10k_desc_to_olflags_v(desc, rx_pkts) do {} while (0)
203 #define fm10k_desc_to_pktype_v(desc, rx_pkts) do {} while (0)
204 #endif
205
206 int __rte_cold
207 fm10k_rx_vec_condition_check(struct rte_eth_dev *dev)
208 {
209 #ifndef RTE_LIBRTE_IEEE1588
210         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
211         struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
212
213 #ifndef RTE_FM10K_RX_OLFLAGS_ENABLE
214         /* whithout rx ol_flags, no VP flag report */
215         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
216                 return -1;
217 #endif
218
219         /* no fdir support */
220         if (fconf->mode != RTE_FDIR_MODE_NONE)
221                 return -1;
222
223         /* no header split support */
224         if (rxmode->offloads & DEV_RX_OFFLOAD_HEADER_SPLIT)
225                 return -1;
226
227         return 0;
228 #else
229         RTE_SET_USED(dev);
230         return -1;
231 #endif
232 }
233
234 int __rte_cold
235 fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)
236 {
237         uintptr_t p;
238         struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
239
240         mb_def.nb_segs = 1;
241         /* data_off will be ajusted after new mbuf allocated for 512-byte
242          * alignment.
243          */
244         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
245         mb_def.port = rxq->port_id;
246         rte_mbuf_refcnt_set(&mb_def, 1);
247
248         /* prevent compiler reordering: rearm_data covers previous fields */
249         rte_compiler_barrier();
250         p = (uintptr_t)&mb_def.rearm_data;
251         rxq->mbuf_initializer = *(uint64_t *)p;
252         return 0;
253 }
254
255 static inline void
256 fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)
257 {
258         int i;
259         uint16_t rx_id;
260         volatile union fm10k_rx_desc *rxdp;
261         struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];
262         struct rte_mbuf *mb0, *mb1;
263         __m128i head_off = _mm_set_epi64x(
264                         RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,
265                         RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);
266         __m128i dma_addr0, dma_addr1;
267         /* Rx buffer need to be aligned with 512 byte */
268         const __m128i hba_msk = _mm_set_epi64x(0,
269                                 UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);
270
271         rxdp = rxq->hw_ring + rxq->rxrearm_start;
272
273         /* Pull 'n' more MBUFs into the software ring */
274         if (rte_mempool_get_bulk(rxq->mp,
275                                  (void *)mb_alloc,
276                                  RTE_FM10K_RXQ_REARM_THRESH) < 0) {
277                 dma_addr0 = _mm_setzero_si128();
278                 /* Clean up all the HW/SW ring content */
279                 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) {
280                         mb_alloc[i] = &rxq->fake_mbuf;
281                         _mm_store_si128((__m128i *)&rxdp[i].q,
282                                                 dma_addr0);
283                 }
284
285                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
286                         RTE_FM10K_RXQ_REARM_THRESH;
287                 return;
288         }
289
290         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
291         for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {
292                 __m128i vaddr0, vaddr1;
293                 uintptr_t p0, p1;
294
295                 mb0 = mb_alloc[0];
296                 mb1 = mb_alloc[1];
297
298                 /* Flush mbuf with pkt template.
299                  * Data to be rearmed is 6 bytes long.
300                  */
301                 p0 = (uintptr_t)&mb0->rearm_data;
302                 *(uint64_t *)p0 = rxq->mbuf_initializer;
303                 p1 = (uintptr_t)&mb1->rearm_data;
304                 *(uint64_t *)p1 = rxq->mbuf_initializer;
305
306                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
307                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
308                                 offsetof(struct rte_mbuf, buf_addr) + 8);
309                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
310                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
311
312                 /* convert pa to dma_addr hdr/data */
313                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
314                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
315
316                 /* add headroom to pa values */
317                 dma_addr0 = _mm_add_epi64(dma_addr0, head_off);
318                 dma_addr1 = _mm_add_epi64(dma_addr1, head_off);
319
320                 /* Do 512 byte alignment to satisfy HW requirement, in the
321                  * meanwhile, set Header Buffer Address to zero.
322                  */
323                 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
324                 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
325
326                 /* flush desc with pa dma_addr */
327                 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);
328                 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);
329
330                 /* enforce 512B alignment on default Rx virtual addresses */
331                 mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr
332                                 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
333                                 - (char *)mb0->buf_addr);
334                 mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr
335                                 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
336                                 - (char *)mb1->buf_addr);
337         }
338
339         rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;
340         if (rxq->rxrearm_start >= rxq->nb_desc)
341                 rxq->rxrearm_start = 0;
342
343         rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;
344
345         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
346                         (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));
347
348         /* Update the tail pointer on the NIC */
349         FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);
350 }
351
352 void __rte_cold
353 fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq)
354 {
355         const unsigned mask = rxq->nb_desc - 1;
356         unsigned i;
357
358         if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_desc)
359                 return;
360
361         /* free all mbufs that are valid in the ring */
362         if (rxq->rxrearm_nb == 0) {
363                 for (i = 0; i < rxq->nb_desc; i++)
364                         if (rxq->sw_ring[i] != NULL)
365                                 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
366         } else {
367                 for (i = rxq->next_dd; i != rxq->rxrearm_start;
368                                 i = (i + 1) & mask)
369                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
370         }
371         rxq->rxrearm_nb = rxq->nb_desc;
372
373         /* set all entries to NULL */
374         memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_desc);
375 }
376
377 static inline uint16_t
378 fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
379                 uint16_t nb_pkts, uint8_t *split_packet)
380 {
381         volatile union fm10k_rx_desc *rxdp;
382         struct rte_mbuf **mbufp;
383         uint16_t nb_pkts_recd;
384         int pos;
385         struct fm10k_rx_queue *rxq = rx_queue;
386         uint64_t var;
387         __m128i shuf_msk;
388         __m128i dd_check, eop_check;
389         uint16_t next_dd;
390
391         next_dd = rxq->next_dd;
392
393         /* Just the act of getting into the function from the application is
394          * going to cost about 7 cycles
395          */
396         rxdp = rxq->hw_ring + next_dd;
397
398         rte_prefetch0(rxdp);
399
400         /* See if we need to rearm the RX queue - gives the prefetch a bit
401          * of time to act
402          */
403         if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH)
404                 fm10k_rxq_rearm(rxq);
405
406         /* Before we start moving massive data around, check to see if
407          * there is actually a packet available
408          */
409         if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD))
410                 return 0;
411
412         /* Vecotr RX will process 4 packets at a time, strip the unaligned
413          * tails in case it's not multiple of 4.
414          */
415         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP);
416
417         /* 4 packets DD mask */
418         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
419
420         /* 4 packets EOP mask */
421         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
422
423         /* mask to shuffle from desc. to mbuf */
424         shuf_msk = _mm_set_epi8(
425                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
426                 15, 14,      /* octet 14~15, low 16 bits vlan_macip */
427                 13, 12,      /* octet 12~13, 16 bits data_len */
428                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
429                 13, 12,      /* octet 12~13, low 16 bits pkt_len */
430                 0xFF, 0xFF,  /* skip high 16 bits pkt_type */
431                 0xFF, 0xFF   /* Skip pkt_type field in shuffle operation */
432                 );
433         /*
434          * Compile-time verify the shuffle mask
435          * NOTE: some field positions already verified above, but duplicated
436          * here for completeness in case of future modifications.
437          */
438         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
439                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
440         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
441                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
442         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
443                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
444         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
445                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
446
447         /* Cache is empty -> need to scan the buffer rings, but first move
448          * the next 'n' mbufs into the cache
449          */
450         mbufp = &rxq->sw_ring[next_dd];
451
452         /* A. load 4 packet in one loop
453          * [A*. mask out 4 unused dirty field in desc]
454          * B. copy 4 mbuf point from swring to rx_pkts
455          * C. calc the number of DD bits among the 4 packets
456          * [C*. extract the end-of-packet bit, if requested]
457          * D. fill info. from desc to mbuf
458          */
459         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
460                         pos += RTE_FM10K_DESCS_PER_LOOP,
461                         rxdp += RTE_FM10K_DESCS_PER_LOOP) {
462                 __m128i descs0[RTE_FM10K_DESCS_PER_LOOP];
463                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
464                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
465                 __m128i mbp1;
466                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
467 #if defined(RTE_ARCH_X86_64)
468                 __m128i mbp2;
469 #endif
470
471                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
472                 mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]);
473
474                 /* Read desc statuses backwards to avoid race condition */
475                 /* A.1 load desc[3] */
476                 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
477                 rte_compiler_barrier();
478
479                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
480                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
481
482 #if defined(RTE_ARCH_X86_64)
483                 /* B.1 load 2 64 bit mbuf poitns */
484                 mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]);
485 #endif
486
487                 /* A.1 load desc[2-0] */
488                 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
489                 rte_compiler_barrier();
490                 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
491                 rte_compiler_barrier();
492                 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
493
494 #if defined(RTE_ARCH_X86_64)
495                 /* B.2 copy 2 mbuf point into rx_pkts  */
496                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
497 #endif
498
499                 /* avoid compiler reorder optimization */
500                 rte_compiler_barrier();
501
502                 if (split_packet) {
503                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
504                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
505                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
506                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
507                 }
508
509                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
510                 pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk);
511                 pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk);
512
513                 /* C.1 4=>2 filter staterr info only */
514                 sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]);
515                 /* C.1 4=>2 filter staterr info only */
516                 sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]);
517
518                 /* set ol_flags with vlan packet type */
519                 fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]);
520
521                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
522                 pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk);
523                 pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk);
524
525                 /* C.2 get 4 pkts staterr value  */
526                 zero = _mm_xor_si128(dd_check, dd_check);
527                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
528
529                 /* D.3 copy final 3,4 data to rx_pkts */
530                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
531                                 pkt_mb4);
532                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
533                                 pkt_mb3);
534
535                 /* C* extract and record EOP bit */
536                 if (split_packet) {
537                         __m128i eop_shuf_mask = _mm_set_epi8(
538                                         0xFF, 0xFF, 0xFF, 0xFF,
539                                         0xFF, 0xFF, 0xFF, 0xFF,
540                                         0xFF, 0xFF, 0xFF, 0xFF,
541                                         0x04, 0x0C, 0x00, 0x08
542                                         );
543
544                         /* and with mask to extract bits, flipping 1-0 */
545                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
546                         /* the staterr values are not in order, as the count
547                          * of dd bits doesn't care. However, for end of
548                          * packet tracking, we do care, so shuffle. This also
549                          * compresses the 32-bit values to 8-bit
550                          */
551                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
552                         /* store the resulting 32-bit value */
553                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
554                         split_packet += RTE_FM10K_DESCS_PER_LOOP;
555
556                         /* zero-out next pointers */
557                         rx_pkts[pos]->next = NULL;
558                         rx_pkts[pos + 1]->next = NULL;
559                         rx_pkts[pos + 2]->next = NULL;
560                         rx_pkts[pos + 3]->next = NULL;
561                 }
562
563                 /* C.3 calc available number of desc */
564                 staterr = _mm_and_si128(staterr, dd_check);
565                 staterr = _mm_packs_epi32(staterr, zero);
566
567                 /* D.3 copy final 1,2 data to rx_pkts */
568                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
569                                 pkt_mb2);
570                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
571                                 pkt_mb1);
572
573                 fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]);
574
575                 /* C.4 calc avaialbe number of desc */
576                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
577                 nb_pkts_recd += var;
578                 if (likely(var != RTE_FM10K_DESCS_PER_LOOP))
579                         break;
580         }
581
582         /* Update our internal tail pointer */
583         rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd);
584         rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1));
585         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
586
587         return nb_pkts_recd;
588 }
589
590 /* vPMD receive routine
591  *
592  * Notice:
593  * - don't support ol_flags for rss and csum err
594  */
595 uint16_t
596 fm10k_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
597                 uint16_t nb_pkts)
598 {
599         return fm10k_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
600 }
601
602 static inline uint16_t
603 fm10k_reassemble_packets(struct fm10k_rx_queue *rxq,
604                 struct rte_mbuf **rx_bufs,
605                 uint16_t nb_bufs, uint8_t *split_flags)
606 {
607         struct rte_mbuf *pkts[RTE_FM10K_MAX_RX_BURST]; /*finished pkts*/
608         struct rte_mbuf *start = rxq->pkt_first_seg;
609         struct rte_mbuf *end =  rxq->pkt_last_seg;
610         unsigned pkt_idx, buf_idx;
611
612         for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
613                 if (end != NULL) {
614                         /* processing a split packet */
615                         end->next = rx_bufs[buf_idx];
616                         start->nb_segs++;
617                         start->pkt_len += rx_bufs[buf_idx]->data_len;
618                         end = end->next;
619
620                         if (!split_flags[buf_idx]) {
621                                 /* it's the last packet of the set */
622 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
623                                 start->hash = end->hash;
624                                 start->ol_flags = end->ol_flags;
625                                 start->packet_type = end->packet_type;
626 #endif
627                                 pkts[pkt_idx++] = start;
628                                 start = end = NULL;
629                         }
630                 } else {
631                         /* not processing a split packet */
632                         if (!split_flags[buf_idx]) {
633                                 /* not a split packet, save and skip */
634                                 pkts[pkt_idx++] = rx_bufs[buf_idx];
635                                 continue;
636                         }
637                         end = start = rx_bufs[buf_idx];
638                 }
639         }
640
641         /* save the partial packet for next time */
642         rxq->pkt_first_seg = start;
643         rxq->pkt_last_seg = end;
644         memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
645         return pkt_idx;
646 }
647
648 /**
649  * vPMD receive routine that reassembles single burst of 32 scattered packets
650  *
651  * Notice:
652  * - don't support ol_flags for rss and csum err
653  */
654 static uint16_t
655 fm10k_recv_scattered_burst_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
656                                uint16_t nb_pkts)
657 {
658         struct fm10k_rx_queue *rxq = rx_queue;
659         uint8_t split_flags[RTE_FM10K_MAX_RX_BURST] = {0};
660         unsigned i = 0;
661
662         /* Split_flags only can support max of RTE_FM10K_MAX_RX_BURST */
663         nb_pkts = RTE_MIN(nb_pkts, RTE_FM10K_MAX_RX_BURST);
664         /* get some new buffers */
665         uint16_t nb_bufs = fm10k_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
666                         split_flags);
667         if (nb_bufs == 0)
668                 return 0;
669
670         /* happy day case, full burst + no packets to be joined */
671         const uint64_t *split_fl64 = (uint64_t *)split_flags;
672
673         if (rxq->pkt_first_seg == NULL &&
674                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
675                         split_fl64[2] == 0 && split_fl64[3] == 0)
676                 return nb_bufs;
677
678         /* reassemble any packets that need reassembly*/
679         if (rxq->pkt_first_seg == NULL) {
680                 /* find the first split flag, and only reassemble then*/
681                 while (i < nb_bufs && !split_flags[i])
682                         i++;
683                 if (i == nb_bufs)
684                         return nb_bufs;
685                 rxq->pkt_first_seg = rx_pkts[i];
686         }
687         return i + fm10k_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
688                 &split_flags[i]);
689 }
690
691 /**
692  * vPMD receive routine that reassembles scattered packets.
693  */
694 uint16_t
695 fm10k_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
696                               uint16_t nb_pkts)
697 {
698         uint16_t retval = 0;
699
700         while (nb_pkts > RTE_FM10K_MAX_RX_BURST) {
701                 uint16_t burst;
702
703                 burst = fm10k_recv_scattered_burst_vec(rx_queue,
704                                                        rx_pkts + retval,
705                                                        RTE_FM10K_MAX_RX_BURST);
706                 retval += burst;
707                 nb_pkts -= burst;
708                 if (burst < RTE_FM10K_MAX_RX_BURST)
709                         return retval;
710         }
711
712         return retval + fm10k_recv_scattered_burst_vec(rx_queue,
713                                                        rx_pkts + retval,
714                                                        nb_pkts);
715 }
716
717 static const struct fm10k_txq_ops vec_txq_ops = {
718         .reset = fm10k_reset_tx_queue,
719 };
720
721 void __rte_cold
722 fm10k_txq_vec_setup(struct fm10k_tx_queue *txq)
723 {
724         txq->ops = &vec_txq_ops;
725 }
726
727 int __rte_cold
728 fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq)
729 {
730         /* Vector TX can't offload any features yet */
731         if (txq->offloads != 0)
732                 return -1;
733
734         if (txq->tx_ftag_en)
735                 return -1;
736
737         return 0;
738 }
739
740 static inline void
741 vtx1(volatile struct fm10k_tx_desc *txdp,
742                 struct rte_mbuf *pkt, uint64_t flags)
743 {
744         __m128i descriptor = _mm_set_epi64x(flags << 56 |
745                         (uint64_t)pkt->vlan_tci << 16 | (uint64_t)pkt->data_len,
746                         MBUF_DMA_ADDR(pkt));
747         _mm_store_si128((__m128i *)txdp, descriptor);
748 }
749
750 static inline void
751 vtx(volatile struct fm10k_tx_desc *txdp,
752                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
753 {
754         int i;
755
756         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
757                 vtx1(txdp, *pkt, flags);
758 }
759
760 static __rte_always_inline int
761 fm10k_tx_free_bufs(struct fm10k_tx_queue *txq)
762 {
763         struct rte_mbuf **txep;
764         uint8_t flags;
765         uint32_t n;
766         uint32_t i;
767         int nb_free = 0;
768         struct rte_mbuf *m, *free[RTE_FM10K_TX_MAX_FREE_BUF_SZ];
769
770         /* check DD bit on threshold descriptor */
771         flags = txq->hw_ring[txq->next_dd].flags;
772         if (!(flags & FM10K_TXD_FLAG_DONE))
773                 return 0;
774
775         n = txq->rs_thresh;
776
777         /* First buffer to free from S/W ring is at index
778          * next_dd - (rs_thresh-1)
779          */
780         txep = &txq->sw_ring[txq->next_dd - (n - 1)];
781         m = rte_pktmbuf_prefree_seg(txep[0]);
782         if (likely(m != NULL)) {
783                 free[0] = m;
784                 nb_free = 1;
785                 for (i = 1; i < n; i++) {
786                         m = rte_pktmbuf_prefree_seg(txep[i]);
787                         if (likely(m != NULL)) {
788                                 if (likely(m->pool == free[0]->pool))
789                                         free[nb_free++] = m;
790                                 else {
791                                         rte_mempool_put_bulk(free[0]->pool,
792                                                         (void *)free, nb_free);
793                                         free[0] = m;
794                                         nb_free = 1;
795                                 }
796                         }
797                 }
798                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
799         } else {
800                 for (i = 1; i < n; i++) {
801                         m = rte_pktmbuf_prefree_seg(txep[i]);
802                         if (m != NULL)
803                                 rte_mempool_put(m->pool, m);
804                 }
805         }
806
807         /* buffers were freed, update counters */
808         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
809         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
810         if (txq->next_dd >= txq->nb_desc)
811                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
812
813         return txq->rs_thresh;
814 }
815
816 static __rte_always_inline void
817 tx_backlog_entry(struct rte_mbuf **txep,
818                  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
819 {
820         int i;
821
822         for (i = 0; i < (int)nb_pkts; ++i)
823                 txep[i] = tx_pkts[i];
824 }
825
826 uint16_t
827 fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
828                            uint16_t nb_pkts)
829 {
830         struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
831         volatile struct fm10k_tx_desc *txdp;
832         struct rte_mbuf **txep;
833         uint16_t n, nb_commit, tx_id;
834         uint64_t flags = FM10K_TXD_FLAG_LAST;
835         uint64_t rs = FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_LAST;
836         int i;
837
838         /* cross rx_thresh boundary is not allowed */
839         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
840
841         if (txq->nb_free < txq->free_thresh)
842                 fm10k_tx_free_bufs(txq);
843
844         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
845         if (unlikely(nb_pkts == 0))
846                 return 0;
847
848         tx_id = txq->next_free;
849         txdp = &txq->hw_ring[tx_id];
850         txep = &txq->sw_ring[tx_id];
851
852         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
853
854         n = (uint16_t)(txq->nb_desc - tx_id);
855         if (nb_commit >= n) {
856                 tx_backlog_entry(txep, tx_pkts, n);
857
858                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
859                         vtx1(txdp, *tx_pkts, flags);
860
861                 vtx1(txdp, *tx_pkts++, rs);
862
863                 nb_commit = (uint16_t)(nb_commit - n);
864
865                 tx_id = 0;
866                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
867
868                 /* avoid reach the end of ring */
869                 txdp = &(txq->hw_ring[tx_id]);
870                 txep = &txq->sw_ring[tx_id];
871         }
872
873         tx_backlog_entry(txep, tx_pkts, nb_commit);
874
875         vtx(txdp, tx_pkts, nb_commit, flags);
876
877         tx_id = (uint16_t)(tx_id + nb_commit);
878         if (tx_id > txq->next_rs) {
879                 txq->hw_ring[txq->next_rs].flags |= FM10K_TXD_FLAG_RS;
880                 txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh);
881         }
882
883         txq->next_free = tx_id;
884
885         FM10K_PCI_REG_WRITE(txq->tail_ptr, txq->next_free);
886
887         return nb_pkts;
888 }
889
890 static void __rte_cold
891 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
892 {
893         static const struct fm10k_tx_desc zeroed_desc = {0};
894         struct rte_mbuf **txe = txq->sw_ring;
895         uint16_t i;
896
897         /* Zero out HW ring memory */
898         for (i = 0; i < txq->nb_desc; i++)
899                 txq->hw_ring[i] = zeroed_desc;
900
901         /* Initialize SW ring entries */
902         for (i = 0; i < txq->nb_desc; i++)
903                 txe[i] = NULL;
904
905         txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
906         txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
907
908         txq->next_free = 0;
909         txq->nb_used = 0;
910         /* Always allow 1 descriptor to be un-allocated to avoid
911          * a H/W race condition
912          */
913         txq->nb_free = (uint16_t)(txq->nb_desc - 1);
914         FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);
915 }