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36 #include <rte_ethdev.h>
37 #include <rte_common.h>
39 #include "base/fm10k_type.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq);
50 /* Handling the offload flags (olflags) field takes computation
51 * time when receiving packets. Therefore we provide a flag to disable
52 * the processing of the olflags field when they are not needed. This
53 * gives improved performance, at the cost of losing the offload info
54 * in the received packet
56 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
58 /* Vlan present flag shift */
61 #define L3TYPE_SHIFT (4)
63 #define L4TYPE_SHIFT (7)
65 #define HBOFLAG_SHIFT (10)
67 #define RXEFLAG_SHIFT (13)
68 /* IPE/L4E flag shift */
69 #define L3L4EFLAG_SHIFT (14)
72 fm10k_desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
74 __m128i ptype0, ptype1, vtag0, vtag1, eflag0, eflag1, cksumflag;
80 const __m128i pkttype_msk = _mm_set_epi16(
81 0x0000, 0x0000, 0x0000, 0x0000,
82 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT,
83 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);
85 /* mask everything except rss type */
86 const __m128i rsstype_msk = _mm_set_epi16(
87 0x0000, 0x0000, 0x0000, 0x0000,
88 0x000F, 0x000F, 0x000F, 0x000F);
90 /* mask for HBO and RXE flag flags */
91 const __m128i rxe_msk = _mm_set_epi16(
92 0x0000, 0x0000, 0x0000, 0x0000,
93 0x0001, 0x0001, 0x0001, 0x0001);
95 const __m128i l3l4cksum_flag = _mm_set_epi8(0, 0, 0, 0,
98 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD,
99 PKT_RX_IP_CKSUM_BAD, PKT_RX_L4_CKSUM_BAD, 0);
101 const __m128i rxe_flag = _mm_set_epi8(0, 0, 0, 0,
104 0, 0, PKT_RX_RECIP_ERR, 0);
106 /* map rss type to rss hash flag */
107 const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
108 0, 0, 0, PKT_RX_RSS_HASH,
109 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
110 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
112 /* Calculate RSS_hash and Vlan fields */
113 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
114 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
115 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
116 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
118 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
119 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
120 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
122 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
125 vtag1 = _mm_srli_epi16(vtag1, VP_SHIFT);
126 vtag1 = _mm_and_si128(vtag1, pkttype_msk);
128 vtag1 = _mm_or_si128(ptype0, vtag1);
130 /* Process err flags, simply set RECIP_ERR bit if HBO/IXE is set */
131 eflag1 = _mm_srli_epi16(eflag0, RXEFLAG_SHIFT);
132 eflag0 = _mm_srli_epi16(eflag0, HBOFLAG_SHIFT);
133 eflag0 = _mm_or_si128(eflag0, eflag1);
134 eflag0 = _mm_and_si128(eflag0, rxe_msk);
135 eflag0 = _mm_shuffle_epi8(rxe_flag, eflag0);
137 vtag1 = _mm_or_si128(eflag0, vtag1);
139 /* Process L4/L3 checksum error flags */
140 cksumflag = _mm_srli_epi16(cksumflag, L3L4EFLAG_SHIFT);
141 cksumflag = _mm_shuffle_epi8(l3l4cksum_flag, cksumflag);
142 vtag1 = _mm_or_si128(cksumflag, vtag1);
144 vol.dword = _mm_cvtsi128_si64(vtag1);
146 rx_pkts[0]->ol_flags = vol.e[0];
147 rx_pkts[1]->ol_flags = vol.e[1];
148 rx_pkts[2]->ol_flags = vol.e[2];
149 rx_pkts[3]->ol_flags = vol.e[3];
153 fm10k_desc_to_pktype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
155 __m128i l3l4type0, l3l4type1, l3type, l4type;
161 /* L3 pkt type mask Bit4 to Bit6 */
162 const __m128i l3type_msk = _mm_set_epi16(
163 0x0000, 0x0000, 0x0000, 0x0000,
164 0x0070, 0x0070, 0x0070, 0x0070);
166 /* L4 pkt type mask Bit7 to Bit9 */
167 const __m128i l4type_msk = _mm_set_epi16(
168 0x0000, 0x0000, 0x0000, 0x0000,
169 0x0380, 0x0380, 0x0380, 0x0380);
171 /* convert RRC l3 type to mbuf format */
172 const __m128i l3type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
173 0, 0, 0, RTE_PTYPE_L3_IPV6_EXT,
174 RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV4_EXT,
175 RTE_PTYPE_L3_IPV4, 0);
177 /* Convert RRC l4 type to mbuf format l4type_flags shift-left 8 bits
178 * to fill into8 bits length.
180 const __m128i l4type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
181 RTE_PTYPE_TUNNEL_GENEVE >> 8,
182 RTE_PTYPE_TUNNEL_NVGRE >> 8,
183 RTE_PTYPE_TUNNEL_VXLAN >> 8,
184 RTE_PTYPE_TUNNEL_GRE >> 8,
185 RTE_PTYPE_L4_UDP >> 8,
186 RTE_PTYPE_L4_TCP >> 8,
189 l3l4type0 = _mm_unpacklo_epi16(descs[0], descs[1]);
190 l3l4type1 = _mm_unpacklo_epi16(descs[2], descs[3]);
191 l3l4type0 = _mm_unpacklo_epi32(l3l4type0, l3l4type1);
193 l3type = _mm_and_si128(l3l4type0, l3type_msk);
194 l4type = _mm_and_si128(l3l4type0, l4type_msk);
196 l3type = _mm_srli_epi16(l3type, L3TYPE_SHIFT);
197 l4type = _mm_srli_epi16(l4type, L4TYPE_SHIFT);
199 l3type = _mm_shuffle_epi8(l3type_flags, l3type);
200 /* l4type_flags shift-left for 8 bits, need shift-right back */
201 l4type = _mm_shuffle_epi8(l4type_flags, l4type);
203 l4type = _mm_slli_epi16(l4type, 8);
204 l3l4type0 = _mm_or_si128(l3type, l4type);
205 vol.dword = _mm_cvtsi128_si64(l3l4type0);
207 rx_pkts[0]->packet_type = vol.e[0];
208 rx_pkts[1]->packet_type = vol.e[1];
209 rx_pkts[2]->packet_type = vol.e[2];
210 rx_pkts[3]->packet_type = vol.e[3];
213 #define fm10k_desc_to_olflags_v(desc, rx_pkts) do {} while (0)
214 #define fm10k_desc_to_pktype_v(desc, rx_pkts) do {} while (0)
217 int __attribute__((cold))
218 fm10k_rx_vec_condition_check(struct rte_eth_dev *dev)
220 #ifndef RTE_LIBRTE_IEEE1588
221 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
222 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
224 #ifndef RTE_FM10K_RX_OLFLAGS_ENABLE
225 /* whithout rx ol_flags, no VP flag report */
226 if (rxmode->hw_vlan_extend != 0)
230 /* no fdir support */
231 if (fconf->mode != RTE_FDIR_MODE_NONE)
234 /* - no csum error report support
235 * - no header split support
237 if (rxmode->hw_ip_checksum == 1 ||
238 rxmode->header_split == 1)
248 int __attribute__((cold))
249 fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)
252 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
255 /* data_off will be ajusted after new mbuf allocated for 512-byte
258 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
259 mb_def.port = rxq->port_id;
260 rte_mbuf_refcnt_set(&mb_def, 1);
262 /* prevent compiler reordering: rearm_data covers previous fields */
263 rte_compiler_barrier();
264 p = (uintptr_t)&mb_def.rearm_data;
265 rxq->mbuf_initializer = *(uint64_t *)p;
270 fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)
274 volatile union fm10k_rx_desc *rxdp;
275 struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];
276 struct rte_mbuf *mb0, *mb1;
277 __m128i head_off = _mm_set_epi64x(
278 RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,
279 RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);
280 __m128i dma_addr0, dma_addr1;
281 /* Rx buffer need to be aligned with 512 byte */
282 const __m128i hba_msk = _mm_set_epi64x(0,
283 UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);
285 rxdp = rxq->hw_ring + rxq->rxrearm_start;
287 /* Pull 'n' more MBUFs into the software ring */
288 if (rte_mempool_get_bulk(rxq->mp,
290 RTE_FM10K_RXQ_REARM_THRESH) < 0) {
291 dma_addr0 = _mm_setzero_si128();
292 /* Clean up all the HW/SW ring content */
293 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) {
294 mb_alloc[i] = &rxq->fake_mbuf;
295 _mm_store_si128((__m128i *)&rxdp[i].q,
299 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
300 RTE_FM10K_RXQ_REARM_THRESH;
304 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
305 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {
306 __m128i vaddr0, vaddr1;
312 /* Flush mbuf with pkt template.
313 * Data to be rearmed is 6 bytes long.
314 * Though, RX will overwrite ol_flags that are coming next
315 * anyway. So overwrite whole 8 bytes with one load:
316 * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
318 p0 = (uintptr_t)&mb0->rearm_data;
319 *(uint64_t *)p0 = rxq->mbuf_initializer;
320 p1 = (uintptr_t)&mb1->rearm_data;
321 *(uint64_t *)p1 = rxq->mbuf_initializer;
323 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
324 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
325 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
327 /* convert pa to dma_addr hdr/data */
328 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
329 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
331 /* add headroom to pa values */
332 dma_addr0 = _mm_add_epi64(dma_addr0, head_off);
333 dma_addr1 = _mm_add_epi64(dma_addr1, head_off);
335 /* Do 512 byte alignment to satisfy HW requirement, in the
336 * meanwhile, set Header Buffer Address to zero.
338 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
339 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
341 /* flush desc with pa dma_addr */
342 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);
343 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);
345 /* enforce 512B alignment on default Rx virtual addresses */
346 mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr
347 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
348 - (char *)mb0->buf_addr);
349 mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr
350 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
351 - (char *)mb1->buf_addr);
354 rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;
355 if (rxq->rxrearm_start >= rxq->nb_desc)
356 rxq->rxrearm_start = 0;
358 rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;
360 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
361 (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));
363 /* Update the tail pointer on the NIC */
364 FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);
367 void __attribute__((cold))
368 fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq)
370 const unsigned mask = rxq->nb_desc - 1;
373 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_desc)
376 /* free all mbufs that are valid in the ring */
377 for (i = rxq->next_dd; i != rxq->rxrearm_start; i = (i + 1) & mask)
378 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
379 rxq->rxrearm_nb = rxq->nb_desc;
381 /* set all entries to NULL */
382 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_desc);
385 static inline uint16_t
386 fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
387 uint16_t nb_pkts, uint8_t *split_packet)
389 volatile union fm10k_rx_desc *rxdp;
390 struct rte_mbuf **mbufp;
391 uint16_t nb_pkts_recd;
393 struct fm10k_rx_queue *rxq = rx_queue;
396 __m128i dd_check, eop_check;
399 next_dd = rxq->next_dd;
401 /* Just the act of getting into the function from the application is
402 * going to cost about 7 cycles
404 rxdp = rxq->hw_ring + next_dd;
406 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
408 /* See if we need to rearm the RX queue - gives the prefetch a bit
411 if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH)
412 fm10k_rxq_rearm(rxq);
414 /* Before we start moving massive data around, check to see if
415 * there is actually a packet available
417 if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD))
420 /* Vecotr RX will process 4 packets at a time, strip the unaligned
421 * tails in case it's not multiple of 4.
423 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP);
425 /* 4 packets DD mask */
426 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
428 /* 4 packets EOP mask */
429 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
431 /* mask to shuffle from desc. to mbuf */
432 shuf_msk = _mm_set_epi8(
433 7, 6, 5, 4, /* octet 4~7, 32bits rss */
434 15, 14, /* octet 14~15, low 16 bits vlan_macip */
435 13, 12, /* octet 12~13, 16 bits data_len */
436 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
437 13, 12, /* octet 12~13, low 16 bits pkt_len */
438 0xFF, 0xFF, /* skip high 16 bits pkt_type */
439 0xFF, 0xFF /* Skip pkt_type field in shuffle operation */
442 /* Cache is empty -> need to scan the buffer rings, but first move
443 * the next 'n' mbufs into the cache
445 mbufp = &rxq->sw_ring[next_dd];
447 /* A. load 4 packet in one loop
448 * [A*. mask out 4 unused dirty field in desc]
449 * B. copy 4 mbuf point from swring to rx_pkts
450 * C. calc the number of DD bits among the 4 packets
451 * [C*. extract the end-of-packet bit, if requested]
452 * D. fill info. from desc to mbuf
454 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
455 pos += RTE_FM10K_DESCS_PER_LOOP,
456 rxdp += RTE_FM10K_DESCS_PER_LOOP) {
457 __m128i descs0[RTE_FM10K_DESCS_PER_LOOP];
458 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
459 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
460 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
462 /* B.1 load 1 mbuf point */
463 mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]);
465 /* Read desc statuses backwards to avoid race condition */
466 /* A.1 load 4 pkts desc */
467 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
469 /* B.2 copy 2 mbuf point into rx_pkts */
470 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
472 /* B.1 load 1 mbuf point */
473 mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]);
475 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
476 /* B.1 load 2 mbuf point */
477 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
478 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
480 /* B.2 copy 2 mbuf point into rx_pkts */
481 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
483 /* avoid compiler reorder optimization */
484 rte_compiler_barrier();
487 rte_prefetch0(&rx_pkts[pos]->cacheline1);
488 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
489 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
490 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
493 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
494 pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk);
495 pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk);
497 /* C.1 4=>2 filter staterr info only */
498 sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]);
499 /* C.1 4=>2 filter staterr info only */
500 sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]);
502 /* set ol_flags with vlan packet type */
503 fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]);
505 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
506 pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk);
507 pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk);
509 /* C.2 get 4 pkts staterr value */
510 zero = _mm_xor_si128(dd_check, dd_check);
511 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
513 /* D.3 copy final 3,4 data to rx_pkts */
514 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
516 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
519 /* C* extract and record EOP bit */
521 __m128i eop_shuf_mask = _mm_set_epi8(
522 0xFF, 0xFF, 0xFF, 0xFF,
523 0xFF, 0xFF, 0xFF, 0xFF,
524 0xFF, 0xFF, 0xFF, 0xFF,
525 0x04, 0x0C, 0x00, 0x08
528 /* and with mask to extract bits, flipping 1-0 */
529 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
530 /* the staterr values are not in order, as the count
531 * count of dd bits doesn't care. However, for end of
532 * packet tracking, we do care, so shuffle. This also
533 * compresses the 32-bit values to 8-bit
535 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
536 /* store the resulting 32-bit value */
537 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
538 split_packet += RTE_FM10K_DESCS_PER_LOOP;
540 /* zero-out next pointers */
541 rx_pkts[pos]->next = NULL;
542 rx_pkts[pos + 1]->next = NULL;
543 rx_pkts[pos + 2]->next = NULL;
544 rx_pkts[pos + 3]->next = NULL;
547 /* C.3 calc available number of desc */
548 staterr = _mm_and_si128(staterr, dd_check);
549 staterr = _mm_packs_epi32(staterr, zero);
551 /* D.3 copy final 1,2 data to rx_pkts */
552 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
554 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
557 fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]);
559 /* C.4 calc avaialbe number of desc */
560 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
562 if (likely(var != RTE_FM10K_DESCS_PER_LOOP))
566 /* Update our internal tail pointer */
567 rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd);
568 rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1));
569 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
574 /* vPMD receive routine
577 * - don't support ol_flags for rss and csum err
580 fm10k_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
583 return fm10k_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
586 static inline uint16_t
587 fm10k_reassemble_packets(struct fm10k_rx_queue *rxq,
588 struct rte_mbuf **rx_bufs,
589 uint16_t nb_bufs, uint8_t *split_flags)
591 struct rte_mbuf *pkts[RTE_FM10K_MAX_RX_BURST]; /*finished pkts*/
592 struct rte_mbuf *start = rxq->pkt_first_seg;
593 struct rte_mbuf *end = rxq->pkt_last_seg;
594 unsigned pkt_idx, buf_idx;
596 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
598 /* processing a split packet */
599 end->next = rx_bufs[buf_idx];
601 start->pkt_len += rx_bufs[buf_idx]->data_len;
604 if (!split_flags[buf_idx]) {
605 /* it's the last packet of the set */
606 start->hash = end->hash;
607 start->ol_flags = end->ol_flags;
608 pkts[pkt_idx++] = start;
612 /* not processing a split packet */
613 if (!split_flags[buf_idx]) {
614 /* not a split packet, save and skip */
615 pkts[pkt_idx++] = rx_bufs[buf_idx];
618 end = start = rx_bufs[buf_idx];
622 /* save the partial packet for next time */
623 rxq->pkt_first_seg = start;
624 rxq->pkt_last_seg = end;
625 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
630 * vPMD receive routine that reassembles scattered packets
633 * - don't support ol_flags for rss and csum err
634 * - nb_pkts > RTE_FM10K_MAX_RX_BURST, only scan RTE_FM10K_MAX_RX_BURST
638 fm10k_recv_scattered_pkts_vec(void *rx_queue,
639 struct rte_mbuf **rx_pkts,
642 struct fm10k_rx_queue *rxq = rx_queue;
643 uint8_t split_flags[RTE_FM10K_MAX_RX_BURST] = {0};
646 /* Split_flags only can support max of RTE_FM10K_MAX_RX_BURST */
647 nb_pkts = RTE_MIN(nb_pkts, RTE_FM10K_MAX_RX_BURST);
648 /* get some new buffers */
649 uint16_t nb_bufs = fm10k_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
654 /* happy day case, full burst + no packets to be joined */
655 const uint64_t *split_fl64 = (uint64_t *)split_flags;
657 if (rxq->pkt_first_seg == NULL &&
658 split_fl64[0] == 0 && split_fl64[1] == 0 &&
659 split_fl64[2] == 0 && split_fl64[3] == 0)
662 /* reassemble any packets that need reassembly*/
663 if (rxq->pkt_first_seg == NULL) {
664 /* find the first split flag, and only reassemble then*/
665 while (i < nb_bufs && !split_flags[i])
670 return i + fm10k_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
674 static const struct fm10k_txq_ops vec_txq_ops = {
675 .reset = fm10k_reset_tx_queue,
678 void __attribute__((cold))
679 fm10k_txq_vec_setup(struct fm10k_tx_queue *txq)
681 txq->ops = &vec_txq_ops;
684 int __attribute__((cold))
685 fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq)
687 /* Vector TX can't offload any features yet */
688 if ((txq->txq_flags & FM10K_SIMPLE_TX_FLAG) != FM10K_SIMPLE_TX_FLAG)
695 vtx1(volatile struct fm10k_tx_desc *txdp,
696 struct rte_mbuf *pkt, uint64_t flags)
698 __m128i descriptor = _mm_set_epi64x(flags << 56 |
699 pkt->vlan_tci << 16 | pkt->data_len,
701 _mm_store_si128((__m128i *)txdp, descriptor);
705 vtx(volatile struct fm10k_tx_desc *txdp,
706 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
710 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
711 vtx1(txdp, *pkt, flags);
714 static inline int __attribute__((always_inline))
715 fm10k_tx_free_bufs(struct fm10k_tx_queue *txq)
717 struct rte_mbuf **txep;
722 struct rte_mbuf *m, *free[RTE_FM10K_TX_MAX_FREE_BUF_SZ];
724 /* check DD bit on threshold descriptor */
725 flags = txq->hw_ring[txq->next_dd].flags;
726 if (!(flags & FM10K_TXD_FLAG_DONE))
731 /* First buffer to free from S/W ring is at index
732 * next_dd - (rs_thresh-1)
734 txep = &txq->sw_ring[txq->next_dd - (n - 1)];
735 m = __rte_pktmbuf_prefree_seg(txep[0]);
736 if (likely(m != NULL)) {
739 for (i = 1; i < n; i++) {
740 m = __rte_pktmbuf_prefree_seg(txep[i]);
741 if (likely(m != NULL)) {
742 if (likely(m->pool == free[0]->pool))
745 rte_mempool_put_bulk(free[0]->pool,
746 (void *)free, nb_free);
752 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
754 for (i = 1; i < n; i++) {
755 m = __rte_pktmbuf_prefree_seg(txep[i]);
757 rte_mempool_put(m->pool, m);
761 /* buffers were freed, update counters */
762 txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
763 txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
764 if (txq->next_dd >= txq->nb_desc)
765 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
767 return txq->rs_thresh;
770 static inline void __attribute__((always_inline))
771 tx_backlog_entry(struct rte_mbuf **txep,
772 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
776 for (i = 0; i < (int)nb_pkts; ++i)
777 txep[i] = tx_pkts[i];
781 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
784 struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
785 volatile struct fm10k_tx_desc *txdp;
786 struct rte_mbuf **txep;
787 uint16_t n, nb_commit, tx_id;
788 uint64_t flags = FM10K_TXD_FLAG_LAST;
789 uint64_t rs = FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_LAST;
792 /* cross rx_thresh boundary is not allowed */
793 nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
795 if (txq->nb_free < txq->free_thresh)
796 fm10k_tx_free_bufs(txq);
798 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
799 if (unlikely(nb_pkts == 0))
802 tx_id = txq->next_free;
803 txdp = &txq->hw_ring[tx_id];
804 txep = &txq->sw_ring[tx_id];
806 txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
808 n = (uint16_t)(txq->nb_desc - tx_id);
809 if (nb_commit >= n) {
810 tx_backlog_entry(txep, tx_pkts, n);
812 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
813 vtx1(txdp, *tx_pkts, flags);
815 vtx1(txdp, *tx_pkts++, rs);
817 nb_commit = (uint16_t)(nb_commit - n);
820 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
822 /* avoid reach the end of ring */
823 txdp = &(txq->hw_ring[tx_id]);
824 txep = &txq->sw_ring[tx_id];
827 tx_backlog_entry(txep, tx_pkts, nb_commit);
829 vtx(txdp, tx_pkts, nb_commit, flags);
831 tx_id = (uint16_t)(tx_id + nb_commit);
832 if (tx_id > txq->next_rs) {
833 txq->hw_ring[txq->next_rs].flags |= FM10K_TXD_FLAG_RS;
834 txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh);
837 txq->next_free = tx_id;
839 FM10K_PCI_REG_WRITE(txq->tail_ptr, txq->next_free);
844 static void __attribute__((cold))
845 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
847 static const struct fm10k_tx_desc zeroed_desc = {0};
848 struct rte_mbuf **txe = txq->sw_ring;
851 /* Zero out HW ring memory */
852 for (i = 0; i < txq->nb_desc; i++)
853 txq->hw_ring[i] = zeroed_desc;
855 /* Initialize SW ring entries */
856 for (i = 0; i < txq->nb_desc; i++)
859 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
860 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
864 /* Always allow 1 descriptor to be un-allocated to avoid
865 * a H/W race condition
867 txq->nb_free = (uint16_t)(txq->nb_desc - 1);
868 FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);