drivers/net/fm10k/fm10k_rxtx_vec.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2013-2015 Intel Corporation
   3  */
   4
   5 #include <inttypes.h>
   6
   7 #include <rte_ethdev_driver.h>
   8 #include <rte_common.h>
   9 #include "fm10k.h"
  10 #include "base/fm10k_type.h"
  11
  12 #include <tmmintrin.h>
  13
  14 #ifndef __INTEL_COMPILER
  15 #pragma GCC diagnostic ignored "-Wcast-qual"
  16 #endif
  17
  18 static void
  19 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq);
  20
  21 /* Handling the offload flags (olflags) field takes computation
  22  * time when receiving packets. Therefore we provide a flag to disable
  23  * the processing of the olflags field when they are not needed. This
  24  * gives improved performance, at the cost of losing the offload info
  25  * in the received packet
  26  */
  27 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
  28
  29 /* Vlan present flag shift */
  30 #define VP_SHIFT     (2)
  31 /* L3 type shift */
  32 #define L3TYPE_SHIFT     (4)
  33 /* L4 type shift */
  34 #define L4TYPE_SHIFT     (7)
  35 /* HBO flag shift */
  36 #define HBOFLAG_SHIFT     (10)
  37 /* RXE flag shift */
  38 #define RXEFLAG_SHIFT     (13)
  39 /* IPE/L4E flag shift */
  40 #define L3L4EFLAG_SHIFT     (14)
  41 /* shift PKT_RX_L4_CKSUM_GOOD into one byte by 1 bit */
  42 #define CKSUM_SHIFT     (1)
  43
  44 static inline void
  45 fm10k_desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
  46 {
  47         __m128i ptype0, ptype1, vtag0, vtag1, eflag0, eflag1, cksumflag;
  48         union {
  49                 uint16_t e[4];
  50                 uint64_t dword;
  51         } vol;
  52
  53         const __m128i pkttype_msk = _mm_set_epi16(
  54                         0x0000, 0x0000, 0x0000, 0x0000,
  55                         PKT_RX_VLAN, PKT_RX_VLAN,
  56                         PKT_RX_VLAN, PKT_RX_VLAN);
  57
  58         /* mask everything except rss type */
  59         const __m128i rsstype_msk = _mm_set_epi16(
  60                         0x0000, 0x0000, 0x0000, 0x0000,
  61                         0x000F, 0x000F, 0x000F, 0x000F);
  62
  63         /* mask for HBO and RXE flag flags */
  64         const __m128i rxe_msk = _mm_set_epi16(
  65                         0x0000, 0x0000, 0x0000, 0x0000,
  66                         0x0001, 0x0001, 0x0001, 0x0001);
  67
  68         /* mask the lower byte of ol_flags */
  69         const __m128i ol_flags_msk = _mm_set_epi16(
  70                         0x0000, 0x0000, 0x0000, 0x0000,
  71                         0x00FF, 0x00FF, 0x00FF, 0x00FF);
  72
  73         const __m128i l3l4cksum_flag = _mm_set_epi8(0, 0, 0, 0,
  74                         0, 0, 0, 0,
  75                         0, 0, 0, 0,
  76                         (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
  77                         (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT,
  78                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
  79                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT);
  80
  81         const __m128i rxe_flag = _mm_set_epi8(0, 0, 0, 0,
  82                         0, 0, 0, 0,
  83                         0, 0, 0, 0,
  84                         0, 0, 0, 0);
  85
  86         /* map rss type to rss hash flag */
  87         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
  88                         0, 0, 0, PKT_RX_RSS_HASH,
  89                         PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
  90                         PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
  91
  92         /* Calculate RSS_hash and Vlan fields */
  93         ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
  94         ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
  95         vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
  96         vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
  97
  98         ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
  99         ptype0 = _mm_and_si128(ptype0, rsstype_msk);
 100         ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
 101
 102         vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
 103         eflag0 = vtag1;
 104         cksumflag = vtag1;
 105         vtag1 = _mm_srli_epi16(vtag1, VP_SHIFT);
 106         vtag1 = _mm_and_si128(vtag1, pkttype_msk);
 107
 108         vtag1 = _mm_or_si128(ptype0, vtag1);
 109
 110         /* Process err flags, simply set RECIP_ERR bit if HBO/IXE is set */
 111         eflag1 = _mm_srli_epi16(eflag0, RXEFLAG_SHIFT);
 112         eflag0 = _mm_srli_epi16(eflag0, HBOFLAG_SHIFT);
 113         eflag0 = _mm_or_si128(eflag0, eflag1);
 114         eflag0 = _mm_and_si128(eflag0, rxe_msk);
 115         eflag0 = _mm_shuffle_epi8(rxe_flag, eflag0);
 116
 117         vtag1 = _mm_or_si128(eflag0, vtag1);
 118
 119         /* Process L4/L3 checksum error flags */
 120         cksumflag = _mm_srli_epi16(cksumflag, L3L4EFLAG_SHIFT);
 121         cksumflag = _mm_shuffle_epi8(l3l4cksum_flag, cksumflag);
 122
 123         /* clean the higher byte and shift back the flag bits */
 124         cksumflag = _mm_and_si128(cksumflag, ol_flags_msk);
 125         cksumflag = _mm_slli_epi16(cksumflag, CKSUM_SHIFT);
 126         vtag1 = _mm_or_si128(cksumflag, vtag1);
 127
 128         vol.dword = _mm_cvtsi128_si64(vtag1);
 129
 130         rx_pkts[0]->ol_flags = vol.e[0];
 131         rx_pkts[1]->ol_flags = vol.e[1];
 132         rx_pkts[2]->ol_flags = vol.e[2];
 133         rx_pkts[3]->ol_flags = vol.e[3];
 134 }
 135
 136 /* @note: When this function is changed, make corresponding change to
 137  * fm10k_dev_supported_ptypes_get().
 138  */
 139 static inline void
 140 fm10k_desc_to_pktype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 141 {
 142         __m128i l3l4type0, l3l4type1, l3type, l4type;
 143         union {
 144                 uint16_t e[4];
 145                 uint64_t dword;
 146         } vol;
 147
 148         /* L3 pkt type mask  Bit4 to Bit6 */
 149         const __m128i l3type_msk = _mm_set_epi16(
 150                         0x0000, 0x0000, 0x0000, 0x0000,
 151                         0x0070, 0x0070, 0x0070, 0x0070);
 152
 153         /* L4 pkt type mask  Bit7 to Bit9 */
 154         const __m128i l4type_msk = _mm_set_epi16(
 155                         0x0000, 0x0000, 0x0000, 0x0000,
 156                         0x0380, 0x0380, 0x0380, 0x0380);
 157
 158         /* convert RRC l3 type to mbuf format */
 159         const __m128i l3type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 160                         0, 0, 0, RTE_PTYPE_L3_IPV6_EXT,
 161                         RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV4_EXT,
 162                         RTE_PTYPE_L3_IPV4, 0);
 163
 164         /* Convert RRC l4 type to mbuf format l4type_flags shift-left 8 bits
 165          * to fill into8 bits length.
 166          */
 167         const __m128i l4type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
 168                         RTE_PTYPE_TUNNEL_GENEVE >> 8,
 169                         RTE_PTYPE_TUNNEL_NVGRE >> 8,
 170                         RTE_PTYPE_TUNNEL_VXLAN >> 8,
 171                         RTE_PTYPE_TUNNEL_GRE >> 8,
 172                         RTE_PTYPE_L4_UDP >> 8,
 173                         RTE_PTYPE_L4_TCP >> 8,
 174                         0);
 175
 176         l3l4type0 = _mm_unpacklo_epi16(descs[0], descs[1]);
 177         l3l4type1 = _mm_unpacklo_epi16(descs[2], descs[3]);
 178         l3l4type0 = _mm_unpacklo_epi32(l3l4type0, l3l4type1);
 179
 180         l3type = _mm_and_si128(l3l4type0, l3type_msk);
 181         l4type = _mm_and_si128(l3l4type0, l4type_msk);
 182
 183         l3type = _mm_srli_epi16(l3type, L3TYPE_SHIFT);
 184         l4type = _mm_srli_epi16(l4type, L4TYPE_SHIFT);
 185
 186         l3type = _mm_shuffle_epi8(l3type_flags, l3type);
 187         /* l4type_flags shift-left for 8 bits, need shift-right back */
 188         l4type = _mm_shuffle_epi8(l4type_flags, l4type);
 189
 190         l4type = _mm_slli_epi16(l4type, 8);
 191         l3l4type0 = _mm_or_si128(l3type, l4type);
 192         vol.dword = _mm_cvtsi128_si64(l3l4type0);
 193
 194         rx_pkts[0]->packet_type = vol.e[0];
 195         rx_pkts[1]->packet_type = vol.e[1];
 196         rx_pkts[2]->packet_type = vol.e[2];
 197         rx_pkts[3]->packet_type = vol.e[3];
 198 }
 199 #else
 200 #define fm10k_desc_to_olflags_v(desc, rx_pkts) do {} while (0)
 201 #define fm10k_desc_to_pktype_v(desc, rx_pkts) do {} while (0)
 202 #endif
 203
 204 int __attribute__((cold))
 205 fm10k_rx_vec_condition_check(struct rte_eth_dev *dev)
 206 {
 207 #ifndef RTE_LIBRTE_IEEE1588
 208         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 209         struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
 210
 211 #ifndef RTE_FM10K_RX_OLFLAGS_ENABLE
 212         /* whithout rx ol_flags, no VP flag report */
 213         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
 214                 return -1;
 215 #endif
 216
 217         /* no fdir support */
 218         if (fconf->mode != RTE_FDIR_MODE_NONE)
 219                 return -1;
 220
 221         /* no header split support */
 222         if (rxmode->offloads & DEV_RX_OFFLOAD_HEADER_SPLIT)
 223                 return -1;
 224
 225         return 0;
 226 #else
 227         RTE_SET_USED(dev);
 228         return -1;
 229 #endif
 230 }
 231
 232 int __attribute__((cold))
 233 fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)
 234 {
 235         uintptr_t p;
 236         struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
 237
 238         mb_def.nb_segs = 1;
 239         /* data_off will be ajusted after new mbuf allocated for 512-byte
 240          * alignment.
 241          */
 242         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
 243         mb_def.port = rxq->port_id;
 244         rte_mbuf_refcnt_set(&mb_def, 1);
 245
 246         /* prevent compiler reordering: rearm_data covers previous fields */
 247         rte_compiler_barrier();
 248         p = (uintptr_t)&mb_def.rearm_data;
 249         rxq->mbuf_initializer = *(uint64_t *)p;
 250         return 0;
 251 }
 252
 253 static inline void
 254 fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)
 255 {
 256         int i;
 257         uint16_t rx_id;
 258         volatile union fm10k_rx_desc *rxdp;
 259         struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];
 260         struct rte_mbuf *mb0, *mb1;
 261         __m128i head_off = _mm_set_epi64x(
 262                         RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,
 263                         RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);
 264         __m128i dma_addr0, dma_addr1;
 265         /* Rx buffer need to be aligned with 512 byte */
 266         const __m128i hba_msk = _mm_set_epi64x(0,
 267                                 UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);
 268
 269         rxdp = rxq->hw_ring + rxq->rxrearm_start;
 270
 271         /* Pull 'n' more MBUFs into the software ring */
 272         if (rte_mempool_get_bulk(rxq->mp,
 273                                  (void *)mb_alloc,
 274                                  RTE_FM10K_RXQ_REARM_THRESH) < 0) {
 275                 dma_addr0 = _mm_setzero_si128();
 276                 /* Clean up all the HW/SW ring content */
 277                 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) {
 278                         mb_alloc[i] = &rxq->fake_mbuf;
 279                         _mm_store_si128((__m128i *)&rxdp[i].q,
 280                                                 dma_addr0);
 281                 }
 282
 283                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
 284                         RTE_FM10K_RXQ_REARM_THRESH;
 285                 return;
 286         }
 287
 288         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
 289         for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {
 290                 __m128i vaddr0, vaddr1;
 291                 uintptr_t p0, p1;
 292
 293                 mb0 = mb_alloc[0];
 294                 mb1 = mb_alloc[1];
 295
 296                 /* Flush mbuf with pkt template.
 297                  * Data to be rearmed is 6 bytes long.
 298                  */
 299                 p0 = (uintptr_t)&mb0->rearm_data;
 300                 *(uint64_t *)p0 = rxq->mbuf_initializer;
 301                 p1 = (uintptr_t)&mb1->rearm_data;
 302                 *(uint64_t *)p1 = rxq->mbuf_initializer;
 303
 304                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
 305                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
 306                                 offsetof(struct rte_mbuf, buf_addr) + 8);
 307                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 308                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 309
 310                 /* convert pa to dma_addr hdr/data */
 311                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
 312                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
 313
 314                 /* add headroom to pa values */
 315                 dma_addr0 = _mm_add_epi64(dma_addr0, head_off);
 316                 dma_addr1 = _mm_add_epi64(dma_addr1, head_off);
 317
 318                 /* Do 512 byte alignment to satisfy HW requirement, in the
 319                  * meanwhile, set Header Buffer Address to zero.
 320                  */
 321                 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
 322                 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
 323
 324                 /* flush desc with pa dma_addr */
 325                 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);
 326                 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);
 327
 328                 /* enforce 512B alignment on default Rx virtual addresses */
 329                 mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr
 330                                 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
 331                                 - (char *)mb0->buf_addr);
 332                 mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr
 333                                 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
 334                                 - (char *)mb1->buf_addr);
 335         }
 336
 337         rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;
 338         if (rxq->rxrearm_start >= rxq->nb_desc)
 339                 rxq->rxrearm_start = 0;
 340
 341         rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;
 342
 343         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 344                         (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));
 345
 346         /* Update the tail pointer on the NIC */
 347         FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);
 348 }
 349
 350 void __attribute__((cold))
 351 fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq)
 352 {
 353         const unsigned mask = rxq->nb_desc - 1;
 354         unsigned i;
 355
 356         if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_desc)
 357                 return;
 358
 359         /* free all mbufs that are valid in the ring */
 360         for (i = rxq->next_dd; i != rxq->rxrearm_start; i = (i + 1) & mask)
 361                 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 362         rxq->rxrearm_nb = rxq->nb_desc;
 363
 364         /* set all entries to NULL */
 365         memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_desc);
 366 }
 367
 368 static inline uint16_t
 369 fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 370                 uint16_t nb_pkts, uint8_t *split_packet)
 371 {
 372         volatile union fm10k_rx_desc *rxdp;
 373         struct rte_mbuf **mbufp;
 374         uint16_t nb_pkts_recd;
 375         int pos;
 376         struct fm10k_rx_queue *rxq = rx_queue;
 377         uint64_t var;
 378         __m128i shuf_msk;
 379         __m128i dd_check, eop_check;
 380         uint16_t next_dd;
 381
 382         next_dd = rxq->next_dd;
 383
 384         /* Just the act of getting into the function from the application is
 385          * going to cost about 7 cycles
 386          */
 387         rxdp = rxq->hw_ring + next_dd;
 388
 389         rte_prefetch0(rxdp);
 390
 391         /* See if we need to rearm the RX queue - gives the prefetch a bit
 392          * of time to act
 393          */
 394         if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH)
 395                 fm10k_rxq_rearm(rxq);
 396
 397         /* Before we start moving massive data around, check to see if
 398          * there is actually a packet available
 399          */
 400         if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD))
 401                 return 0;
 402
 403         /* Vecotr RX will process 4 packets at a time, strip the unaligned
 404          * tails in case it's not multiple of 4.
 405          */
 406         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP);
 407
 408         /* 4 packets DD mask */
 409         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 410
 411         /* 4 packets EOP mask */
 412         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 413
 414         /* mask to shuffle from desc. to mbuf */
 415         shuf_msk = _mm_set_epi8(
 416                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 417                 15, 14,      /* octet 14~15, low 16 bits vlan_macip */
 418                 13, 12,      /* octet 12~13, 16 bits data_len */
 419                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 420                 13, 12,      /* octet 12~13, low 16 bits pkt_len */
 421                 0xFF, 0xFF,  /* skip high 16 bits pkt_type */
 422                 0xFF, 0xFF   /* Skip pkt_type field in shuffle operation */
 423                 );
 424         /*
 425          * Compile-time verify the shuffle mask
 426          * NOTE: some field positions already verified above, but duplicated
 427          * here for completeness in case of future modifications.
 428          */
 429         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 430                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 431         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 432                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 433         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 434                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 435         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 436                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 437
 438         /* Cache is empty -> need to scan the buffer rings, but first move
 439          * the next 'n' mbufs into the cache
 440          */
 441         mbufp = &rxq->sw_ring[next_dd];
 442
 443         /* A. load 4 packet in one loop
 444          * [A*. mask out 4 unused dirty field in desc]
 445          * B. copy 4 mbuf point from swring to rx_pkts
 446          * C. calc the number of DD bits among the 4 packets
 447          * [C*. extract the end-of-packet bit, if requested]
 448          * D. fill info. from desc to mbuf
 449          */
 450         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 451                         pos += RTE_FM10K_DESCS_PER_LOOP,
 452                         rxdp += RTE_FM10K_DESCS_PER_LOOP) {
 453                 __m128i descs0[RTE_FM10K_DESCS_PER_LOOP];
 454                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 455                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 456                 __m128i mbp1;
 457                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
 458 #if defined(RTE_ARCH_X86_64)
 459                 __m128i mbp2;
 460 #endif
 461
 462                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
 463                 mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]);
 464
 465                 /* Read desc statuses backwards to avoid race condition */
 466                 /* A.1 load 4 pkts desc */
 467                 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 468                 rte_compiler_barrier();
 469
 470                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
 471                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 472
 473 #if defined(RTE_ARCH_X86_64)
 474                 /* B.1 load 2 64 bit mbuf poitns */
 475                 mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]);
 476 #endif
 477
 478                 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 479                 rte_compiler_barrier();
 480                 /* B.1 load 2 mbuf point */
 481                 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 482                 rte_compiler_barrier();
 483                 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
 484
 485 #if defined(RTE_ARCH_X86_64)
 486                 /* B.2 copy 2 mbuf point into rx_pkts  */
 487                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 488 #endif
 489
 490                 /* avoid compiler reorder optimization */
 491                 rte_compiler_barrier();
 492
 493                 if (split_packet) {
 494                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 495                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 496                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 497                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 498                 }
 499
 500                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 501                 pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk);
 502                 pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk);
 503
 504                 /* C.1 4=>2 filter staterr info only */
 505                 sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]);
 506                 /* C.1 4=>2 filter staterr info only */
 507                 sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]);
 508
 509                 /* set ol_flags with vlan packet type */
 510                 fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]);
 511
 512                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 513                 pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk);
 514                 pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk);
 515
 516                 /* C.2 get 4 pkts staterr value  */
 517                 zero = _mm_xor_si128(dd_check, dd_check);
 518                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 519
 520                 /* D.3 copy final 3,4 data to rx_pkts */
 521                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 522                                 pkt_mb4);
 523                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 524                                 pkt_mb3);
 525
 526                 /* C* extract and record EOP bit */
 527                 if (split_packet) {
 528                         __m128i eop_shuf_mask = _mm_set_epi8(
 529                                         0xFF, 0xFF, 0xFF, 0xFF,
 530                                         0xFF, 0xFF, 0xFF, 0xFF,
 531                                         0xFF, 0xFF, 0xFF, 0xFF,
 532                                         0x04, 0x0C, 0x00, 0x08
 533                                         );
 534
 535                         /* and with mask to extract bits, flipping 1-0 */
 536                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 537                         /* the staterr values are not in order, as the count
 538                          * count of dd bits doesn't care. However, for end of
 539                          * packet tracking, we do care, so shuffle. This also
 540                          * compresses the 32-bit values to 8-bit
 541                          */
 542                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 543                         /* store the resulting 32-bit value */
 544                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 545                         split_packet += RTE_FM10K_DESCS_PER_LOOP;
 546
 547                         /* zero-out next pointers */
 548                         rx_pkts[pos]->next = NULL;
 549                         rx_pkts[pos + 1]->next = NULL;
 550                         rx_pkts[pos + 2]->next = NULL;
 551                         rx_pkts[pos + 3]->next = NULL;
 552                 }
 553
 554                 /* C.3 calc available number of desc */
 555                 staterr = _mm_and_si128(staterr, dd_check);
 556                 staterr = _mm_packs_epi32(staterr, zero);
 557
 558                 /* D.3 copy final 1,2 data to rx_pkts */
 559                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 560                                 pkt_mb2);
 561                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 562                                 pkt_mb1);
 563
 564                 fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]);
 565
 566                 /* C.4 calc avaialbe number of desc */
 567                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 568                 nb_pkts_recd += var;
 569                 if (likely(var != RTE_FM10K_DESCS_PER_LOOP))
 570                         break;
 571         }
 572
 573         /* Update our internal tail pointer */
 574         rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd);
 575         rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1));
 576         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 577
 578         return nb_pkts_recd;
 579 }
 580
 581 /* vPMD receive routine
 582  *
 583  * Notice:
 584  * - don't support ol_flags for rss and csum err
 585  */
 586 uint16_t
 587 fm10k_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 588                 uint16_t nb_pkts)
 589 {
 590         return fm10k_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 591 }
 592
 593 static inline uint16_t
 594 fm10k_reassemble_packets(struct fm10k_rx_queue *rxq,
 595                 struct rte_mbuf **rx_bufs,
 596                 uint16_t nb_bufs, uint8_t *split_flags)
 597 {
 598         struct rte_mbuf *pkts[RTE_FM10K_MAX_RX_BURST]; /*finished pkts*/
 599         struct rte_mbuf *start = rxq->pkt_first_seg;
 600         struct rte_mbuf *end =  rxq->pkt_last_seg;
 601         unsigned pkt_idx, buf_idx;
 602
 603         for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
 604                 if (end != NULL) {
 605                         /* processing a split packet */
 606                         end->next = rx_bufs[buf_idx];
 607                         start->nb_segs++;
 608                         start->pkt_len += rx_bufs[buf_idx]->data_len;
 609                         end = end->next;
 610
 611                         if (!split_flags[buf_idx]) {
 612                                 /* it's the last packet of the set */
 613 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
 614                                 start->hash = end->hash;
 615                                 start->ol_flags = end->ol_flags;
 616                                 start->packet_type = end->packet_type;
 617 #endif
 618                                 pkts[pkt_idx++] = start;
 619                                 start = end = NULL;
 620                         }
 621                 } else {
 622                         /* not processing a split packet */
 623                         if (!split_flags[buf_idx]) {
 624                                 /* not a split packet, save and skip */
 625                                 pkts[pkt_idx++] = rx_bufs[buf_idx];
 626                                 continue;
 627                         }
 628                         end = start = rx_bufs[buf_idx];
 629                 }
 630         }
 631
 632         /* save the partial packet for next time */
 633         rxq->pkt_first_seg = start;
 634         rxq->pkt_last_seg = end;
 635         memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
 636         return pkt_idx;
 637 }
 638
 639 /*
 640  * vPMD receive routine that reassembles scattered packets
 641  *
 642  * Notice:
 643  * - don't support ol_flags for rss and csum err
 644  * - nb_pkts > RTE_FM10K_MAX_RX_BURST, only scan RTE_FM10K_MAX_RX_BURST
 645  *   numbers of DD bit
 646  */
 647 uint16_t
 648 fm10k_recv_scattered_pkts_vec(void *rx_queue,
 649                                 struct rte_mbuf **rx_pkts,
 650                                 uint16_t nb_pkts)
 651 {
 652         struct fm10k_rx_queue *rxq = rx_queue;
 653         uint8_t split_flags[RTE_FM10K_MAX_RX_BURST] = {0};
 654         unsigned i = 0;
 655
 656         /* Split_flags only can support max of RTE_FM10K_MAX_RX_BURST */
 657         nb_pkts = RTE_MIN(nb_pkts, RTE_FM10K_MAX_RX_BURST);
 658         /* get some new buffers */
 659         uint16_t nb_bufs = fm10k_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 660                         split_flags);
 661         if (nb_bufs == 0)
 662                 return 0;
 663
 664         /* happy day case, full burst + no packets to be joined */
 665         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 666
 667         if (rxq->pkt_first_seg == NULL &&
 668                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 669                         split_fl64[2] == 0 && split_fl64[3] == 0)
 670                 return nb_bufs;
 671
 672         /* reassemble any packets that need reassembly*/
 673         if (rxq->pkt_first_seg == NULL) {
 674                 /* find the first split flag, and only reassemble then*/
 675                 while (i < nb_bufs && !split_flags[i])
 676                         i++;
 677                 if (i == nb_bufs)
 678                         return nb_bufs;
 679         }
 680         return i + fm10k_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 681                 &split_flags[i]);
 682 }
 683
 684 static const struct fm10k_txq_ops vec_txq_ops = {
 685         .reset = fm10k_reset_tx_queue,
 686 };
 687
 688 void __attribute__((cold))
 689 fm10k_txq_vec_setup(struct fm10k_tx_queue *txq)
 690 {
 691         txq->ops = &vec_txq_ops;
 692 }
 693
 694 int __attribute__((cold))
 695 fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq)
 696 {
 697         /* Vector TX can't offload any features yet */
 698         if ((txq->txq_flags & FM10K_SIMPLE_TX_FLAG) != FM10K_SIMPLE_TX_FLAG)
 699                 return -1;
 700
 701         if (txq->tx_ftag_en)
 702                 return -1;
 703
 704         return 0;
 705 }
 706
 707 static inline void
 708 vtx1(volatile struct fm10k_tx_desc *txdp,
 709                 struct rte_mbuf *pkt, uint64_t flags)
 710 {
 711         __m128i descriptor = _mm_set_epi64x(flags << 56 |
 712                         pkt->vlan_tci << 16 | pkt->data_len,
 713                         MBUF_DMA_ADDR(pkt));
 714         _mm_store_si128((__m128i *)txdp, descriptor);
 715 }
 716
 717 static inline void
 718 vtx(volatile struct fm10k_tx_desc *txdp,
 719                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 720 {
 721         int i;
 722
 723         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 724                 vtx1(txdp, *pkt, flags);
 725 }
 726
 727 static __rte_always_inline int
 728 fm10k_tx_free_bufs(struct fm10k_tx_queue *txq)
 729 {
 730         struct rte_mbuf **txep;
 731         uint8_t flags;
 732         uint32_t n;
 733         uint32_t i;
 734         int nb_free = 0;
 735         struct rte_mbuf *m, *free[RTE_FM10K_TX_MAX_FREE_BUF_SZ];
 736
 737         /* check DD bit on threshold descriptor */
 738         flags = txq->hw_ring[txq->next_dd].flags;
 739         if (!(flags & FM10K_TXD_FLAG_DONE))
 740                 return 0;
 741
 742         n = txq->rs_thresh;
 743
 744         /* First buffer to free from S/W ring is at index
 745          * next_dd - (rs_thresh-1)
 746          */
 747         txep = &txq->sw_ring[txq->next_dd - (n - 1)];
 748         m = rte_pktmbuf_prefree_seg(txep[0]);
 749         if (likely(m != NULL)) {
 750                 free[0] = m;
 751                 nb_free = 1;
 752                 for (i = 1; i < n; i++) {
 753                         m = rte_pktmbuf_prefree_seg(txep[i]);
 754                         if (likely(m != NULL)) {
 755                                 if (likely(m->pool == free[0]->pool))
 756                                         free[nb_free++] = m;
 757                                 else {
 758                                         rte_mempool_put_bulk(free[0]->pool,
 759                                                         (void *)free, nb_free);
 760                                         free[0] = m;
 761                                         nb_free = 1;
 762                                 }
 763                         }
 764                 }
 765                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 766         } else {
 767                 for (i = 1; i < n; i++) {
 768                         m = rte_pktmbuf_prefree_seg(txep[i]);
 769                         if (m != NULL)
 770                                 rte_mempool_put(m->pool, m);
 771                 }
 772         }
 773
 774         /* buffers were freed, update counters */
 775         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
 776         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
 777         if (txq->next_dd >= txq->nb_desc)
 778                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
 779
 780         return txq->rs_thresh;
 781 }
 782
 783 static __rte_always_inline void
 784 tx_backlog_entry(struct rte_mbuf **txep,
 785                  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 786 {
 787         int i;
 788
 789         for (i = 0; i < (int)nb_pkts; ++i)
 790                 txep[i] = tx_pkts[i];
 791 }
 792
 793 uint16_t
 794 fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 795                            uint16_t nb_pkts)
 796 {
 797         struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
 798         volatile struct fm10k_tx_desc *txdp;
 799         struct rte_mbuf **txep;
 800         uint16_t n, nb_commit, tx_id;
 801         uint64_t flags = FM10K_TXD_FLAG_LAST;
 802         uint64_t rs = FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_LAST;
 803         int i;
 804
 805         /* cross rx_thresh boundary is not allowed */
 806         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
 807
 808         if (txq->nb_free < txq->free_thresh)
 809                 fm10k_tx_free_bufs(txq);
 810
 811         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
 812         if (unlikely(nb_pkts == 0))
 813                 return 0;
 814
 815         tx_id = txq->next_free;
 816         txdp = &txq->hw_ring[tx_id];
 817         txep = &txq->sw_ring[tx_id];
 818
 819         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
 820
 821         n = (uint16_t)(txq->nb_desc - tx_id);
 822         if (nb_commit >= n) {
 823                 tx_backlog_entry(txep, tx_pkts, n);
 824
 825                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 826                         vtx1(txdp, *tx_pkts, flags);
 827
 828                 vtx1(txdp, *tx_pkts++, rs);
 829
 830                 nb_commit = (uint16_t)(nb_commit - n);
 831
 832                 tx_id = 0;
 833                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 834
 835                 /* avoid reach the end of ring */
 836                 txdp = &(txq->hw_ring[tx_id]);
 837                 txep = &txq->sw_ring[tx_id];
 838         }
 839
 840         tx_backlog_entry(txep, tx_pkts, nb_commit);
 841
 842         vtx(txdp, tx_pkts, nb_commit, flags);
 843
 844         tx_id = (uint16_t)(tx_id + nb_commit);
 845         if (tx_id > txq->next_rs) {
 846                 txq->hw_ring[txq->next_rs].flags |= FM10K_TXD_FLAG_RS;
 847                 txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh);
 848         }
 849
 850         txq->next_free = tx_id;
 851
 852         FM10K_PCI_REG_WRITE(txq->tail_ptr, txq->next_free);
 853
 854         return nb_pkts;
 855 }
 856
 857 static void __attribute__((cold))
 858 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
 859 {
 860         static const struct fm10k_tx_desc zeroed_desc = {0};
 861         struct rte_mbuf **txe = txq->sw_ring;
 862         uint16_t i;
 863
 864         /* Zero out HW ring memory */
 865         for (i = 0; i < txq->nb_desc; i++)
 866                 txq->hw_ring[i] = zeroed_desc;
 867
 868         /* Initialize SW ring entries */
 869         for (i = 0; i < txq->nb_desc; i++)
 870                 txe[i] = NULL;
 871
 872         txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
 873         txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 874
 875         txq->next_free = 0;
 876         txq->nb_used = 0;
 877         /* Always allow 1 descriptor to be un-allocated to avoid
 878          * a H/W race condition
 879          */
 880         txq->nb_free = (uint16_t)(txq->nb_desc - 1);
 881         FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);
 882 }