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36 #include <rte_ethdev.h>
37 #include <rte_common.h>
39 #include "base/fm10k_type.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq);
50 /* Handling the offload flags (olflags) field takes computation
51 * time when receiving packets. Therefore we provide a flag to disable
52 * the processing of the olflags field when they are not needed. This
53 * gives improved performance, at the cost of losing the offload info
54 * in the received packet
56 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
58 /* Vlan present flag shift */
61 #define L3TYPE_SHIFT (4)
63 #define L4TYPE_SHIFT (7)
65 #define HBOFLAG_SHIFT (10)
67 #define RXEFLAG_SHIFT (13)
68 /* IPE/L4E flag shift */
69 #define L3L4EFLAG_SHIFT (14)
70 /* shift PKT_RX_L4_CKSUM_GOOD into one byte by 1 bit */
71 #define CKSUM_SHIFT (1)
74 fm10k_desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
76 __m128i ptype0, ptype1, vtag0, vtag1, eflag0, eflag1, cksumflag;
82 const __m128i pkttype_msk = _mm_set_epi16(
83 0x0000, 0x0000, 0x0000, 0x0000,
84 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT,
85 PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);
87 /* mask everything except rss type */
88 const __m128i rsstype_msk = _mm_set_epi16(
89 0x0000, 0x0000, 0x0000, 0x0000,
90 0x000F, 0x000F, 0x000F, 0x000F);
92 /* mask for HBO and RXE flag flags */
93 const __m128i rxe_msk = _mm_set_epi16(
94 0x0000, 0x0000, 0x0000, 0x0000,
95 0x0001, 0x0001, 0x0001, 0x0001);
97 /* mask the lower byte of ol_flags */
98 const __m128i ol_flags_msk = _mm_set_epi16(
99 0x0000, 0x0000, 0x0000, 0x0000,
100 0x00FF, 0x00FF, 0x00FF, 0x00FF);
102 const __m128i l3l4cksum_flag = _mm_set_epi8(0, 0, 0, 0,
105 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
106 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT,
107 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
108 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT);
110 const __m128i rxe_flag = _mm_set_epi8(0, 0, 0, 0,
115 /* map rss type to rss hash flag */
116 const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
117 0, 0, 0, PKT_RX_RSS_HASH,
118 PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
119 PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
121 /* Calculate RSS_hash and Vlan fields */
122 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
123 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
124 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
125 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
127 ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
128 ptype0 = _mm_and_si128(ptype0, rsstype_msk);
129 ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
131 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
134 vtag1 = _mm_srli_epi16(vtag1, VP_SHIFT);
135 vtag1 = _mm_and_si128(vtag1, pkttype_msk);
137 vtag1 = _mm_or_si128(ptype0, vtag1);
139 /* Process err flags, simply set RECIP_ERR bit if HBO/IXE is set */
140 eflag1 = _mm_srli_epi16(eflag0, RXEFLAG_SHIFT);
141 eflag0 = _mm_srli_epi16(eflag0, HBOFLAG_SHIFT);
142 eflag0 = _mm_or_si128(eflag0, eflag1);
143 eflag0 = _mm_and_si128(eflag0, rxe_msk);
144 eflag0 = _mm_shuffle_epi8(rxe_flag, eflag0);
146 vtag1 = _mm_or_si128(eflag0, vtag1);
148 /* Process L4/L3 checksum error flags */
149 cksumflag = _mm_srli_epi16(cksumflag, L3L4EFLAG_SHIFT);
150 cksumflag = _mm_shuffle_epi8(l3l4cksum_flag, cksumflag);
152 /* clean the higher byte and shift back the flag bits */
153 cksumflag = _mm_and_si128(cksumflag, ol_flags_msk);
154 cksumflag = _mm_slli_epi16(cksumflag, CKSUM_SHIFT);
155 vtag1 = _mm_or_si128(cksumflag, vtag1);
157 vol.dword = _mm_cvtsi128_si64(vtag1);
159 rx_pkts[0]->ol_flags = vol.e[0];
160 rx_pkts[1]->ol_flags = vol.e[1];
161 rx_pkts[2]->ol_flags = vol.e[2];
162 rx_pkts[3]->ol_flags = vol.e[3];
165 /* @note: When this function is changed, make corresponding change to
166 * fm10k_dev_supported_ptypes_get().
169 fm10k_desc_to_pktype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
171 __m128i l3l4type0, l3l4type1, l3type, l4type;
177 /* L3 pkt type mask Bit4 to Bit6 */
178 const __m128i l3type_msk = _mm_set_epi16(
179 0x0000, 0x0000, 0x0000, 0x0000,
180 0x0070, 0x0070, 0x0070, 0x0070);
182 /* L4 pkt type mask Bit7 to Bit9 */
183 const __m128i l4type_msk = _mm_set_epi16(
184 0x0000, 0x0000, 0x0000, 0x0000,
185 0x0380, 0x0380, 0x0380, 0x0380);
187 /* convert RRC l3 type to mbuf format */
188 const __m128i l3type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
189 0, 0, 0, RTE_PTYPE_L3_IPV6_EXT,
190 RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV4_EXT,
191 RTE_PTYPE_L3_IPV4, 0);
193 /* Convert RRC l4 type to mbuf format l4type_flags shift-left 8 bits
194 * to fill into8 bits length.
196 const __m128i l4type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
197 RTE_PTYPE_TUNNEL_GENEVE >> 8,
198 RTE_PTYPE_TUNNEL_NVGRE >> 8,
199 RTE_PTYPE_TUNNEL_VXLAN >> 8,
200 RTE_PTYPE_TUNNEL_GRE >> 8,
201 RTE_PTYPE_L4_UDP >> 8,
202 RTE_PTYPE_L4_TCP >> 8,
205 l3l4type0 = _mm_unpacklo_epi16(descs[0], descs[1]);
206 l3l4type1 = _mm_unpacklo_epi16(descs[2], descs[3]);
207 l3l4type0 = _mm_unpacklo_epi32(l3l4type0, l3l4type1);
209 l3type = _mm_and_si128(l3l4type0, l3type_msk);
210 l4type = _mm_and_si128(l3l4type0, l4type_msk);
212 l3type = _mm_srli_epi16(l3type, L3TYPE_SHIFT);
213 l4type = _mm_srli_epi16(l4type, L4TYPE_SHIFT);
215 l3type = _mm_shuffle_epi8(l3type_flags, l3type);
216 /* l4type_flags shift-left for 8 bits, need shift-right back */
217 l4type = _mm_shuffle_epi8(l4type_flags, l4type);
219 l4type = _mm_slli_epi16(l4type, 8);
220 l3l4type0 = _mm_or_si128(l3type, l4type);
221 vol.dword = _mm_cvtsi128_si64(l3l4type0);
223 rx_pkts[0]->packet_type = vol.e[0];
224 rx_pkts[1]->packet_type = vol.e[1];
225 rx_pkts[2]->packet_type = vol.e[2];
226 rx_pkts[3]->packet_type = vol.e[3];
229 #define fm10k_desc_to_olflags_v(desc, rx_pkts) do {} while (0)
230 #define fm10k_desc_to_pktype_v(desc, rx_pkts) do {} while (0)
233 int __attribute__((cold))
234 fm10k_rx_vec_condition_check(struct rte_eth_dev *dev)
236 #ifndef RTE_LIBRTE_IEEE1588
237 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
238 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
240 #ifndef RTE_FM10K_RX_OLFLAGS_ENABLE
241 /* whithout rx ol_flags, no VP flag report */
242 if (rxmode->hw_vlan_extend != 0)
246 /* no fdir support */
247 if (fconf->mode != RTE_FDIR_MODE_NONE)
250 /* no header split support */
251 if (rxmode->header_split == 1)
261 int __attribute__((cold))
262 fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)
265 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
268 /* data_off will be ajusted after new mbuf allocated for 512-byte
271 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
272 mb_def.port = rxq->port_id;
273 rte_mbuf_refcnt_set(&mb_def, 1);
275 /* prevent compiler reordering: rearm_data covers previous fields */
276 rte_compiler_barrier();
277 p = (uintptr_t)&mb_def.rearm_data;
278 rxq->mbuf_initializer = *(uint64_t *)p;
283 fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)
287 volatile union fm10k_rx_desc *rxdp;
288 struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];
289 struct rte_mbuf *mb0, *mb1;
290 __m128i head_off = _mm_set_epi64x(
291 RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,
292 RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);
293 __m128i dma_addr0, dma_addr1;
294 /* Rx buffer need to be aligned with 512 byte */
295 const __m128i hba_msk = _mm_set_epi64x(0,
296 UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);
298 rxdp = rxq->hw_ring + rxq->rxrearm_start;
300 /* Pull 'n' more MBUFs into the software ring */
301 if (rte_mempool_get_bulk(rxq->mp,
303 RTE_FM10K_RXQ_REARM_THRESH) < 0) {
304 dma_addr0 = _mm_setzero_si128();
305 /* Clean up all the HW/SW ring content */
306 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) {
307 mb_alloc[i] = &rxq->fake_mbuf;
308 _mm_store_si128((__m128i *)&rxdp[i].q,
312 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
313 RTE_FM10K_RXQ_REARM_THRESH;
317 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
318 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {
319 __m128i vaddr0, vaddr1;
325 /* Flush mbuf with pkt template.
326 * Data to be rearmed is 6 bytes long.
328 p0 = (uintptr_t)&mb0->rearm_data;
329 *(uint64_t *)p0 = rxq->mbuf_initializer;
330 p1 = (uintptr_t)&mb1->rearm_data;
331 *(uint64_t *)p1 = rxq->mbuf_initializer;
333 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
334 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
335 offsetof(struct rte_mbuf, buf_addr) + 8);
336 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
337 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
339 /* convert pa to dma_addr hdr/data */
340 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
341 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
343 /* add headroom to pa values */
344 dma_addr0 = _mm_add_epi64(dma_addr0, head_off);
345 dma_addr1 = _mm_add_epi64(dma_addr1, head_off);
347 /* Do 512 byte alignment to satisfy HW requirement, in the
348 * meanwhile, set Header Buffer Address to zero.
350 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
351 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
353 /* flush desc with pa dma_addr */
354 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);
355 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);
357 /* enforce 512B alignment on default Rx virtual addresses */
358 mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr
359 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
360 - (char *)mb0->buf_addr);
361 mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr
362 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
363 - (char *)mb1->buf_addr);
366 rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;
367 if (rxq->rxrearm_start >= rxq->nb_desc)
368 rxq->rxrearm_start = 0;
370 rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;
372 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
373 (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));
375 /* Update the tail pointer on the NIC */
376 FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);
379 void __attribute__((cold))
380 fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq)
382 const unsigned mask = rxq->nb_desc - 1;
385 if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_desc)
388 /* free all mbufs that are valid in the ring */
389 for (i = rxq->next_dd; i != rxq->rxrearm_start; i = (i + 1) & mask)
390 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
391 rxq->rxrearm_nb = rxq->nb_desc;
393 /* set all entries to NULL */
394 memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_desc);
397 static inline uint16_t
398 fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
399 uint16_t nb_pkts, uint8_t *split_packet)
401 volatile union fm10k_rx_desc *rxdp;
402 struct rte_mbuf **mbufp;
403 uint16_t nb_pkts_recd;
405 struct fm10k_rx_queue *rxq = rx_queue;
408 __m128i dd_check, eop_check;
411 next_dd = rxq->next_dd;
413 /* Just the act of getting into the function from the application is
414 * going to cost about 7 cycles
416 rxdp = rxq->hw_ring + next_dd;
420 /* See if we need to rearm the RX queue - gives the prefetch a bit
423 if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH)
424 fm10k_rxq_rearm(rxq);
426 /* Before we start moving massive data around, check to see if
427 * there is actually a packet available
429 if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD))
432 /* Vecotr RX will process 4 packets at a time, strip the unaligned
433 * tails in case it's not multiple of 4.
435 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP);
437 /* 4 packets DD mask */
438 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
440 /* 4 packets EOP mask */
441 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
443 /* mask to shuffle from desc. to mbuf */
444 shuf_msk = _mm_set_epi8(
445 7, 6, 5, 4, /* octet 4~7, 32bits rss */
446 15, 14, /* octet 14~15, low 16 bits vlan_macip */
447 13, 12, /* octet 12~13, 16 bits data_len */
448 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
449 13, 12, /* octet 12~13, low 16 bits pkt_len */
450 0xFF, 0xFF, /* skip high 16 bits pkt_type */
451 0xFF, 0xFF /* Skip pkt_type field in shuffle operation */
454 * Compile-time verify the shuffle mask
455 * NOTE: some field positions already verified above, but duplicated
456 * here for completeness in case of future modifications.
458 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
459 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
460 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
461 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
462 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
463 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
464 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
465 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
467 /* Cache is empty -> need to scan the buffer rings, but first move
468 * the next 'n' mbufs into the cache
470 mbufp = &rxq->sw_ring[next_dd];
472 /* A. load 4 packet in one loop
473 * [A*. mask out 4 unused dirty field in desc]
474 * B. copy 4 mbuf point from swring to rx_pkts
475 * C. calc the number of DD bits among the 4 packets
476 * [C*. extract the end-of-packet bit, if requested]
477 * D. fill info. from desc to mbuf
479 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
480 pos += RTE_FM10K_DESCS_PER_LOOP,
481 rxdp += RTE_FM10K_DESCS_PER_LOOP) {
482 __m128i descs0[RTE_FM10K_DESCS_PER_LOOP];
483 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
484 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
486 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
487 #if defined(RTE_ARCH_X86_64)
491 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
492 mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]);
494 /* Read desc statuses backwards to avoid race condition */
495 /* A.1 load 4 pkts desc */
496 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
497 rte_compiler_barrier();
499 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
500 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
502 #if defined(RTE_ARCH_X86_64)
503 /* B.1 load 2 64 bit mbuf poitns */
504 mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]);
507 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
508 rte_compiler_barrier();
509 /* B.1 load 2 mbuf point */
510 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
511 rte_compiler_barrier();
512 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
514 #if defined(RTE_ARCH_X86_64)
515 /* B.2 copy 2 mbuf point into rx_pkts */
516 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
519 /* avoid compiler reorder optimization */
520 rte_compiler_barrier();
523 rte_mbuf_prefetch_part2(rx_pkts[pos]);
524 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
525 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
526 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
529 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
530 pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk);
531 pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk);
533 /* C.1 4=>2 filter staterr info only */
534 sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]);
535 /* C.1 4=>2 filter staterr info only */
536 sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]);
538 /* set ol_flags with vlan packet type */
539 fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]);
541 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
542 pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk);
543 pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk);
545 /* C.2 get 4 pkts staterr value */
546 zero = _mm_xor_si128(dd_check, dd_check);
547 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
549 /* D.3 copy final 3,4 data to rx_pkts */
550 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
552 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
555 /* C* extract and record EOP bit */
557 __m128i eop_shuf_mask = _mm_set_epi8(
558 0xFF, 0xFF, 0xFF, 0xFF,
559 0xFF, 0xFF, 0xFF, 0xFF,
560 0xFF, 0xFF, 0xFF, 0xFF,
561 0x04, 0x0C, 0x00, 0x08
564 /* and with mask to extract bits, flipping 1-0 */
565 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
566 /* the staterr values are not in order, as the count
567 * count of dd bits doesn't care. However, for end of
568 * packet tracking, we do care, so shuffle. This also
569 * compresses the 32-bit values to 8-bit
571 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
572 /* store the resulting 32-bit value */
573 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
574 split_packet += RTE_FM10K_DESCS_PER_LOOP;
576 /* zero-out next pointers */
577 rx_pkts[pos]->next = NULL;
578 rx_pkts[pos + 1]->next = NULL;
579 rx_pkts[pos + 2]->next = NULL;
580 rx_pkts[pos + 3]->next = NULL;
583 /* C.3 calc available number of desc */
584 staterr = _mm_and_si128(staterr, dd_check);
585 staterr = _mm_packs_epi32(staterr, zero);
587 /* D.3 copy final 1,2 data to rx_pkts */
588 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
590 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
593 fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]);
595 /* C.4 calc avaialbe number of desc */
596 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
598 if (likely(var != RTE_FM10K_DESCS_PER_LOOP))
602 /* Update our internal tail pointer */
603 rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd);
604 rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1));
605 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
610 /* vPMD receive routine
613 * - don't support ol_flags for rss and csum err
616 fm10k_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
619 return fm10k_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
622 static inline uint16_t
623 fm10k_reassemble_packets(struct fm10k_rx_queue *rxq,
624 struct rte_mbuf **rx_bufs,
625 uint16_t nb_bufs, uint8_t *split_flags)
627 struct rte_mbuf *pkts[RTE_FM10K_MAX_RX_BURST]; /*finished pkts*/
628 struct rte_mbuf *start = rxq->pkt_first_seg;
629 struct rte_mbuf *end = rxq->pkt_last_seg;
630 unsigned pkt_idx, buf_idx;
632 for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
634 /* processing a split packet */
635 end->next = rx_bufs[buf_idx];
637 start->pkt_len += rx_bufs[buf_idx]->data_len;
640 if (!split_flags[buf_idx]) {
641 /* it's the last packet of the set */
642 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
643 start->hash = end->hash;
644 start->ol_flags = end->ol_flags;
645 start->packet_type = end->packet_type;
647 pkts[pkt_idx++] = start;
651 /* not processing a split packet */
652 if (!split_flags[buf_idx]) {
653 /* not a split packet, save and skip */
654 pkts[pkt_idx++] = rx_bufs[buf_idx];
657 end = start = rx_bufs[buf_idx];
661 /* save the partial packet for next time */
662 rxq->pkt_first_seg = start;
663 rxq->pkt_last_seg = end;
664 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
669 * vPMD receive routine that reassembles scattered packets
672 * - don't support ol_flags for rss and csum err
673 * - nb_pkts > RTE_FM10K_MAX_RX_BURST, only scan RTE_FM10K_MAX_RX_BURST
677 fm10k_recv_scattered_pkts_vec(void *rx_queue,
678 struct rte_mbuf **rx_pkts,
681 struct fm10k_rx_queue *rxq = rx_queue;
682 uint8_t split_flags[RTE_FM10K_MAX_RX_BURST] = {0};
685 /* Split_flags only can support max of RTE_FM10K_MAX_RX_BURST */
686 nb_pkts = RTE_MIN(nb_pkts, RTE_FM10K_MAX_RX_BURST);
687 /* get some new buffers */
688 uint16_t nb_bufs = fm10k_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
693 /* happy day case, full burst + no packets to be joined */
694 const uint64_t *split_fl64 = (uint64_t *)split_flags;
696 if (rxq->pkt_first_seg == NULL &&
697 split_fl64[0] == 0 && split_fl64[1] == 0 &&
698 split_fl64[2] == 0 && split_fl64[3] == 0)
701 /* reassemble any packets that need reassembly*/
702 if (rxq->pkt_first_seg == NULL) {
703 /* find the first split flag, and only reassemble then*/
704 while (i < nb_bufs && !split_flags[i])
709 return i + fm10k_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
713 static const struct fm10k_txq_ops vec_txq_ops = {
714 .reset = fm10k_reset_tx_queue,
717 void __attribute__((cold))
718 fm10k_txq_vec_setup(struct fm10k_tx_queue *txq)
720 txq->ops = &vec_txq_ops;
723 int __attribute__((cold))
724 fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq)
726 /* Vector TX can't offload any features yet */
727 if ((txq->txq_flags & FM10K_SIMPLE_TX_FLAG) != FM10K_SIMPLE_TX_FLAG)
737 vtx1(volatile struct fm10k_tx_desc *txdp,
738 struct rte_mbuf *pkt, uint64_t flags)
740 __m128i descriptor = _mm_set_epi64x(flags << 56 |
741 pkt->vlan_tci << 16 | pkt->data_len,
743 _mm_store_si128((__m128i *)txdp, descriptor);
747 vtx(volatile struct fm10k_tx_desc *txdp,
748 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
752 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
753 vtx1(txdp, *pkt, flags);
756 static __rte_always_inline int
757 fm10k_tx_free_bufs(struct fm10k_tx_queue *txq)
759 struct rte_mbuf **txep;
764 struct rte_mbuf *m, *free[RTE_FM10K_TX_MAX_FREE_BUF_SZ];
766 /* check DD bit on threshold descriptor */
767 flags = txq->hw_ring[txq->next_dd].flags;
768 if (!(flags & FM10K_TXD_FLAG_DONE))
773 /* First buffer to free from S/W ring is at index
774 * next_dd - (rs_thresh-1)
776 txep = &txq->sw_ring[txq->next_dd - (n - 1)];
777 m = rte_pktmbuf_prefree_seg(txep[0]);
778 if (likely(m != NULL)) {
781 for (i = 1; i < n; i++) {
782 m = rte_pktmbuf_prefree_seg(txep[i]);
783 if (likely(m != NULL)) {
784 if (likely(m->pool == free[0]->pool))
787 rte_mempool_put_bulk(free[0]->pool,
788 (void *)free, nb_free);
794 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
796 for (i = 1; i < n; i++) {
797 m = rte_pktmbuf_prefree_seg(txep[i]);
799 rte_mempool_put(m->pool, m);
803 /* buffers were freed, update counters */
804 txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
805 txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
806 if (txq->next_dd >= txq->nb_desc)
807 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
809 return txq->rs_thresh;
812 static __rte_always_inline void
813 tx_backlog_entry(struct rte_mbuf **txep,
814 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
818 for (i = 0; i < (int)nb_pkts; ++i)
819 txep[i] = tx_pkts[i];
823 fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
826 struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
827 volatile struct fm10k_tx_desc *txdp;
828 struct rte_mbuf **txep;
829 uint16_t n, nb_commit, tx_id;
830 uint64_t flags = FM10K_TXD_FLAG_LAST;
831 uint64_t rs = FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_LAST;
834 /* cross rx_thresh boundary is not allowed */
835 nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
837 if (txq->nb_free < txq->free_thresh)
838 fm10k_tx_free_bufs(txq);
840 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
841 if (unlikely(nb_pkts == 0))
844 tx_id = txq->next_free;
845 txdp = &txq->hw_ring[tx_id];
846 txep = &txq->sw_ring[tx_id];
848 txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
850 n = (uint16_t)(txq->nb_desc - tx_id);
851 if (nb_commit >= n) {
852 tx_backlog_entry(txep, tx_pkts, n);
854 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
855 vtx1(txdp, *tx_pkts, flags);
857 vtx1(txdp, *tx_pkts++, rs);
859 nb_commit = (uint16_t)(nb_commit - n);
862 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
864 /* avoid reach the end of ring */
865 txdp = &(txq->hw_ring[tx_id]);
866 txep = &txq->sw_ring[tx_id];
869 tx_backlog_entry(txep, tx_pkts, nb_commit);
871 vtx(txdp, tx_pkts, nb_commit, flags);
873 tx_id = (uint16_t)(tx_id + nb_commit);
874 if (tx_id > txq->next_rs) {
875 txq->hw_ring[txq->next_rs].flags |= FM10K_TXD_FLAG_RS;
876 txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh);
879 txq->next_free = tx_id;
881 FM10K_PCI_REG_WRITE(txq->tail_ptr, txq->next_free);
886 static void __attribute__((cold))
887 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
889 static const struct fm10k_tx_desc zeroed_desc = {0};
890 struct rte_mbuf **txe = txq->sw_ring;
893 /* Zero out HW ring memory */
894 for (i = 0; i < txq->nb_desc; i++)
895 txq->hw_ring[i] = zeroed_desc;
897 /* Initialize SW ring entries */
898 for (i = 0; i < txq->nb_desc; i++)
901 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
902 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
906 /* Always allow 1 descriptor to be un-allocated to avoid
907 * a H/W race condition
909 txq->nb_free = (uint16_t)(txq->nb_desc - 1);
910 FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);