drivers/net/fm10k/fm10k_rxtx_vec.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <inttypes.h>
  35
  36 #include <rte_ethdev.h>
  37 #include <rte_common.h>
  38 #include "fm10k.h"
  39 #include "base/fm10k_type.h"
  40
  41 #include <tmmintrin.h>
  42
  43 #ifndef __INTEL_COMPILER
  44 #pragma GCC diagnostic ignored "-Wcast-qual"
  45 #endif
  46
  47 static void
  48 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq);
  49
  50 /* Handling the offload flags (olflags) field takes computation
  51  * time when receiving packets. Therefore we provide a flag to disable
  52  * the processing of the olflags field when they are not needed. This
  53  * gives improved performance, at the cost of losing the offload info
  54  * in the received packet
  55  */
  56 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
  57
  58 /* Vlan present flag shift */
  59 #define VP_SHIFT     (2)
  60 /* L3 type shift */
  61 #define L3TYPE_SHIFT     (4)
  62 /* L4 type shift */
  63 #define L4TYPE_SHIFT     (7)
  64
  65 static inline void
  66 fm10k_desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
  67 {
  68         __m128i ptype0, ptype1, vtag0, vtag1;
  69         union {
  70                 uint16_t e[4];
  71                 uint64_t dword;
  72         } vol;
  73
  74         const __m128i pkttype_msk = _mm_set_epi16(
  75                         0x0000, 0x0000, 0x0000, 0x0000,
  76                         PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT,
  77                         PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);
  78
  79         /* mask everything except rss type */
  80         const __m128i rsstype_msk = _mm_set_epi16(
  81                         0x0000, 0x0000, 0x0000, 0x0000,
  82                         0x000F, 0x000F, 0x000F, 0x000F);
  83
  84         /* map rss type to rss hash flag */
  85         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
  86                         0, 0, 0, PKT_RX_RSS_HASH,
  87                         PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,
  88                         PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);
  89
  90         ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
  91         ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
  92         vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
  93         vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
  94
  95         ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
  96         ptype0 = _mm_and_si128(ptype0, rsstype_msk);
  97         ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
  98
  99         vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
 100         vtag1 = _mm_srli_epi16(vtag1, VP_SHIFT);
 101         vtag1 = _mm_and_si128(vtag1, pkttype_msk);
 102
 103         vtag1 = _mm_or_si128(ptype0, vtag1);
 104         vol.dword = _mm_cvtsi128_si64(vtag1);
 105
 106         rx_pkts[0]->ol_flags = vol.e[0];
 107         rx_pkts[1]->ol_flags = vol.e[1];
 108         rx_pkts[2]->ol_flags = vol.e[2];
 109         rx_pkts[3]->ol_flags = vol.e[3];
 110 }
 111
 112 static inline void
 113 fm10k_desc_to_pktype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 114 {
 115         __m128i l3l4type0, l3l4type1, l3type, l4type;
 116         union {
 117                 uint16_t e[4];
 118                 uint64_t dword;
 119         } vol;
 120
 121         /* L3 pkt type mask  Bit4 to Bit6 */
 122         const __m128i l3type_msk = _mm_set_epi16(
 123                         0x0000, 0x0000, 0x0000, 0x0000,
 124                         0x0070, 0x0070, 0x0070, 0x0070);
 125
 126         /* L4 pkt type mask  Bit7 to Bit9 */
 127         const __m128i l4type_msk = _mm_set_epi16(
 128                         0x0000, 0x0000, 0x0000, 0x0000,
 129                         0x0380, 0x0380, 0x0380, 0x0380);
 130
 131         /* convert RRC l3 type to mbuf format */
 132         const __m128i l3type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 133                         0, 0, 0, RTE_PTYPE_L3_IPV6_EXT,
 134                         RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV4_EXT,
 135                         RTE_PTYPE_L3_IPV4, 0);
 136
 137         /* Convert RRC l4 type to mbuf format l4type_flags shift-left 8 bits
 138          * to fill into8 bits length.
 139          */
 140         const __m128i l4type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
 141                         RTE_PTYPE_TUNNEL_GENEVE >> 8,
 142                         RTE_PTYPE_TUNNEL_NVGRE >> 8,
 143                         RTE_PTYPE_TUNNEL_VXLAN >> 8,
 144                         RTE_PTYPE_TUNNEL_GRE >> 8,
 145                         RTE_PTYPE_L4_UDP >> 8,
 146                         RTE_PTYPE_L4_TCP >> 8,
 147                         0);
 148
 149         l3l4type0 = _mm_unpacklo_epi16(descs[0], descs[1]);
 150         l3l4type1 = _mm_unpacklo_epi16(descs[2], descs[3]);
 151         l3l4type0 = _mm_unpacklo_epi32(l3l4type0, l3l4type1);
 152
 153         l3type = _mm_and_si128(l3l4type0, l3type_msk);
 154         l4type = _mm_and_si128(l3l4type0, l4type_msk);
 155
 156         l3type = _mm_srli_epi16(l3type, L3TYPE_SHIFT);
 157         l4type = _mm_srli_epi16(l4type, L4TYPE_SHIFT);
 158
 159         l3type = _mm_shuffle_epi8(l3type_flags, l3type);
 160         /* l4type_flags shift-left for 8 bits, need shift-right back */
 161         l4type = _mm_shuffle_epi8(l4type_flags, l4type);
 162
 163         l4type = _mm_slli_epi16(l4type, 8);
 164         l3l4type0 = _mm_or_si128(l3type, l4type);
 165         vol.dword = _mm_cvtsi128_si64(l3l4type0);
 166
 167         rx_pkts[0]->packet_type = vol.e[0];
 168         rx_pkts[1]->packet_type = vol.e[1];
 169         rx_pkts[2]->packet_type = vol.e[2];
 170         rx_pkts[3]->packet_type = vol.e[3];
 171 }
 172 #else
 173 #define fm10k_desc_to_olflags_v(desc, rx_pkts) do {} while (0)
 174 #define fm10k_desc_to_pktype_v(desc, rx_pkts) do {} while (0)
 175 #endif
 176
 177 int __attribute__((cold))
 178 fm10k_rx_vec_condition_check(struct rte_eth_dev *dev)
 179 {
 180 #ifndef RTE_LIBRTE_IEEE1588
 181         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 182         struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
 183
 184 #ifndef RTE_FM10K_RX_OLFLAGS_ENABLE
 185         /* whithout rx ol_flags, no VP flag report */
 186         if (rxmode->hw_vlan_extend != 0)
 187                 return -1;
 188 #endif
 189
 190         /* no fdir support */
 191         if (fconf->mode != RTE_FDIR_MODE_NONE)
 192                 return -1;
 193
 194         /* - no csum error report support
 195          * - no header split support
 196          */
 197         if (rxmode->hw_ip_checksum == 1 ||
 198             rxmode->header_split == 1)
 199                 return -1;
 200
 201         return 0;
 202 #else
 203         RTE_SET_USED(dev);
 204         return -1;
 205 #endif
 206 }
 207
 208 int __attribute__((cold))
 209 fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)
 210 {
 211         uintptr_t p;
 212         struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
 213
 214         mb_def.nb_segs = 1;
 215         /* data_off will be ajusted after new mbuf allocated for 512-byte
 216          * alignment.
 217          */
 218         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
 219         mb_def.port = rxq->port_id;
 220         rte_mbuf_refcnt_set(&mb_def, 1);
 221
 222         /* prevent compiler reordering: rearm_data covers previous fields */
 223         rte_compiler_barrier();
 224         p = (uintptr_t)&mb_def.rearm_data;
 225         rxq->mbuf_initializer = *(uint64_t *)p;
 226         return 0;
 227 }
 228
 229 static inline void
 230 fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)
 231 {
 232         int i;
 233         uint16_t rx_id;
 234         volatile union fm10k_rx_desc *rxdp;
 235         struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];
 236         struct rte_mbuf *mb0, *mb1;
 237         __m128i head_off = _mm_set_epi64x(
 238                         RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,
 239                         RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);
 240         __m128i dma_addr0, dma_addr1;
 241         /* Rx buffer need to be aligned with 512 byte */
 242         const __m128i hba_msk = _mm_set_epi64x(0,
 243                                 UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);
 244
 245         rxdp = rxq->hw_ring + rxq->rxrearm_start;
 246
 247         /* Pull 'n' more MBUFs into the software ring */
 248         if (rte_mempool_get_bulk(rxq->mp,
 249                                  (void *)mb_alloc,
 250                                  RTE_FM10K_RXQ_REARM_THRESH) < 0) {
 251                 dma_addr0 = _mm_setzero_si128();
 252                 /* Clean up all the HW/SW ring content */
 253                 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) {
 254                         mb_alloc[i] = &rxq->fake_mbuf;
 255                         _mm_store_si128((__m128i *)&rxdp[i].q,
 256                                                 dma_addr0);
 257                 }
 258
 259                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
 260                         RTE_FM10K_RXQ_REARM_THRESH;
 261                 return;
 262         }
 263
 264         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
 265         for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {
 266                 __m128i vaddr0, vaddr1;
 267                 uintptr_t p0, p1;
 268
 269                 mb0 = mb_alloc[0];
 270                 mb1 = mb_alloc[1];
 271
 272                 /* Flush mbuf with pkt template.
 273                  * Data to be rearmed is 6 bytes long.
 274                  * Though, RX will overwrite ol_flags that are coming next
 275                  * anyway. So overwrite whole 8 bytes with one load:
 276                  * 6 bytes of rearm_data plus first 2 bytes of ol_flags.
 277                  */
 278                 p0 = (uintptr_t)&mb0->rearm_data;
 279                 *(uint64_t *)p0 = rxq->mbuf_initializer;
 280                 p1 = (uintptr_t)&mb1->rearm_data;
 281                 *(uint64_t *)p1 = rxq->mbuf_initializer;
 282
 283                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
 284                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 285                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 286
 287                 /* convert pa to dma_addr hdr/data */
 288                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
 289                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
 290
 291                 /* add headroom to pa values */
 292                 dma_addr0 = _mm_add_epi64(dma_addr0, head_off);
 293                 dma_addr1 = _mm_add_epi64(dma_addr1, head_off);
 294
 295                 /* Do 512 byte alignment to satisfy HW requirement, in the
 296                  * meanwhile, set Header Buffer Address to zero.
 297                  */
 298                 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
 299                 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
 300
 301                 /* flush desc with pa dma_addr */
 302                 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);
 303                 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);
 304
 305                 /* enforce 512B alignment on default Rx virtual addresses */
 306                 mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr
 307                                 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
 308                                 - (char *)mb0->buf_addr);
 309                 mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr
 310                                 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
 311                                 - (char *)mb1->buf_addr);
 312         }
 313
 314         rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;
 315         if (rxq->rxrearm_start >= rxq->nb_desc)
 316                 rxq->rxrearm_start = 0;
 317
 318         rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;
 319
 320         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 321                         (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));
 322
 323         /* Update the tail pointer on the NIC */
 324         FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);
 325 }
 326
 327 void __attribute__((cold))
 328 fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq)
 329 {
 330         const unsigned mask = rxq->nb_desc - 1;
 331         unsigned i;
 332
 333         if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_desc)
 334                 return;
 335
 336         /* free all mbufs that are valid in the ring */
 337         for (i = rxq->next_dd; i != rxq->rxrearm_start; i = (i + 1) & mask)
 338                 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 339         rxq->rxrearm_nb = rxq->nb_desc;
 340
 341         /* set all entries to NULL */
 342         memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_desc);
 343 }
 344
 345 static inline uint16_t
 346 fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 347                 uint16_t nb_pkts, uint8_t *split_packet)
 348 {
 349         volatile union fm10k_rx_desc *rxdp;
 350         struct rte_mbuf **mbufp;
 351         uint16_t nb_pkts_recd;
 352         int pos;
 353         struct fm10k_rx_queue *rxq = rx_queue;
 354         uint64_t var;
 355         __m128i shuf_msk;
 356         __m128i dd_check, eop_check;
 357         uint16_t next_dd;
 358
 359         next_dd = rxq->next_dd;
 360
 361         /* Just the act of getting into the function from the application is
 362          * going to cost about 7 cycles
 363          */
 364         rxdp = rxq->hw_ring + next_dd;
 365
 366         _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
 367
 368         /* See if we need to rearm the RX queue - gives the prefetch a bit
 369          * of time to act
 370          */
 371         if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH)
 372                 fm10k_rxq_rearm(rxq);
 373
 374         /* Before we start moving massive data around, check to see if
 375          * there is actually a packet available
 376          */
 377         if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD))
 378                 return 0;
 379
 380         /* Vecotr RX will process 4 packets at a time, strip the unaligned
 381          * tails in case it's not multiple of 4.
 382          */
 383         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP);
 384
 385         /* 4 packets DD mask */
 386         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 387
 388         /* 4 packets EOP mask */
 389         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 390
 391         /* mask to shuffle from desc. to mbuf */
 392         shuf_msk = _mm_set_epi8(
 393                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 394                 15, 14,      /* octet 14~15, low 16 bits vlan_macip */
 395                 13, 12,      /* octet 12~13, 16 bits data_len */
 396                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 397                 13, 12,      /* octet 12~13, low 16 bits pkt_len */
 398                 0xFF, 0xFF,  /* skip high 16 bits pkt_type */
 399                 0xFF, 0xFF   /* Skip pkt_type field in shuffle operation */
 400                 );
 401
 402         /* Cache is empty -> need to scan the buffer rings, but first move
 403          * the next 'n' mbufs into the cache
 404          */
 405         mbufp = &rxq->sw_ring[next_dd];
 406
 407         /* A. load 4 packet in one loop
 408          * [A*. mask out 4 unused dirty field in desc]
 409          * B. copy 4 mbuf point from swring to rx_pkts
 410          * C. calc the number of DD bits among the 4 packets
 411          * [C*. extract the end-of-packet bit, if requested]
 412          * D. fill info. from desc to mbuf
 413          */
 414         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 415                         pos += RTE_FM10K_DESCS_PER_LOOP,
 416                         rxdp += RTE_FM10K_DESCS_PER_LOOP) {
 417                 __m128i descs0[RTE_FM10K_DESCS_PER_LOOP];
 418                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 419                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 420                 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
 421
 422                 /* B.1 load 1 mbuf point */
 423                 mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]);
 424
 425                 /* Read desc statuses backwards to avoid race condition */
 426                 /* A.1 load 4 pkts desc */
 427                 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 428
 429                 /* B.2 copy 2 mbuf point into rx_pkts  */
 430                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 431
 432                 /* B.1 load 1 mbuf point */
 433                 mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]);
 434
 435                 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 436                 /* B.1 load 2 mbuf point */
 437                 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 438                 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
 439
 440                 /* B.2 copy 2 mbuf point into rx_pkts  */
 441                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 442
 443                 /* avoid compiler reorder optimization */
 444                 rte_compiler_barrier();
 445
 446                 if (split_packet) {
 447                         rte_prefetch0(&rx_pkts[pos]->cacheline1);
 448                         rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
 449                         rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
 450                         rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
 451                 }
 452
 453                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 454                 pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk);
 455                 pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk);
 456
 457                 /* C.1 4=>2 filter staterr info only */
 458                 sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]);
 459                 /* C.1 4=>2 filter staterr info only */
 460                 sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]);
 461
 462                 /* set ol_flags with vlan packet type */
 463                 fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]);
 464
 465                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 466                 pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk);
 467                 pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk);
 468
 469                 /* C.2 get 4 pkts staterr value  */
 470                 zero = _mm_xor_si128(dd_check, dd_check);
 471                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 472
 473                 /* D.3 copy final 3,4 data to rx_pkts */
 474                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 475                                 pkt_mb4);
 476                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 477                                 pkt_mb3);
 478
 479                 /* C* extract and record EOP bit */
 480                 if (split_packet) {
 481                         __m128i eop_shuf_mask = _mm_set_epi8(
 482                                         0xFF, 0xFF, 0xFF, 0xFF,
 483                                         0xFF, 0xFF, 0xFF, 0xFF,
 484                                         0xFF, 0xFF, 0xFF, 0xFF,
 485                                         0x04, 0x0C, 0x00, 0x08
 486                                         );
 487
 488                         /* and with mask to extract bits, flipping 1-0 */
 489                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 490                         /* the staterr values are not in order, as the count
 491                          * count of dd bits doesn't care. However, for end of
 492                          * packet tracking, we do care, so shuffle. This also
 493                          * compresses the 32-bit values to 8-bit
 494                          */
 495                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 496                         /* store the resulting 32-bit value */
 497                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 498                         split_packet += RTE_FM10K_DESCS_PER_LOOP;
 499
 500                         /* zero-out next pointers */
 501                         rx_pkts[pos]->next = NULL;
 502                         rx_pkts[pos + 1]->next = NULL;
 503                         rx_pkts[pos + 2]->next = NULL;
 504                         rx_pkts[pos + 3]->next = NULL;
 505                 }
 506
 507                 /* C.3 calc available number of desc */
 508                 staterr = _mm_and_si128(staterr, dd_check);
 509                 staterr = _mm_packs_epi32(staterr, zero);
 510
 511                 /* D.3 copy final 1,2 data to rx_pkts */
 512                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 513                                 pkt_mb2);
 514                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 515                                 pkt_mb1);
 516
 517                 fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]);
 518
 519                 /* C.4 calc avaialbe number of desc */
 520                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 521                 nb_pkts_recd += var;
 522                 if (likely(var != RTE_FM10K_DESCS_PER_LOOP))
 523                         break;
 524         }
 525
 526         /* Update our internal tail pointer */
 527         rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd);
 528         rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1));
 529         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 530
 531         return nb_pkts_recd;
 532 }
 533
 534 /* vPMD receive routine
 535  *
 536  * Notice:
 537  * - don't support ol_flags for rss and csum err
 538  */
 539 uint16_t
 540 fm10k_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 541                 uint16_t nb_pkts)
 542 {
 543         return fm10k_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 544 }
 545
 546 static inline uint16_t
 547 fm10k_reassemble_packets(struct fm10k_rx_queue *rxq,
 548                 struct rte_mbuf **rx_bufs,
 549                 uint16_t nb_bufs, uint8_t *split_flags)
 550 {
 551         struct rte_mbuf *pkts[RTE_FM10K_MAX_RX_BURST]; /*finished pkts*/
 552         struct rte_mbuf *start = rxq->pkt_first_seg;
 553         struct rte_mbuf *end =  rxq->pkt_last_seg;
 554         unsigned pkt_idx, buf_idx;
 555
 556         for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
 557                 if (end != NULL) {
 558                         /* processing a split packet */
 559                         end->next = rx_bufs[buf_idx];
 560                         start->nb_segs++;
 561                         start->pkt_len += rx_bufs[buf_idx]->data_len;
 562                         end = end->next;
 563
 564                         if (!split_flags[buf_idx]) {
 565                                 /* it's the last packet of the set */
 566                                 start->hash = end->hash;
 567                                 start->ol_flags = end->ol_flags;
 568                                 pkts[pkt_idx++] = start;
 569                                 start = end = NULL;
 570                         }
 571                 } else {
 572                         /* not processing a split packet */
 573                         if (!split_flags[buf_idx]) {
 574                                 /* not a split packet, save and skip */
 575                                 pkts[pkt_idx++] = rx_bufs[buf_idx];
 576                                 continue;
 577                         }
 578                         end = start = rx_bufs[buf_idx];
 579                 }
 580         }
 581
 582         /* save the partial packet for next time */
 583         rxq->pkt_first_seg = start;
 584         rxq->pkt_last_seg = end;
 585         memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
 586         return pkt_idx;
 587 }
 588
 589 /*
 590  * vPMD receive routine that reassembles scattered packets
 591  *
 592  * Notice:
 593  * - don't support ol_flags for rss and csum err
 594  * - nb_pkts > RTE_FM10K_MAX_RX_BURST, only scan RTE_FM10K_MAX_RX_BURST
 595  *   numbers of DD bit
 596  */
 597 uint16_t
 598 fm10k_recv_scattered_pkts_vec(void *rx_queue,
 599                                 struct rte_mbuf **rx_pkts,
 600                                 uint16_t nb_pkts)
 601 {
 602         struct fm10k_rx_queue *rxq = rx_queue;
 603         uint8_t split_flags[RTE_FM10K_MAX_RX_BURST] = {0};
 604         unsigned i = 0;
 605
 606         /* Split_flags only can support max of RTE_FM10K_MAX_RX_BURST */
 607         nb_pkts = RTE_MIN(nb_pkts, RTE_FM10K_MAX_RX_BURST);
 608         /* get some new buffers */
 609         uint16_t nb_bufs = fm10k_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 610                         split_flags);
 611         if (nb_bufs == 0)
 612                 return 0;
 613
 614         /* happy day case, full burst + no packets to be joined */
 615         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 616
 617         if (rxq->pkt_first_seg == NULL &&
 618                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 619                         split_fl64[2] == 0 && split_fl64[3] == 0)
 620                 return nb_bufs;
 621
 622         /* reassemble any packets that need reassembly*/
 623         if (rxq->pkt_first_seg == NULL) {
 624                 /* find the first split flag, and only reassemble then*/
 625                 while (i < nb_bufs && !split_flags[i])
 626                         i++;
 627                 if (i == nb_bufs)
 628                         return nb_bufs;
 629         }
 630         return i + fm10k_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 631                 &split_flags[i]);
 632 }
 633
 634 static const struct fm10k_txq_ops vec_txq_ops = {
 635         .reset = fm10k_reset_tx_queue,
 636 };
 637
 638 void __attribute__((cold))
 639 fm10k_txq_vec_setup(struct fm10k_tx_queue *txq)
 640 {
 641         txq->ops = &vec_txq_ops;
 642 }
 643
 644 static inline void
 645 vtx1(volatile struct fm10k_tx_desc *txdp,
 646                 struct rte_mbuf *pkt, uint64_t flags)
 647 {
 648         __m128i descriptor = _mm_set_epi64x(flags << 56 |
 649                         pkt->vlan_tci << 16 | pkt->data_len,
 650                         MBUF_DMA_ADDR(pkt));
 651         _mm_store_si128((__m128i *)txdp, descriptor);
 652 }
 653
 654 static inline void
 655 vtx(volatile struct fm10k_tx_desc *txdp,
 656                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 657 {
 658         int i;
 659
 660         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 661                 vtx1(txdp, *pkt, flags);
 662 }
 663
 664 static inline int __attribute__((always_inline))
 665 fm10k_tx_free_bufs(struct fm10k_tx_queue *txq)
 666 {
 667         struct rte_mbuf **txep;
 668         uint8_t flags;
 669         uint32_t n;
 670         uint32_t i;
 671         int nb_free = 0;
 672         struct rte_mbuf *m, *free[RTE_FM10K_TX_MAX_FREE_BUF_SZ];
 673
 674         /* check DD bit on threshold descriptor */
 675         flags = txq->hw_ring[txq->next_dd].flags;
 676         if (!(flags & FM10K_TXD_FLAG_DONE))
 677                 return 0;
 678
 679         n = txq->rs_thresh;
 680
 681         /* First buffer to free from S/W ring is at index
 682          * next_dd - (rs_thresh-1)
 683          */
 684         txep = &txq->sw_ring[txq->next_dd - (n - 1)];
 685         m = __rte_pktmbuf_prefree_seg(txep[0]);
 686         if (likely(m != NULL)) {
 687                 free[0] = m;
 688                 nb_free = 1;
 689                 for (i = 1; i < n; i++) {
 690                         m = __rte_pktmbuf_prefree_seg(txep[i]);
 691                         if (likely(m != NULL)) {
 692                                 if (likely(m->pool == free[0]->pool))
 693                                         free[nb_free++] = m;
 694                                 else {
 695                                         rte_mempool_put_bulk(free[0]->pool,
 696                                                         (void *)free, nb_free);
 697                                         free[0] = m;
 698                                         nb_free = 1;
 699                                 }
 700                         }
 701                 }
 702                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 703         } else {
 704                 for (i = 1; i < n; i++) {
 705                         m = __rte_pktmbuf_prefree_seg(txep[i]);
 706                         if (m != NULL)
 707                                 rte_mempool_put(m->pool, m);
 708                 }
 709         }
 710
 711         /* buffers were freed, update counters */
 712         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
 713         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
 714         if (txq->next_dd >= txq->nb_desc)
 715                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
 716
 717         return txq->rs_thresh;
 718 }
 719
 720 static inline void __attribute__((always_inline))
 721 tx_backlog_entry(struct rte_mbuf **txep,
 722                  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 723 {
 724         int i;
 725
 726         for (i = 0; i < (int)nb_pkts; ++i)
 727                 txep[i] = tx_pkts[i];
 728 }
 729
 730 uint16_t
 731 fm10k_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 732                         uint16_t nb_pkts)
 733 {
 734         struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
 735         volatile struct fm10k_tx_desc *txdp;
 736         struct rte_mbuf **txep;
 737         uint16_t n, nb_commit, tx_id;
 738         uint64_t flags = FM10K_TXD_FLAG_LAST;
 739         uint64_t rs = FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_LAST;
 740         int i;
 741
 742         /* cross rx_thresh boundary is not allowed */
 743         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
 744
 745         if (txq->nb_free < txq->free_thresh)
 746                 fm10k_tx_free_bufs(txq);
 747
 748         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
 749         if (unlikely(nb_pkts == 0))
 750                 return 0;
 751
 752         tx_id = txq->next_free;
 753         txdp = &txq->hw_ring[tx_id];
 754         txep = &txq->sw_ring[tx_id];
 755
 756         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
 757
 758         n = (uint16_t)(txq->nb_desc - tx_id);
 759         if (nb_commit >= n) {
 760                 tx_backlog_entry(txep, tx_pkts, n);
 761
 762                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 763                         vtx1(txdp, *tx_pkts, flags);
 764
 765                 vtx1(txdp, *tx_pkts++, rs);
 766
 767                 nb_commit = (uint16_t)(nb_commit - n);
 768
 769                 tx_id = 0;
 770                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 771
 772                 /* avoid reach the end of ring */
 773                 txdp = &(txq->hw_ring[tx_id]);
 774                 txep = &txq->sw_ring[tx_id];
 775         }
 776
 777         tx_backlog_entry(txep, tx_pkts, nb_commit);
 778
 779         vtx(txdp, tx_pkts, nb_commit, flags);
 780
 781         tx_id = (uint16_t)(tx_id + nb_commit);
 782         if (tx_id > txq->next_rs) {
 783                 txq->hw_ring[txq->next_rs].flags |= FM10K_TXD_FLAG_RS;
 784                 txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh);
 785         }
 786
 787         txq->next_free = tx_id;
 788
 789         FM10K_PCI_REG_WRITE(txq->tail_ptr, txq->next_free);
 790
 791         return nb_pkts;
 792 }
 793
 794 static void __attribute__((cold))
 795 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
 796 {
 797         static const struct fm10k_tx_desc zeroed_desc = {0};
 798         struct rte_mbuf **txe = txq->sw_ring;
 799         uint16_t i;
 800
 801         /* Zero out HW ring memory */
 802         for (i = 0; i < txq->nb_desc; i++)
 803                 txq->hw_ring[i] = zeroed_desc;
 804
 805         /* Initialize SW ring entries */
 806         for (i = 0; i < txq->nb_desc; i++)
 807                 txe[i] = NULL;
 808
 809         txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
 810         txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 811
 812         txq->next_free = 0;
 813         txq->nb_used = 0;
 814         /* Always allow 1 descriptor to be un-allocated to avoid
 815          * a H/W race condition
 816          */
 817         txq->nb_free = (uint16_t)(txq->nb_desc - 1);
 818         FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);
 819 }