1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
8 #define HINIC_CSR_GLOBAL_BASE_ADDR 0x4000
10 /* HW interface registers */
11 #define HINIC_CSR_FUNC_ATTR0_ADDR 0x0
12 #define HINIC_CSR_FUNC_ATTR1_ADDR 0x4
13 #define HINIC_CSR_FUNC_ATTR2_ADDR 0x8
14 #define HINIC_CSR_FUNC_ATTR4_ADDR 0x10
15 #define HINIC_CSR_FUNC_ATTR5_ADDR 0x14
17 #define HINIC_FUNC_CSR_MAILBOX_DATA_OFF 0x80
18 #define HINIC_FUNC_CSR_MAILBOX_CONTROL_OFF 0x0100
19 #define HINIC_FUNC_CSR_MAILBOX_INT_OFFSET_OFF 0x0104
20 #define HINIC_FUNC_CSR_MAILBOX_RESULT_H_OFF 0x0108
21 #define HINIC_FUNC_CSR_MAILBOX_RESULT_L_OFF 0x010C
23 #define HINIC_CSR_DMA_ATTR_TBL_BASE 0xC80
25 #define HINIC_ELECTION_BASE 0x200
27 #define HINIC_CSR_DMA_ATTR_TBL_STRIDE 0x4
28 #define HINIC_CSR_DMA_ATTR_TBL_ADDR(idx) \
29 (HINIC_CSR_DMA_ATTR_TBL_BASE \
30 + (idx) * HINIC_CSR_DMA_ATTR_TBL_STRIDE)
32 #define HINIC_PPF_ELECTION_STRIDE 0x4
33 #define HINIC_CSR_MAX_PORTS 4
34 #define HINIC_CSR_PPF_ELECTION_ADDR \
35 (HINIC_CSR_GLOBAL_BASE_ADDR + HINIC_ELECTION_BASE)
38 #define HINIC_CSR_MSIX_CTRL_BASE 0x2000
39 #define HINIC_CSR_MSIX_CNT_BASE 0x2004
41 #define HINIC_CSR_MSIX_STRIDE 0x8
43 #define HINIC_CSR_MSIX_CTRL_ADDR(idx) \
44 (HINIC_CSR_MSIX_CTRL_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
46 #define HINIC_CSR_MSIX_CNT_ADDR(idx) \
47 (HINIC_CSR_MSIX_CNT_BASE + (idx) * HINIC_CSR_MSIX_STRIDE)
50 #define HINIC_AEQ_MTT_OFF_BASE_ADDR 0x200
52 #define HINIC_EQ_MTT_OFF_STRIDE 0x40
54 #define HINIC_CSR_AEQ_MTT_OFF(id) \
55 (HINIC_AEQ_MTT_OFF_BASE_ADDR + (id) * HINIC_EQ_MTT_OFF_STRIDE)
57 #define HINIC_CSR_EQ_PAGE_OFF_STRIDE 8
59 #define HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) \
60 (HINIC_CSR_AEQ_MTT_OFF(q_id) + \
61 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE)
63 #define HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) \
64 (HINIC_CSR_AEQ_MTT_OFF(q_id) + \
65 (pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
67 #define HINIC_EQ_HI_PHYS_ADDR_REG(type, q_id, pg_num) \
68 ((u32)(HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))
70 #define HINIC_EQ_LO_PHYS_ADDR_REG(type, q_id, pg_num) \
71 ((u32)(HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))
73 #define HINIC_AEQ_CTRL_0_ADDR_BASE 0xE00
74 #define HINIC_AEQ_CTRL_1_ADDR_BASE 0xE04
75 #define HINIC_AEQ_CONS_IDX_0_ADDR_BASE 0xE08
76 #define HINIC_AEQ_CONS_IDX_1_ADDR_BASE 0xE0C
78 #define HINIC_EQ_OFF_STRIDE 0x80
80 #define HINIC_CSR_AEQ_CTRL_0_ADDR(idx) \
81 (HINIC_AEQ_CTRL_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
83 #define HINIC_CSR_AEQ_CTRL_1_ADDR(idx) \
84 (HINIC_AEQ_CTRL_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
86 #define HINIC_CSR_AEQ_CONS_IDX_ADDR(idx) \
87 (HINIC_AEQ_CONS_IDX_0_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
89 #define HINIC_CSR_AEQ_PROD_IDX_ADDR(idx) \
90 (HINIC_AEQ_CONS_IDX_1_ADDR_BASE + (idx) * HINIC_EQ_OFF_STRIDE)
92 /* API CMD registers */
93 #define HINIC_CSR_API_CMD_BASE 0xF000
95 #define HINIC_CSR_API_CMD_STRIDE 0x100
97 #define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx) \
98 (HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
100 #define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx) \
101 (HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
103 #define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx) \
104 (HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
106 #define HINIC_CSR_API_CMD_STATUS_LO_ADDR(idx) \
107 (HINIC_CSR_API_CMD_BASE + 0xC + (idx) * HINIC_CSR_API_CMD_STRIDE)
109 #define HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR(idx) \
110 (HINIC_CSR_API_CMD_BASE + 0x10 + (idx) * HINIC_CSR_API_CMD_STRIDE)
112 #define HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR(idx) \
113 (HINIC_CSR_API_CMD_BASE + 0x14 + (idx) * HINIC_CSR_API_CMD_STRIDE)
115 #define HINIC_CSR_API_CMD_CHAIN_PI_ADDR(idx) \
116 (HINIC_CSR_API_CMD_BASE + 0x1C + (idx) * HINIC_CSR_API_CMD_STRIDE)
118 #define HINIC_CSR_API_CMD_CHAIN_REQ_ADDR(idx) \
119 (HINIC_CSR_API_CMD_BASE + 0x20 + (idx) * HINIC_CSR_API_CMD_STRIDE)
121 #define HINIC_CSR_API_CMD_STATUS_0_ADDR(idx) \
122 (HINIC_CSR_API_CMD_BASE + 0x30 + (idx) * HINIC_CSR_API_CMD_STRIDE)
124 /* VF control registers in pf */
125 #define HINIC_PF_CSR_VF_FLUSH_BASE 0x1F400
126 #define HINIC_PF_CSR_VF_FLUSH_STRIDE 0x4
128 #define HINIC_GLB_DMA_SO_RO_REPLACE_ADDR 0x488C
130 #define HINIC_ICPL_RESERVD_ADDR 0x9204
132 #define HINIC_PF_CSR_VF_FLUSH_OFF(idx) \
133 (HINIC_PF_CSR_VF_FLUSH_BASE + (idx) * HINIC_PF_CSR_VF_FLUSH_STRIDE)
135 #endif /* _HINIC_CSR_H_ */