1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #ifndef _HINIC_PMD_API_CMD_H_
6 #define _HINIC_PMD_API_CMD_H_
8 #define HINIC_API_CMD_CELL_CTRL_CELL_LEN_SHIFT 0
9 #define HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_OFF_SHIFT 16
10 #define HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_OFF_SHIFT 24
11 #define HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_SHIFT 56
13 #define HINIC_API_CMD_CELL_CTRL_CELL_LEN_MASK 0x3FU
14 #define HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_OFF_MASK 0x3FU
15 #define HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_OFF_MASK 0x3FU
16 #define HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_MASK 0xFFU
18 #define HINIC_API_CMD_CELL_CTRL_SET(val, member) \
19 ((((u64)val) & HINIC_API_CMD_CELL_CTRL_##member##_MASK) << \
20 HINIC_API_CMD_CELL_CTRL_##member##_SHIFT)
22 #define HINIC_API_CMD_CELL_CTRL_CLEAR(val, member) \
23 ((val) & (~((u64)HINIC_API_CMD_CELL_CTRL_##member##_MASK << \
24 HINIC_API_CMD_CELL_CTRL_##member##_SHIFT)))
26 #define HINIC_API_CMD_DESC_API_TYPE_SHIFT 0
27 #define HINIC_API_CMD_DESC_RD_WR_SHIFT 1
28 #define HINIC_API_CMD_DESC_MGMT_BYPASS_SHIFT 2
29 #define HINIC_API_CMD_DESC_RESP_AEQE_EN_SHIFT 3
30 #define HINIC_API_CMD_DESC_PRIV_DATA_SHIFT 8
31 #define HINIC_API_CMD_DESC_DEST_SHIFT 32
32 #define HINIC_API_CMD_DESC_SIZE_SHIFT 40
33 #define HINIC_API_CMD_DESC_XOR_CHKSUM_SHIFT 56
35 #define HINIC_API_CMD_DESC_API_TYPE_MASK 0x1U
36 #define HINIC_API_CMD_DESC_RD_WR_MASK 0x1U
37 #define HINIC_API_CMD_DESC_MGMT_BYPASS_MASK 0x1U
38 #define HINIC_API_CMD_DESC_RESP_AEQE_EN_MASK 0x1U
39 #define HINIC_API_CMD_DESC_DEST_MASK 0x1FU
40 #define HINIC_API_CMD_DESC_SIZE_MASK 0x7FFU
41 #define HINIC_API_CMD_DESC_XOR_CHKSUM_MASK 0xFFU
42 #define HINIC_API_CMD_DESC_PRIV_DATA_MASK 0xFFFFFFU
44 #define HINIC_API_CMD_DESC_SET(val, member) \
45 ((((u64)val) & HINIC_API_CMD_DESC_##member##_MASK) << \
46 HINIC_API_CMD_DESC_##member##_SHIFT)
48 #define HINIC_API_CMD_DESC_CLEAR(val, member) \
49 ((val) & (~((u64)HINIC_API_CMD_DESC_##member##_MASK << \
50 HINIC_API_CMD_DESC_##member##_SHIFT)))
52 #define HINIC_API_CMD_STATUS_HEADER_VALID_SHIFT 0
53 #define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_SHIFT 16
55 #define HINIC_API_CMD_STATUS_HEADER_VALID_MASK 0xFFU
56 #define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_MASK 0xFFU
58 #define HINIC_API_CMD_STATUS_VALID_CODE 0xFF
60 #define HINIC_API_CMD_STATUS_HEADER_GET(val, member) \
61 (((val) >> HINIC_API_CMD_STATUS_HEADER_##member##_SHIFT) & \
62 HINIC_API_CMD_STATUS_HEADER_##member##_MASK)
64 #define HINIC_API_CMD_CHAIN_REQ_RESTART_SHIFT 1
65 #define HINIC_API_CMD_CHAIN_REQ_WB_TRIGGER_SHIFT 2
67 #define HINIC_API_CMD_CHAIN_REQ_RESTART_MASK 0x1U
68 #define HINIC_API_CMD_CHAIN_REQ_WB_TRIGGER_MASK 0x1U
70 #define HINIC_API_CMD_CHAIN_REQ_SET(val, member) \
71 (((val) & HINIC_API_CMD_CHAIN_REQ_##member##_MASK) << \
72 HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT)
74 #define HINIC_API_CMD_CHAIN_REQ_GET(val, member) \
75 (((val) >> HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT) & \
76 HINIC_API_CMD_CHAIN_REQ_##member##_MASK)
78 #define HINIC_API_CMD_CHAIN_REQ_CLEAR(val, member) \
79 ((val) & (~(HINIC_API_CMD_CHAIN_REQ_##member##_MASK << \
80 HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT)))
82 #define HINIC_API_CMD_CHAIN_CTRL_RESTART_EN_SHIFT 1
83 #define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_SHIFT 2
84 #define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_SHIFT 4
85 #define HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_SHIFT 8
86 #define HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_SHIFT 28
87 #define HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_SHIFT 30
89 #define HINIC_API_CMD_CHAIN_CTRL_RESTART_EN_MASK 0x1U
90 #define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_MASK 0x1U
91 #define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_MASK 0x1U
92 #define HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_MASK 0x3U
93 #define HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_MASK 0x3U
94 #define HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_MASK 0x3U
96 #define HINIC_API_CMD_CHAIN_CTRL_SET(val, member) \
97 (((val) & HINIC_API_CMD_CHAIN_CTRL_##member##_MASK) << \
98 HINIC_API_CMD_CHAIN_CTRL_##member##_SHIFT)
100 #define HINIC_API_CMD_CHAIN_CTRL_CLEAR(val, member) \
101 ((val) & (~(HINIC_API_CMD_CHAIN_CTRL_##member##_MASK << \
102 HINIC_API_CMD_CHAIN_CTRL_##member##_SHIFT)))
104 #define HINIC_API_CMD_RESP_HEAD_VALID_MASK 0xFF
105 #define HINIC_API_CMD_RESP_HEAD_VALID_CODE 0xFF
107 #define HINIC_API_CMD_RESP_HEADER_VALID(val) \
108 (((val) & HINIC_API_CMD_RESP_HEAD_VALID_MASK) == \
109 HINIC_API_CMD_RESP_HEAD_VALID_CODE)
111 #define HINIC_API_CMD_RESP_HEAD_STATUS_SHIFT 8
112 #define HINIC_API_CMD_RESP_HEAD_STATUS_MASK 0xFFU
114 #define HINIC_API_CMD_RESP_HEAD_ERR_CODE 0x1
115 #define HINIC_API_CMD_RESP_HEAD_ERR(val) \
116 ((((val) >> HINIC_API_CMD_RESP_HEAD_STATUS_SHIFT) & \
117 HINIC_API_CMD_RESP_HEAD_STATUS_MASK) == \
118 HINIC_API_CMD_RESP_HEAD_ERR_CODE)
120 #define HINIC_API_CMD_RESP_HEAD_CHAIN_ID_SHIFT 16
121 #define HINIC_API_CMD_RESP_HEAD_CHAIN_ID_MASK 0xFF
123 #define HINIC_API_CMD_RESP_RESERVED 3
124 #define HINIC_API_CMD_RESP_HEAD_CHAIN_ID(val) \
125 (((val) >> HINIC_API_CMD_RESP_HEAD_CHAIN_ID_SHIFT) & \
126 HINIC_API_CMD_RESP_HEAD_CHAIN_ID_MASK)
128 #define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_SHIFT 40
129 #define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK 0xFFFFFFU
131 #define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV(val) \
132 (u16)(((val) >> HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_SHIFT) & \
133 HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK)
135 #define HINIC_API_CMD_STATUS_HEAD_VALID_MASK 0xFFU
136 #define HINIC_API_CMD_STATUS_HEAD_VALID_SHIFT 0
138 #define HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_MASK 0xFFU
139 #define HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_VALID_SHIFT 16
141 #define HINIC_API_CMD_STATUS_CONS_IDX_MASK 0xFFFFFFU
142 #define HINIC_API_CMD_STATUS_CONS_IDX_SHIFT 0
144 #define HINIC_API_CMD_STATUS_FSM_MASK 0xFU
145 #define HINIC_API_CMD_STATUS_FSM_SHIFT 24
147 #define HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK 0x3U
148 #define HINIC_API_CMD_STATUS_CHKSUM_ERR_SHIFT 28
150 #define HINIC_API_CMD_STATUS_CPLD_ERR_MASK 0x1U
151 #define HINIC_API_CMD_STATUS_CPLD_ERR_SHIFT 30
153 #define HINIC_API_CMD_STATUS_CHAIN_ID(val) \
154 (((val) >> HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_VALID_SHIFT) & \
155 HINIC_API_CMD_STATUS_HEAD_VALID_MASK)
157 #define HINIC_API_CMD_STATUS_CONS_IDX(val) \
158 ((val) & HINIC_API_CMD_STATUS_CONS_IDX_MASK)
160 #define HINIC_API_CMD_STATUS_CHKSUM_ERR(val) \
161 (((val) >> HINIC_API_CMD_STATUS_CHKSUM_ERR_SHIFT) & \
162 HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK)
164 #define HINIC_API_CMD_STATUS_GET(val, member) \
165 (((val) >> HINIC_API_CMD_STATUS_##member##_SHIFT) & \
166 HINIC_API_CMD_STATUS_##member##_MASK)
168 enum hinic_api_cmd_chain_type {
169 /* read from mgmt cpu command with completion */
170 HINIC_API_CMD_WRITE_ASYNC_TO_MGMT_CPU = 6,
171 /* PMD business api chain */
172 HINIC_API_CMD_PMD_WRITE_TO_MGMT = 7,
177 HINIC_NODE_ID_MGMT_HOST = 21,
180 struct hinic_api_cmd_status {
190 struct hinic_api_cmd_cell {
193 /* address is 64 bit in HW struct */
205 u64 hw_wb_resp_paddr;
211 struct hinic_api_cmd_cell_ctxt {
212 dma_addr_t cell_paddr;
213 struct hinic_api_cmd_cell *cell_vaddr;
215 dma_addr_t cell_paddr_free;
216 void *cell_vaddr_free;
218 dma_addr_t api_cmd_paddr;
221 dma_addr_t api_cmd_paddr_free;
222 void *api_cmd_vaddr_free;
229 struct hinic_api_cmd_chain_attr {
230 struct hinic_hwdev *hwdev;
231 enum hinic_api_cmd_chain_type chain_type;
238 struct hinic_api_cmd_chain {
239 struct hinic_hwdev *hwdev;
240 enum hinic_api_cmd_chain_type chain_type;
246 /* HW members is 24 bit format */
250 /* Async cmd can not be scheduled */
251 spinlock_t async_lock;
253 dma_addr_t wb_status_paddr;
254 struct hinic_api_cmd_status *wb_status;
256 dma_addr_t head_cell_paddr;
257 struct hinic_api_cmd_cell *head_node;
259 struct hinic_api_cmd_cell_ctxt *cell_ctxt;
260 struct hinic_api_cmd_cell *curr_node;
263 int hinic_api_cmd_write(struct hinic_api_cmd_chain *chain,
264 enum hinic_node_id dest, void *cmd, u16 size);
266 int hinic_api_cmd_init(struct hinic_hwdev *hwdev,
267 struct hinic_api_cmd_chain **chain);
269 void hinic_api_cmd_free(struct hinic_api_cmd_chain **chain);
271 #endif /* _HINIC_PMD_API_CMD_H_ */