drivers/net/hinic/base/hinic_pmd_cmd.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   3  */
   4
   5 #ifndef _HINIC_PORT_CMD_H_
   6 #define _HINIC_PORT_CMD_H_
   7
   8 enum hinic_eq_type {
   9         HINIC_AEQ,
  10         HINIC_CEQ
  11 };
  12
  13 enum hinic_resp_aeq_num {
  14         HINIC_AEQ0 = 0,
  15         HINIC_AEQ1 = 1,
  16         HINIC_AEQ2 = 2,
  17         HINIC_AEQ3 = 3,
  18 };
  19
  20 enum hinic_mod_type {
  21         HINIC_MOD_COMM = 0,     /* HW communication module */
  22         HINIC_MOD_L2NIC = 1,    /* L2NIC module */
  23         HINIC_MOD_CFGM = 7,     /* Configuration module */
  24         HINIC_MOD_HILINK = 14,
  25         HINIC_MOD_MAX   = 15
  26 };
  27
  28 /* only used by VFD communicating with PFD to register or unregister,
  29  * command mode type is HINIC_MOD_L2NIC
  30  */
  31 #define HINIC_PORT_CMD_VF_REGISTER      0x0
  32 #define HINIC_PORT_CMD_VF_UNREGISTER    0x1
  33
  34 /* cmd of mgmt CPU message for NIC module */
  35 enum hinic_port_cmd {
  36         HINIC_PORT_CMD_MGMT_RESET               = 0x0,
  37
  38         HINIC_PORT_CMD_CHANGE_MTU               = 0x2,
  39
  40         HINIC_PORT_CMD_ADD_VLAN                 = 0x3,
  41         HINIC_PORT_CMD_DEL_VLAN,
  42
  43         HINIC_PORT_CMD_SET_ETS                  = 0x7,
  44         HINIC_PORT_CMD_GET_ETS,
  45
  46         HINIC_PORT_CMD_SET_MAC                  = 0x9,
  47         HINIC_PORT_CMD_GET_MAC,
  48         HINIC_PORT_CMD_DEL_MAC,
  49
  50         HINIC_PORT_CMD_SET_RX_MODE              = 0xc,
  51         HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE     = 0xd,
  52
  53         HINIC_PORT_CMD_GET_PAUSE_INFO           = 0x14,
  54         HINIC_PORT_CMD_SET_PAUSE_INFO,
  55
  56         HINIC_PORT_CMD_GET_LINK_STATE           = 0x18,
  57         HINIC_PORT_CMD_SET_LRO                  = 0x19,
  58         HINIC_PORT_CMD_SET_RX_CSUM              = 0x1a,
  59         HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD      = 0x1b,
  60
  61         HINIC_PORT_CMD_GET_PORT_STATISTICS      = 0x1c,
  62         HINIC_PORT_CMD_CLEAR_PORT_STATISTICS,
  63         HINIC_PORT_CMD_GET_VPORT_STAT,
  64         HINIC_PORT_CMD_CLEAN_VPORT_STAT,
  65
  66         HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,
  67         HINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL,
  68
  69         HINIC_PORT_CMD_SET_PORT_ENABLE          = 0x29,
  70         HINIC_PORT_CMD_GET_PORT_ENABLE,
  71
  72         HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL     = 0x2b,
  73         HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL,
  74         HINIC_PORT_CMD_SET_RSS_HASH_ENGINE,
  75         HINIC_PORT_CMD_GET_RSS_HASH_ENGINE,
  76         HINIC_PORT_CMD_GET_RSS_CTX_TBL,
  77         HINIC_PORT_CMD_SET_RSS_CTX_TBL,
  78         HINIC_PORT_CMD_RSS_TEMP_MGR,
  79
  80         HINIC_PORT_CMD_RSS_CFG                  = 0x42,
  81
  82         HINIC_PORT_CMD_GET_PHY_TYPE             = 0x44,
  83         HINIC_PORT_CMD_INIT_FUNC                = 0x45,
  84
  85         HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE     = 0x4a,
  86         HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,
  87
  88         HINIC_PORT_CMD_GET_PORT_TYPE            = 0x5b,
  89
  90         HINIC_PORT_CMD_GET_VPORT_ENABLE         = 0x5c,
  91         HINIC_PORT_CMD_SET_VPORT_ENABLE,
  92
  93         HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID   = 0x5e,
  94
  95         HINIC_PORT_CMD_GET_LRO                  = 0x63,
  96
  97         HINIC_PORT_CMD_GET_DMA_CS               = 0x64,
  98         HINIC_PORT_CMD_SET_DMA_CS,
  99
 100         HINIC_PORT_CMD_GET_GLOBAL_QPN           = 0x66,
 101
 102         HINIC_PORT_CMD_SET_PFC_MISC             = 0x67,
 103         HINIC_PORT_CMD_GET_PFC_MISC,
 104
 105         HINIC_PORT_CMD_SET_VF_RATE              = 0x69,
 106         HINIC_PORT_CMD_SET_VF_VLAN,
 107         HINIC_PORT_CMD_CLR_VF_VLAN,
 108
 109         HINIC_PORT_CMD_SET_RQ_IQ_MAP            = 0x73,
 110         HINIC_PORT_CMD_SET_PFC_THD              = 0x75,
 111
 112         HINIC_PORT_CMD_LINK_STATUS_REPORT       = 0xa0,
 113
 114         HINIC_PORT_CMD_SET_LOSSLESS_ETH         = 0xa3,
 115         HINIC_PORT_CMD_UPDATE_MAC               = 0xa4,
 116
 117         HINIC_PORT_CMD_GET_PORT_INFO            = 0xaa,
 118
 119         HINIC_PORT_CMD_SET_IPSU_MAC             = 0xcb,
 120         HINIC_PORT_CMD_GET_IPSU_MAC             = 0xcc,
 121
 122         HINIC_PORT_CMD_GET_LINK_MODE            = 0xD9,
 123         HINIC_PORT_CMD_SET_SPEED                = 0xDA,
 124         HINIC_PORT_CMD_SET_AUTONEG              = 0xDB,
 125
 126         HINIC_PORT_CMD_CLEAR_QP_RES             = 0xDD,
 127         HINIC_PORT_CMD_SET_SUPER_CQE            = 0xDE,
 128         HINIC_PORT_CMD_SET_VF_COS               = 0xDF,
 129         HINIC_PORT_CMD_GET_VF_COS               = 0xE1,
 130
 131         HINIC_PORT_CMD_CABLE_PLUG_EVENT         = 0xE5,
 132         HINIC_PORT_CMD_LINK_ERR_EVENT           = 0xE6,
 133
 134         HINIC_PORT_CMD_SET_COS_UP_MAP           = 0xE8,
 135
 136         HINIC_PORT_CMD_RESET_LINK_CFG           = 0xEB,
 137
 138         HINIC_PORT_CMD_FORCE_PKT_DROP           = 0xF3,
 139         HINIC_PORT_CMD_SET_LRO_TIMER            = 0xF4,
 140
 141         HINIC_PORT_CMD_SET_VHD_CFG              = 0xF7,
 142         HINIC_PORT_CMD_SET_LINK_FOLLOW          = 0xF8,
 143 };
 144
 145 /* cmd of mgmt CPU message for HW module */
 146 enum hinic_mgmt_cmd {
 147         HINIC_MGMT_CMD_RESET_MGMT               = 0x0,
 148         HINIC_MGMT_CMD_START_FLR                = 0x1,
 149         HINIC_MGMT_CMD_FLUSH_DOORBELL           = 0x2,
 150         HINIC_MGMT_CMD_GET_IO_STATUS            = 0x3,
 151         HINIC_MGMT_CMD_DMA_ATTR_SET             = 0x4,
 152
 153         HINIC_MGMT_CMD_CMDQ_CTXT_SET            = 0x10,
 154         HINIC_MGMT_CMD_CMDQ_CTXT_GET,
 155
 156         HINIC_MGMT_CMD_VAT_SET                  = 0x12,
 157         HINIC_MGMT_CMD_VAT_GET,
 158
 159         HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET     = 0x14,
 160         HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET,
 161
 162         HINIC_MGMT_CMD_PPF_HT_GPA_SET           = 0x23,
 163         HINIC_MGMT_CMD_RES_STATE_SET            = 0x24,
 164         HINIC_MGMT_CMD_FUNC_CACHE_OUT           = 0x25,
 165         HINIC_MGMT_CMD_FFM_SET                  = 0x26,
 166
 167         HINIC_MGMT_CMD_FUNC_RES_CLEAR           = 0x29,
 168
 169         HINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP    = 0x33,
 170         HINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP,
 171         HINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP,
 172
 173         HINIC_MGMT_CMD_VF_RANDOM_ID_SET         = 0x36,
 174         HINIC_MGMT_CMD_FAULT_REPORT             = 0x37,
 175
 176         HINIC_MGMT_CMD_VPD_SET                  = 0x40,
 177         HINIC_MGMT_CMD_VPD_GET,
 178         HINIC_MGMT_CMD_LABEL_SET,
 179         HINIC_MGMT_CMD_LABEL_GET,
 180         HINIC_MGMT_CMD_SATIC_MAC_SET,
 181         HINIC_MGMT_CMD_SATIC_MAC_GET,
 182         HINIC_MGMT_CMD_SYNC_TIME                = 0x46,
 183         HINIC_MGMT_CMD_SET_LED_STATUS           = 0x4A,
 184         HINIC_MGMT_CMD_L2NIC_RESET              = 0x4b,
 185         HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET    = 0x4d,
 186         HINIC_MGMT_CMD_BIOS_NV_DATA_MGMT        = 0x4E,
 187         HINIC_MGMT_CMD_ACTIVATE_FW              = 0x4F,
 188         HINIC_MGMT_CMD_PAGESIZE_SET             = 0x50,
 189         HINIC_MGMT_CMD_PAGESIZE_GET             = 0x51,
 190         HINIC_MGMT_CMD_GET_BOARD_INFO           = 0x52,
 191         HINIC_MGMT_CMD_WATCHDOG_INFO            = 0x56,
 192         HINIC_MGMT_CMD_FMW_ACT_NTC              = 0x57,
 193         HINIC_MGMT_CMD_SET_VF_RANDOM_ID         = 0x61,
 194         HINIC_MGMT_CMD_GET_PPF_STATE            = 0x63,
 195         HINIC_MGMT_CMD_PCIE_DFX_NTC             = 0x65,
 196         HINIC_MGMT_CMD_PCIE_DFX_GET             = 0x66,
 197 };
 198
 199 /* cmd of mgmt CPU message for HILINK module */
 200 enum hinic_hilink_cmd {
 201         HINIC_HILINK_CMD_GET_LINK_INFO          = 0x3,
 202         HINIC_HILINK_CMD_SET_LINK_SETTINGS      = 0x8,
 203 };
 204
 205 /* uCode related commands */
 206 enum hinic_ucode_cmd {
 207         HINIC_UCODE_CMD_MDY_QUEUE_CONTEXT       = 0,
 208         HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
 209         HINIC_UCODE_CMD_ARM_SQ,
 210         HINIC_UCODE_CMD_ARM_RQ,
 211         HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
 212         HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
 213         HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
 214         HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
 215         HINIC_UCODE_CMD_SET_IQ_ENABLE,
 216         HINIC_UCODE_CMD_SET_RQ_FLUSH            = 10
 217 };
 218
 219 enum cfg_sub_cmd {
 220         /* PPF(PF) <-> FW */
 221         HINIC_CFG_NIC_CAP = 0,
 222         CFG_FW_VERSION,
 223         CFG_UCODE_VERSION,
 224         HINIC_CFG_MBOX_CAP = 6
 225 };
 226
 227 enum hinic_ack_type {
 228         HINIC_ACK_TYPE_CMDQ,
 229         HINIC_ACK_TYPE_SHARE_CQN,
 230         HINIC_ACK_TYPE_APP_CQN,
 231
 232         HINIC_MOD_ACK_MAX = 15,
 233 };
 234
 235 enum sq_l4offload_type {
 236         OFFLOAD_DISABLE   = 0,
 237         TCP_OFFLOAD_ENABLE  = 1,
 238         SCTP_OFFLOAD_ENABLE = 2,
 239         UDP_OFFLOAD_ENABLE  = 3,
 240 };
 241
 242 enum sq_vlan_offload_flag {
 243         VLAN_OFFLOAD_DISABLE = 0,
 244         VLAN_OFFLOAD_ENABLE  = 1,
 245 };
 246
 247 enum sq_pkt_parsed_flag {
 248         PKT_NOT_PARSED = 0,
 249         PKT_PARSED     = 1,
 250 };
 251
 252 enum sq_l3_type {
 253         UNKNOWN_L3TYPE = 0,
 254         IPV6_PKT = 1,
 255         IPV4_PKT_NO_CHKSUM_OFFLOAD = 2,
 256         IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,
 257 };
 258
 259 enum sq_md_type {
 260         UNKNOWN_MD_TYPE = 0,
 261 };
 262
 263 enum sq_l2type {
 264         ETHERNET = 0,
 265 };
 266
 267 enum sq_tunnel_l4_type {
 268         NOT_TUNNEL,
 269         TUNNEL_UDP_NO_CSUM,
 270         TUNNEL_UDP_CSUM,
 271 };
 272
 273 #define NIC_RSS_CMD_TEMP_ALLOC  0x01
 274 #define NIC_RSS_CMD_TEMP_FREE   0x02
 275
 276 #define HINIC_RSS_TYPE_VALID_SHIFT                      23
 277 #define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT               24
 278 #define HINIC_RSS_TYPE_IPV6_EXT_SHIFT                   25
 279 #define HINIC_RSS_TYPE_TCP_IPV6_SHIFT                   26
 280 #define HINIC_RSS_TYPE_IPV6_SHIFT                       27
 281 #define HINIC_RSS_TYPE_TCP_IPV4_SHIFT                   28
 282 #define HINIC_RSS_TYPE_IPV4_SHIFT                       29
 283 #define HINIC_RSS_TYPE_UDP_IPV6_SHIFT                   30
 284 #define HINIC_RSS_TYPE_UDP_IPV4_SHIFT                   31
 285
 286 #define HINIC_RSS_TYPE_SET(val, member)         \
 287                 (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)
 288
 289 #define HINIC_RSS_TYPE_GET(val, member)         \
 290                 (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)
 291
 292 enum hinic_speed {
 293         HINIC_SPEED_10MB_LINK = 0,
 294         HINIC_SPEED_100MB_LINK,
 295         HINIC_SPEED_1000MB_LINK,
 296         HINIC_SPEED_10GB_LINK,
 297         HINIC_SPEED_25GB_LINK,
 298         HINIC_SPEED_40GB_LINK,
 299         HINIC_SPEED_100GB_LINK,
 300         HINIC_SPEED_UNKNOWN = 0xFF,
 301 };
 302
 303 enum {
 304         HINIC_IFLA_VF_LINK_STATE_AUTO,  /* link state of the uplink */
 305         HINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */
 306         HINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */
 307 };
 308
 309 #define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT         0
 310 #define HINIC_AF0_P2P_IDX_SHIFT                 10
 311 #define HINIC_AF0_PCI_INTF_IDX_SHIFT            14
 312 #define HINIC_AF0_VF_IN_PF_SHIFT                16
 313 #define HINIC_AF0_FUNC_TYPE_SHIFT               24
 314
 315 #define HINIC_AF0_FUNC_GLOBAL_IDX_MASK          0x3FF
 316 #define HINIC_AF0_P2P_IDX_MASK                  0xF
 317 #define HINIC_AF0_PCI_INTF_IDX_MASK             0x3
 318 #define HINIC_AF0_VF_IN_PF_MASK                 0xFF
 319 #define HINIC_AF0_FUNC_TYPE_MASK                0x1
 320
 321 #define HINIC_AF0_GET(val, member)                              \
 322         (((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK)
 323
 324 #define HINIC_AF1_PPF_IDX_SHIFT                 0
 325 #define HINIC_AF1_AEQS_PER_FUNC_SHIFT           8
 326 #define HINIC_AF1_CEQS_PER_FUNC_SHIFT           12
 327 #define HINIC_AF1_IRQS_PER_FUNC_SHIFT           20
 328 #define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT       24
 329 #define HINIC_AF1_MGMT_INIT_STATUS_SHIFT        30
 330 #define HINIC_AF1_PF_INIT_STATUS_SHIFT          31
 331
 332 #define HINIC_AF1_PPF_IDX_MASK                  0x1F
 333 #define HINIC_AF1_AEQS_PER_FUNC_MASK            0x3
 334 #define HINIC_AF1_CEQS_PER_FUNC_MASK            0x7
 335 #define HINIC_AF1_IRQS_PER_FUNC_MASK            0xF
 336 #define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK        0x7
 337 #define HINIC_AF1_MGMT_INIT_STATUS_MASK         0x1
 338 #define HINIC_AF1_PF_INIT_STATUS_MASK           0x1
 339
 340 #define HINIC_AF1_GET(val, member)                              \
 341         (((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK)
 342
 343 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT      16
 344 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK       0x3FF
 345
 346 #define HINIC_AF2_GET(val, member)                              \
 347         (((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK)
 348
 349 #define HINIC_AF4_OUTBOUND_CTRL_SHIFT           0
 350 #define HINIC_AF4_DOORBELL_CTRL_SHIFT           1
 351 #define HINIC_AF4_OUTBOUND_CTRL_MASK            0x1
 352 #define HINIC_AF4_DOORBELL_CTRL_MASK            0x1
 353
 354 #define HINIC_AF4_GET(val, member)                              \
 355         (((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK)
 356
 357 #define HINIC_AF4_SET(val, member)                              \
 358         (((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT)
 359
 360 #define HINIC_AF4_CLEAR(val, member)                            \
 361         ((val) & (~(HINIC_AF4_##member##_MASK <<                \
 362         HINIC_AF4_##member##_SHIFT)))
 363
 364 #define HINIC_AF5_PF_STATUS_SHIFT               0
 365 #define HINIC_AF5_PF_STATUS_MASK                0xFFFF
 366
 367 #define HINIC_AF5_SET(val, member)                              \
 368         (((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT)
 369
 370 #define HINIC_AF5_GET(val, member)                              \
 371         (((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK)
 372
 373 #define HINIC_AF5_CLEAR(val, member)                            \
 374         ((val) & (~(HINIC_AF5_##member##_MASK <<                \
 375         HINIC_AF5_##member##_SHIFT)))
 376
 377 #define HINIC_PPF_ELECTION_IDX_SHIFT            0
 378
 379 #define HINIC_PPF_ELECTION_IDX_MASK             0x1F
 380
 381 #define HINIC_PPF_ELECTION_SET(val, member)                     \
 382         (((val) & HINIC_PPF_ELECTION_##member##_MASK) <<        \
 383                 HINIC_PPF_ELECTION_##member##_SHIFT)
 384
 385 #define HINIC_PPF_ELECTION_GET(val, member)                     \
 386         (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) &       \
 387                 HINIC_PPF_ELECTION_##member##_MASK)
 388
 389 #define HINIC_PPF_ELECTION_CLEAR(val, member)                   \
 390         ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK  \
 391                 << HINIC_PPF_ELECTION_##member##_SHIFT)))
 392
 393 #define DB_IDX(db, db_base)     \
 394         ((u32)(((unsigned long)(db) - (unsigned long)(db_base)) /       \
 395         HINIC_DB_PAGE_SIZE))
 396
 397 enum hinic_pcie_nosnoop {
 398         HINIC_PCIE_SNOOP = 0,
 399         HINIC_PCIE_NO_SNOOP = 1,
 400 };
 401
 402 enum hinic_pcie_tph {
 403         HINIC_PCIE_TPH_DISABLE = 0,
 404         HINIC_PCIE_TPH_ENABLE = 1,
 405 };
 406
 407 enum hinic_outbound_ctrl {
 408         ENABLE_OUTBOUND  = 0x0,
 409         DISABLE_OUTBOUND = 0x1,
 410 };
 411
 412 enum hinic_doorbell_ctrl {
 413         ENABLE_DOORBELL  = 0x0,
 414         DISABLE_DOORBELL = 0x1,
 415 };
 416
 417 enum hinic_pf_status {
 418         HINIC_PF_STATUS_INIT = 0X0,
 419         HINIC_PF_STATUS_ACTIVE_FLAG = 0x11,
 420         HINIC_PF_STATUS_FLR_START_FLAG = 0x12,
 421         HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,
 422 };
 423
 424 /* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */
 425 #define HINIC_DB_DWQE_SIZE      0x00080000
 426
 427 /* db page size: 4K */
 428 #define HINIC_DB_PAGE_SIZE      0x00001000ULL
 429
 430 #define HINIC_DB_MAX_AREAS      (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
 431
 432 #define HINIC_PCI_MSIX_ENTRY_SIZE                       16
 433 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL                12
 434 #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT               1
 435
 436 struct hinic_mgmt_msg_head {
 437         u8      status;
 438         u8      version;
 439         u8      resp_aeq_num;
 440         u8      rsvd0[5];
 441 };
 442
 443 struct hinic_root_ctxt {
 444         struct hinic_mgmt_msg_head mgmt_msg_head;
 445
 446         u16     func_idx;
 447         u16     rsvd1;
 448         u8      set_cmdq_depth;
 449         u8      cmdq_depth;
 450         u8      lro_en;
 451         u8      rsvd2;
 452         u8      ppf_idx;
 453         u8      rsvd3;
 454         u16     rq_depth;
 455         u16     rx_buf_sz;
 456         u16     sq_depth;
 457 };
 458
 459 #endif /* _HINIC_PORT_CMD_H_ */