1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #include <rte_bus_pci.h>
7 #include "hinic_compat.h"
9 #include "hinic_pmd_hwdev.h"
10 #include "hinic_pmd_hwif.h"
12 #define HINIC_CFG_REGS_BAR 0
13 #define HINIC_INTR_MSI_BAR 2
14 #define HINIC_DB_MEM_BAR 4
16 #define HINIC_MSIX_CNT_RESEND_TIMER_SHIFT 29
17 #define HINIC_MSIX_CNT_RESEND_TIMER_MASK 0x7U
19 #define HINIC_MSIX_CNT_SET(val, member) \
20 (((val) & HINIC_MSIX_CNT_##member##_MASK) << \
21 HINIC_MSIX_CNT_##member##_SHIFT)
24 * hwif_ready - test if the HW initialization passed
25 * @hwdev: the pointer to the private hardware device object
26 * Return: 0 - success, negative - failure
28 static int hwif_ready(struct hinic_hwdev *hwdev)
32 addr = HINIC_CSR_FUNC_ATTR1_ADDR;
33 attr1 = hinic_hwif_read_reg(hwdev->hwif, addr);
35 if (!HINIC_AF1_GET(attr1, MGMT_INIT_STATUS))
42 * set_hwif_attr - set the attributes as members in hwif
43 * @hwif: the hardware interface of a pci function device
44 * @attr0: the first attribute that was read from the hw
45 * @attr1: the second attribute that was read from the hw
46 * @attr2: the third attribute that was read from the hw
48 static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1,
51 hwif->attr.func_global_idx = HINIC_AF0_GET(attr0, FUNC_GLOBAL_IDX);
52 hwif->attr.port_to_port_idx = HINIC_AF0_GET(attr0, P2P_IDX);
53 hwif->attr.pci_intf_idx = HINIC_AF0_GET(attr0, PCI_INTF_IDX);
54 hwif->attr.vf_in_pf = HINIC_AF0_GET(attr0, VF_IN_PF);
55 hwif->attr.func_type = HINIC_AF0_GET(attr0, FUNC_TYPE);
57 hwif->attr.ppf_idx = HINIC_AF1_GET(attr1, PPF_IDX);
59 hwif->attr.num_aeqs = BIT(HINIC_AF1_GET(attr1, AEQS_PER_FUNC));
60 hwif->attr.num_ceqs = BIT(HINIC_AF1_GET(attr1, CEQS_PER_FUNC));
61 hwif->attr.num_irqs = BIT(HINIC_AF1_GET(attr1, IRQS_PER_FUNC));
62 hwif->attr.num_dma_attr = BIT(HINIC_AF1_GET(attr1, DMA_ATTR_PER_FUNC));
64 hwif->attr.global_vf_id_of_pf = HINIC_AF2_GET(attr2,
69 * get_hwif_attr - read and set the attributes as members in hwif
70 * @hwif: the hardware interface of a pci function device
72 static void get_hwif_attr(struct hinic_hwif *hwif)
74 u32 addr, attr0, attr1, attr2;
76 addr = HINIC_CSR_FUNC_ATTR0_ADDR;
77 attr0 = hinic_hwif_read_reg(hwif, addr);
79 addr = HINIC_CSR_FUNC_ATTR1_ADDR;
80 attr1 = hinic_hwif_read_reg(hwif, addr);
82 addr = HINIC_CSR_FUNC_ATTR2_ADDR;
83 attr2 = hinic_hwif_read_reg(hwif, addr);
85 set_hwif_attr(hwif, attr0, attr1, attr2);
88 void hinic_set_pf_status(struct hinic_hwif *hwif, enum hinic_pf_status status)
90 u32 attr5 = HINIC_AF5_SET(status, PF_STATUS);
91 u32 addr = HINIC_CSR_FUNC_ATTR5_ADDR;
93 hinic_hwif_write_reg(hwif, addr, attr5);
96 enum hinic_pf_status hinic_get_pf_status(struct hinic_hwif *hwif)
98 u32 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR);
100 return HINIC_AF5_GET(attr5, PF_STATUS);
103 static enum hinic_doorbell_ctrl
104 hinic_get_doorbell_ctrl_status(struct hinic_hwif *hwif)
106 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);
108 return HINIC_AF4_GET(attr4, DOORBELL_CTRL);
111 static enum hinic_outbound_ctrl
112 hinic_get_outbound_ctrl_status(struct hinic_hwif *hwif)
114 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR);
116 return HINIC_AF4_GET(attr4, OUTBOUND_CTRL);
119 void hinic_enable_doorbell(struct hinic_hwif *hwif)
123 addr = HINIC_CSR_FUNC_ATTR4_ADDR;
124 attr4 = hinic_hwif_read_reg(hwif, addr);
126 attr4 = HINIC_AF4_CLEAR(attr4, DOORBELL_CTRL);
127 attr4 |= HINIC_AF4_SET(ENABLE_DOORBELL, DOORBELL_CTRL);
129 hinic_hwif_write_reg(hwif, addr, attr4);
132 void hinic_disable_doorbell(struct hinic_hwif *hwif)
136 addr = HINIC_CSR_FUNC_ATTR4_ADDR;
137 attr4 = hinic_hwif_read_reg(hwif, addr);
139 attr4 = HINIC_AF4_CLEAR(attr4, DOORBELL_CTRL);
140 attr4 |= HINIC_AF4_SET(DISABLE_DOORBELL, DOORBELL_CTRL);
142 hinic_hwif_write_reg(hwif, addr, attr4);
146 * set_ppf - try to set hwif as ppf and set the type of hwif in this case
147 * @hwif: the hardware interface of a pci function device
149 static void set_ppf(struct hinic_hwif *hwif)
151 struct hinic_func_attr *attr = &hwif->attr;
152 u32 addr, val, ppf_election;
154 /* Read Modify Write */
155 addr = HINIC_CSR_PPF_ELECTION_ADDR;
157 val = hinic_hwif_read_reg(hwif, addr);
158 val = HINIC_PPF_ELECTION_CLEAR(val, IDX);
160 ppf_election = HINIC_PPF_ELECTION_SET(attr->func_global_idx, IDX);
163 hinic_hwif_write_reg(hwif, addr, val);
166 val = hinic_hwif_read_reg(hwif, addr);
168 attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX);
169 if (attr->ppf_idx == attr->func_global_idx)
170 attr->func_type = TYPE_PPF;
173 static void init_db_area_idx(struct hinic_free_db_area *free_db_area)
177 for (i = 0; i < HINIC_DB_MAX_AREAS; i++)
178 free_db_area->db_idx[i] = i;
180 free_db_area->alloc_pos = 0;
181 free_db_area->return_pos = 0;
183 free_db_area->num_free = HINIC_DB_MAX_AREAS;
185 spin_lock_init(&free_db_area->idx_lock);
188 static int get_db_idx(struct hinic_hwif *hwif, u32 *idx)
190 struct hinic_free_db_area *free_db_area = &hwif->free_db_area;
194 spin_lock(&free_db_area->idx_lock);
196 if (free_db_area->num_free == 0) {
197 spin_unlock(&free_db_area->idx_lock);
201 free_db_area->num_free--;
203 pos = free_db_area->alloc_pos++;
204 pos &= HINIC_DB_MAX_AREAS - 1;
206 pg_idx = free_db_area->db_idx[pos];
208 free_db_area->db_idx[pos] = 0xFFFFFFFF;
210 spin_unlock(&free_db_area->idx_lock);
217 static void free_db_idx(struct hinic_hwif *hwif, u32 idx)
219 struct hinic_free_db_area *free_db_area = &hwif->free_db_area;
222 spin_lock(&free_db_area->idx_lock);
224 pos = free_db_area->return_pos++;
225 pos &= HINIC_DB_MAX_AREAS - 1;
227 free_db_area->db_idx[pos] = idx;
229 free_db_area->num_free++;
231 spin_unlock(&free_db_area->idx_lock);
234 void hinic_free_db_addr(void *hwdev, void __iomem *db_base)
236 struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
237 u32 idx = DB_IDX(db_base, hwif->db_base);
239 free_db_idx(hwif, idx);
242 int hinic_alloc_db_addr(void *hwdev, void __iomem **db_base)
244 struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
248 err = get_db_idx(hwif, &idx);
252 *db_base = hwif->db_base + idx * HINIC_DB_PAGE_SIZE;
257 void hinic_set_msix_state(void *hwdev, u16 msix_idx, enum hinic_msix_state flag)
259 struct hinic_hwdev *hw = hwdev;
260 struct hinic_hwif *hwif = hw->hwif;
261 u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE
262 + HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL;
265 /* vfio-pci does not mmap msi-x vector table to user space,
266 * we can not access the space when kernel driver is vfio-pci
268 if (hw->pcidev_hdl->kdrv == RTE_KDRV_VFIO)
271 mask_bits = readl(hwif->intr_regs_base + offset);
272 mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT;
274 mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT;
276 writel(mask_bits, hwif->intr_regs_base + offset);
279 static void disable_all_msix(struct hinic_hwdev *hwdev)
281 u16 num_irqs = hwdev->hwif->attr.num_irqs;
284 for (i = 0; i < num_irqs; i++)
285 hinic_set_msix_state(hwdev, i, HINIC_MSIX_DISABLE);
288 static int wait_until_doorbell_and_outbound_enabled(struct hinic_hwif *hwif)
291 enum hinic_doorbell_ctrl db_ctrl;
292 enum hinic_outbound_ctrl outbound_ctrl;
295 msecs_to_jiffies(HINIC_WAIT_DOORBELL_AND_OUTBOUND_TIMEOUT);
297 db_ctrl = hinic_get_doorbell_ctrl_status(hwif);
298 outbound_ctrl = hinic_get_outbound_ctrl_status(hwif);
300 if (outbound_ctrl == ENABLE_OUTBOUND &&
301 db_ctrl == ENABLE_DOORBELL)
305 } while (time_before(jiffies, end));
310 u16 hinic_global_func_id(void *hwdev)
312 struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
314 return hwif->attr.func_global_idx;
317 enum func_type hinic_func_type(void *hwdev)
319 struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
321 return hwif->attr.func_type;
324 u8 hinic_ppf_idx(void *hwdev)
326 struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
328 return hwif->attr.ppf_idx;
332 * hinic_init_hwif - initialize the hw interface
333 * @hwdev: the pointer to the private hardware device object
334 * @cfg_reg_base: base physical address of configuration registers
335 * @intr_reg_base: base physical address of msi-x vector table
336 * @db_base_phy: base physical address of doorbell registers
337 * @db_base: base virtual address of doorbell registers
338 * @dwqe_mapping: direct wqe io mapping address
339 * Return: 0 - success, negative - failure
341 static int hinic_init_hwif(struct hinic_hwdev *hwdev, void *cfg_reg_base,
342 void *intr_reg_base, u64 db_base_phy,
343 void *db_base, __rte_unused void *dwqe_mapping)
345 struct hinic_hwif *hwif;
350 hwif->cfg_regs_base = (u8 __iomem *)cfg_reg_base;
351 hwif->intr_regs_base = (u8 __iomem *)intr_reg_base;
353 hwif->db_base_phy = db_base_phy;
354 hwif->db_base = (u8 __iomem *)db_base;
355 init_db_area_idx(&hwif->free_db_area);
359 err = hwif_ready(hwdev);
361 PMD_DRV_LOG(ERR, "Hwif is not ready");
365 err = wait_until_doorbell_and_outbound_enabled(hwif);
367 PMD_DRV_LOG(ERR, "Hw doorbell/outbound is disabled");
371 if (!HINIC_IS_VF(hwdev))
377 spin_lock_deinit(&hwif->free_db_area.idx_lock);
382 #define HINIC_HWIF_ATTR_REG_PRINT_NUM (6)
383 #define HINIC_HWIF_APICMD_REG_PRINT_NUM (2)
384 #define HINIC_HWIF_EQ_REG_PRINT_NUM (2)
386 static void hinic_parse_hwif_attr(struct hinic_hwdev *hwdev)
388 struct hinic_hwif *hwif = hwdev->hwif;
390 PMD_DRV_LOG(INFO, "Device %s hwif attribute:", hwdev->pcidev_hdl->name);
391 PMD_DRV_LOG(INFO, "func_idx:%u, p2p_idx:%u, pciintf_idx:%u, "
392 "vf_in_pf:%u, ppf_idx:%u, global_vf_id:%u, func_type:%u",
393 hwif->attr.func_global_idx,
394 hwif->attr.port_to_port_idx, hwif->attr.pci_intf_idx,
395 hwif->attr.vf_in_pf, hwif->attr.ppf_idx,
396 hwif->attr.global_vf_id_of_pf, hwif->attr.func_type);
397 PMD_DRV_LOG(INFO, "num_aeqs:%u, num_ceqs:%u, num_irqs:%u, dma_attr:%u",
398 hwif->attr.num_aeqs, hwif->attr.num_ceqs,
399 hwif->attr.num_irqs, hwif->attr.num_dma_attr);
402 static void hinic_get_mmio(struct hinic_hwdev *hwdev, void **cfg_regs_base,
403 void **intr_base, void **db_base)
405 struct rte_pci_device *pci_dev = hwdev->pcidev_hdl;
407 *cfg_regs_base = pci_dev->mem_resource[HINIC_CFG_REGS_BAR].addr;
408 *intr_base = pci_dev->mem_resource[HINIC_INTR_MSI_BAR].addr;
409 *db_base = pci_dev->mem_resource[HINIC_DB_MEM_BAR].addr;
412 void hinic_hwif_res_free(struct hinic_hwdev *hwdev)
414 rte_free(hwdev->hwif);
418 int hinic_hwif_res_init(struct hinic_hwdev *hwdev)
420 int err = HINIC_ERROR;
421 void *cfg_regs_base, *db_base, *intr_base = NULL;
423 /* hinic related init */
424 hwdev->hwif = rte_zmalloc("hinic_hwif", sizeof(*hwdev->hwif),
425 RTE_CACHE_LINE_SIZE);
427 PMD_DRV_LOG(ERR, "Allocate hwif failed, dev_name: %s",
428 hwdev->pcidev_hdl->name);
432 hinic_get_mmio(hwdev, &cfg_regs_base, &intr_base, &db_base);
434 err = hinic_init_hwif(hwdev, cfg_regs_base,
435 intr_base, 0, db_base, NULL);
437 PMD_DRV_LOG(ERR, "Initialize hwif failed, dev_name: %s",
438 hwdev->pcidev_hdl->name);
442 /* disable msix interrupt in hw device */
443 disable_all_msix(hwdev);
445 /* print hwif attributes */
446 hinic_parse_hwif_attr(hwdev);
451 rte_free(hwdev->hwif);
458 * hinic_misx_intr_clear_resend_bit - clear interrupt resend configuration
459 * @hwdev: the hardware interface of a nic device
460 * @msix_idx: Index of msix interrupt
461 * @clear_resend_en: enable flag of clear resend configuration
463 void hinic_misx_intr_clear_resend_bit(void *hwdev, u16 msix_idx,
466 struct hinic_hwif *hwif = ((struct hinic_hwdev *)hwdev)->hwif;
467 u32 msix_ctrl = 0, addr;
469 msix_ctrl = HINIC_MSIX_CNT_SET(clear_resend_en, RESEND_TIMER);
471 addr = HINIC_CSR_MSIX_CNT_ADDR(msix_idx);
473 hinic_hwif_write_reg(hwif, addr, msix_ctrl);