1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #ifndef _HINIC_PMD_NICIO_H_
6 #define _HINIC_PMD_NICIO_H_
8 #define RX_BUF_LEN_16K 16384
9 #define RX_BUF_LEN_1_5K 1536
12 #define HINIC_VHD_TYPE_0B 2
13 #define HINIC_VHD_TYPE_10B 1
14 #define HINIC_VHD_TYPE_12B 0
16 #define HINIC_Q_CTXT_MAX 42
18 /* performance: ci addr RTE_CACHE_SIZE(64B) alignment */
19 #define HINIC_CI_Q_ADDR_SIZE 64
21 #define CI_TABLE_SIZE(num_qps, pg_sz) \
22 (ALIGN((num_qps) * HINIC_CI_Q_ADDR_SIZE, pg_sz))
24 #define HINIC_CI_VADDR(base_addr, q_id) \
25 ((u8 *)(base_addr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
27 #define HINIC_CI_PADDR(base_paddr, q_id) \
28 ((base_paddr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
30 #define Q_CTXT_SIZE 48
31 #define TSO_LRO_CTXT_SIZE 240
33 #define SQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
34 (((max_rqs) + (max_sqs)) * TSO_LRO_CTXT_SIZE + \
37 #define RQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
38 (((max_rqs) + (max_sqs)) * TSO_LRO_CTXT_SIZE + \
39 (max_sqs) * Q_CTXT_SIZE + (q_id) * Q_CTXT_SIZE)
41 #define SQ_CTXT_SIZE(num_sqs) \
42 ((u16)(sizeof(struct hinic_qp_ctxt_header) + \
43 (num_sqs) * sizeof(struct hinic_sq_ctxt)))
45 #define RQ_CTXT_SIZE(num_rqs) \
46 ((u16)(sizeof(struct hinic_qp_ctxt_header) + \
47 (num_rqs) * sizeof(struct hinic_rq_ctxt)))
49 #define SQ_CTXT_CEQ_ATTR_CEQ_ID_SHIFT 8
50 #define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT 13
51 #define SQ_CTXT_CEQ_ATTR_EN_SHIFT 23
52 #define SQ_CTXT_CEQ_ATTR_ARM_SHIFT 31
54 #define SQ_CTXT_CEQ_ATTR_CEQ_ID_MASK 0x1FU
55 #define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FFU
56 #define SQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
57 #define SQ_CTXT_CEQ_ATTR_ARM_MASK 0x1U
59 #define SQ_CTXT_CEQ_ATTR_SET(val, member) \
60 (((val) & SQ_CTXT_CEQ_ATTR_##member##_MASK) << \
61 SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
63 #define SQ_CTXT_CI_IDX_SHIFT 11
64 #define SQ_CTXT_CI_OWNER_SHIFT 23
66 #define SQ_CTXT_CI_IDX_MASK 0xFFFU
67 #define SQ_CTXT_CI_OWNER_MASK 0x1U
69 #define SQ_CTXT_CI_SET(val, member) \
70 (((val) & SQ_CTXT_CI_##member##_MASK) << SQ_CTXT_CI_##member##_SHIFT)
72 #define SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
73 #define SQ_CTXT_WQ_PAGE_PI_SHIFT 20
75 #define SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
76 #define SQ_CTXT_WQ_PAGE_PI_MASK 0xFFFU
78 #define SQ_CTXT_WQ_PAGE_SET(val, member) \
79 (((val) & SQ_CTXT_WQ_PAGE_##member##_MASK) << \
80 SQ_CTXT_WQ_PAGE_##member##_SHIFT)
82 #define SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
83 #define SQ_CTXT_PREF_CACHE_MAX_SHIFT 14
84 #define SQ_CTXT_PREF_CACHE_MIN_SHIFT 25
86 #define SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFFU
87 #define SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FFU
88 #define SQ_CTXT_PREF_CACHE_MIN_MASK 0x7FU
90 #define SQ_CTXT_PREF_WQ_PFN_HI_SHIFT 0
91 #define SQ_CTXT_PREF_CI_SHIFT 20
93 #define SQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
94 #define SQ_CTXT_PREF_CI_MASK 0xFFFU
96 #define SQ_CTXT_PREF_SET(val, member) \
97 (((val) & SQ_CTXT_PREF_##member##_MASK) << \
98 SQ_CTXT_PREF_##member##_SHIFT)
100 #define SQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
102 #define SQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
104 #define SQ_CTXT_WQ_BLOCK_SET(val, member) \
105 (((val) & SQ_CTXT_WQ_BLOCK_##member##_MASK) << \
106 SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
108 #define RQ_CTXT_CEQ_ATTR_EN_SHIFT 0
109 #define RQ_CTXT_CEQ_ATTR_OWNER_SHIFT 1
111 #define RQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
112 #define RQ_CTXT_CEQ_ATTR_OWNER_MASK 0x1U
114 #define RQ_CTXT_CEQ_ATTR_SET(val, member) \
115 (((val) & RQ_CTXT_CEQ_ATTR_##member##_MASK) << \
116 RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
118 #define RQ_CTXT_PI_IDX_SHIFT 0
119 #define RQ_CTXT_PI_INTR_SHIFT 22
120 #define RQ_CTXT_PI_CEQ_ARM_SHIFT 31
122 #define RQ_CTXT_PI_IDX_MASK 0xFFFU
123 #define RQ_CTXT_PI_INTR_MASK 0x3FFU
124 #define RQ_CTXT_PI_CEQ_ARM_MASK 0x1U
126 #define RQ_CTXT_PI_SET(val, member) \
127 (((val) & RQ_CTXT_PI_##member##_MASK) << RQ_CTXT_PI_##member##_SHIFT)
129 #define RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
130 #define RQ_CTXT_WQ_PAGE_CI_SHIFT 20
132 #define RQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
133 #define RQ_CTXT_WQ_PAGE_CI_MASK 0xFFFU
135 #define RQ_CTXT_WQ_PAGE_SET(val, member) \
136 (((val) & RQ_CTXT_WQ_PAGE_##member##_MASK) << \
137 RQ_CTXT_WQ_PAGE_##member##_SHIFT)
139 #define RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
140 #define RQ_CTXT_PREF_CACHE_MAX_SHIFT 14
141 #define RQ_CTXT_PREF_CACHE_MIN_SHIFT 25
143 #define RQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFFU
144 #define RQ_CTXT_PREF_CACHE_MAX_MASK 0x7FFU
145 #define RQ_CTXT_PREF_CACHE_MIN_MASK 0x7FU
147 #define RQ_CTXT_PREF_WQ_PFN_HI_SHIFT 0
148 #define RQ_CTXT_PREF_CI_SHIFT 20
150 #define RQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
151 #define RQ_CTXT_PREF_CI_MASK 0xFFFU
153 #define RQ_CTXT_PREF_SET(val, member) \
154 (((val) & RQ_CTXT_PREF_##member##_MASK) << \
155 RQ_CTXT_PREF_##member##_SHIFT)
157 #define RQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
159 #define RQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
161 #define RQ_CTXT_WQ_BLOCK_SET(val, member) \
162 (((val) & RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
163 RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
165 #define SIZE_16BYTES(size) (ALIGN((size), 16) >> 4)
167 enum hinic_qp_ctxt_type {
168 HINIC_QP_CTXT_TYPE_SQ,
169 HINIC_QP_CTXT_TYPE_RQ,
174 volatile u16 *cons_idx_addr;
175 void __iomem *db_addr;
184 volatile u16 *pi_virt_addr;
185 dma_addr_t pi_dma_addr;
199 void (*tx_ack)(void *handle, u16 q_id);
200 /* status: 0 - link down; 1 - link up */
201 void (*link_change)(void *handle, int status);
204 struct hinic_nic_io {
205 struct hinic_hwdev *hwdev;
209 struct hinic_wq *sq_wq;
210 struct hinic_wq *rq_wq;
224 struct hinic_qp *qps;
225 /* sq ci mem base addr of the function */
227 dma_addr_t ci_dma_base;
229 struct hinic_event event;
237 int hinic_init_qp_ctxts(struct hinic_hwdev *hwdev);
239 void hinic_free_qp_ctxts(struct hinic_hwdev *hwdev);
241 int hinic_rx_tx_flush(struct hinic_hwdev *hwdev);
243 int hinic_get_sq_free_wqebbs(struct hinic_hwdev *hwdev, u16 q_id);
245 u16 hinic_get_sq_local_ci(struct hinic_hwdev *hwdev, u16 q_id);
247 void hinic_update_sq_local_ci(struct hinic_hwdev *hwdev, u16 q_id,
250 void hinic_return_sq_wqe(struct hinic_hwdev *hwdev, u16 q_id,
251 int num_wqebbs, u16 owner);
253 int hinic_get_rq_free_wqebbs(struct hinic_hwdev *hwdev, u16 q_id);
255 void *hinic_get_rq_wqe(struct hinic_hwdev *hwdev, u16 q_id, u16 *pi);
257 void hinic_return_rq_wqe(struct hinic_hwdev *hwdev, u16 q_id, int num_wqebbs);
259 u16 hinic_get_rq_local_ci(struct hinic_hwdev *hwdev, u16 q_id);
261 void hinic_update_rq_local_ci(struct hinic_hwdev *hwdev, u16 q_id, int wqe_cnt);
263 int hinic_init_nicio(struct hinic_hwdev *hwdev);
265 void hinic_deinit_nicio(struct hinic_hwdev *hwdev);
267 int hinic_convert_rx_buf_size(u32 rx_buf_sz, u32 *match_sz);
269 #endif /* _HINIC_PMD_NICIO_H_ */