1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #ifndef _HINIC_PMD_NICIO_H_
6 #define _HINIC_PMD_NICIO_H_
8 #define RX_BUF_LEN_16K 16384
9 #define RX_BUF_LEN_1_5K 1536
11 #define HINIC_Q_CTXT_MAX 42
13 /* performance: ci addr RTE_CACHE_SIZE(64B) alignment */
14 #define HINIC_CI_Q_ADDR_SIZE 64
16 #define CI_TABLE_SIZE(num_qps, pg_sz) \
17 (ALIGN((num_qps) * HINIC_CI_Q_ADDR_SIZE, pg_sz))
19 #define HINIC_CI_VADDR(base_addr, q_id) \
20 ((u8 *)(base_addr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
22 #define HINIC_CI_PADDR(base_paddr, q_id) \
23 ((base_paddr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
25 #define Q_CTXT_SIZE 48
26 #define TSO_LRO_CTXT_SIZE 240
28 #define SQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
29 (((max_rqs) + (max_sqs)) * TSO_LRO_CTXT_SIZE + \
32 #define RQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
33 (((max_rqs) + (max_sqs)) * TSO_LRO_CTXT_SIZE + \
34 (max_sqs) * Q_CTXT_SIZE + (q_id) * Q_CTXT_SIZE)
36 #define SQ_CTXT_SIZE(num_sqs) \
37 ((u16)(sizeof(struct hinic_qp_ctxt_header) + \
38 (num_sqs) * sizeof(struct hinic_sq_ctxt)))
40 #define RQ_CTXT_SIZE(num_rqs) \
41 ((u16)(sizeof(struct hinic_qp_ctxt_header) + \
42 (num_rqs) * sizeof(struct hinic_rq_ctxt)))
44 #define SQ_CTXT_CEQ_ATTR_CEQ_ID_SHIFT 8
45 #define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT 13
46 #define SQ_CTXT_CEQ_ATTR_EN_SHIFT 23
47 #define SQ_CTXT_CEQ_ATTR_ARM_SHIFT 31
49 #define SQ_CTXT_CEQ_ATTR_CEQ_ID_MASK 0x1FU
50 #define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FFU
51 #define SQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
52 #define SQ_CTXT_CEQ_ATTR_ARM_MASK 0x1U
54 #define SQ_CTXT_CEQ_ATTR_SET(val, member) \
55 (((val) & SQ_CTXT_CEQ_ATTR_##member##_MASK) << \
56 SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
58 #define SQ_CTXT_CI_IDX_SHIFT 11
59 #define SQ_CTXT_CI_OWNER_SHIFT 23
61 #define SQ_CTXT_CI_IDX_MASK 0xFFFU
62 #define SQ_CTXT_CI_OWNER_MASK 0x1U
64 #define SQ_CTXT_CI_SET(val, member) \
65 (((val) & SQ_CTXT_CI_##member##_MASK) << SQ_CTXT_CI_##member##_SHIFT)
67 #define SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
68 #define SQ_CTXT_WQ_PAGE_PI_SHIFT 20
70 #define SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
71 #define SQ_CTXT_WQ_PAGE_PI_MASK 0xFFFU
73 #define SQ_CTXT_WQ_PAGE_SET(val, member) \
74 (((val) & SQ_CTXT_WQ_PAGE_##member##_MASK) << \
75 SQ_CTXT_WQ_PAGE_##member##_SHIFT)
77 #define SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
78 #define SQ_CTXT_PREF_CACHE_MAX_SHIFT 14
79 #define SQ_CTXT_PREF_CACHE_MIN_SHIFT 25
81 #define SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFFU
82 #define SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FFU
83 #define SQ_CTXT_PREF_CACHE_MIN_MASK 0x7FU
85 #define SQ_CTXT_PREF_WQ_PFN_HI_SHIFT 0
86 #define SQ_CTXT_PREF_CI_SHIFT 20
88 #define SQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
89 #define SQ_CTXT_PREF_CI_MASK 0xFFFU
91 #define SQ_CTXT_PREF_SET(val, member) \
92 (((val) & SQ_CTXT_PREF_##member##_MASK) << \
93 SQ_CTXT_PREF_##member##_SHIFT)
95 #define SQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
97 #define SQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
99 #define SQ_CTXT_WQ_BLOCK_SET(val, member) \
100 (((val) & SQ_CTXT_WQ_BLOCK_##member##_MASK) << \
101 SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
103 #define RQ_CTXT_CEQ_ATTR_EN_SHIFT 0
104 #define RQ_CTXT_CEQ_ATTR_OWNER_SHIFT 1
106 #define RQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
107 #define RQ_CTXT_CEQ_ATTR_OWNER_MASK 0x1U
109 #define RQ_CTXT_CEQ_ATTR_SET(val, member) \
110 (((val) & RQ_CTXT_CEQ_ATTR_##member##_MASK) << \
111 RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
113 #define RQ_CTXT_PI_IDX_SHIFT 0
114 #define RQ_CTXT_PI_INTR_SHIFT 22
115 #define RQ_CTXT_PI_CEQ_ARM_SHIFT 31
117 #define RQ_CTXT_PI_IDX_MASK 0xFFFU
118 #define RQ_CTXT_PI_INTR_MASK 0x3FFU
119 #define RQ_CTXT_PI_CEQ_ARM_MASK 0x1U
121 #define RQ_CTXT_PI_SET(val, member) \
122 (((val) & RQ_CTXT_PI_##member##_MASK) << RQ_CTXT_PI_##member##_SHIFT)
124 #define RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
125 #define RQ_CTXT_WQ_PAGE_CI_SHIFT 20
127 #define RQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
128 #define RQ_CTXT_WQ_PAGE_CI_MASK 0xFFFU
130 #define RQ_CTXT_WQ_PAGE_SET(val, member) \
131 (((val) & RQ_CTXT_WQ_PAGE_##member##_MASK) << \
132 RQ_CTXT_WQ_PAGE_##member##_SHIFT)
134 #define RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
135 #define RQ_CTXT_PREF_CACHE_MAX_SHIFT 14
136 #define RQ_CTXT_PREF_CACHE_MIN_SHIFT 25
138 #define RQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFFU
139 #define RQ_CTXT_PREF_CACHE_MAX_MASK 0x7FFU
140 #define RQ_CTXT_PREF_CACHE_MIN_MASK 0x7FU
142 #define RQ_CTXT_PREF_WQ_PFN_HI_SHIFT 0
143 #define RQ_CTXT_PREF_CI_SHIFT 20
145 #define RQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
146 #define RQ_CTXT_PREF_CI_MASK 0xFFFU
148 #define RQ_CTXT_PREF_SET(val, member) \
149 (((val) & RQ_CTXT_PREF_##member##_MASK) << \
150 RQ_CTXT_PREF_##member##_SHIFT)
152 #define RQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
154 #define RQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
156 #define RQ_CTXT_WQ_BLOCK_SET(val, member) \
157 (((val) & RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
158 RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
160 #define SIZE_16BYTES(size) (ALIGN((size), 16) >> 4)
162 enum hinic_qp_ctxt_type {
163 HINIC_QP_CTXT_TYPE_SQ,
164 HINIC_QP_CTXT_TYPE_RQ,
169 volatile u16 *cons_idx_addr;
170 void __iomem *db_addr;
179 volatile u16 *pi_virt_addr;
180 dma_addr_t pi_dma_addr;
194 void (*tx_ack)(void *handle, u16 q_id);
195 /* status: 0 - link down; 1 - link up */
196 void (*link_change)(void *handle, int status);
199 struct hinic_nic_io {
200 struct hinic_hwdev *hwdev;
204 struct hinic_wq *sq_wq;
205 struct hinic_wq *rq_wq;
219 struct hinic_qp *qps;
220 /* sq ci mem base addr of the function */
222 dma_addr_t ci_dma_base;
224 struct hinic_event event;
232 int hinic_init_qp_ctxts(struct hinic_hwdev *hwdev);
234 void hinic_free_qp_ctxts(struct hinic_hwdev *hwdev);
236 int hinic_rx_tx_flush(struct hinic_hwdev *hwdev);
238 int hinic_get_sq_free_wqebbs(struct hinic_hwdev *hwdev, u16 q_id);
240 u16 hinic_get_sq_local_ci(struct hinic_hwdev *hwdev, u16 q_id);
242 void hinic_update_sq_local_ci(struct hinic_hwdev *hwdev, u16 q_id,
245 void hinic_return_sq_wqe(struct hinic_hwdev *hwdev, u16 q_id,
246 int num_wqebbs, u16 owner);
248 int hinic_get_rq_free_wqebbs(struct hinic_hwdev *hwdev, u16 q_id);
250 void *hinic_get_rq_wqe(struct hinic_hwdev *hwdev, u16 q_id, u16 *pi);
252 void hinic_return_rq_wqe(struct hinic_hwdev *hwdev, u16 q_id, int num_wqebbs);
254 u16 hinic_get_rq_local_ci(struct hinic_hwdev *hwdev, u16 q_id);
256 void hinic_update_rq_local_ci(struct hinic_hwdev *hwdev, u16 q_id, int wqe_cnt);
258 int hinic_init_nicio(struct hinic_hwdev *hwdev);
260 void hinic_deinit_nicio(struct hinic_hwdev *hwdev);
262 int hinic_convert_rx_buf_size(u32 rx_buf_sz, u32 *match_sz);
264 #endif /* _HINIC_PMD_NICIO_H_ */