1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
6 #include <rte_bus_pci.h>
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
10 #include <rte_memcpy.h>
11 #include <rte_mempool.h>
12 #include <rte_errno.h>
14 #include "base/hinic_compat.h"
15 #include "base/hinic_pmd_hwdev.h"
16 #include "base/hinic_pmd_hwif.h"
17 #include "base/hinic_pmd_wq.h"
18 #include "base/hinic_pmd_cfg.h"
19 #include "base/hinic_pmd_mgmt.h"
20 #include "base/hinic_pmd_cmdq.h"
21 #include "base/hinic_pmd_niccfg.h"
22 #include "base/hinic_pmd_nicio.h"
23 #include "hinic_pmd_ethdev.h"
24 #include "hinic_pmd_tx.h"
25 #include "hinic_pmd_rx.h"
27 /* Vendor ID used by Huawei devices */
28 #define HINIC_HUAWEI_VENDOR_ID 0x19E5
31 #define HINIC_DEV_ID_PRD 0x1822
32 #define HINIC_DEV_ID_MEZZ_25GE 0x0210
33 #define HINIC_DEV_ID_MEZZ_40GE 0x020D
34 #define HINIC_DEV_ID_MEZZ_100GE 0x0205
36 #define HINIC_SERVICE_MODE_NIC 2
38 #define HINIC_INTR_CB_UNREG_MAX_RETRIES 10
40 #define DEFAULT_BASE_COS 4
43 #define HINIC_MIN_RX_BUF_SIZE 1024
44 #define HINIC_MAX_MAC_ADDRS 1
46 /** Driver-specific log messages type. */
49 struct hinic_xstats_name_off {
50 char name[RTE_ETH_XSTATS_NAME_SIZE];
54 #define HINIC_FUNC_STAT(_stat_item) { \
55 .name = #_stat_item, \
56 .offset = offsetof(struct hinic_vport_stats, _stat_item) \
59 #define HINIC_PORT_STAT(_stat_item) { \
60 .name = #_stat_item, \
61 .offset = offsetof(struct hinic_phy_port_stats, _stat_item) \
64 static const struct hinic_xstats_name_off hinic_vport_stats_strings[] = {
65 HINIC_FUNC_STAT(tx_unicast_pkts_vport),
66 HINIC_FUNC_STAT(tx_unicast_bytes_vport),
67 HINIC_FUNC_STAT(tx_multicast_pkts_vport),
68 HINIC_FUNC_STAT(tx_multicast_bytes_vport),
69 HINIC_FUNC_STAT(tx_broadcast_pkts_vport),
70 HINIC_FUNC_STAT(tx_broadcast_bytes_vport),
72 HINIC_FUNC_STAT(rx_unicast_pkts_vport),
73 HINIC_FUNC_STAT(rx_unicast_bytes_vport),
74 HINIC_FUNC_STAT(rx_multicast_pkts_vport),
75 HINIC_FUNC_STAT(rx_multicast_bytes_vport),
76 HINIC_FUNC_STAT(rx_broadcast_pkts_vport),
77 HINIC_FUNC_STAT(rx_broadcast_bytes_vport),
79 HINIC_FUNC_STAT(tx_discard_vport),
80 HINIC_FUNC_STAT(rx_discard_vport),
81 HINIC_FUNC_STAT(tx_err_vport),
82 HINIC_FUNC_STAT(rx_err_vport),
85 #define HINIC_VPORT_XSTATS_NUM (sizeof(hinic_vport_stats_strings) / \
86 sizeof(hinic_vport_stats_strings[0]))
88 static const struct hinic_xstats_name_off hinic_phyport_stats_strings[] = {
89 HINIC_PORT_STAT(mac_rx_total_pkt_num),
90 HINIC_PORT_STAT(mac_rx_total_oct_num),
91 HINIC_PORT_STAT(mac_rx_bad_pkt_num),
92 HINIC_PORT_STAT(mac_rx_bad_oct_num),
93 HINIC_PORT_STAT(mac_rx_good_pkt_num),
94 HINIC_PORT_STAT(mac_rx_good_oct_num),
95 HINIC_PORT_STAT(mac_rx_uni_pkt_num),
96 HINIC_PORT_STAT(mac_rx_multi_pkt_num),
97 HINIC_PORT_STAT(mac_rx_broad_pkt_num),
98 HINIC_PORT_STAT(mac_tx_total_pkt_num),
99 HINIC_PORT_STAT(mac_tx_total_oct_num),
100 HINIC_PORT_STAT(mac_tx_bad_pkt_num),
101 HINIC_PORT_STAT(mac_tx_bad_oct_num),
102 HINIC_PORT_STAT(mac_tx_good_pkt_num),
103 HINIC_PORT_STAT(mac_tx_good_oct_num),
104 HINIC_PORT_STAT(mac_tx_uni_pkt_num),
105 HINIC_PORT_STAT(mac_tx_multi_pkt_num),
106 HINIC_PORT_STAT(mac_tx_broad_pkt_num),
107 HINIC_PORT_STAT(mac_rx_fragment_pkt_num),
108 HINIC_PORT_STAT(mac_rx_undersize_pkt_num),
109 HINIC_PORT_STAT(mac_rx_undermin_pkt_num),
110 HINIC_PORT_STAT(mac_rx_64_oct_pkt_num),
111 HINIC_PORT_STAT(mac_rx_65_127_oct_pkt_num),
112 HINIC_PORT_STAT(mac_rx_128_255_oct_pkt_num),
113 HINIC_PORT_STAT(mac_rx_256_511_oct_pkt_num),
114 HINIC_PORT_STAT(mac_rx_512_1023_oct_pkt_num),
115 HINIC_PORT_STAT(mac_rx_1024_1518_oct_pkt_num),
116 HINIC_PORT_STAT(mac_rx_1519_2047_oct_pkt_num),
117 HINIC_PORT_STAT(mac_rx_2048_4095_oct_pkt_num),
118 HINIC_PORT_STAT(mac_rx_4096_8191_oct_pkt_num),
119 HINIC_PORT_STAT(mac_rx_8192_9216_oct_pkt_num),
120 HINIC_PORT_STAT(mac_rx_9217_12287_oct_pkt_num),
121 HINIC_PORT_STAT(mac_rx_12288_16383_oct_pkt_num),
122 HINIC_PORT_STAT(mac_rx_1519_max_bad_pkt_num),
123 HINIC_PORT_STAT(mac_rx_1519_max_good_pkt_num),
124 HINIC_PORT_STAT(mac_rx_oversize_pkt_num),
125 HINIC_PORT_STAT(mac_rx_jabber_pkt_num),
126 HINIC_PORT_STAT(mac_rx_mac_pause_num),
127 HINIC_PORT_STAT(mac_rx_pfc_pkt_num),
128 HINIC_PORT_STAT(mac_rx_pfc_pri0_pkt_num),
129 HINIC_PORT_STAT(mac_rx_pfc_pri1_pkt_num),
130 HINIC_PORT_STAT(mac_rx_pfc_pri2_pkt_num),
131 HINIC_PORT_STAT(mac_rx_pfc_pri3_pkt_num),
132 HINIC_PORT_STAT(mac_rx_pfc_pri4_pkt_num),
133 HINIC_PORT_STAT(mac_rx_pfc_pri5_pkt_num),
134 HINIC_PORT_STAT(mac_rx_pfc_pri6_pkt_num),
135 HINIC_PORT_STAT(mac_rx_pfc_pri7_pkt_num),
136 HINIC_PORT_STAT(mac_rx_mac_control_pkt_num),
137 HINIC_PORT_STAT(mac_rx_sym_err_pkt_num),
138 HINIC_PORT_STAT(mac_rx_fcs_err_pkt_num),
139 HINIC_PORT_STAT(mac_rx_send_app_good_pkt_num),
140 HINIC_PORT_STAT(mac_rx_send_app_bad_pkt_num),
141 HINIC_PORT_STAT(mac_tx_fragment_pkt_num),
142 HINIC_PORT_STAT(mac_tx_undersize_pkt_num),
143 HINIC_PORT_STAT(mac_tx_undermin_pkt_num),
144 HINIC_PORT_STAT(mac_tx_64_oct_pkt_num),
145 HINIC_PORT_STAT(mac_tx_65_127_oct_pkt_num),
146 HINIC_PORT_STAT(mac_tx_128_255_oct_pkt_num),
147 HINIC_PORT_STAT(mac_tx_256_511_oct_pkt_num),
148 HINIC_PORT_STAT(mac_tx_512_1023_oct_pkt_num),
149 HINIC_PORT_STAT(mac_tx_1024_1518_oct_pkt_num),
150 HINIC_PORT_STAT(mac_tx_1519_2047_oct_pkt_num),
151 HINIC_PORT_STAT(mac_tx_2048_4095_oct_pkt_num),
152 HINIC_PORT_STAT(mac_tx_4096_8191_oct_pkt_num),
153 HINIC_PORT_STAT(mac_tx_8192_9216_oct_pkt_num),
154 HINIC_PORT_STAT(mac_tx_9217_12287_oct_pkt_num),
155 HINIC_PORT_STAT(mac_tx_12288_16383_oct_pkt_num),
156 HINIC_PORT_STAT(mac_tx_1519_max_bad_pkt_num),
157 HINIC_PORT_STAT(mac_tx_1519_max_good_pkt_num),
158 HINIC_PORT_STAT(mac_tx_oversize_pkt_num),
159 HINIC_PORT_STAT(mac_trans_jabber_pkt_num),
160 HINIC_PORT_STAT(mac_tx_mac_pause_num),
161 HINIC_PORT_STAT(mac_tx_pfc_pkt_num),
162 HINIC_PORT_STAT(mac_tx_pfc_pri0_pkt_num),
163 HINIC_PORT_STAT(mac_tx_pfc_pri1_pkt_num),
164 HINIC_PORT_STAT(mac_tx_pfc_pri2_pkt_num),
165 HINIC_PORT_STAT(mac_tx_pfc_pri3_pkt_num),
166 HINIC_PORT_STAT(mac_tx_pfc_pri4_pkt_num),
167 HINIC_PORT_STAT(mac_tx_pfc_pri5_pkt_num),
168 HINIC_PORT_STAT(mac_tx_pfc_pri6_pkt_num),
169 HINIC_PORT_STAT(mac_tx_pfc_pri7_pkt_num),
170 HINIC_PORT_STAT(mac_tx_mac_control_pkt_num),
171 HINIC_PORT_STAT(mac_tx_err_all_pkt_num),
172 HINIC_PORT_STAT(mac_tx_from_app_good_pkt_num),
173 HINIC_PORT_STAT(mac_tx_from_app_bad_pkt_num),
176 #define HINIC_PHYPORT_XSTATS_NUM (sizeof(hinic_phyport_stats_strings) / \
177 sizeof(hinic_phyport_stats_strings[0]))
179 static const struct hinic_xstats_name_off hinic_rxq_stats_strings[] = {
180 {"rx_nombuf", offsetof(struct hinic_rxq_stats, rx_nombuf)},
181 {"burst_pkt", offsetof(struct hinic_rxq_stats, burst_pkts)},
184 #define HINIC_RXQ_XSTATS_NUM (sizeof(hinic_rxq_stats_strings) / \
185 sizeof(hinic_rxq_stats_strings[0]))
187 static const struct hinic_xstats_name_off hinic_txq_stats_strings[] = {
188 {"tx_busy", offsetof(struct hinic_txq_stats, tx_busy)},
189 {"offload_errors", offsetof(struct hinic_txq_stats, off_errs)},
190 {"copy_pkts", offsetof(struct hinic_txq_stats, cpy_pkts)},
191 {"rl_drop", offsetof(struct hinic_txq_stats, rl_drop)},
192 {"burst_pkts", offsetof(struct hinic_txq_stats, burst_pkts)},
195 #define HINIC_TXQ_XSTATS_NUM (sizeof(hinic_txq_stats_strings) / \
196 sizeof(hinic_txq_stats_strings[0]))
198 static int hinic_xstats_calc_num(struct hinic_nic_dev *nic_dev)
200 return (HINIC_VPORT_XSTATS_NUM +
201 HINIC_PHYPORT_XSTATS_NUM +
202 HINIC_RXQ_XSTATS_NUM * nic_dev->num_rq +
203 HINIC_TXQ_XSTATS_NUM * nic_dev->num_sq);
206 static const struct rte_eth_desc_lim hinic_rx_desc_lim = {
207 .nb_max = HINIC_MAX_QUEUE_DEPTH,
208 .nb_min = HINIC_MIN_QUEUE_DEPTH,
209 .nb_align = HINIC_RXD_ALIGN,
212 static const struct rte_eth_desc_lim hinic_tx_desc_lim = {
213 .nb_max = HINIC_MAX_QUEUE_DEPTH,
214 .nb_min = HINIC_MIN_QUEUE_DEPTH,
215 .nb_align = HINIC_TXD_ALIGN,
220 * Interrupt handler triggered by NIC for handling
223 * @param: The address of parameter (struct rte_eth_dev *) regsitered before.
225 static void hinic_dev_interrupt_handler(void *param)
227 struct rte_eth_dev *dev = param;
228 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
230 if (!hinic_test_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) {
231 PMD_DRV_LOG(WARNING, "Device's interrupt is disabled, ignore interrupt event, dev_name: %s, port_id: %d",
232 nic_dev->proc_dev_name, dev->data->port_id);
236 /* aeq0 msg handler */
237 hinic_dev_handle_aeq_event(nic_dev->hwdev, param);
241 * Ethernet device configuration.
243 * Prepare the driver for a given number of TX and RX queues, mtu size
247 * Pointer to Ethernet device structure.
250 * 0 on success, negative error value otherwise.
252 static int hinic_dev_configure(struct rte_eth_dev *dev)
254 struct hinic_nic_dev *nic_dev;
255 struct hinic_nic_io *nic_io;
258 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
259 nic_io = nic_dev->hwdev->nic_io;
261 nic_dev->num_sq = dev->data->nb_tx_queues;
262 nic_dev->num_rq = dev->data->nb_rx_queues;
264 nic_io->num_sqs = dev->data->nb_tx_queues;
265 nic_io->num_rqs = dev->data->nb_rx_queues;
267 /* queue pair is max_num(sq, rq) */
268 nic_dev->num_qps = (nic_dev->num_sq > nic_dev->num_rq) ?
269 nic_dev->num_sq : nic_dev->num_rq;
270 nic_io->num_qps = nic_dev->num_qps;
272 if (nic_dev->num_qps > nic_io->max_qps) {
274 "Queue number out of range, get queue_num:%d, max_queue_num:%d",
275 nic_dev->num_qps, nic_io->max_qps);
279 /* mtu size is 256~9600 */
280 if (dev->data->dev_conf.rxmode.max_rx_pkt_len < HINIC_MIN_FRAME_SIZE ||
281 dev->data->dev_conf.rxmode.max_rx_pkt_len >
282 HINIC_MAX_JUMBO_FRAME_SIZE) {
284 "Max rx pkt len out of range, get max_rx_pkt_len:%d, "
285 "expect between %d and %d",
286 dev->data->dev_conf.rxmode.max_rx_pkt_len,
287 HINIC_MIN_FRAME_SIZE, HINIC_MAX_JUMBO_FRAME_SIZE);
292 HINIC_PKTLEN_TO_MTU(dev->data->dev_conf.rxmode.max_rx_pkt_len);
295 err = hinic_config_mq_mode(dev, TRUE);
297 PMD_DRV_LOG(ERR, "Config multi-queue failed");
305 * DPDK callback to create the receive queue.
308 * Pointer to Ethernet device structure.
312 * Number of descriptors for receive queue.
314 * NUMA socket on which memory must be allocated.
316 * Thresholds parameters (unused_).
318 * Memory pool for buffer allocations.
321 * 0 on success, negative error value otherwise.
323 static int hinic_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
324 uint16_t nb_desc, unsigned int socket_id,
325 __rte_unused const struct rte_eth_rxconf *rx_conf,
326 struct rte_mempool *mp)
329 struct hinic_nic_dev *nic_dev;
330 struct hinic_hwdev *hwdev;
331 struct hinic_rxq *rxq;
332 u16 rq_depth, rx_free_thresh;
335 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
336 hwdev = nic_dev->hwdev;
338 /* queue depth must be power of 2, otherwise will be aligned up */
339 rq_depth = (nb_desc & (nb_desc - 1)) ?
340 ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc;
343 * Validate number of receive descriptors.
344 * It must not exceed hardware maximum and minimum.
346 if (rq_depth > HINIC_MAX_QUEUE_DEPTH ||
347 rq_depth < HINIC_MIN_QUEUE_DEPTH) {
348 PMD_DRV_LOG(ERR, "RX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)",
349 HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH,
350 (int)nb_desc, (int)rq_depth,
351 (int)dev->data->port_id, (int)queue_idx);
356 * The RX descriptor ring will be cleaned after rxq->rx_free_thresh
357 * descriptors are used or if the number of descriptors required
358 * to transmit a packet is greater than the number of free RX
360 * The following constraints must be satisfied:
361 * rx_free_thresh must be greater than 0.
362 * rx_free_thresh must be less than the size of the ring minus 1.
363 * When set to zero use default values.
365 rx_free_thresh = (u16)((rx_conf->rx_free_thresh) ?
366 rx_conf->rx_free_thresh : HINIC_DEFAULT_RX_FREE_THRESH);
367 if (rx_free_thresh >= (rq_depth - 1)) {
368 PMD_DRV_LOG(ERR, "rx_free_thresh must be less than the number of RX descriptors minus 1. (rx_free_thresh=%u port=%d queue=%d)",
369 (unsigned int)rx_free_thresh,
370 (int)dev->data->port_id,
375 rxq = rte_zmalloc_socket("hinic_rx_queue", sizeof(struct hinic_rxq),
376 RTE_CACHE_LINE_SIZE, socket_id);
378 PMD_DRV_LOG(ERR, "Allocate rxq[%d] failed, dev_name: %s",
379 queue_idx, dev->data->name);
382 nic_dev->rxqs[queue_idx] = rxq;
384 /* alloc rx sq hw wqepage*/
385 rc = hinic_create_rq(hwdev, queue_idx, rq_depth);
387 PMD_DRV_LOG(ERR, "Create rxq[%d] failed, dev_name: %s, rq_depth: %d",
388 queue_idx, dev->data->name, rq_depth);
392 /* mbuf pool must be assigned before setup rx resources */
396 hinic_convert_rx_buf_size(rte_pktmbuf_data_room_size(rxq->mb_pool) -
397 RTE_PKTMBUF_HEADROOM, &buf_size);
399 PMD_DRV_LOG(ERR, "Adjust buf size failed, dev_name: %s",
401 goto adjust_bufsize_fail;
404 /* rx queue info, rearm control */
405 rxq->wq = &hwdev->nic_io->rq_wq[queue_idx];
406 rxq->pi_virt_addr = hwdev->nic_io->qps[queue_idx].rq.pi_virt_addr;
407 rxq->nic_dev = nic_dev;
408 rxq->q_id = queue_idx;
409 rxq->q_depth = rq_depth;
410 rxq->buf_len = (u16)buf_size;
411 rxq->rx_free_thresh = rx_free_thresh;
413 /* the last point cant do mbuf rearm in bulk */
414 rxq->rxinfo_align_end = rxq->q_depth - rxq->rx_free_thresh;
416 /* device port identifier */
417 rxq->port_id = dev->data->port_id;
419 /* alloc rx_cqe and prepare rq_wqe */
420 rc = hinic_setup_rx_resources(rxq);
422 PMD_DRV_LOG(ERR, "Setup rxq[%d] rx_resources failed, dev_name:%s",
423 queue_idx, dev->data->name);
424 goto setup_rx_res_err;
427 /* record nic_dev rxq in rte_eth rx_queues */
428 dev->data->rx_queues[queue_idx] = rxq;
434 hinic_destroy_rq(hwdev, queue_idx);
442 static void hinic_reset_rx_queue(struct rte_eth_dev *dev)
444 struct hinic_rxq *rxq;
445 struct hinic_nic_dev *nic_dev;
448 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
450 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) {
451 rxq = dev->data->rx_queues[q_id];
453 rxq->wq->cons_idx = 0;
454 rxq->wq->prod_idx = 0;
455 rxq->wq->delta = rxq->q_depth;
456 rxq->wq->mask = rxq->q_depth - 1;
458 /* alloc mbuf to rq */
459 hinic_rx_alloc_pkts(rxq);
464 * DPDK callback to configure the transmit queue.
467 * Pointer to Ethernet device structure.
469 * Transmit queue index.
471 * Number of descriptors for transmit queue.
473 * NUMA socket on which memory must be allocated.
475 * Tx queue configuration parameters.
478 * 0 on success, negative error value otherwise.
480 static int hinic_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
481 uint16_t nb_desc, unsigned int socket_id,
482 __rte_unused const struct rte_eth_txconf *tx_conf)
485 struct hinic_nic_dev *nic_dev;
486 struct hinic_hwdev *hwdev;
487 struct hinic_txq *txq;
488 u16 sq_depth, tx_free_thresh;
490 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
491 hwdev = nic_dev->hwdev;
493 /* queue depth must be power of 2, otherwise will be aligned up */
494 sq_depth = (nb_desc & (nb_desc - 1)) ?
495 ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc;
498 * Validate number of transmit descriptors.
499 * It must not exceed hardware maximum and minimum.
501 if (sq_depth > HINIC_MAX_QUEUE_DEPTH ||
502 sq_depth < HINIC_MIN_QUEUE_DEPTH) {
503 PMD_DRV_LOG(ERR, "TX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)",
504 HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH,
505 (int)nb_desc, (int)sq_depth,
506 (int)dev->data->port_id, (int)queue_idx);
511 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
512 * descriptors are used or if the number of descriptors required
513 * to transmit a packet is greater than the number of free TX
515 * The following constraints must be satisfied:
516 * tx_free_thresh must be greater than 0.
517 * tx_free_thresh must be less than the size of the ring minus 1.
518 * When set to zero use default values.
520 tx_free_thresh = (u16)((tx_conf->tx_free_thresh) ?
521 tx_conf->tx_free_thresh : HINIC_DEFAULT_TX_FREE_THRESH);
522 if (tx_free_thresh >= (sq_depth - 1)) {
523 PMD_DRV_LOG(ERR, "tx_free_thresh must be less than the number of TX descriptors minus 1. (tx_free_thresh=%u port=%d queue=%d)",
524 (unsigned int)tx_free_thresh, (int)dev->data->port_id,
529 txq = rte_zmalloc_socket("hinic_tx_queue", sizeof(struct hinic_txq),
530 RTE_CACHE_LINE_SIZE, socket_id);
532 PMD_DRV_LOG(ERR, "Allocate txq[%d] failed, dev_name: %s",
533 queue_idx, dev->data->name);
536 nic_dev->txqs[queue_idx] = txq;
538 /* alloc tx sq hw wqepage */
539 rc = hinic_create_sq(hwdev, queue_idx, sq_depth);
541 PMD_DRV_LOG(ERR, "Create txq[%d] failed, dev_name: %s, sq_depth: %d",
542 queue_idx, dev->data->name, sq_depth);
546 txq->q_id = queue_idx;
547 txq->q_depth = sq_depth;
548 txq->port_id = dev->data->port_id;
549 txq->tx_free_thresh = tx_free_thresh;
550 txq->nic_dev = nic_dev;
551 txq->wq = &hwdev->nic_io->sq_wq[queue_idx];
552 txq->sq = &hwdev->nic_io->qps[queue_idx].sq;
553 txq->cons_idx_addr = hwdev->nic_io->qps[queue_idx].sq.cons_idx_addr;
554 txq->sq_head_addr = HINIC_GET_WQ_HEAD(txq);
555 txq->sq_bot_sge_addr = HINIC_GET_WQ_TAIL(txq) -
556 sizeof(struct hinic_sq_bufdesc);
557 txq->cos = nic_dev->default_cos;
559 /* alloc software txinfo */
560 rc = hinic_setup_tx_resources(txq);
562 PMD_DRV_LOG(ERR, "Setup txq[%d] tx_resources failed, dev_name: %s",
563 queue_idx, dev->data->name);
564 goto setup_tx_res_fail;
567 /* record nic_dev txq in rte_eth tx_queues */
568 dev->data->tx_queues[queue_idx] = txq;
573 hinic_destroy_sq(hwdev, queue_idx);
581 static void hinic_reset_tx_queue(struct rte_eth_dev *dev)
583 struct hinic_nic_dev *nic_dev;
584 struct hinic_txq *txq;
585 struct hinic_nic_io *nic_io;
586 struct hinic_hwdev *hwdev;
587 volatile u32 *ci_addr;
590 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
591 hwdev = nic_dev->hwdev;
592 nic_io = hwdev->nic_io;
594 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) {
595 txq = dev->data->tx_queues[q_id];
597 txq->wq->cons_idx = 0;
598 txq->wq->prod_idx = 0;
599 txq->wq->delta = txq->q_depth;
600 txq->wq->mask = txq->q_depth - 1;
602 /*clear hardware ci*/
603 ci_addr = (volatile u32 *)HINIC_CI_VADDR(nic_io->ci_vaddr_base,
610 * Get link speed from NIC.
613 * Pointer to Ethernet device structure.
615 * Pointer to link speed structure.
617 static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa)
619 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
620 u32 supported_link, advertised_link;
623 #define HINIC_LINK_MODE_SUPPORT_1G (1U << HINIC_GE_BASE_KX)
625 #define HINIC_LINK_MODE_SUPPORT_10G (1U << HINIC_10GE_BASE_KR)
627 #define HINIC_LINK_MODE_SUPPORT_25G ((1U << HINIC_25GE_BASE_KR_S) | \
628 (1U << HINIC_25GE_BASE_CR_S) | \
629 (1U << HINIC_25GE_BASE_KR) | \
630 (1U << HINIC_25GE_BASE_CR))
632 #define HINIC_LINK_MODE_SUPPORT_40G ((1U << HINIC_40GE_BASE_KR4) | \
633 (1U << HINIC_40GE_BASE_CR4))
635 #define HINIC_LINK_MODE_SUPPORT_100G ((1U << HINIC_100GE_BASE_KR4) | \
636 (1U << HINIC_100GE_BASE_CR4))
638 err = hinic_get_link_mode(nic_dev->hwdev,
639 &supported_link, &advertised_link);
640 if (err || supported_link == HINIC_SUPPORTED_UNKNOWN ||
641 advertised_link == HINIC_SUPPORTED_UNKNOWN) {
642 PMD_DRV_LOG(WARNING, "Get speed capability info failed, device: %s, port_id: %u",
643 nic_dev->proc_dev_name, dev->data->port_id);
646 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_1G))
647 *speed_capa |= ETH_LINK_SPEED_1G;
648 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_10G))
649 *speed_capa |= ETH_LINK_SPEED_10G;
650 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_25G))
651 *speed_capa |= ETH_LINK_SPEED_25G;
652 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_40G))
653 *speed_capa |= ETH_LINK_SPEED_40G;
654 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_100G))
655 *speed_capa |= ETH_LINK_SPEED_100G;
660 * DPDK callback to get information about the device.
663 * Pointer to Ethernet device structure.
665 * Pointer to Info structure output buffer.
668 hinic_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
670 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
672 info->max_rx_queues = nic_dev->nic_cap.max_rqs;
673 info->max_tx_queues = nic_dev->nic_cap.max_sqs;
674 info->min_rx_bufsize = HINIC_MIN_RX_BUF_SIZE;
675 info->max_rx_pktlen = HINIC_MAX_JUMBO_FRAME_SIZE;
676 info->max_mac_addrs = HINIC_MAX_MAC_ADDRS;
678 hinic_get_speed_capa(dev, &info->speed_capa);
679 info->rx_queue_offload_capa = 0;
680 info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
681 DEV_RX_OFFLOAD_IPV4_CKSUM |
682 DEV_RX_OFFLOAD_UDP_CKSUM |
683 DEV_RX_OFFLOAD_TCP_CKSUM;
685 info->tx_queue_offload_capa = 0;
686 info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
687 DEV_TX_OFFLOAD_IPV4_CKSUM |
688 DEV_TX_OFFLOAD_UDP_CKSUM |
689 DEV_TX_OFFLOAD_TCP_CKSUM |
690 DEV_TX_OFFLOAD_SCTP_CKSUM |
691 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
692 DEV_TX_OFFLOAD_TCP_TSO |
693 DEV_TX_OFFLOAD_MULTI_SEGS;
695 info->hash_key_size = HINIC_RSS_KEY_SIZE;
696 info->reta_size = HINIC_RSS_INDIR_SIZE;
697 info->flow_type_rss_offloads = HINIC_RSS_OFFLOAD_ALL;
698 info->rx_desc_lim = hinic_rx_desc_lim;
699 info->tx_desc_lim = hinic_tx_desc_lim;
704 static int hinic_config_rx_mode(struct hinic_nic_dev *nic_dev, u32 rx_mode_ctrl)
708 err = hinic_set_rx_mode(nic_dev->hwdev, rx_mode_ctrl);
710 PMD_DRV_LOG(ERR, "Failed to set rx mode");
713 nic_dev->rx_mode_status = rx_mode_ctrl;
719 static int hinic_rxtx_configure(struct rte_eth_dev *dev)
722 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
724 /* rx configure, if rss enable, need to init default configuration */
725 err = hinic_rx_configure(dev);
727 PMD_DRV_LOG(ERR, "Configure rss failed");
732 err = hinic_config_rx_mode(nic_dev, HINIC_DEFAULT_RX_MODE);
734 PMD_DRV_LOG(ERR, "Configure rx_mode:0x%x failed",
735 HINIC_DEFAULT_RX_MODE);
736 goto set_rx_mode_fail;
742 hinic_rx_remove_configure(dev);
747 static void hinic_remove_rxtx_configure(struct rte_eth_dev *dev)
749 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
751 (void)hinic_config_rx_mode(nic_dev, 0);
752 hinic_rx_remove_configure(dev);
755 static int hinic_priv_get_dev_link_status(struct hinic_nic_dev *nic_dev,
756 struct rte_eth_link *link)
759 u8 port_link_status = 0;
760 struct nic_port_info port_link_info;
761 struct hinic_hwdev *nic_hwdev = nic_dev->hwdev;
762 uint32_t port_speed[LINK_SPEED_MAX] = {ETH_SPEED_NUM_10M,
763 ETH_SPEED_NUM_100M, ETH_SPEED_NUM_1G,
764 ETH_SPEED_NUM_10G, ETH_SPEED_NUM_25G,
765 ETH_SPEED_NUM_40G, ETH_SPEED_NUM_100G};
767 rc = hinic_get_link_status(nic_hwdev, &port_link_status);
771 if (!port_link_status) {
772 link->link_status = ETH_LINK_DOWN;
773 link->link_speed = 0;
774 link->link_duplex = ETH_LINK_HALF_DUPLEX;
775 link->link_autoneg = ETH_LINK_FIXED;
779 memset(&port_link_info, 0, sizeof(port_link_info));
780 rc = hinic_get_port_info(nic_hwdev, &port_link_info);
784 link->link_speed = port_speed[port_link_info.speed % LINK_SPEED_MAX];
785 link->link_duplex = port_link_info.duplex;
786 link->link_autoneg = port_link_info.autoneg_state;
787 link->link_status = port_link_status;
793 * DPDK callback to retrieve physical link information.
796 * Pointer to Ethernet device structure.
797 * @param wait_to_complete
798 * Wait for request completion.
801 * 0 link status changed, -1 link status not changed
803 static int hinic_link_update(struct rte_eth_dev *dev, int wait_to_complete)
805 #define CHECK_INTERVAL 10 /* 10ms */
806 #define MAX_REPEAT_TIME 100 /* 1s (100 * 10ms) in total */
808 struct rte_eth_link link;
809 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
810 unsigned int rep_cnt = MAX_REPEAT_TIME;
812 memset(&link, 0, sizeof(link));
814 /* Get link status information from hardware */
815 rc = hinic_priv_get_dev_link_status(nic_dev, &link);
816 if (rc != HINIC_OK) {
817 link.link_speed = ETH_SPEED_NUM_NONE;
818 link.link_duplex = ETH_LINK_FULL_DUPLEX;
819 PMD_DRV_LOG(ERR, "Get link status failed");
823 if (!wait_to_complete || link.link_status)
826 rte_delay_ms(CHECK_INTERVAL);
830 rc = rte_eth_linkstatus_set(dev, &link);
835 * DPDK callback to start the device.
838 * Pointer to Ethernet device structure.
841 * 0 on success, negative errno value on failure.
843 static int hinic_dev_start(struct rte_eth_dev *dev)
847 struct hinic_nic_dev *nic_dev;
849 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
850 name = dev->data->name;
852 /* reset rx and tx queue */
853 hinic_reset_rx_queue(dev);
854 hinic_reset_tx_queue(dev);
856 /* get func rx buf size */
857 hinic_get_func_rx_buf_size(nic_dev);
859 /* init txq and rxq context */
860 rc = hinic_init_qp_ctxts(nic_dev->hwdev);
862 PMD_DRV_LOG(ERR, "Initialize qp context failed, dev_name:%s",
868 rc = hinic_config_mq_mode(dev, TRUE);
870 PMD_DRV_LOG(ERR, "Configure mq mode failed, dev_name: %s",
872 goto cfg_mq_mode_fail;
875 /* set default mtu */
876 rc = hinic_set_port_mtu(nic_dev->hwdev, nic_dev->mtu_size);
878 PMD_DRV_LOG(ERR, "Set mtu_size[%d] failed, dev_name: %s",
879 nic_dev->mtu_size, name);
883 /* configure rss rx_mode and other rx or tx default feature */
884 rc = hinic_rxtx_configure(dev);
886 PMD_DRV_LOG(ERR, "Configure tx and rx failed, dev_name: %s",
891 /* open virtual port and ready to start packet receiving */
892 rc = hinic_set_vport_enable(nic_dev->hwdev, true);
894 PMD_DRV_LOG(ERR, "Enable vport failed, dev_name:%s", name);
898 /* open physical port and start packet receiving */
899 rc = hinic_set_port_enable(nic_dev->hwdev, true);
901 PMD_DRV_LOG(ERR, "Enable physical port failed, dev_name:%s",
906 /* update eth_dev link status */
907 if (dev->data->dev_conf.intr_conf.lsc != 0)
908 (void)hinic_link_update(dev, 0);
910 hinic_set_bit(HINIC_DEV_START, &nic_dev->dev_status);
915 (void)hinic_set_vport_enable(nic_dev->hwdev, false);
918 /* Flush tx && rx chip resources in case of set vport fake fail */
919 (void)hinic_flush_qp_res(nic_dev->hwdev);
922 hinic_remove_rxtx_configure(dev);
927 hinic_free_qp_ctxts(nic_dev->hwdev);
930 hinic_free_all_rx_mbuf(dev);
931 hinic_free_all_tx_mbuf(dev);
937 * DPDK callback to release the receive queue.
940 * Generic receive queue pointer.
942 static void hinic_rx_queue_release(void *queue)
944 struct hinic_rxq *rxq = queue;
945 struct hinic_nic_dev *nic_dev;
948 PMD_DRV_LOG(WARNING, "Rxq is null when release");
951 nic_dev = rxq->nic_dev;
953 /* free rxq_pkt mbuf */
954 hinic_free_all_rx_skbs(rxq);
956 /* free rxq_cqe, rxq_info */
957 hinic_free_rx_resources(rxq);
959 /* free root rq wq */
960 hinic_destroy_rq(nic_dev->hwdev, rxq->q_id);
962 nic_dev->rxqs[rxq->q_id] = NULL;
969 * DPDK callback to release the transmit queue.
972 * Generic transmit queue pointer.
974 static void hinic_tx_queue_release(void *queue)
976 struct hinic_txq *txq = queue;
977 struct hinic_nic_dev *nic_dev;
980 PMD_DRV_LOG(WARNING, "Txq is null when release");
983 nic_dev = txq->nic_dev;
985 /* free txq_pkt mbuf */
986 hinic_free_all_tx_skbs(txq);
989 hinic_free_tx_resources(txq);
991 /* free root sq wq */
992 hinic_destroy_sq(nic_dev->hwdev, txq->q_id);
993 nic_dev->txqs[txq->q_id] = NULL;
999 static void hinic_free_all_rq(struct hinic_nic_dev *nic_dev)
1003 for (q_id = 0; q_id < nic_dev->num_rq; q_id++)
1004 hinic_destroy_rq(nic_dev->hwdev, q_id);
1007 static void hinic_free_all_sq(struct hinic_nic_dev *nic_dev)
1011 for (q_id = 0; q_id < nic_dev->num_sq; q_id++)
1012 hinic_destroy_sq(nic_dev->hwdev, q_id);
1016 * DPDK callback to stop the device.
1019 * Pointer to Ethernet device structure.
1021 static void hinic_dev_stop(struct rte_eth_dev *dev)
1026 struct hinic_nic_dev *nic_dev;
1027 struct rte_eth_link link;
1029 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1030 name = dev->data->name;
1031 port_id = dev->data->port_id;
1033 if (!hinic_test_and_clear_bit(HINIC_DEV_START, &nic_dev->dev_status)) {
1034 PMD_DRV_LOG(INFO, "Device %s already stopped", name);
1038 /* just stop phy port and vport */
1039 rc = hinic_set_port_enable(nic_dev->hwdev, false);
1041 PMD_DRV_LOG(WARNING, "Disable phy port failed, error: %d, dev_name:%s, port_id:%d",
1044 rc = hinic_set_vport_enable(nic_dev->hwdev, false);
1046 PMD_DRV_LOG(WARNING, "Disable vport failed, error: %d, dev_name:%s, port_id:%d",
1049 /* Clear recorded link status */
1050 memset(&link, 0, sizeof(link));
1051 (void)rte_eth_linkstatus_set(dev, &link);
1053 /* flush pending io request */
1054 rc = hinic_rx_tx_flush(nic_dev->hwdev);
1056 PMD_DRV_LOG(WARNING, "Flush pending io failed, error: %d, dev_name: %s, port_id: %d",
1059 /* clean rss table and rx_mode */
1060 hinic_remove_rxtx_configure(dev);
1062 /* clean root context */
1063 hinic_free_qp_ctxts(nic_dev->hwdev);
1066 hinic_free_all_rx_mbuf(dev);
1067 hinic_free_all_tx_mbuf(dev);
1070 static void hinic_disable_interrupt(struct rte_eth_dev *dev)
1072 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1073 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1074 int ret, retries = 0;
1076 hinic_clear_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status);
1078 /* disable msix interrupt in hardware */
1079 hinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE);
1081 /* disable rte interrupt */
1082 ret = rte_intr_disable(&pci_dev->intr_handle);
1084 PMD_DRV_LOG(ERR, "Disable intr failed: %d", ret);
1088 rte_intr_callback_unregister(&pci_dev->intr_handle,
1089 hinic_dev_interrupt_handler, dev);
1092 } else if (ret == -EAGAIN) {
1096 PMD_DRV_LOG(ERR, "intr callback unregister failed: %d",
1100 } while (retries < HINIC_INTR_CB_UNREG_MAX_RETRIES);
1102 if (retries == HINIC_INTR_CB_UNREG_MAX_RETRIES)
1103 PMD_DRV_LOG(ERR, "Unregister intr callback failed after %d retries",
1107 static int hinic_set_dev_promiscuous(struct hinic_nic_dev *nic_dev, bool enable)
1109 u32 rx_mode_ctrl = nic_dev->rx_mode_status;
1112 rx_mode_ctrl |= HINIC_RX_MODE_PROMISC;
1114 rx_mode_ctrl &= (~HINIC_RX_MODE_PROMISC);
1116 return hinic_config_rx_mode(nic_dev, rx_mode_ctrl);
1120 * DPDK callback to get device statistics.
1123 * Pointer to Ethernet device structure.
1125 * Stats structure output buffer.
1128 * 0 on success and stats is filled,
1129 * negative error value otherwise.
1132 hinic_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1135 u64 rx_discards_pmd = 0;
1136 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1137 struct hinic_vport_stats vport_stats;
1138 struct hinic_rxq *rxq = NULL;
1139 struct hinic_rxq_stats rxq_stats;
1140 struct hinic_txq *txq = NULL;
1141 struct hinic_txq_stats txq_stats;
1143 err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats);
1145 PMD_DRV_LOG(ERR, "Get vport stats from fw failed, nic_dev: %s",
1146 nic_dev->proc_dev_name);
1150 /* rx queue stats */
1151 q_num = (nic_dev->num_rq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ?
1152 nic_dev->num_rq : RTE_ETHDEV_QUEUE_STAT_CNTRS;
1153 for (i = 0; i < q_num; i++) {
1154 rxq = nic_dev->rxqs[i];
1155 hinic_rxq_get_stats(rxq, &rxq_stats);
1156 stats->q_ipackets[i] = rxq_stats.packets;
1157 stats->q_ibytes[i] = rxq_stats.bytes;
1158 stats->q_errors[i] = rxq_stats.rx_discards;
1160 stats->ierrors += rxq_stats.errors;
1161 rx_discards_pmd += rxq_stats.rx_discards;
1162 dev->data->rx_mbuf_alloc_failed += rxq_stats.rx_nombuf;
1165 /* tx queue stats */
1166 q_num = (nic_dev->num_sq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ?
1167 nic_dev->num_sq : RTE_ETHDEV_QUEUE_STAT_CNTRS;
1168 for (i = 0; i < q_num; i++) {
1169 txq = nic_dev->txqs[i];
1170 hinic_txq_get_stats(txq, &txq_stats);
1171 stats->q_opackets[i] = txq_stats.packets;
1172 stats->q_obytes[i] = txq_stats.bytes;
1173 stats->oerrors += (txq_stats.tx_busy + txq_stats.off_errs);
1177 stats->oerrors += vport_stats.tx_discard_vport;
1179 stats->imissed = vport_stats.rx_discard_vport + rx_discards_pmd;
1181 stats->ipackets = (vport_stats.rx_unicast_pkts_vport +
1182 vport_stats.rx_multicast_pkts_vport +
1183 vport_stats.rx_broadcast_pkts_vport -
1186 stats->opackets = (vport_stats.tx_unicast_pkts_vport +
1187 vport_stats.tx_multicast_pkts_vport +
1188 vport_stats.tx_broadcast_pkts_vport);
1190 stats->ibytes = (vport_stats.rx_unicast_bytes_vport +
1191 vport_stats.rx_multicast_bytes_vport +
1192 vport_stats.rx_broadcast_bytes_vport);
1194 stats->obytes = (vport_stats.tx_unicast_bytes_vport +
1195 vport_stats.tx_multicast_bytes_vport +
1196 vport_stats.tx_broadcast_bytes_vport);
1201 * DPDK callback to clear device statistics.
1204 * Pointer to Ethernet device structure.
1206 static int hinic_dev_stats_reset(struct rte_eth_dev *dev)
1209 struct hinic_rxq *rxq = NULL;
1210 struct hinic_txq *txq = NULL;
1211 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1214 ret = hinic_clear_vport_stats(nic_dev->hwdev);
1218 for (qid = 0; qid < nic_dev->num_rq; qid++) {
1219 rxq = nic_dev->rxqs[qid];
1220 hinic_rxq_stats_reset(rxq);
1223 for (qid = 0; qid < nic_dev->num_sq; qid++) {
1224 txq = nic_dev->txqs[qid];
1225 hinic_txq_stats_reset(txq);
1232 * DPDK callback to clear device extended statistics.
1235 * Pointer to Ethernet device structure.
1237 static int hinic_dev_xstats_reset(struct rte_eth_dev *dev)
1239 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1242 ret = hinic_dev_stats_reset(dev);
1246 if (hinic_func_type(nic_dev->hwdev) != TYPE_VF) {
1247 ret = hinic_clear_phy_port_stats(nic_dev->hwdev);
1255 static void hinic_gen_random_mac_addr(struct rte_ether_addr *mac_addr)
1257 uint64_t random_value;
1259 /* Set Organizationally Unique Identifier (OUI) prefix */
1260 mac_addr->addr_bytes[0] = 0x00;
1261 mac_addr->addr_bytes[1] = 0x09;
1262 mac_addr->addr_bytes[2] = 0xC0;
1263 /* Force indication of locally assigned MAC address. */
1264 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1265 /* Generate the last 3 bytes of the MAC address with a random number. */
1266 random_value = rte_rand();
1267 memcpy(&mac_addr->addr_bytes[3], &random_value, 3);
1271 * Init mac_vlan table in NIC.
1274 * Pointer to Ethernet device structure.
1277 * 0 on success and stats is filled,
1278 * negative error value otherwise.
1280 static int hinic_init_mac_addr(struct rte_eth_dev *eth_dev)
1282 struct hinic_nic_dev *nic_dev =
1283 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1284 uint8_t addr_bytes[RTE_ETHER_ADDR_LEN];
1288 rc = hinic_get_default_mac(nic_dev->hwdev, addr_bytes);
1292 memmove(eth_dev->data->mac_addrs->addr_bytes,
1293 addr_bytes, RTE_ETHER_ADDR_LEN);
1295 if (rte_is_zero_ether_addr(eth_dev->data->mac_addrs))
1296 hinic_gen_random_mac_addr(eth_dev->data->mac_addrs);
1298 func_id = hinic_global_func_id(nic_dev->hwdev);
1299 rc = hinic_set_mac(nic_dev->hwdev, eth_dev->data->mac_addrs->addr_bytes,
1301 if (rc && rc != HINIC_PF_SET_VF_ALREADY)
1308 * Deinit mac_vlan table in NIC.
1311 * Pointer to Ethernet device structure.
1314 * 0 on success and stats is filled,
1315 * negative error value otherwise.
1317 static void hinic_deinit_mac_addr(struct rte_eth_dev *eth_dev)
1319 struct hinic_nic_dev *nic_dev =
1320 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1324 if (rte_is_zero_ether_addr(eth_dev->data->mac_addrs))
1327 func_id = hinic_global_func_id(nic_dev->hwdev);
1328 rc = hinic_del_mac(nic_dev->hwdev,
1329 eth_dev->data->mac_addrs->addr_bytes,
1331 if (rc && rc != HINIC_PF_SET_VF_ALREADY)
1332 PMD_DRV_LOG(ERR, "Delete mac table failed, dev_name: %s",
1333 eth_dev->data->name);
1337 * DPDK callback to enable promiscuous mode.
1340 * Pointer to Ethernet device structure.
1344 * negative error value otherwise.
1346 static int hinic_dev_promiscuous_enable(struct rte_eth_dev *dev)
1349 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1351 PMD_DRV_LOG(INFO, "Enable promiscuous, nic_dev: %s, port_id: %d, promisc: %d",
1352 nic_dev->proc_dev_name, dev->data->port_id,
1353 dev->data->promiscuous);
1355 rc = hinic_set_dev_promiscuous(nic_dev, true);
1357 PMD_DRV_LOG(ERR, "Enable promiscuous failed");
1363 * DPDK callback to disable promiscuous mode.
1366 * Pointer to Ethernet device structure.
1370 * negative error value otherwise.
1372 static int hinic_dev_promiscuous_disable(struct rte_eth_dev *dev)
1375 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1377 PMD_DRV_LOG(INFO, "Disable promiscuous, nic_dev: %s, port_id: %d, promisc: %d",
1378 nic_dev->proc_dev_name, dev->data->port_id,
1379 dev->data->promiscuous);
1381 rc = hinic_set_dev_promiscuous(nic_dev, false);
1383 PMD_DRV_LOG(ERR, "Disable promiscuous failed");
1389 * DPDK callback to update the RSS hash key and RSS hash type.
1392 * Pointer to Ethernet device structure.
1394 * RSS configuration data.
1397 * 0 on success, negative error value otherwise.
1399 static int hinic_rss_hash_update(struct rte_eth_dev *dev,
1400 struct rte_eth_rss_conf *rss_conf)
1402 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1403 u8 tmpl_idx = nic_dev->rss_tmpl_idx;
1404 u8 hashkey[HINIC_RSS_KEY_SIZE] = {0};
1405 u8 prio_tc[HINIC_DCB_UP_MAX] = {0};
1406 u64 rss_hf = rss_conf->rss_hf;
1407 struct nic_rss_type rss_type = {0};
1410 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) {
1411 PMD_DRV_LOG(WARNING, "RSS is not enabled");
1415 if (rss_conf->rss_key_len > HINIC_RSS_KEY_SIZE) {
1416 PMD_DRV_LOG(ERR, "Invalid rss key, rss_key_len:%d",
1417 rss_conf->rss_key_len);
1421 if (rss_conf->rss_key) {
1422 memcpy(hashkey, rss_conf->rss_key, rss_conf->rss_key_len);
1423 err = hinic_rss_set_template_tbl(nic_dev->hwdev, tmpl_idx,
1426 PMD_DRV_LOG(ERR, "Set rss template table failed");
1431 rss_type.ipv4 = (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4)) ? 1 : 0;
1432 rss_type.tcp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) ? 1 : 0;
1433 rss_type.ipv6 = (rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6)) ? 1 : 0;
1434 rss_type.ipv6_ext = (rss_hf & ETH_RSS_IPV6_EX) ? 1 : 0;
1435 rss_type.tcp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) ? 1 : 0;
1436 rss_type.tcp_ipv6_ext = (rss_hf & ETH_RSS_IPV6_TCP_EX) ? 1 : 0;
1437 rss_type.udp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) ? 1 : 0;
1438 rss_type.udp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) ? 1 : 0;
1440 err = hinic_set_rss_type(nic_dev->hwdev, tmpl_idx, rss_type);
1442 PMD_DRV_LOG(ERR, "Set rss type table failed");
1449 memset(prio_tc, 0, sizeof(prio_tc));
1450 (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc);
1455 * DPDK callback to get the RSS hash configuration.
1458 * Pointer to Ethernet device structure.
1460 * RSS configuration data.
1463 * 0 on success, negative error value otherwise.
1465 static int hinic_rss_conf_get(struct rte_eth_dev *dev,
1466 struct rte_eth_rss_conf *rss_conf)
1468 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1469 u8 tmpl_idx = nic_dev->rss_tmpl_idx;
1470 u8 hashkey[HINIC_RSS_KEY_SIZE] = {0};
1471 struct nic_rss_type rss_type = {0};
1474 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) {
1475 PMD_DRV_LOG(WARNING, "RSS is not enabled");
1479 err = hinic_rss_get_template_tbl(nic_dev->hwdev, tmpl_idx, hashkey);
1483 if (rss_conf->rss_key &&
1484 rss_conf->rss_key_len >= HINIC_RSS_KEY_SIZE) {
1485 memcpy(rss_conf->rss_key, hashkey, sizeof(hashkey));
1486 rss_conf->rss_key_len = sizeof(hashkey);
1489 err = hinic_get_rss_type(nic_dev->hwdev, tmpl_idx, &rss_type);
1493 rss_conf->rss_hf = 0;
1494 rss_conf->rss_hf |= rss_type.ipv4 ?
1495 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4) : 0;
1496 rss_conf->rss_hf |= rss_type.tcp_ipv4 ? ETH_RSS_NONFRAG_IPV4_TCP : 0;
1497 rss_conf->rss_hf |= rss_type.ipv6 ?
1498 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6) : 0;
1499 rss_conf->rss_hf |= rss_type.ipv6_ext ? ETH_RSS_IPV6_EX : 0;
1500 rss_conf->rss_hf |= rss_type.tcp_ipv6 ? ETH_RSS_NONFRAG_IPV6_TCP : 0;
1501 rss_conf->rss_hf |= rss_type.tcp_ipv6_ext ? ETH_RSS_IPV6_TCP_EX : 0;
1502 rss_conf->rss_hf |= rss_type.udp_ipv4 ? ETH_RSS_NONFRAG_IPV4_UDP : 0;
1503 rss_conf->rss_hf |= rss_type.udp_ipv6 ? ETH_RSS_NONFRAG_IPV6_UDP : 0;
1509 * DPDK callback to update the RETA indirection table.
1512 * Pointer to Ethernet device structure.
1514 * Pointer to RETA configuration structure array.
1516 * Size of the RETA table.
1519 * 0 on success, negative error value otherwise.
1521 static int hinic_rss_indirtbl_update(struct rte_eth_dev *dev,
1522 struct rte_eth_rss_reta_entry64 *reta_conf,
1525 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1526 u8 tmpl_idx = nic_dev->rss_tmpl_idx;
1527 u8 prio_tc[HINIC_DCB_UP_MAX] = {0};
1528 u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0};
1533 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG))
1536 if (reta_size != NIC_RSS_INDIR_SIZE) {
1537 PMD_DRV_LOG(ERR, "Invalid reta size, reta_size:%d", reta_size);
1541 err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);
1545 /* update rss indir_tbl */
1546 for (i = 0; i < reta_size; i++) {
1547 idx = i / RTE_RETA_GROUP_SIZE;
1548 shift = i % RTE_RETA_GROUP_SIZE;
1549 if (reta_conf[idx].mask & (1ULL << shift))
1550 indirtbl[i] = reta_conf[idx].reta[shift];
1553 for (i = 0 ; i < reta_size; i++) {
1554 if (indirtbl[i] >= nic_dev->num_rq) {
1555 PMD_DRV_LOG(ERR, "Invalid reta entry, index:%d, num_rq:%d",
1556 i, nic_dev->num_rq);
1561 err = hinic_rss_set_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);
1565 nic_dev->rss_indir_flag = true;
1570 memset(prio_tc, 0, sizeof(prio_tc));
1571 (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc);
1578 * DPDK callback to get the RETA indirection table.
1581 * Pointer to Ethernet device structure.
1583 * Pointer to RETA configuration structure array.
1585 * Size of the RETA table.
1588 * 0 on success, negative error value otherwise.
1590 static int hinic_rss_indirtbl_query(struct rte_eth_dev *dev,
1591 struct rte_eth_rss_reta_entry64 *reta_conf,
1594 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1595 u8 tmpl_idx = nic_dev->rss_tmpl_idx;
1597 u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0};
1601 if (reta_size != NIC_RSS_INDIR_SIZE) {
1602 PMD_DRV_LOG(ERR, "Invalid reta size, reta_size:%d", reta_size);
1606 err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl);
1608 PMD_DRV_LOG(ERR, "Get rss indirect table failed, error:%d",
1613 for (i = 0; i < reta_size; i++) {
1614 idx = i / RTE_RETA_GROUP_SIZE;
1615 shift = i % RTE_RETA_GROUP_SIZE;
1616 if (reta_conf[idx].mask & (1ULL << shift))
1617 reta_conf[idx].reta[shift] = (uint16_t)indirtbl[i];
1624 * DPDK callback to get extended device statistics.
1627 * Pointer to Ethernet device.
1629 * Pointer to rte extended stats table.
1631 * The size of the stats table.
1634 * Number of extended stats on success and stats is filled,
1635 * negative error value otherwise.
1637 static int hinic_dev_xstats_get(struct rte_eth_dev *dev,
1638 struct rte_eth_xstat *xstats,
1644 struct hinic_nic_dev *nic_dev;
1645 struct hinic_phy_port_stats port_stats;
1646 struct hinic_vport_stats vport_stats;
1647 struct hinic_rxq *rxq = NULL;
1648 struct hinic_rxq_stats rxq_stats;
1649 struct hinic_txq *txq = NULL;
1650 struct hinic_txq_stats txq_stats;
1652 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1653 count = hinic_xstats_calc_num(nic_dev);
1659 /* Get stats from hinic_rxq_stats */
1660 for (qid = 0; qid < nic_dev->num_rq; qid++) {
1661 rxq = nic_dev->rxqs[qid];
1662 hinic_rxq_get_stats(rxq, &rxq_stats);
1664 for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) {
1665 xstats[count].value =
1666 *(uint64_t *)(((char *)&rxq_stats) +
1667 hinic_rxq_stats_strings[i].offset);
1668 xstats[count].id = count;
1673 /* Get stats from hinic_txq_stats */
1674 for (qid = 0; qid < nic_dev->num_sq; qid++) {
1675 txq = nic_dev->txqs[qid];
1676 hinic_txq_get_stats(txq, &txq_stats);
1678 for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) {
1679 xstats[count].value =
1680 *(uint64_t *)(((char *)&txq_stats) +
1681 hinic_txq_stats_strings[i].offset);
1682 xstats[count].id = count;
1687 /* Get stats from hinic_vport_stats */
1688 err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats);
1692 for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) {
1693 xstats[count].value =
1694 *(uint64_t *)(((char *)&vport_stats) +
1695 hinic_vport_stats_strings[i].offset);
1696 xstats[count].id = count;
1700 /* Get stats from hinic_phy_port_stats */
1701 err = hinic_get_phy_port_stats(nic_dev->hwdev, &port_stats);
1705 for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) {
1706 xstats[count].value = *(uint64_t *)(((char *)&port_stats) +
1707 hinic_phyport_stats_strings[i].offset);
1708 xstats[count].id = count;
1716 * DPDK callback to retrieve names of extended device statistics
1719 * Pointer to Ethernet device structure.
1720 * @param xstats_names
1721 * Buffer to insert names into.
1724 * Number of xstats names.
1726 static int hinic_dev_xstats_get_names(struct rte_eth_dev *dev,
1727 struct rte_eth_xstat_name *xstats_names,
1728 __rte_unused unsigned int limit)
1730 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
1734 if (xstats_names == NULL)
1735 return hinic_xstats_calc_num(nic_dev);
1737 /* get pmd rxq stats */
1738 for (q_num = 0; q_num < nic_dev->num_rq; q_num++) {
1739 for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) {
1740 snprintf(xstats_names[count].name,
1741 sizeof(xstats_names[count].name),
1743 q_num, hinic_rxq_stats_strings[i].name);
1748 /* get pmd txq stats */
1749 for (q_num = 0; q_num < nic_dev->num_sq; q_num++) {
1750 for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) {
1751 snprintf(xstats_names[count].name,
1752 sizeof(xstats_names[count].name),
1754 q_num, hinic_txq_stats_strings[i].name);
1759 /* get vport stats */
1760 for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) {
1761 snprintf(xstats_names[count].name,
1762 sizeof(xstats_names[count].name),
1764 hinic_vport_stats_strings[i].name);
1768 /* get phy port stats */
1769 for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) {
1770 snprintf(xstats_names[count].name,
1771 sizeof(xstats_names[count].name),
1773 hinic_phyport_stats_strings[i].name);
1780 static int hinic_set_default_pause_feature(struct hinic_nic_dev *nic_dev)
1782 struct nic_pause_config pause_config = {0};
1784 pause_config.auto_neg = 0;
1785 pause_config.rx_pause = HINIC_DEFAUT_PAUSE_CONFIG;
1786 pause_config.tx_pause = HINIC_DEFAUT_PAUSE_CONFIG;
1788 return hinic_set_pause_config(nic_dev->hwdev, pause_config);
1791 static int hinic_set_default_dcb_feature(struct hinic_nic_dev *nic_dev)
1793 u8 up_tc[HINIC_DCB_UP_MAX] = {0};
1794 u8 up_pgid[HINIC_DCB_UP_MAX] = {0};
1795 u8 up_bw[HINIC_DCB_UP_MAX] = {0};
1796 u8 pg_bw[HINIC_DCB_UP_MAX] = {0};
1797 u8 up_strict[HINIC_DCB_UP_MAX] = {0};
1801 for (i = 0; i < HINIC_DCB_UP_MAX; i++)
1804 return hinic_dcb_set_ets(nic_dev->hwdev, up_tc, pg_bw,
1805 up_pgid, up_bw, up_strict);
1808 static void hinic_init_default_cos(struct hinic_nic_dev *nic_dev)
1810 nic_dev->default_cos =
1811 (hinic_global_func_id(nic_dev->hwdev) +
1812 DEFAULT_BASE_COS) % NR_MAX_COS;
1815 static int hinic_set_default_hw_feature(struct hinic_nic_dev *nic_dev)
1819 hinic_init_default_cos(nic_dev);
1821 /* Restore DCB configure to default status */
1822 err = hinic_set_default_dcb_feature(nic_dev);
1827 err = hinic_set_rx_lro(nic_dev->hwdev, 0, 0, (u8)0);
1831 /* Set pause enable, and up will disable pfc. */
1832 err = hinic_set_default_pause_feature(nic_dev);
1836 err = hinic_reset_port_link_cfg(nic_dev->hwdev);
1840 err = hinic_set_link_status_follow(nic_dev->hwdev,
1841 HINIC_LINK_FOLLOW_PORT);
1842 if (err == HINIC_MGMT_CMD_UNSUPPORTED)
1843 PMD_DRV_LOG(WARNING, "Don't support to set link status follow phy port status");
1847 return hinic_set_anti_attack(nic_dev->hwdev, true);
1850 static int32_t hinic_card_workmode_check(struct hinic_nic_dev *nic_dev)
1852 struct hinic_board_info info = { 0 };
1855 rc = hinic_get_board_info(nic_dev->hwdev, &info);
1859 return (info.service_mode == HINIC_SERVICE_MODE_NIC ? HINIC_OK :
1863 static int hinic_copy_mempool_init(struct hinic_nic_dev *nic_dev)
1865 nic_dev->cpy_mpool = rte_mempool_lookup(nic_dev->proc_dev_name);
1866 if (nic_dev->cpy_mpool == NULL) {
1867 nic_dev->cpy_mpool =
1868 rte_pktmbuf_pool_create(nic_dev->proc_dev_name,
1869 HINIC_COPY_MEMPOOL_DEPTH,
1870 RTE_CACHE_LINE_SIZE, 0,
1871 HINIC_COPY_MBUF_SIZE,
1873 if (!nic_dev->cpy_mpool) {
1874 PMD_DRV_LOG(ERR, "Create copy mempool failed, errno: %d, dev_name: %s",
1875 rte_errno, nic_dev->proc_dev_name);
1883 static void hinic_copy_mempool_uninit(struct hinic_nic_dev *nic_dev)
1885 if (nic_dev->cpy_mpool != NULL)
1886 rte_mempool_free(nic_dev->cpy_mpool);
1889 static int hinic_init_sw_rxtxqs(struct hinic_nic_dev *nic_dev)
1894 /* allocate software txq array */
1895 txq_size = nic_dev->nic_cap.max_sqs * sizeof(*nic_dev->txqs);
1896 nic_dev->txqs = kzalloc_aligned(txq_size, GFP_KERNEL);
1897 if (!nic_dev->txqs) {
1898 PMD_DRV_LOG(ERR, "Allocate txqs failed");
1902 /* allocate software rxq array */
1903 rxq_size = nic_dev->nic_cap.max_rqs * sizeof(*nic_dev->rxqs);
1904 nic_dev->rxqs = kzalloc_aligned(rxq_size, GFP_KERNEL);
1905 if (!nic_dev->rxqs) {
1907 kfree(nic_dev->txqs);
1908 nic_dev->txqs = NULL;
1910 PMD_DRV_LOG(ERR, "Allocate rxqs failed");
1917 static void hinic_deinit_sw_rxtxqs(struct hinic_nic_dev *nic_dev)
1919 kfree(nic_dev->txqs);
1920 nic_dev->txqs = NULL;
1922 kfree(nic_dev->rxqs);
1923 nic_dev->rxqs = NULL;
1926 static int hinic_nic_dev_create(struct rte_eth_dev *eth_dev)
1928 struct hinic_nic_dev *nic_dev =
1929 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1932 nic_dev->hwdev = rte_zmalloc("hinic_hwdev", sizeof(*nic_dev->hwdev),
1933 RTE_CACHE_LINE_SIZE);
1934 if (!nic_dev->hwdev) {
1935 PMD_DRV_LOG(ERR, "Allocate hinic hwdev memory failed, dev_name: %s",
1936 eth_dev->data->name);
1939 nic_dev->hwdev->pcidev_hdl = RTE_ETH_DEV_TO_PCI(eth_dev);
1942 rc = hinic_osdep_init(nic_dev->hwdev);
1944 PMD_DRV_LOG(ERR, "Initialize os_dep failed, dev_name: %s",
1945 eth_dev->data->name);
1946 goto init_osdep_fail;
1950 rc = hinic_hwif_res_init(nic_dev->hwdev);
1952 PMD_DRV_LOG(ERR, "Initialize hwif failed, dev_name: %s",
1953 eth_dev->data->name);
1954 goto init_hwif_fail;
1958 rc = init_cfg_mgmt(nic_dev->hwdev);
1960 PMD_DRV_LOG(ERR, "Initialize cfg_mgmt failed, dev_name: %s",
1961 eth_dev->data->name);
1962 goto init_cfgmgnt_fail;
1966 rc = hinic_comm_aeqs_init(nic_dev->hwdev);
1968 PMD_DRV_LOG(ERR, "Initialize aeqs failed, dev_name: %s",
1969 eth_dev->data->name);
1970 goto init_aeqs_fail;
1973 /* init_pf_to_mgnt */
1974 rc = hinic_comm_pf_to_mgmt_init(nic_dev->hwdev);
1976 PMD_DRV_LOG(ERR, "Initialize pf_to_mgmt failed, dev_name: %s",
1977 eth_dev->data->name);
1978 goto init_pf_to_mgmt_fail;
1981 rc = hinic_card_workmode_check(nic_dev);
1983 PMD_DRV_LOG(ERR, "Check card workmode failed, dev_name: %s",
1984 eth_dev->data->name);
1985 goto workmode_check_fail;
1988 /* do l2nic reset to make chip clear */
1989 rc = hinic_l2nic_reset(nic_dev->hwdev);
1991 PMD_DRV_LOG(ERR, "Do l2nic reset failed, dev_name: %s",
1992 eth_dev->data->name);
1993 goto l2nic_reset_fail;
1996 /* init dma and aeq msix attribute table */
1997 (void)hinic_init_attr_table(nic_dev->hwdev);
2000 rc = hinic_comm_cmdqs_init(nic_dev->hwdev);
2002 PMD_DRV_LOG(ERR, "Initialize cmdq failed, dev_name: %s",
2003 eth_dev->data->name);
2004 goto init_cmdq_fail;
2007 /* set hardware state active */
2008 rc = hinic_activate_hwdev_state(nic_dev->hwdev);
2010 PMD_DRV_LOG(ERR, "Initialize resources state failed, dev_name: %s",
2011 eth_dev->data->name);
2012 goto init_resources_state_fail;
2015 /* init_capability */
2016 rc = hinic_init_capability(nic_dev->hwdev);
2018 PMD_DRV_LOG(ERR, "Initialize capability failed, dev_name: %s",
2019 eth_dev->data->name);
2023 /* get nic capability */
2024 if (!hinic_support_nic(nic_dev->hwdev, &nic_dev->nic_cap))
2025 goto nic_check_fail;
2027 /* init root cla and function table */
2028 rc = hinic_init_nicio(nic_dev->hwdev);
2030 PMD_DRV_LOG(ERR, "Initialize nic_io failed, dev_name: %s",
2031 eth_dev->data->name);
2032 goto init_nicio_fail;
2035 /* init_software_txrxq */
2036 rc = hinic_init_sw_rxtxqs(nic_dev);
2038 PMD_DRV_LOG(ERR, "Initialize sw_rxtxqs failed, dev_name: %s",
2039 eth_dev->data->name);
2040 goto init_sw_rxtxqs_fail;
2043 rc = hinic_copy_mempool_init(nic_dev);
2045 PMD_DRV_LOG(ERR, "Create copy mempool failed, dev_name: %s",
2046 eth_dev->data->name);
2047 goto init_mpool_fail;
2050 /* set hardware feature to default status */
2051 rc = hinic_set_default_hw_feature(nic_dev);
2053 PMD_DRV_LOG(ERR, "Initialize hardware default features failed, dev_name: %s",
2054 eth_dev->data->name);
2055 goto set_default_hw_feature_fail;
2060 set_default_hw_feature_fail:
2061 hinic_copy_mempool_uninit(nic_dev);
2064 hinic_deinit_sw_rxtxqs(nic_dev);
2066 init_sw_rxtxqs_fail:
2067 hinic_deinit_nicio(nic_dev->hwdev);
2072 hinic_deactivate_hwdev_state(nic_dev->hwdev);
2074 init_resources_state_fail:
2075 hinic_comm_cmdqs_free(nic_dev->hwdev);
2079 workmode_check_fail:
2080 hinic_comm_pf_to_mgmt_free(nic_dev->hwdev);
2082 init_pf_to_mgmt_fail:
2083 hinic_comm_aeqs_free(nic_dev->hwdev);
2086 free_cfg_mgmt(nic_dev->hwdev);
2089 hinic_hwif_res_free(nic_dev->hwdev);
2092 hinic_osdep_deinit(nic_dev->hwdev);
2095 rte_free(nic_dev->hwdev);
2096 nic_dev->hwdev = NULL;
2101 static void hinic_nic_dev_destroy(struct rte_eth_dev *eth_dev)
2103 struct hinic_nic_dev *nic_dev =
2104 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
2106 (void)hinic_set_link_status_follow(nic_dev->hwdev,
2107 HINIC_LINK_FOLLOW_DEFAULT);
2108 hinic_copy_mempool_uninit(nic_dev);
2109 hinic_deinit_sw_rxtxqs(nic_dev);
2110 hinic_deinit_nicio(nic_dev->hwdev);
2111 hinic_deactivate_hwdev_state(nic_dev->hwdev);
2112 hinic_comm_cmdqs_free(nic_dev->hwdev);
2113 hinic_comm_pf_to_mgmt_free(nic_dev->hwdev);
2114 hinic_comm_aeqs_free(nic_dev->hwdev);
2115 free_cfg_mgmt(nic_dev->hwdev);
2116 hinic_hwif_res_free(nic_dev->hwdev);
2117 hinic_osdep_deinit(nic_dev->hwdev);
2118 rte_free(nic_dev->hwdev);
2119 nic_dev->hwdev = NULL;
2122 static int hinic_func_init(struct rte_eth_dev *eth_dev)
2124 struct rte_pci_device *pci_dev;
2125 struct rte_ether_addr *eth_addr;
2126 struct hinic_nic_dev *nic_dev;
2129 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2131 /* EAL is SECONDARY and eth_dev is already created */
2132 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2133 rc = rte_intr_callback_register(&pci_dev->intr_handle,
2134 hinic_dev_interrupt_handler,
2137 PMD_DRV_LOG(ERR, "Initialize %s failed in secondary process",
2138 eth_dev->data->name);
2143 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
2144 memset(nic_dev, 0, sizeof(*nic_dev));
2146 snprintf(nic_dev->proc_dev_name,
2147 sizeof(nic_dev->proc_dev_name),
2148 "hinic-%.4x:%.2x:%.2x.%x",
2149 pci_dev->addr.domain, pci_dev->addr.bus,
2150 pci_dev->addr.devid, pci_dev->addr.function);
2152 /* alloc mac_addrs */
2153 eth_addr = rte_zmalloc("hinic_mac", sizeof(*eth_addr), 0);
2155 PMD_DRV_LOG(ERR, "Allocate ethernet addresses' memory failed, dev_name: %s",
2156 eth_dev->data->name);
2160 eth_dev->data->mac_addrs = eth_addr;
2163 * Pass the information to the rte_eth_dev_close() that it should also
2164 * release the private port resources.
2166 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2168 /* create hardware nic_device */
2169 rc = hinic_nic_dev_create(eth_dev);
2171 PMD_DRV_LOG(ERR, "Create nic device failed, dev_name: %s",
2172 eth_dev->data->name);
2173 goto create_nic_dev_fail;
2176 rc = hinic_init_mac_addr(eth_dev);
2178 PMD_DRV_LOG(ERR, "Initialize mac table failed, dev_name: %s",
2179 eth_dev->data->name);
2183 /* register callback func to eal lib */
2184 rc = rte_intr_callback_register(&pci_dev->intr_handle,
2185 hinic_dev_interrupt_handler,
2188 PMD_DRV_LOG(ERR, "Register rte interrupt callback failed, dev_name: %s",
2189 eth_dev->data->name);
2190 goto reg_intr_cb_fail;
2193 /* enable uio/vfio intr/eventfd mapping */
2194 rc = rte_intr_enable(&pci_dev->intr_handle);
2196 PMD_DRV_LOG(ERR, "Enable rte interrupt failed, dev_name: %s",
2197 eth_dev->data->name);
2198 goto enable_intr_fail;
2200 hinic_set_bit(HINIC_DEV_INTR_EN, &nic_dev->dev_status);
2202 hinic_set_bit(HINIC_DEV_INIT, &nic_dev->dev_status);
2203 PMD_DRV_LOG(INFO, "Initialize %s in primary successfully",
2204 eth_dev->data->name);
2209 (void)rte_intr_callback_unregister(&pci_dev->intr_handle,
2210 hinic_dev_interrupt_handler,
2214 hinic_deinit_mac_addr(eth_dev);
2217 hinic_nic_dev_destroy(eth_dev);
2219 create_nic_dev_fail:
2221 eth_dev->data->mac_addrs = NULL;
2224 PMD_DRV_LOG(ERR, "Initialize %s in primary failed",
2225 eth_dev->data->name);
2230 * DPDK callback to close the device.
2233 * Pointer to Ethernet device structure.
2235 static void hinic_dev_close(struct rte_eth_dev *dev)
2237 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
2239 if (hinic_test_and_set_bit(HINIC_DEV_CLOSE, &nic_dev->dev_status)) {
2240 PMD_DRV_LOG(WARNING, "Device %s already closed",
2245 /* stop device first */
2246 hinic_dev_stop(dev);
2248 /* rx_cqe, rx_info */
2249 hinic_free_all_rx_resources(dev);
2252 hinic_free_all_tx_resources(dev);
2254 /* free wq, pi_dma_addr */
2255 hinic_free_all_rq(nic_dev);
2257 /* free wq, db_addr */
2258 hinic_free_all_sq(nic_dev);
2260 /* deinit mac vlan tbl */
2261 hinic_deinit_mac_addr(dev);
2263 /* disable hardware and uio interrupt */
2264 hinic_disable_interrupt(dev);
2266 /* deinit nic hardware device */
2267 hinic_nic_dev_destroy(dev);
2270 static const struct eth_dev_ops hinic_pmd_ops = {
2271 .dev_configure = hinic_dev_configure,
2272 .dev_infos_get = hinic_dev_infos_get,
2273 .rx_queue_setup = hinic_rx_queue_setup,
2274 .tx_queue_setup = hinic_tx_queue_setup,
2275 .dev_start = hinic_dev_start,
2276 .link_update = hinic_link_update,
2277 .rx_queue_release = hinic_rx_queue_release,
2278 .tx_queue_release = hinic_tx_queue_release,
2279 .dev_stop = hinic_dev_stop,
2280 .dev_close = hinic_dev_close,
2281 .promiscuous_enable = hinic_dev_promiscuous_enable,
2282 .promiscuous_disable = hinic_dev_promiscuous_disable,
2283 .rss_hash_update = hinic_rss_hash_update,
2284 .rss_hash_conf_get = hinic_rss_conf_get,
2285 .reta_update = hinic_rss_indirtbl_update,
2286 .reta_query = hinic_rss_indirtbl_query,
2287 .stats_get = hinic_dev_stats_get,
2288 .stats_reset = hinic_dev_stats_reset,
2289 .xstats_get = hinic_dev_xstats_get,
2290 .xstats_reset = hinic_dev_xstats_reset,
2291 .xstats_get_names = hinic_dev_xstats_get_names,
2294 static int hinic_dev_init(struct rte_eth_dev *eth_dev)
2296 struct rte_pci_device *pci_dev;
2298 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2300 PMD_DRV_LOG(INFO, "Initializing pf hinic-%.4x:%.2x:%.2x.%x in %s process",
2301 pci_dev->addr.domain, pci_dev->addr.bus,
2302 pci_dev->addr.devid, pci_dev->addr.function,
2303 (rte_eal_process_type() == RTE_PROC_PRIMARY) ?
2304 "primary" : "secondary");
2306 /* rte_eth_dev ops, rx_burst and tx_burst */
2307 eth_dev->dev_ops = &hinic_pmd_ops;
2308 eth_dev->rx_pkt_burst = hinic_recv_pkts;
2309 eth_dev->tx_pkt_burst = hinic_xmit_pkts;
2311 return hinic_func_init(eth_dev);
2314 static int hinic_dev_uninit(struct rte_eth_dev *dev)
2316 struct hinic_nic_dev *nic_dev;
2318 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);
2319 hinic_clear_bit(HINIC_DEV_INIT, &nic_dev->dev_status);
2321 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2324 hinic_dev_close(dev);
2326 dev->dev_ops = NULL;
2327 dev->rx_pkt_burst = NULL;
2328 dev->tx_pkt_burst = NULL;
2330 rte_free(dev->data->mac_addrs);
2331 dev->data->mac_addrs = NULL;
2336 static struct rte_pci_id pci_id_hinic_map[] = {
2337 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_PRD) },
2338 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_25GE) },
2339 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_40GE) },
2340 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_100GE) },
2344 static int hinic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2345 struct rte_pci_device *pci_dev)
2347 return rte_eth_dev_pci_generic_probe(pci_dev,
2348 sizeof(struct hinic_nic_dev), hinic_dev_init);
2351 static int hinic_pci_remove(struct rte_pci_device *pci_dev)
2353 return rte_eth_dev_pci_generic_remove(pci_dev, hinic_dev_uninit);
2356 static struct rte_pci_driver rte_hinic_pmd = {
2357 .id_table = pci_id_hinic_map,
2358 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2359 .probe = hinic_pci_probe,
2360 .remove = hinic_pci_remove,
2363 RTE_PMD_REGISTER_PCI(net_hinic, rte_hinic_pmd);
2364 RTE_PMD_REGISTER_PCI_TABLE(net_hinic, pci_id_hinic_map);
2366 RTE_INIT(hinic_init_log)
2368 hinic_logtype = rte_log_register("pmd.net.hinic");
2369 if (hinic_logtype >= 0)
2370 rte_log_set_level(hinic_logtype, RTE_LOG_INFO);