net/mlx5: add header reformat HW steering action
[dpdk.git] / drivers / net / hinic / hinic_pmd_ethdev.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
3  */
4
5 #ifndef _HINIC_PMD_ETHDEV_H_
6 #define _HINIC_PMD_ETHDEV_H_
7
8 #include <rte_ethdev.h>
9 #include <rte_ethdev_core.h>
10 #include <ethdev_driver.h>
11
12 #include "base/hinic_compat.h"
13 #include "base/hinic_pmd_cfg.h"
14
15 #define HINIC_DEV_NAME_LEN      32
16 #define HINIC_MAX_RX_QUEUES     64
17
18 /* mbuf pool for copy invalid mbuf segs */
19 #define HINIC_COPY_MEMPOOL_DEPTH        128
20 #define HINIC_COPY_MBUF_SIZE            4096
21
22 #define SIZE_8BYTES(size)       (ALIGN((u32)(size), 8) >> 3)
23
24 #define HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev) \
25         ((struct hinic_nic_dev *)(dev)->data->dev_private)
26
27 #define HINIC_MAX_QUEUE_DEPTH           4096
28 #define HINIC_MIN_QUEUE_DEPTH           128
29 #define HINIC_TXD_ALIGN                 1
30 #define HINIC_RXD_ALIGN                 1
31
32 #define HINIC_UINT32_BIT_SIZE      (CHAR_BIT * sizeof(uint32_t))
33 #define HINIC_VFTA_SIZE            (4096 / HINIC_UINT32_BIT_SIZE)
34
35 #define HINIC_MAX_MTU_SIZE              9600
36 #define HINIC_MIN_MTU_SIZE              256
37
38 #define HINIC_ETH_OVERHEAD \
39         (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN * 2)
40
41 #define HINIC_MIN_FRAME_SIZE        (HINIC_MIN_MTU_SIZE + HINIC_ETH_OVERHEAD)
42 #define HINIC_MAX_JUMBO_FRAME_SIZE  (HINIC_MAX_MTU_SIZE + HINIC_ETH_OVERHEAD)
43
44 #define HINIC_MTU_TO_PKTLEN(mtu)    ((mtu) + HINIC_ETH_OVERHEAD)
45
46 #define HINIC_PKTLEN_TO_MTU(pktlen) ((pktlen) - HINIC_ETH_OVERHEAD)
47
48 /* The max frame size with default MTU */
49 #define HINIC_ETH_MAX_LEN           (RTE_ETHER_MTU + HINIC_ETH_OVERHEAD)
50
51 enum hinic_dev_status {
52         HINIC_DEV_INIT,
53         HINIC_DEV_CLOSE,
54         HINIC_DEV_START,
55         HINIC_DEV_INTR_EN,
56 };
57
58 #define HINIC_MAX_Q_FILTERS     64 /* hinic just support 64 filter types */
59 #define HINIC_PKT_TYPE_FIND_ID(pkt_type) ((pkt_type) - HINIC_MAX_Q_FILTERS)
60
61 /* 5tuple filter info */
62 struct hinic_5tuple_filter_info {
63         uint32_t dst_ip;
64         uint32_t src_ip;
65         uint16_t dst_port;
66         uint16_t src_port;
67         uint8_t proto; /* l4 protocol. */
68         /*
69          * seven levels (001b-111b), 111b is highest,
70          * used when more than one filter matches.
71          */
72         uint8_t priority;
73
74         /* if mask is 1b, do not compare the response bit domain */
75         uint8_t dst_ip_mask:1,
76                 src_ip_mask:1,
77                 dst_port_mask:1,
78                 src_port_mask:1,
79                 proto_mask:1;
80 };
81
82 /* 5tuple filter structure */
83 struct hinic_5tuple_filter {
84         TAILQ_ENTRY(hinic_5tuple_filter) entries;
85         uint16_t index;       /* the index of 5tuple filter */
86         struct hinic_5tuple_filter_info filter_info;
87         uint16_t queue;       /* rx queue assigned to */
88 };
89
90 TAILQ_HEAD(hinic_5tuple_filter_list, hinic_5tuple_filter);
91
92 /*
93  * If this filter is added by configuration,
94  * it should not be removed.
95  */
96 struct hinic_pkt_filter {
97         uint16_t pkt_proto;
98         uint8_t qid;
99         bool    enable;
100 };
101
102 /* Structure to store filters' info. */
103 struct hinic_filter_info {
104         uint8_t pkt_type;
105         uint8_t qid;
106         uint64_t type_mask;  /* Bit mask for every used filter */
107         struct hinic_5tuple_filter_list fivetuple_list;
108         struct hinic_pkt_filter pkt_filters[HINIC_MAX_Q_FILTERS];
109 };
110
111 /* Information about the fdir mode. */
112 struct hinic_hw_fdir_mask {
113         uint32_t src_ipv4_mask;
114         uint32_t dst_ipv4_mask;
115         uint16_t src_port_mask;
116         uint16_t dst_port_mask;
117         uint16_t proto_mask;
118         uint16_t tunnel_flag;
119         uint16_t tunnel_inner_src_port_mask;
120         uint16_t tunnel_inner_dst_port_mask;
121         uint16_t dst_ipv6_mask;
122 };
123
124 /* Flow Director attribute */
125 struct hinic_atr_input {
126         uint32_t dst_ip;
127         uint32_t src_ip;
128         uint16_t src_port;
129         uint16_t dst_port;
130         uint16_t proto;
131         uint16_t tunnel_flag;
132         uint16_t tunnel_inner_src_port;
133         uint16_t tunnel_inner_dst_port;
134         uint8_t  dst_ipv6[16];
135 };
136
137 enum hinic_fdir_mode {
138         HINIC_FDIR_MODE_NORMAL      = 0,
139         HINIC_FDIR_MODE_TCAM        = 1,
140 };
141
142 #define HINIC_PF_MAX_TCAM_FILTERS       1024
143 #define HINIC_VF_MAX_TCAM_FILTERS       128
144 #define HINIC_SUPPORT_PF_MAX_NUM        4
145 #define HINIC_TOTAL_PF_MAX_NUM          16
146 #define HINIC_SUPPORT_VF_MAX_NUM        32
147 #define HINIC_TCAM_BLOCK_TYPE_PF        0 /* 1024 tcam index of a block */
148 #define HINIC_TCAM_BLOCK_TYPE_VF        1 /* 128 tcam index of a block */
149
150 #define HINIC_PKT_VF_TCAM_INDEX_START(block_index)  \
151                 (HINIC_PF_MAX_TCAM_FILTERS * HINIC_SUPPORT_PF_MAX_NUM + \
152                 HINIC_VF_MAX_TCAM_FILTERS * (block_index))
153
154 TAILQ_HEAD(hinic_tcam_filter_list, hinic_tcam_filter);
155
156 struct hinic_tcam_info {
157         struct hinic_tcam_filter_list tcam_list;
158         u8 tcam_index_array[HINIC_PF_MAX_TCAM_FILTERS];
159         u16 tcam_block_index;
160         u16 tcam_rule_nums;
161 };
162
163 struct tag_tcam_key_mem {
164 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN)
165
166                 u32 rsvd0:16;
167                 u32 function_id:16;
168
169                 u32 protocol:8;
170                 /*
171                  * tunnel packet, mask must be 0xff, spec value is 1;
172                  * normal packet, mask must be 0, spec value is 0;
173                  * if tunnel packet, ucode use
174                  * sip/dip/protocol/src_port/dst_dport from inner packet
175                  */
176                 u32 tunnel_flag:8;
177                 u32 sip_h:16;
178
179                 u32 sip_l:16;
180                 u32 dip_h:16;
181
182                 u32 dip_l:16;
183                 u32 src_port:16;
184
185                 u32 dst_port:16;
186                 /*
187                  * tunnel packet and normal packet,
188                  * ext_dip mask must be 0xffffffff
189                  */
190                 u32 ext_dip_h:16;
191                 u32 ext_dip_l:16;
192                 u32 rsvd2:16;
193 #else
194                 u32 function_id:16;
195                 u32 rsvd0:16;
196
197                 u32 sip_h:16;
198                 u32 tunnel_flag:8;
199                 u32 protocol:8;
200
201                 u32 dip_h:16;
202                 u32 sip_l:16;
203
204                 u32 src_port:16;
205                 u32 dip_l:16;
206
207                 u32 ext_dip_h:16;
208                 u32 dst_port:16;
209
210                 u32 rsvd2:16;
211                 u32 ext_dip_l:16;
212 #endif
213 };
214
215 struct tag_tcam_key_ipv6_mem {
216 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN)
217                 u32 rsvd0:16;
218                 u32 ipv6_flag:1;
219                 u32 protocol:7;
220                 u32 function_id:8;
221
222                 u32 dst_port:16;
223                 u32 ipv6_key0:16;
224
225                 u32 ipv6_key1:16;
226                 u32 ipv6_key2:16;
227
228                 u32 ipv6_key3:16;
229                 u32 ipv6_key4:16;
230
231                 u32 ipv6_key5:16;
232                 u32 ipv6_key6:16;
233
234                 u32 ipv6_key7:16;
235                 u32 rsvd2:16;
236 #else
237                 u32 function_id:8;
238                 u32 protocol:7;
239                 u32 ipv6_flag:1;
240                 u32 rsvd0:16;
241
242                 u32 ipv6_key0:16;
243                 u32 dst_port:16;
244
245                 u32 ipv6_key2:16;
246                 u32 ipv6_key1:16;
247
248                 u32 ipv6_key4:16;
249                 u32 ipv6_key3:16;
250
251                 u32 ipv6_key6:16;
252                 u32 ipv6_key5:16;
253
254                 u32 rsvd2:16;
255                 u32 ipv6_key7:16;
256 #endif
257 };
258
259 struct tag_tcam_key {
260         union {
261                 struct tag_tcam_key_mem key_info;
262                 struct tag_tcam_key_ipv6_mem key_info_ipv6;
263         };
264
265         union {
266                 struct tag_tcam_key_mem key_mask;
267                 struct tag_tcam_key_ipv6_mem key_mask_ipv6;
268         };
269 };
270
271 struct hinic_fdir_rule {
272         struct hinic_hw_fdir_mask mask;
273         struct hinic_atr_input hinic_fdir; /* key of fdir filter */
274         uint8_t queue; /* queue assigned when matched */
275         enum hinic_fdir_mode mode; /* fdir type */
276         u16 tcam_index;
277 };
278
279 /* ntuple filter list structure */
280 struct hinic_ntuple_filter_ele {
281         TAILQ_ENTRY(hinic_ntuple_filter_ele) entries;
282         struct rte_eth_ntuple_filter filter_info;
283 };
284
285 /* ethertype filter list structure */
286 struct hinic_ethertype_filter_ele {
287         TAILQ_ENTRY(hinic_ethertype_filter_ele) entries;
288         struct rte_eth_ethertype_filter filter_info;
289 };
290
291 /* fdir filter list structure */
292 struct hinic_fdir_rule_ele {
293         TAILQ_ENTRY(hinic_fdir_rule_ele) entries;
294         struct hinic_fdir_rule filter_info;
295 };
296
297 struct hinic_tcam_filter {
298         TAILQ_ENTRY(hinic_tcam_filter) entries;
299         uint16_t index; /* tcam index */
300         struct tag_tcam_key tcam_key;
301         uint16_t queue; /* rx queue assigned to */
302 };
303
304 struct rte_flow {
305         enum rte_filter_type filter_type;
306         void *rule;
307 };
308
309 /* hinic_flow memory list structure */
310 struct hinic_flow_mem {
311         TAILQ_ENTRY(hinic_flow_mem) entries;
312         struct rte_flow *flow;
313 };
314
315 TAILQ_HEAD(hinic_ntuple_filter_list, hinic_ntuple_filter_ele);
316 TAILQ_HEAD(hinic_ethertype_filter_list, hinic_ethertype_filter_ele);
317 TAILQ_HEAD(hinic_fdir_rule_filter_list, hinic_fdir_rule_ele);
318 TAILQ_HEAD(hinic_flow_mem_list, hinic_flow_mem);
319
320 extern const struct rte_flow_ops hinic_flow_ops;
321
322 /* hinic nic_device */
323 struct hinic_nic_dev {
324         /* hardware device */
325         struct hinic_hwdev *hwdev;
326         struct hinic_txq **txqs;
327         struct hinic_rxq **rxqs;
328         struct rte_mempool *cpy_mpool;
329         u16 num_qps;
330         u16 num_sq;
331         u16 num_rq;
332         u16 mtu_size;
333         u8 rss_tmpl_idx;
334         u8 rss_indir_flag;
335         u8 num_rss;
336         u8 rx_queue_list[HINIC_MAX_RX_QUEUES];
337
338         bool pause_set;
339         struct nic_pause_config nic_pause;
340
341         u32 vfta[HINIC_VFTA_SIZE];      /* VLAN bitmap */
342
343         struct rte_ether_addr default_addr;
344         struct rte_ether_addr *mc_list;
345         /* info */
346         unsigned int flags;
347         struct nic_service_cap nic_cap;
348         u32 rx_mode_status;     /* promisc or allmulticast */
349         pthread_mutex_t rx_mode_mutex;
350         u32 dev_status;
351
352         char proc_dev_name[HINIC_DEV_NAME_LEN];
353         /* PF0->COS4, PF1->COS5, PF2->COS6, PF3->COS7,
354          * vf: the same with associate pf
355          */
356         u32 default_cos;
357         u32 rx_csum_en;
358
359         struct hinic_filter_info    filter;
360         struct hinic_tcam_info      tcam;
361         struct hinic_ntuple_filter_list filter_ntuple_list;
362         struct hinic_ethertype_filter_list filter_ethertype_list;
363         struct hinic_fdir_rule_filter_list filter_fdir_rule_list;
364         struct hinic_flow_mem_list hinic_flow_list;
365 };
366
367 void hinic_free_fdir_filter(struct hinic_nic_dev *nic_dev);
368
369 void hinic_destroy_fdir_filter(struct rte_eth_dev *dev);
370 #endif /* _HINIC_PMD_ETHDEV_H_ */