1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #ifndef _HINIC_PMD_ETHDEV_H_
6 #define _HINIC_PMD_ETHDEV_H_
8 #include <rte_ethdev.h>
9 #include <rte_ethdev_core.h>
10 #include <ethdev_driver.h>
12 #include "base/hinic_compat.h"
13 #include "base/hinic_pmd_cfg.h"
15 #define HINIC_DEV_NAME_LEN 32
16 #define HINIC_MAX_RX_QUEUES 64
18 /* mbuf pool for copy invalid mbuf segs */
19 #define HINIC_COPY_MEMPOOL_DEPTH 128
20 #define HINIC_COPY_MBUF_SIZE 4096
22 #define SIZE_8BYTES(size) (ALIGN((u32)(size), 8) >> 3)
24 #define HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev) \
25 ((struct hinic_nic_dev *)(dev)->data->dev_private)
27 #define HINIC_MAX_QUEUE_DEPTH 4096
28 #define HINIC_MIN_QUEUE_DEPTH 128
29 #define HINIC_TXD_ALIGN 1
30 #define HINIC_RXD_ALIGN 1
32 #define HINIC_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
33 #define HINIC_VFTA_SIZE (4096 / HINIC_UINT32_BIT_SIZE)
35 #define HINIC_MAX_MTU_SIZE 9600
36 #define HINIC_MIN_MTU_SIZE 256
38 #define HINIC_VLAN_TAG_SIZE 4
39 #define HINIC_ETH_OVERHEAD \
40 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HINIC_VLAN_TAG_SIZE * 2)
42 #define HINIC_MIN_FRAME_SIZE (HINIC_MIN_MTU_SIZE + HINIC_ETH_OVERHEAD)
43 #define HINIC_MAX_JUMBO_FRAME_SIZE (HINIC_MAX_MTU_SIZE + HINIC_ETH_OVERHEAD)
45 #define HINIC_MTU_TO_PKTLEN(mtu) ((mtu) + HINIC_ETH_OVERHEAD)
47 #define HINIC_PKTLEN_TO_MTU(pktlen) ((pktlen) - HINIC_ETH_OVERHEAD)
49 /* The max frame size with default MTU */
50 #define HINIC_ETH_MAX_LEN (RTE_ETHER_MTU + HINIC_ETH_OVERHEAD)
52 enum hinic_dev_status {
59 #define HINIC_MAX_Q_FILTERS 64 /* hinic just support 64 filter types */
60 #define HINIC_PKT_TYPE_FIND_ID(pkt_type) ((pkt_type) - HINIC_MAX_Q_FILTERS)
62 /* 5tuple filter info */
63 struct hinic_5tuple_filter_info {
68 uint8_t proto; /* l4 protocol. */
70 * seven levels (001b-111b), 111b is highest,
71 * used when more than one filter matches.
75 /* if mask is 1b, do not compare the response bit domain */
76 uint8_t dst_ip_mask:1,
83 /* 5tuple filter structure */
84 struct hinic_5tuple_filter {
85 TAILQ_ENTRY(hinic_5tuple_filter) entries;
86 uint16_t index; /* the index of 5tuple filter */
87 struct hinic_5tuple_filter_info filter_info;
88 uint16_t queue; /* rx queue assigned to */
91 TAILQ_HEAD(hinic_5tuple_filter_list, hinic_5tuple_filter);
94 * If this filter is added by configuration,
95 * it should not be removed.
97 struct hinic_pkt_filter {
103 /* Structure to store filters' info. */
104 struct hinic_filter_info {
107 uint64_t type_mask; /* Bit mask for every used filter */
108 struct hinic_5tuple_filter_list fivetuple_list;
109 struct hinic_pkt_filter pkt_filters[HINIC_MAX_Q_FILTERS];
112 /* Information about the fdir mode. */
113 struct hinic_hw_fdir_mask {
114 uint32_t src_ipv4_mask;
115 uint32_t dst_ipv4_mask;
116 uint16_t src_port_mask;
117 uint16_t dst_port_mask;
119 uint16_t tunnel_flag;
120 uint16_t tunnel_inner_src_port_mask;
121 uint16_t tunnel_inner_dst_port_mask;
122 uint16_t dst_ipv6_mask;
125 /* Flow Director attribute */
126 struct hinic_atr_input {
132 uint16_t tunnel_flag;
133 uint16_t tunnel_inner_src_port;
134 uint16_t tunnel_inner_dst_port;
135 uint8_t dst_ipv6[16];
138 enum hinic_fdir_mode {
139 HINIC_FDIR_MODE_NORMAL = 0,
140 HINIC_FDIR_MODE_TCAM = 1,
143 #define HINIC_PF_MAX_TCAM_FILTERS 1024
144 #define HINIC_VF_MAX_TCAM_FILTERS 128
145 #define HINIC_SUPPORT_PF_MAX_NUM 4
146 #define HINIC_TOTAL_PF_MAX_NUM 16
147 #define HINIC_SUPPORT_VF_MAX_NUM 32
148 #define HINIC_TCAM_BLOCK_TYPE_PF 0 /* 1024 tcam index of a block */
149 #define HINIC_TCAM_BLOCK_TYPE_VF 1 /* 128 tcam index of a block */
151 #define HINIC_PKT_VF_TCAM_INDEX_START(block_index) \
152 (HINIC_PF_MAX_TCAM_FILTERS * HINIC_SUPPORT_PF_MAX_NUM + \
153 HINIC_VF_MAX_TCAM_FILTERS * (block_index))
155 TAILQ_HEAD(hinic_tcam_filter_list, hinic_tcam_filter);
157 struct hinic_tcam_info {
158 struct hinic_tcam_filter_list tcam_list;
159 u8 tcam_index_array[HINIC_PF_MAX_TCAM_FILTERS];
160 u16 tcam_block_index;
164 struct tag_tcam_key_mem {
165 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN)
172 * tunnel packet, mask must be 0xff, spec value is 1;
173 * normal packet, mask must be 0, spec value is 0;
174 * if tunnal packet, ucode use
175 * sip/dip/protocol/src_port/dst_dport from inner packet
188 * tunnel packet and normal packet,
189 * ext_dip mask must be 0xffffffff
216 struct tag_tcam_key_ipv6_mem {
217 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN)
260 struct tag_tcam_key {
262 struct tag_tcam_key_mem key_info;
263 struct tag_tcam_key_ipv6_mem key_info_ipv6;
267 struct tag_tcam_key_mem key_mask;
268 struct tag_tcam_key_ipv6_mem key_mask_ipv6;
272 struct hinic_fdir_rule {
273 struct hinic_hw_fdir_mask mask;
274 struct hinic_atr_input hinic_fdir; /* key of fdir filter */
275 uint8_t queue; /* queue assigned when matched */
276 enum hinic_fdir_mode mode; /* fdir type */
280 /* ntuple filter list structure */
281 struct hinic_ntuple_filter_ele {
282 TAILQ_ENTRY(hinic_ntuple_filter_ele) entries;
283 struct rte_eth_ntuple_filter filter_info;
286 /* ethertype filter list structure */
287 struct hinic_ethertype_filter_ele {
288 TAILQ_ENTRY(hinic_ethertype_filter_ele) entries;
289 struct rte_eth_ethertype_filter filter_info;
292 /* fdir filter list structure */
293 struct hinic_fdir_rule_ele {
294 TAILQ_ENTRY(hinic_fdir_rule_ele) entries;
295 struct hinic_fdir_rule filter_info;
298 struct hinic_tcam_filter {
299 TAILQ_ENTRY(hinic_tcam_filter) entries;
300 uint16_t index; /* tcam index */
301 struct tag_tcam_key tcam_key;
302 uint16_t queue; /* rx queue assigned to */
306 enum rte_filter_type filter_type;
310 /* hinic_flow memory list structure */
311 struct hinic_flow_mem {
312 TAILQ_ENTRY(hinic_flow_mem) entries;
313 struct rte_flow *flow;
316 TAILQ_HEAD(hinic_ntuple_filter_list, hinic_ntuple_filter_ele);
317 TAILQ_HEAD(hinic_ethertype_filter_list, hinic_ethertype_filter_ele);
318 TAILQ_HEAD(hinic_fdir_rule_filter_list, hinic_fdir_rule_ele);
319 TAILQ_HEAD(hinic_flow_mem_list, hinic_flow_mem);
321 extern const struct rte_flow_ops hinic_flow_ops;
323 /* hinic nic_device */
324 struct hinic_nic_dev {
325 /* hardware device */
326 struct hinic_hwdev *hwdev;
327 struct hinic_txq **txqs;
328 struct hinic_rxq **rxqs;
329 struct rte_mempool *cpy_mpool;
337 u8 rx_queue_list[HINIC_MAX_RX_QUEUES];
340 struct nic_pause_config nic_pause;
342 u32 vfta[HINIC_VFTA_SIZE]; /* VLAN bitmap */
344 struct rte_ether_addr default_addr;
345 struct rte_ether_addr *mc_list;
348 struct nic_service_cap nic_cap;
349 u32 rx_mode_status; /* promisc or allmulticast */
350 pthread_mutex_t rx_mode_mutex;
353 char proc_dev_name[HINIC_DEV_NAME_LEN];
354 /* PF0->COS4, PF1->COS5, PF2->COS6, PF3->COS7,
355 * vf: the same with associate pf
360 struct hinic_filter_info filter;
361 struct hinic_tcam_info tcam;
362 struct hinic_ntuple_filter_list filter_ntuple_list;
363 struct hinic_ethertype_filter_list filter_ethertype_list;
364 struct hinic_fdir_rule_filter_list filter_fdir_rule_list;
365 struct hinic_flow_mem_list hinic_flow_list;
368 void hinic_free_fdir_filter(struct hinic_nic_dev *nic_dev);
370 void hinic_destroy_fdir_filter(struct rte_eth_dev *dev);
371 #endif /* _HINIC_PMD_ETHDEV_H_ */