1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
14 #include "base/hinic_compat.h"
15 #include "base/hinic_pmd_hwdev.h"
16 #include "base/hinic_pmd_hwif.h"
17 #include "base/hinic_pmd_wq.h"
18 #include "base/hinic_pmd_nicio.h"
19 #include "base/hinic_pmd_niccfg.h"
20 #include "hinic_pmd_ethdev.h"
21 #include "hinic_pmd_tx.h"
23 /* packet header and tx offload info */
24 #define ETHER_LEN_NO_VLAN 14
25 #define ETHER_LEN_WITH_VLAN 18
26 #define HEADER_LEN_OFFSET 2
28 #define MAX_PLD_OFFSET 221
29 #define MAX_SINGLE_SGE_SIZE 65536
31 #define TX_MSS_DEFAULT 0x3E00
32 #define TX_MSS_MIN 0x50
34 #define HINIC_NONTSO_PKT_MAX_SGE 17 /* non-tso max sge 17 */
35 #define HINIC_NONTSO_SEG_NUM_INVALID(num) \
36 ((num) > HINIC_NONTSO_PKT_MAX_SGE)
38 #define HINIC_TSO_PKT_MAX_SGE 127 /* tso max sge 127 */
39 #define HINIC_TSO_SEG_NUM_INVALID(num) ((num) > HINIC_TSO_PKT_MAX_SGE)
41 #define HINIC_TX_OUTER_CHECKSUM_FLAG_SET 1
42 #define HINIC_TX_OUTER_CHECKSUM_FLAG_NO_SET 0
44 /* sizeof(struct hinic_sq_bufdesc) == 16, shift 4 */
45 #define HINIC_BUF_DESC_SIZE(nr_descs) (SIZE_8BYTES(((u32)nr_descs) << 4))
47 #define MASKED_SQ_IDX(sq, idx) ((idx) & (sq)->wq->mask)
50 #define SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
51 #define SQ_CTRL_TASKSECT_LEN_SHIFT 16
52 #define SQ_CTRL_DATA_FORMAT_SHIFT 22
53 #define SQ_CTRL_LEN_SHIFT 29
54 #define SQ_CTRL_OWNER_SHIFT 31
56 #define SQ_CTRL_BUFDESC_SECT_LEN_MASK 0xFFU
57 #define SQ_CTRL_TASKSECT_LEN_MASK 0x1FU
58 #define SQ_CTRL_DATA_FORMAT_MASK 0x1U
59 #define SQ_CTRL_LEN_MASK 0x3U
60 #define SQ_CTRL_OWNER_MASK 0x1U
62 #define SQ_CTRL_SET(val, member) \
63 (((val) & SQ_CTRL_##member##_MASK) << SQ_CTRL_##member##_SHIFT)
65 #define SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT 2
66 #define SQ_CTRL_QUEUE_INFO_UFO_SHIFT 10
67 #define SQ_CTRL_QUEUE_INFO_TSO_SHIFT 11
68 #define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT 12
69 #define SQ_CTRL_QUEUE_INFO_MSS_SHIFT 13
70 #define SQ_CTRL_QUEUE_INFO_SCTP_SHIFT 27
71 #define SQ_CTRL_QUEUE_INFO_UC_SHIFT 28
72 #define SQ_CTRL_QUEUE_INFO_PRI_SHIFT 29
74 #define SQ_CTRL_QUEUE_INFO_PLDOFF_MASK 0xFFU
75 #define SQ_CTRL_QUEUE_INFO_UFO_MASK 0x1U
76 #define SQ_CTRL_QUEUE_INFO_TSO_MASK 0x1U
77 #define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK 0x1U
78 #define SQ_CTRL_QUEUE_INFO_MSS_MASK 0x3FFFU
79 #define SQ_CTRL_QUEUE_INFO_SCTP_MASK 0x1U
80 #define SQ_CTRL_QUEUE_INFO_UC_MASK 0x1U
81 #define SQ_CTRL_QUEUE_INFO_PRI_MASK 0x7U
83 #define SQ_CTRL_QUEUE_INFO_SET(val, member) \
84 (((u32)(val) & SQ_CTRL_QUEUE_INFO_##member##_MASK) << \
85 SQ_CTRL_QUEUE_INFO_##member##_SHIFT)
87 #define SQ_CTRL_QUEUE_INFO_GET(val, member) \
88 (((val) >> SQ_CTRL_QUEUE_INFO_##member##_SHIFT) & \
89 SQ_CTRL_QUEUE_INFO_##member##_MASK)
91 #define SQ_CTRL_QUEUE_INFO_CLEAR(val, member) \
92 ((val) & (~(SQ_CTRL_QUEUE_INFO_##member##_MASK << \
93 SQ_CTRL_QUEUE_INFO_##member##_SHIFT)))
95 #define SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0
96 #define SQ_TASK_INFO0_L4OFFLOAD_SHIFT 8
97 #define SQ_TASK_INFO0_INNER_L3TYPE_SHIFT 10
98 #define SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT 12
99 #define SQ_TASK_INFO0_PARSE_FLAG_SHIFT 13
100 #define SQ_TASK_INFO0_UFO_AVD_SHIFT 14
101 #define SQ_TASK_INFO0_TSO_UFO_SHIFT 15
102 #define SQ_TASK_INFO0_VLAN_TAG_SHIFT 16
104 #define SQ_TASK_INFO0_L2HDR_LEN_MASK 0xFFU
105 #define SQ_TASK_INFO0_L4OFFLOAD_MASK 0x3U
106 #define SQ_TASK_INFO0_INNER_L3TYPE_MASK 0x3U
107 #define SQ_TASK_INFO0_VLAN_OFFLOAD_MASK 0x1U
108 #define SQ_TASK_INFO0_PARSE_FLAG_MASK 0x1U
109 #define SQ_TASK_INFO0_UFO_AVD_MASK 0x1U
110 #define SQ_TASK_INFO0_TSO_UFO_MASK 0x1U
111 #define SQ_TASK_INFO0_VLAN_TAG_MASK 0xFFFFU
113 #define SQ_TASK_INFO0_SET(val, member) \
114 (((u32)(val) & SQ_TASK_INFO0_##member##_MASK) << \
115 SQ_TASK_INFO0_##member##_SHIFT)
117 #define SQ_TASK_INFO1_MD_TYPE_SHIFT 8
118 #define SQ_TASK_INFO1_INNER_L4LEN_SHIFT 16
119 #define SQ_TASK_INFO1_INNER_L3LEN_SHIFT 24
121 #define SQ_TASK_INFO1_MD_TYPE_MASK 0xFFU
122 #define SQ_TASK_INFO1_INNER_L4LEN_MASK 0xFFU
123 #define SQ_TASK_INFO1_INNER_L3LEN_MASK 0xFFU
125 #define SQ_TASK_INFO1_SET(val, member) \
126 (((val) & SQ_TASK_INFO1_##member##_MASK) << \
127 SQ_TASK_INFO1_##member##_SHIFT)
129 #define SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT 0
130 #define SQ_TASK_INFO2_OUTER_L3LEN_SHIFT 8
131 #define SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT 16
132 #define SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT 24
134 #define SQ_TASK_INFO2_TUNNEL_L4LEN_MASK 0xFFU
135 #define SQ_TASK_INFO2_OUTER_L3LEN_MASK 0xFFU
136 #define SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK 0x7U
137 #define SQ_TASK_INFO2_OUTER_L3TYPE_MASK 0x3U
139 #define SQ_TASK_INFO2_SET(val, member) \
140 (((val) & SQ_TASK_INFO2_##member##_MASK) << \
141 SQ_TASK_INFO2_##member##_SHIFT)
143 #define SQ_TASK_INFO4_L2TYPE_SHIFT 31
145 #define SQ_TASK_INFO4_L2TYPE_MASK 0x1U
147 #define SQ_TASK_INFO4_SET(val, member) \
148 (((u32)(val) & SQ_TASK_INFO4_##member##_MASK) << \
149 SQ_TASK_INFO4_##member##_SHIFT)
152 #define SQ_DB_OFF 0x00000800
153 #define SQ_DB_INFO_HI_PI_SHIFT 0
154 #define SQ_DB_INFO_QID_SHIFT 8
155 #define SQ_DB_INFO_CFLAG_SHIFT 23
156 #define SQ_DB_INFO_COS_SHIFT 24
157 #define SQ_DB_INFO_TYPE_SHIFT 27
159 #define SQ_DB_INFO_HI_PI_MASK 0xFFU
160 #define SQ_DB_INFO_QID_MASK 0x3FFU
161 #define SQ_DB_INFO_CFLAG_MASK 0x1U
162 #define SQ_DB_INFO_COS_MASK 0x7U
163 #define SQ_DB_INFO_TYPE_MASK 0x1FU
164 #define SQ_DB_INFO_SET(val, member) \
165 (((u32)(val) & SQ_DB_INFO_##member##_MASK) << \
166 SQ_DB_INFO_##member##_SHIFT)
169 #define SQ_CFLAG_DP 0 /* CFLAG_DATA_PATH */
171 #define SQ_DB_PI_LOW_MASK 0xFF
172 #define SQ_DB_PI_LOW(pi) ((pi) & SQ_DB_PI_LOW_MASK)
173 #define SQ_DB_PI_HI_SHIFT 8
174 #define SQ_DB_PI_HIGH(pi) ((pi) >> SQ_DB_PI_HI_SHIFT)
175 #define SQ_DB_ADDR(sq, pi) \
176 ((u64 *)((u8 __iomem *)((sq)->db_addr) + SQ_DB_OFF) + SQ_DB_PI_LOW(pi))
178 /* txq wq operations */
179 #define HINIC_GET_SQ_WQE_MASK(txq) ((txq)->wq->mask)
181 #define HINIC_GET_SQ_HW_CI(txq) \
182 ((be16_to_cpu(*(txq)->cons_idx_addr)) & HINIC_GET_SQ_WQE_MASK(txq))
184 #define HINIC_GET_SQ_LOCAL_CI(txq) \
185 (((txq)->wq->cons_idx) & HINIC_GET_SQ_WQE_MASK(txq))
187 #define HINIC_UPDATE_SQ_LOCAL_CI(txq, wqebb_cnt) \
189 (txq)->wq->cons_idx += wqebb_cnt; \
190 (txq)->wq->delta += wqebb_cnt; \
193 #define HINIC_GET_SQ_FREE_WQEBBS(txq) ((txq)->wq->delta - 1)
195 #define HINIC_IS_SQ_EMPTY(txq) (((txq)->wq->delta) == ((txq)->q_depth))
197 #define BUF_DESC_SIZE_SHIFT 4
199 #define HINIC_SQ_WQE_SIZE(num_sge) \
200 (sizeof(struct hinic_sq_ctrl) + sizeof(struct hinic_sq_task) + \
201 (unsigned int)((num_sge) << BUF_DESC_SIZE_SHIFT))
203 #define HINIC_SQ_WQEBB_CNT(num_sge) \
204 (int)(ALIGN(HINIC_SQ_WQE_SIZE((u32)num_sge), \
205 HINIC_SQ_WQEBB_SIZE) >> HINIC_SQ_WQEBB_SHIFT)
208 static inline void hinic_sq_wqe_cpu_to_be32(void *data, int nr_wqebb)
210 #if defined(__X86_64_SSE__)
212 __m128i *wqe_line = (__m128i *)data;
213 __m128i shuf_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10,
214 11, 4, 5, 6, 7, 0, 1, 2, 3);
216 for (i = 0; i < nr_wqebb; i++) {
217 /* convert 64B wqebb using 4 SSE instructions */
218 wqe_line[0] = _mm_shuffle_epi8(wqe_line[0], shuf_mask);
219 wqe_line[1] = _mm_shuffle_epi8(wqe_line[1], shuf_mask);
220 wqe_line[2] = _mm_shuffle_epi8(wqe_line[2], shuf_mask);
221 wqe_line[3] = _mm_shuffle_epi8(wqe_line[3], shuf_mask);
224 #elif defined(__ARM64_NEON__)
226 uint8x16_t *wqe_line = (uint8x16_t *)data;
227 const uint8x16_t shuf_mask = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10,
228 9, 8, 15, 14, 13, 12};
230 for (i = 0; i < nr_wqebb; i++) {
231 wqe_line[0] = vqtbl1q_u8(wqe_line[0], shuf_mask);
232 wqe_line[1] = vqtbl1q_u8(wqe_line[1], shuf_mask);
233 wqe_line[2] = vqtbl1q_u8(wqe_line[2], shuf_mask);
234 wqe_line[3] = vqtbl1q_u8(wqe_line[3], shuf_mask);
238 hinic_cpu_to_be32(data, nr_wqebb * HINIC_SQ_WQEBB_SIZE);
242 static inline void hinic_sge_cpu_to_be32(void *data, int nr_sge)
244 #if defined(__X86_64_SSE__)
246 __m128i *sge_line = (__m128i *)data;
247 __m128i shuf_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10,
248 11, 4, 5, 6, 7, 0, 1, 2, 3);
250 for (i = 0; i < nr_sge; i++) {
251 /* convert 16B sge using 1 SSE instructions */
252 *sge_line = _mm_shuffle_epi8(*sge_line, shuf_mask);
255 #elif defined(__ARM64_NEON__)
257 uint8x16_t *sge_line = (uint8x16_t *)data;
258 const uint8x16_t shuf_mask = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10,
259 9, 8, 15, 14, 13, 12};
261 for (i = 0; i < nr_sge; i++) {
262 *sge_line = vqtbl1q_u8(*sge_line, shuf_mask);
266 hinic_cpu_to_be32(data, nr_sge * sizeof(struct hinic_sq_bufdesc));
270 void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats)
272 if (!txq || !stats) {
273 PMD_DRV_LOG(ERR, "Txq or stats is NULL");
277 memcpy(stats, &txq->txq_stats, sizeof(txq->txq_stats));
280 void hinic_txq_stats_reset(struct hinic_txq *txq)
282 struct hinic_txq_stats *txq_stats;
287 txq_stats = &txq->txq_stats;
288 memset(txq_stats, 0, sizeof(*txq_stats));
291 static inline struct rte_mbuf *hinic_copy_tx_mbuf(struct hinic_nic_dev *nic_dev,
292 struct rte_mbuf *mbuf,
295 struct rte_mbuf *dst_mbuf;
299 if (unlikely(!nic_dev->cpy_mpool))
302 dst_mbuf = rte_pktmbuf_alloc(nic_dev->cpy_mpool);
303 if (unlikely(!dst_mbuf))
306 dst_mbuf->data_off = 0;
307 for (i = 0; i < sge_cnt; i++) {
308 rte_memcpy((char *)dst_mbuf->buf_addr + offset,
309 (char *)mbuf->buf_addr + mbuf->data_off,
311 dst_mbuf->data_len += mbuf->data_len;
312 offset += mbuf->data_len;
319 static inline bool hinic_mbuf_dma_map_sge(struct hinic_txq *txq,
320 struct rte_mbuf *mbuf,
321 struct hinic_sq_bufdesc *sges,
322 struct hinic_wqe_info *sqe_info)
326 u16 nb_segs = sqe_info->sge_cnt - sqe_info->cpy_mbuf_cnt;
327 u16 real_nb_segs = mbuf->nb_segs;
328 struct hinic_sq_bufdesc *sge_idx = sges;
330 if (unlikely(sqe_info->around)) {
331 /* parts of wqe is in sq bottom while parts
332 * of wqe is in sq head
335 for (sge_idx = sges; (u64)sge_idx <= txq->sq_bot_sge_addr;
337 if (unlikely(mbuf == NULL)) {
338 txq->txq_stats.mbuf_null++;
342 dma_addr = rte_mbuf_data_iova(mbuf);
343 if (unlikely(mbuf->data_len == 0)) {
344 txq->txq_stats.sge_len0++;
347 hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr,
353 around_sges = nb_segs - i;
354 sge_idx = (struct hinic_sq_bufdesc *)
355 ((void *)txq->sq_head_addr);
356 for (; i < nb_segs; i++) {
357 if (unlikely(mbuf == NULL)) {
358 txq->txq_stats.mbuf_null++;
362 dma_addr = rte_mbuf_data_iova(mbuf);
363 if (unlikely(mbuf->data_len == 0)) {
364 txq->txq_stats.sge_len0++;
367 hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr,
373 /* covert sges at head to big endian */
374 hinic_sge_cpu_to_be32((void *)txq->sq_head_addr, around_sges);
376 /* wqe is in continuous space */
377 for (i = 0; i < nb_segs; i++) {
378 if (unlikely(mbuf == NULL)) {
379 txq->txq_stats.mbuf_null++;
383 dma_addr = rte_mbuf_data_iova(mbuf);
384 if (unlikely(mbuf->data_len == 0)) {
385 txq->txq_stats.sge_len0++;
388 hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr,
395 /* for now: support non-tso over 17 sge, copy the last 2 mbuf */
396 if (unlikely(sqe_info->cpy_mbuf_cnt != 0)) {
397 /* copy invalid mbuf segs to a valid buffer, lost performance */
398 txq->txq_stats.cpy_pkts += 1;
399 mbuf = hinic_copy_tx_mbuf(txq->nic_dev, mbuf,
400 real_nb_segs - nb_segs);
404 txq->tx_info[sqe_info->pi].cpy_mbuf = mbuf;
406 /* deal with the last mbuf */
407 dma_addr = rte_mbuf_data_iova(mbuf);
408 if (unlikely(mbuf->data_len == 0)) {
409 txq->txq_stats.sge_len0++;
412 hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr,
414 if (unlikely(sqe_info->around))
415 hinic_sge_cpu_to_be32((void *)sge_idx, 1);
421 static inline void hinic_fill_sq_wqe_header(struct hinic_sq_ctrl *ctrl,
422 u32 queue_info, int nr_descs,
425 u32 ctrl_size, task_size, bufdesc_size;
427 ctrl_size = SIZE_8BYTES(sizeof(struct hinic_sq_ctrl));
428 task_size = SIZE_8BYTES(sizeof(struct hinic_sq_task));
429 bufdesc_size = HINIC_BUF_DESC_SIZE(nr_descs);
431 ctrl->ctrl_fmt = SQ_CTRL_SET(bufdesc_size, BUFDESC_SECT_LEN) |
432 SQ_CTRL_SET(task_size, TASKSECT_LEN) |
433 SQ_CTRL_SET(SQ_NORMAL_WQE, DATA_FORMAT) |
434 SQ_CTRL_SET(ctrl_size, LEN) |
435 SQ_CTRL_SET(owner, OWNER);
437 ctrl->queue_info = queue_info;
438 ctrl->queue_info |= SQ_CTRL_QUEUE_INFO_SET(1U, UC);
440 if (!SQ_CTRL_QUEUE_INFO_GET(ctrl->queue_info, MSS)) {
442 SQ_CTRL_QUEUE_INFO_SET(TX_MSS_DEFAULT, MSS);
443 } else if (SQ_CTRL_QUEUE_INFO_GET(ctrl->queue_info, MSS) < TX_MSS_MIN) {
444 /* mss should not be less than 80 */
446 SQ_CTRL_QUEUE_INFO_CLEAR(ctrl->queue_info, MSS);
447 ctrl->queue_info |= SQ_CTRL_QUEUE_INFO_SET(TX_MSS_MIN, MSS);
451 static inline bool hinic_is_tso_sge_valid(struct rte_mbuf *mbuf,
452 struct hinic_tx_offload_info
454 struct hinic_wqe_info *sqe_info)
456 u32 total_len, limit_len, checked_len, left_len;
457 u32 i, first_mss_sges, left_sges;
458 struct rte_mbuf *mbuf_head, *mbuf_pre;
460 left_sges = mbuf->nb_segs;
463 /* tso sge number validation */
464 if (unlikely(left_sges >= HINIC_NONTSO_PKT_MAX_SGE)) {
466 limit_len = mbuf->tso_segsz + poff_info->payload_offset;
467 first_mss_sges = HINIC_NONTSO_PKT_MAX_SGE;
469 /* each continues 17 mbufs segmust do one check */
470 while (left_sges >= HINIC_NONTSO_PKT_MAX_SGE) {
471 /* total len of first 16 mbufs must equal
472 * or more than limit_len
475 for (i = 0; i < first_mss_sges; i++) {
476 total_len += mbuf->data_len;
479 if (total_len >= limit_len) {
480 limit_len = mbuf_head->tso_segsz;
485 checked_len += total_len;
487 /* try to copy if not valid */
488 if (unlikely(first_mss_sges == i)) {
489 left_sges -= first_mss_sges;
490 checked_len -= mbuf_pre->data_len;
492 left_len = mbuf_head->pkt_len - checked_len;
493 if (left_len > HINIC_COPY_MBUF_SIZE)
496 sqe_info->sge_cnt = mbuf_head->nb_segs -
498 sqe_info->cpy_mbuf_cnt = 1;
502 first_mss_sges = (HINIC_NONTSO_PKT_MAX_SGE - 1);
504 /* continue next 16 mbufs */
505 left_sges -= (i + 1);
509 sqe_info->sge_cnt = mbuf_head->nb_segs;
514 hinic_set_l4_csum_info(struct hinic_sq_task *task,
515 u32 *queue_info, struct hinic_tx_offload_info *poff_info)
517 u32 tcp_udp_cs, sctp = 0;
520 if (unlikely(poff_info->inner_l4_type == SCTP_OFFLOAD_ENABLE))
523 tcp_udp_cs = poff_info->inner_l4_tcp_udp;
525 if (poff_info->tunnel_type == TUNNEL_UDP_CSUM ||
526 poff_info->tunnel_type == TUNNEL_UDP_NO_CSUM) {
527 l2hdr_len = poff_info->outer_l2_len;
530 SQ_TASK_INFO2_SET(poff_info->outer_l3_type, OUTER_L3TYPE) |
531 SQ_TASK_INFO2_SET(poff_info->outer_l3_len, OUTER_L3LEN);
533 SQ_TASK_INFO2_SET(poff_info->tunnel_type, TUNNEL_L4TYPE) |
534 SQ_TASK_INFO2_SET(poff_info->tunnel_length, TUNNEL_L4LEN);
536 l2hdr_len = poff_info->inner_l2_len;
539 task->pkt_info0 |= SQ_TASK_INFO0_SET(l2hdr_len, L2HDR_LEN);
541 SQ_TASK_INFO1_SET(poff_info->inner_l3_len, INNER_L3LEN);
543 SQ_TASK_INFO0_SET(poff_info->inner_l3_type, INNER_L3TYPE);
545 SQ_TASK_INFO1_SET(poff_info->inner_l4_len, INNER_L4LEN);
547 SQ_TASK_INFO0_SET(poff_info->inner_l4_type, L4OFFLOAD);
549 SQ_CTRL_QUEUE_INFO_SET(poff_info->payload_offset, PLDOFF) |
550 SQ_CTRL_QUEUE_INFO_SET(tcp_udp_cs, TCPUDP_CS) |
551 SQ_CTRL_QUEUE_INFO_SET(sctp, SCTP);
555 hinic_set_tso_info(struct hinic_sq_task *task,
556 u32 *queue_info, struct rte_mbuf *mbuf,
557 struct hinic_tx_offload_info *poff_info)
559 hinic_set_l4_csum_info(task, queue_info, poff_info);
563 SQ_TASK_INFO0_SET(poff_info->inner_l3_type, INNER_L3TYPE);
564 task->pkt_info0 |= SQ_TASK_INFO0_SET(TSO_ENABLE, TSO_UFO);
565 *queue_info |= SQ_CTRL_QUEUE_INFO_SET(TSO_ENABLE, TSO);
566 /* qsf was initialized in prepare_sq_wqe */
567 *queue_info = SQ_CTRL_QUEUE_INFO_CLEAR(*queue_info, MSS);
568 *queue_info |= SQ_CTRL_QUEUE_INFO_SET(mbuf->tso_segsz, MSS);
572 hinic_set_vlan_tx_offload(struct hinic_sq_task *task,
573 u32 *queue_info, u16 vlan_tag, u16 vlan_pri)
575 task->pkt_info0 |= SQ_TASK_INFO0_SET(vlan_tag, VLAN_TAG) |
576 SQ_TASK_INFO0_SET(1U, VLAN_OFFLOAD);
578 *queue_info |= SQ_CTRL_QUEUE_INFO_SET(vlan_pri, PRI);
582 hinic_fill_tx_offload_info(struct rte_mbuf *mbuf,
583 struct hinic_sq_task *task, u32 *queue_info,
584 struct hinic_tx_offload_info *tx_off_info)
587 uint64_t ol_flags = mbuf->ol_flags;
589 /* clear DW0~2 of task section for offload */
595 if (unlikely(ol_flags & PKT_TX_VLAN_PKT)) {
596 vlan_tag = mbuf->vlan_tci;
597 hinic_set_vlan_tx_offload(task, queue_info, vlan_tag,
598 vlan_tag >> VLAN_PRIO_SHIFT);
601 /* non checksum or tso */
602 if (unlikely(!(ol_flags & HINIC_TX_CKSUM_OFFLOAD_MASK)))
605 if ((ol_flags & PKT_TX_TCP_SEG))
606 /* set tso info for task and qsf */
607 hinic_set_tso_info(task, queue_info, mbuf, tx_off_info);
608 else /* just support l4 checksum offload */
609 hinic_set_l4_csum_info(task, queue_info, tx_off_info);
612 static inline void hinic_xmit_mbuf_cleanup(struct hinic_txq *txq)
614 struct hinic_tx_info *tx_info;
615 struct rte_mbuf *mbuf, *m, *mbuf_free[HINIC_MAX_TX_FREE_BULK];
617 u16 hw_ci, sw_ci, sq_mask;
620 hw_ci = HINIC_GET_SQ_HW_CI(txq);
621 sw_ci = HINIC_GET_SQ_LOCAL_CI(txq);
622 sq_mask = HINIC_GET_SQ_WQE_MASK(txq);
624 for (i = 0; i < txq->tx_free_thresh; ++i) {
625 tx_info = &txq->tx_info[sw_ci];
626 if (hw_ci == sw_ci ||
627 (((hw_ci - sw_ci) & sq_mask) < tx_info->wqebb_cnt))
630 sw_ci = (sw_ci + tx_info->wqebb_cnt) & sq_mask;
632 if (unlikely(tx_info->cpy_mbuf != NULL)) {
633 rte_pktmbuf_free(tx_info->cpy_mbuf);
634 tx_info->cpy_mbuf = NULL;
637 wqebb_cnt += tx_info->wqebb_cnt;
638 mbuf = tx_info->mbuf;
640 if (likely(mbuf->nb_segs == 1)) {
641 m = rte_pktmbuf_prefree_seg(mbuf);
642 tx_info->mbuf = NULL;
644 if (unlikely(m == NULL))
647 mbuf_free[nb_free++] = m;
648 if (unlikely(m->pool != mbuf_free[0]->pool ||
649 nb_free >= HINIC_MAX_TX_FREE_BULK)) {
650 rte_mempool_put_bulk(mbuf_free[0]->pool,
651 (void **)mbuf_free, (nb_free - 1));
653 mbuf_free[nb_free++] = m;
656 rte_pktmbuf_free(mbuf);
657 tx_info->mbuf = NULL;
662 rte_mempool_put_bulk(mbuf_free[0]->pool, (void **)mbuf_free,
665 HINIC_UPDATE_SQ_LOCAL_CI(txq, wqebb_cnt);
668 static inline struct hinic_sq_wqe *
669 hinic_get_sq_wqe(struct hinic_txq *txq, int wqebb_cnt,
670 struct hinic_wqe_info *wqe_info)
674 struct hinic_sq *sq = txq->sq;
675 struct hinic_wq *wq = txq->wq;
677 /* record current pi */
678 cur_pi = MASKED_WQE_IDX(wq, wq->prod_idx);
679 end_pi = cur_pi + wqebb_cnt;
681 /* update next pi and delta */
682 wq->prod_idx += wqebb_cnt;
683 wq->delta -= wqebb_cnt;
685 /* return current pi and owner */
686 wqe_info->pi = cur_pi;
687 wqe_info->owner = sq->owner;
688 wqe_info->around = 0;
689 wqe_info->seq_wqebbs = wqebb_cnt;
691 if (unlikely(end_pi >= txq->q_depth)) {
692 /* update owner of next prod_idx */
693 sq->owner = !sq->owner;
695 /* turn around to head */
696 if (unlikely(end_pi > txq->q_depth)) {
697 wqe_info->around = 1;
698 remain_wqebbs = txq->q_depth - cur_pi;
699 wqe_info->seq_wqebbs = remain_wqebbs;
703 return (struct hinic_sq_wqe *)WQ_WQE_ADDR(wq, cur_pi);
706 static inline uint16_t
707 hinic_ipv4_phdr_cksum(const struct rte_ipv4_hdr *ipv4_hdr, uint64_t ol_flags)
709 struct ipv4_psd_header {
710 uint32_t src_addr; /* IP address of source host. */
711 uint32_t dst_addr; /* IP address of destination host. */
712 uint8_t zero; /* zero. */
713 uint8_t proto; /* L4 protocol type. */
714 uint16_t len; /* L4 length. */
718 psd_hdr.src_addr = ipv4_hdr->src_addr;
719 psd_hdr.dst_addr = ipv4_hdr->dst_addr;
721 psd_hdr.proto = ipv4_hdr->next_proto_id;
722 if (ol_flags & PKT_TX_TCP_SEG) {
725 /* ipv4_hdr->version_ihl is uint8_t big endian, ihl locates
726 * lower 4 bits and unit is 4 bytes
728 ihl = (ipv4_hdr->version_ihl & 0xF) << 2;
730 rte_cpu_to_be_16(rte_be_to_cpu_16(ipv4_hdr->total_length) -
733 return rte_raw_cksum(&psd_hdr, sizeof(psd_hdr));
736 static inline uint16_t
737 hinic_ipv6_phdr_cksum(const struct rte_ipv6_hdr *ipv6_hdr, uint64_t ol_flags)
741 uint32_t len; /* L4 length. */
742 uint32_t proto; /* L4 protocol - top 3 bytes must be zero */
745 psd_hdr.proto = (ipv6_hdr->proto << 24);
746 if (ol_flags & PKT_TX_TCP_SEG)
749 psd_hdr.len = ipv6_hdr->payload_len;
751 sum = __rte_raw_cksum(ipv6_hdr->src_addr,
752 sizeof(ipv6_hdr->src_addr) + sizeof(ipv6_hdr->dst_addr), 0);
753 sum = __rte_raw_cksum(&psd_hdr, sizeof(psd_hdr), sum);
754 return __rte_raw_cksum_reduce(sum);
758 hinic_get_pld_offset(struct rte_mbuf *m, struct hinic_tx_offload_info *off_info,
761 uint64_t ol_flags = m->ol_flags;
763 if (outer_cs_flag == 1) {
764 if ((ol_flags & PKT_TX_UDP_CKSUM) == PKT_TX_UDP_CKSUM) {
765 off_info->payload_offset = m->outer_l2_len +
766 m->outer_l3_len + m->l2_len + m->l3_len;
767 } else if ((ol_flags & PKT_TX_TCP_CKSUM) ||
768 (ol_flags & PKT_TX_TCP_SEG)) {
769 off_info->payload_offset = m->outer_l2_len +
770 m->outer_l3_len + m->l2_len +
771 m->l3_len + m->l4_len;
774 if ((ol_flags & PKT_TX_UDP_CKSUM) == PKT_TX_UDP_CKSUM) {
775 off_info->payload_offset = m->l2_len + m->l3_len;
776 } else if ((ol_flags & PKT_TX_TCP_CKSUM) ||
777 (ol_flags & PKT_TX_TCP_SEG)) {
778 off_info->payload_offset = m->l2_len + m->l3_len +
785 hinic_analyze_tx_info(struct rte_mbuf *mbuf,
786 struct hinic_tx_offload_info *off_info)
788 struct rte_ether_hdr *eth_hdr;
789 struct rte_vlan_hdr *vlan_hdr;
790 struct rte_ipv4_hdr *ip4h;
794 hdr = (u8 *)rte_pktmbuf_mtod(mbuf, u8*);
795 eth_hdr = (struct rte_ether_hdr *)hdr;
796 pkt_type = rte_be_to_cpu_16(eth_hdr->ether_type);
798 if (pkt_type == RTE_ETHER_TYPE_VLAN) {
799 off_info->outer_l2_len = ETHER_LEN_WITH_VLAN;
800 vlan_hdr = (struct rte_vlan_hdr *)(hdr + 1);
801 pkt_type = rte_be_to_cpu_16(vlan_hdr->eth_proto);
803 off_info->outer_l2_len = ETHER_LEN_NO_VLAN;
806 if (pkt_type == RTE_ETHER_TYPE_IPV4) {
807 ip4h = (struct rte_ipv4_hdr *)(hdr + off_info->outer_l2_len);
808 off_info->outer_l3_len = (ip4h->version_ihl & 0xf) <<
810 } else if (pkt_type == RTE_ETHER_TYPE_IPV6) {
811 /* not support ipv6 extension header */
812 off_info->outer_l3_len = sizeof(struct rte_ipv6_hdr);
817 hinic_tx_offload_pkt_prepare(struct rte_mbuf *m,
818 struct hinic_tx_offload_info *off_info)
820 struct rte_ipv4_hdr *ipv4_hdr;
821 struct rte_ipv6_hdr *ipv6_hdr;
822 struct rte_tcp_hdr *tcp_hdr;
823 struct rte_udp_hdr *udp_hdr;
824 struct rte_ether_hdr *eth_hdr;
825 struct rte_vlan_hdr *vlan_hdr;
827 uint64_t inner_l3_offset;
828 uint64_t ol_flags = m->ol_flags;
830 /* Check if the packets set available offload flags */
831 if (!(ol_flags & HINIC_TX_CKSUM_OFFLOAD_MASK))
834 /* Support only vxlan offload */
835 if ((ol_flags & PKT_TX_TUNNEL_MASK) &&
836 !(ol_flags & PKT_TX_TUNNEL_VXLAN))
839 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
840 if (rte_validate_tx_offload(m) != 0)
844 if (ol_flags & PKT_TX_TUNNEL_VXLAN) {
845 if ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
846 (ol_flags & PKT_TX_OUTER_IPV6) ||
847 (ol_flags & PKT_TX_TCP_SEG)) {
848 inner_l3_offset = m->l2_len + m->outer_l2_len +
850 off_info->outer_l2_len = m->outer_l2_len;
851 off_info->outer_l3_len = m->outer_l3_len;
852 /* just support vxlan tunneling pkt */
853 off_info->inner_l2_len = m->l2_len - VXLANLEN -
855 off_info->inner_l3_len = m->l3_len;
856 off_info->inner_l4_len = m->l4_len;
857 off_info->tunnel_length = m->l2_len;
858 off_info->tunnel_type = TUNNEL_UDP_NO_CSUM;
860 hinic_get_pld_offset(m, off_info,
861 HINIC_TX_OUTER_CHECKSUM_FLAG_SET);
863 inner_l3_offset = m->l2_len;
864 hinic_analyze_tx_info(m, off_info);
865 /* just support vxlan tunneling pkt */
866 off_info->inner_l2_len = m->l2_len - VXLANLEN -
867 sizeof(*udp_hdr) - off_info->outer_l2_len -
868 off_info->outer_l3_len;
869 off_info->inner_l3_len = m->l3_len;
870 off_info->inner_l4_len = m->l4_len;
871 off_info->tunnel_length = m->l2_len -
872 off_info->outer_l2_len - off_info->outer_l3_len;
873 off_info->tunnel_type = TUNNEL_UDP_NO_CSUM;
875 hinic_get_pld_offset(m, off_info,
876 HINIC_TX_OUTER_CHECKSUM_FLAG_NO_SET);
879 inner_l3_offset = m->l2_len;
880 off_info->inner_l2_len = m->l2_len;
881 off_info->inner_l3_len = m->l3_len;
882 off_info->inner_l4_len = m->l4_len;
883 off_info->tunnel_type = NOT_TUNNEL;
885 hinic_get_pld_offset(m, off_info,
886 HINIC_TX_OUTER_CHECKSUM_FLAG_NO_SET);
889 /* invalid udp or tcp header */
890 if (unlikely(off_info->payload_offset > MAX_PLD_OFFSET))
893 /* Process outter udp pseudo-header checksum */
894 if ((ol_flags & PKT_TX_TUNNEL_VXLAN) && ((ol_flags & PKT_TX_TCP_SEG) ||
895 (ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
896 (ol_flags & PKT_TX_OUTER_IPV6))) {
898 /* inner_l4_tcp_udp csum should be setted to calculate outter
899 * udp checksum when vxlan packets without inner l3 and l4
901 off_info->inner_l4_tcp_udp = 1;
903 eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
904 eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
906 if (eth_type == RTE_ETHER_TYPE_VLAN) {
907 vlan_hdr = (struct rte_vlan_hdr *)(eth_hdr + 1);
908 eth_type = rte_be_to_cpu_16(vlan_hdr->eth_proto);
911 if (eth_type == RTE_ETHER_TYPE_IPV4) {
913 rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
915 off_info->outer_l3_type = IPV4_PKT_WITH_CHKSUM_OFFLOAD;
916 ipv4_hdr->hdr_checksum = 0;
918 udp_hdr = (struct rte_udp_hdr *)((char *)ipv4_hdr +
920 udp_hdr->dgram_cksum = 0;
921 } else if (eth_type == RTE_ETHER_TYPE_IPV6) {
922 off_info->outer_l3_type = IPV6_PKT;
924 rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
928 rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
931 udp_hdr->dgram_cksum = 0;
933 } else if (ol_flags & PKT_TX_OUTER_IPV4) {
934 off_info->tunnel_type = TUNNEL_UDP_NO_CSUM;
935 off_info->inner_l4_tcp_udp = 1;
936 off_info->outer_l3_type = IPV4_PKT_NO_CHKSUM_OFFLOAD;
939 if (ol_flags & PKT_TX_IPV4)
940 off_info->inner_l3_type = (ol_flags & PKT_TX_IP_CKSUM) ?
941 IPV4_PKT_WITH_CHKSUM_OFFLOAD :
942 IPV4_PKT_NO_CHKSUM_OFFLOAD;
943 else if (ol_flags & PKT_TX_IPV6)
944 off_info->inner_l3_type = IPV6_PKT;
946 /* Process the pseudo-header checksum */
947 if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM) {
948 if (ol_flags & PKT_TX_IPV4) {
950 rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
953 if (ol_flags & PKT_TX_IP_CKSUM)
954 ipv4_hdr->hdr_checksum = 0;
956 udp_hdr = (struct rte_udp_hdr *)((char *)ipv4_hdr +
958 udp_hdr->dgram_cksum =
959 hinic_ipv4_phdr_cksum(ipv4_hdr, ol_flags);
962 rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
966 rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
967 (inner_l3_offset + m->l3_len));
968 udp_hdr->dgram_cksum =
969 hinic_ipv6_phdr_cksum(ipv6_hdr, ol_flags);
972 off_info->inner_l4_type = UDP_OFFLOAD_ENABLE;
973 off_info->inner_l4_tcp_udp = 1;
974 } else if (((ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) ||
975 (ol_flags & PKT_TX_TCP_SEG)) {
976 if (ol_flags & PKT_TX_IPV4) {
978 rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
981 if (ol_flags & PKT_TX_IP_CKSUM)
982 ipv4_hdr->hdr_checksum = 0;
985 tcp_hdr = (struct rte_tcp_hdr *)((char *)ipv4_hdr +
988 hinic_ipv4_phdr_cksum(ipv4_hdr, ol_flags);
991 rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
995 rte_pktmbuf_mtod_offset(m, struct rte_tcp_hdr *,
996 (inner_l3_offset + m->l3_len));
998 hinic_ipv6_phdr_cksum(ipv6_hdr, ol_flags);
1001 off_info->inner_l4_type = TCP_OFFLOAD_ENABLE;
1002 off_info->inner_l4_tcp_udp = 1;
1003 } else if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_SCTP_CKSUM) {
1004 off_info->inner_l4_type = SCTP_OFFLOAD_ENABLE;
1005 off_info->inner_l4_tcp_udp = 0;
1006 off_info->inner_l4_len = sizeof(struct rte_sctp_hdr);
1012 static inline bool hinic_get_sge_txoff_info(struct rte_mbuf *mbuf_pkt,
1013 struct hinic_wqe_info *sqe_info,
1014 struct hinic_tx_offload_info
1017 u16 i, total_len, sge_cnt = mbuf_pkt->nb_segs;
1018 struct rte_mbuf *mbuf;
1021 memset(off_info, 0, sizeof(*off_info));
1023 ret = hinic_tx_offload_pkt_prepare(mbuf_pkt, off_info);
1027 sqe_info->cpy_mbuf_cnt = 0;
1030 if (likely(!(mbuf_pkt->ol_flags & PKT_TX_TCP_SEG))) {
1031 if (unlikely(mbuf_pkt->pkt_len > MAX_SINGLE_SGE_SIZE)) {
1032 /* non tso packet len must less than 64KB */
1034 } else if (unlikely(HINIC_NONTSO_SEG_NUM_INVALID(sge_cnt))) {
1035 /* non tso packet buffer number must less than 17
1036 * the mbuf segs more than 17 must copy to one buffer
1040 for (i = 0; i < (HINIC_NONTSO_PKT_MAX_SGE - 1) ; i++) {
1041 total_len += mbuf->data_len;
1045 /* default support copy total 4k mbuf segs */
1046 if ((u32)(total_len + (u16)HINIC_COPY_MBUF_SIZE) <
1050 sqe_info->sge_cnt = HINIC_NONTSO_PKT_MAX_SGE;
1051 sqe_info->cpy_mbuf_cnt = 1;
1055 /* valid non tso mbuf */
1056 sqe_info->sge_cnt = sge_cnt;
1059 if (unlikely(HINIC_TSO_SEG_NUM_INVALID(sge_cnt)))
1060 /* too many mbuf segs */
1063 /* check tso mbuf segs are valid or not */
1064 if (unlikely(!hinic_is_tso_sge_valid(mbuf_pkt,
1065 off_info, sqe_info)))
1072 static inline void hinic_sq_write_db(struct hinic_sq *sq, int cos)
1076 struct hinic_sq_db sq_db;
1078 prod_idx = MASKED_SQ_IDX(sq, sq->wq->prod_idx);
1079 hi_prod_idx = SQ_DB_PI_HIGH(prod_idx);
1081 sq_db.db_info = SQ_DB_INFO_SET(hi_prod_idx, HI_PI) |
1082 SQ_DB_INFO_SET(SQ_DB, TYPE) |
1083 SQ_DB_INFO_SET(SQ_CFLAG_DP, CFLAG) |
1084 SQ_DB_INFO_SET(cos, COS) |
1085 SQ_DB_INFO_SET(sq->q_id, QID);
1087 /* Data should be written to HW in Big Endian Format */
1088 sq_db.db_info = cpu_to_be32(sq_db.db_info);
1090 /* Write all before the doorbell */
1092 writel(sq_db.db_info, SQ_DB_ADDR(sq, prod_idx));
1095 u16 hinic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, u16 nb_pkts)
1097 int free_wqebb_cnt, wqe_wqebb_cnt;
1098 u32 queue_info, tx_bytes = 0;
1100 struct hinic_wqe_info sqe_info;
1101 struct hinic_tx_offload_info off_info;
1102 struct rte_mbuf *mbuf_pkt;
1103 struct hinic_txq *txq = tx_queue;
1104 struct hinic_tx_info *tx_info;
1105 struct hinic_sq_wqe *sq_wqe;
1106 struct hinic_sq_task *task;
1108 /* reclaim tx mbuf before xmit new packet */
1109 if (HINIC_GET_SQ_FREE_WQEBBS(txq) < txq->tx_free_thresh)
1110 hinic_xmit_mbuf_cleanup(txq);
1112 /* tx loop routine */
1113 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1114 mbuf_pkt = *tx_pkts++;
1117 /* 1. parse sge and tx offlod info from mbuf */
1118 if (unlikely(!hinic_get_sge_txoff_info(mbuf_pkt,
1119 &sqe_info, &off_info))) {
1120 txq->txq_stats.off_errs++;
1124 /* 2. try to get enough wqebb */
1125 wqe_wqebb_cnt = HINIC_SQ_WQEBB_CNT(sqe_info.sge_cnt);
1126 free_wqebb_cnt = HINIC_GET_SQ_FREE_WQEBBS(txq);
1127 if (unlikely(wqe_wqebb_cnt > free_wqebb_cnt)) {
1129 hinic_xmit_mbuf_cleanup(txq);
1130 free_wqebb_cnt = HINIC_GET_SQ_FREE_WQEBBS(txq);
1131 if (unlikely(wqe_wqebb_cnt > free_wqebb_cnt)) {
1132 txq->txq_stats.tx_busy += (nb_pkts - nb_tx);
1137 /* 3. get sq tail wqe address from wqe_page,
1138 * sq have enough wqebb for this packet
1140 sq_wqe = hinic_get_sq_wqe(txq, wqe_wqebb_cnt, &sqe_info);
1142 /* 4. fill sq wqe sge section */
1143 if (unlikely(!hinic_mbuf_dma_map_sge(txq, mbuf_pkt,
1146 hinic_return_sq_wqe(txq->nic_dev->hwdev, txq->q_id,
1147 wqe_wqebb_cnt, sqe_info.owner);
1148 txq->txq_stats.off_errs++;
1152 /* 5. fill sq wqe task section and queue info */
1153 task = &sq_wqe->task;
1155 /* tx packet offload configure */
1156 hinic_fill_tx_offload_info(mbuf_pkt, task, &queue_info,
1159 /* 6. record tx info */
1160 tx_info = &txq->tx_info[sqe_info.pi];
1161 tx_info->mbuf = mbuf_pkt;
1162 tx_info->wqebb_cnt = wqe_wqebb_cnt;
1164 /* 7. fill sq wqe header section */
1165 hinic_fill_sq_wqe_header(&sq_wqe->ctrl, queue_info,
1166 sqe_info.sge_cnt, sqe_info.owner);
1168 /* 8.convert continue or bottom wqe byteorder to big endian */
1169 hinic_sq_wqe_cpu_to_be32(sq_wqe, sqe_info.seq_wqebbs);
1171 tx_bytes += mbuf_pkt->pkt_len;
1174 /* 9. write sq doorbell in burst mode */
1176 hinic_sq_write_db(txq->sq, txq->cos);
1178 txq->txq_stats.packets += nb_tx;
1179 txq->txq_stats.bytes += tx_bytes;
1181 txq->txq_stats.burst_pkts = nb_tx;
1186 void hinic_free_all_tx_mbufs(struct hinic_txq *txq)
1189 struct hinic_nic_dev *nic_dev = txq->nic_dev;
1190 struct hinic_tx_info *tx_info;
1191 int free_wqebbs = hinic_get_sq_free_wqebbs(nic_dev->hwdev,
1194 while (free_wqebbs < txq->q_depth) {
1195 ci = hinic_get_sq_local_ci(nic_dev->hwdev, txq->q_id);
1197 tx_info = &txq->tx_info[ci];
1199 if (unlikely(tx_info->cpy_mbuf != NULL)) {
1200 rte_pktmbuf_free(tx_info->cpy_mbuf);
1201 tx_info->cpy_mbuf = NULL;
1204 rte_pktmbuf_free(tx_info->mbuf);
1205 hinic_update_sq_local_ci(nic_dev->hwdev, txq->q_id,
1206 tx_info->wqebb_cnt);
1208 free_wqebbs += tx_info->wqebb_cnt;
1209 tx_info->mbuf = NULL;
1213 void hinic_free_all_tx_resources(struct rte_eth_dev *eth_dev)
1216 struct hinic_nic_dev *nic_dev =
1217 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1219 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) {
1220 eth_dev->data->tx_queues[q_id] = NULL;
1222 if (nic_dev->txqs[q_id] == NULL)
1225 /* stop tx queue free tx mbuf */
1226 hinic_free_all_tx_mbufs(nic_dev->txqs[q_id]);
1227 hinic_free_tx_resources(nic_dev->txqs[q_id]);
1230 kfree(nic_dev->txqs[q_id]);
1231 nic_dev->txqs[q_id] = NULL;
1235 void hinic_free_all_tx_mbuf(struct rte_eth_dev *eth_dev)
1238 struct hinic_nic_dev *nic_dev =
1239 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1241 for (q_id = 0; q_id < nic_dev->num_sq; q_id++)
1242 /* stop tx queue free tx mbuf */
1243 hinic_free_all_tx_mbufs(nic_dev->txqs[q_id]);
1246 int hinic_setup_tx_resources(struct hinic_txq *txq)
1250 tx_info_sz = txq->q_depth * sizeof(*txq->tx_info);
1251 txq->tx_info = rte_zmalloc_socket("tx_info", tx_info_sz,
1252 RTE_CACHE_LINE_SIZE, txq->socket_id);
1259 void hinic_free_tx_resources(struct hinic_txq *txq)
1261 if (txq->tx_info == NULL)
1264 rte_free(txq->tx_info);
1265 txq->tx_info = NULL;
1268 int hinic_create_sq(struct hinic_hwdev *hwdev, u16 q_id,
1269 u16 sq_depth, unsigned int socket_id)
1272 struct hinic_nic_io *nic_io = hwdev->nic_io;
1273 struct hinic_qp *qp = &nic_io->qps[q_id];
1274 struct hinic_sq *sq = &qp->sq;
1275 void __iomem *db_addr;
1276 volatile u32 *ci_addr;
1278 sq->sq_depth = sq_depth;
1279 nic_io->sq_depth = sq_depth;
1282 err = hinic_wq_allocate(nic_io->hwdev, &nic_io->sq_wq[q_id],
1283 HINIC_SQ_WQEBB_SHIFT, nic_io->sq_depth,
1286 PMD_DRV_LOG(ERR, "Failed to allocate WQ for SQ");
1290 /* alloc sq doorbell space */
1291 err = hinic_alloc_db_addr(nic_io->hwdev, &db_addr);
1293 PMD_DRV_LOG(ERR, "Failed to init db addr");
1297 /* clear hardware ci */
1298 ci_addr = (volatile u32 *)HINIC_CI_VADDR(nic_io->ci_vaddr_base, q_id);
1302 sq->wq = &nic_io->sq_wq[q_id];
1304 sq->cons_idx_addr = (volatile u16 *)ci_addr;
1305 sq->db_addr = db_addr;
1310 hinic_wq_free(nic_io->hwdev, &nic_io->sq_wq[q_id]);
1315 void hinic_destroy_sq(struct hinic_hwdev *hwdev, u16 q_id)
1317 struct hinic_nic_io *nic_io;
1318 struct hinic_qp *qp;
1320 nic_io = hwdev->nic_io;
1321 qp = &nic_io->qps[q_id];
1323 if (qp->sq.wq == NULL)
1326 hinic_free_db_addr(nic_io->hwdev, qp->sq.db_addr);
1327 hinic_wq_free(nic_io->hwdev, qp->sq.wq);