drivers/net/hinic/hinic_pmd_tx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   3  */
   4
   5 #include <rte_mbuf.h>
   6 #include <rte_tcp.h>
   7 #include <rte_sctp.h>
   8 #include <rte_udp.h>
   9 #include <rte_ip.h>
  10 #ifdef __ARM64_NEON__
  11 #include <arm_neon.h>
  12 #endif
  13
  14 #include "base/hinic_compat.h"
  15 #include "base/hinic_pmd_hwdev.h"
  16 #include "base/hinic_pmd_hwif.h"
  17 #include "base/hinic_pmd_wq.h"
  18 #include "base/hinic_pmd_nicio.h"
  19 #include "base/hinic_pmd_niccfg.h"
  20 #include "hinic_pmd_ethdev.h"
  21 #include "hinic_pmd_tx.h"
  22
  23 /* packet header and tx offload info */
  24 #define ETHER_LEN_NO_VLAN               14
  25 #define ETHER_LEN_WITH_VLAN             18
  26 #define HEADER_LEN_OFFSET               2
  27 #define VXLANLEN                        8
  28 #define MAX_PLD_OFFSET                  221
  29 #define MAX_SINGLE_SGE_SIZE             65536
  30 #define TSO_ENABLE                      1
  31 #define TX_MSS_DEFAULT                  0x3E00
  32 #define TX_MSS_MIN                      0x50
  33
  34 #define HINIC_NONTSO_PKT_MAX_SGE                17      /* non-tso max sge 17 */
  35 #define HINIC_NONTSO_SEG_NUM_INVALID(num)       \
  36                         ((num) > HINIC_NONTSO_PKT_MAX_SGE)
  37
  38 #define HINIC_TSO_PKT_MAX_SGE                   127     /* tso max sge 127 */
  39 #define HINIC_TSO_SEG_NUM_INVALID(num)          ((num) > HINIC_TSO_PKT_MAX_SGE)
  40
  41 #define HINIC_TX_OUTER_CHECKSUM_FLAG_SET       1
  42 #define HINIC_TX_OUTER_CHECKSUM_FLAG_NO_SET    0
  43
  44 /* sizeof(struct hinic_sq_bufdesc) == 16, shift 4 */
  45 #define HINIC_BUF_DESC_SIZE(nr_descs)   (SIZE_8BYTES(((u32)nr_descs) << 4))
  46
  47 #define MASKED_SQ_IDX(sq, idx)          ((idx) & (sq)->wq->mask)
  48
  49 /* SQ_CTRL */
  50 #define SQ_CTRL_BUFDESC_SECT_LEN_SHIFT          0
  51 #define SQ_CTRL_TASKSECT_LEN_SHIFT              16
  52 #define SQ_CTRL_DATA_FORMAT_SHIFT               22
  53 #define SQ_CTRL_LEN_SHIFT                       29
  54 #define SQ_CTRL_OWNER_SHIFT                     31
  55
  56 #define SQ_CTRL_BUFDESC_SECT_LEN_MASK           0xFFU
  57 #define SQ_CTRL_TASKSECT_LEN_MASK               0x1FU
  58 #define SQ_CTRL_DATA_FORMAT_MASK                0x1U
  59 #define SQ_CTRL_LEN_MASK                        0x3U
  60 #define SQ_CTRL_OWNER_MASK                      0x1U
  61
  62 #define SQ_CTRL_SET(val, member)        \
  63         (((val) & SQ_CTRL_##member##_MASK) << SQ_CTRL_##member##_SHIFT)
  64
  65 #define SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT         2
  66 #define SQ_CTRL_QUEUE_INFO_UFO_SHIFT            10
  67 #define SQ_CTRL_QUEUE_INFO_TSO_SHIFT            11
  68 #define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT      12
  69 #define SQ_CTRL_QUEUE_INFO_MSS_SHIFT            13
  70 #define SQ_CTRL_QUEUE_INFO_SCTP_SHIFT           27
  71 #define SQ_CTRL_QUEUE_INFO_UC_SHIFT             28
  72 #define SQ_CTRL_QUEUE_INFO_PRI_SHIFT            29
  73
  74 #define SQ_CTRL_QUEUE_INFO_PLDOFF_MASK          0xFFU
  75 #define SQ_CTRL_QUEUE_INFO_UFO_MASK             0x1U
  76 #define SQ_CTRL_QUEUE_INFO_TSO_MASK             0x1U
  77 #define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK       0x1U
  78 #define SQ_CTRL_QUEUE_INFO_MSS_MASK             0x3FFFU
  79 #define SQ_CTRL_QUEUE_INFO_SCTP_MASK            0x1U
  80 #define SQ_CTRL_QUEUE_INFO_UC_MASK              0x1U
  81 #define SQ_CTRL_QUEUE_INFO_PRI_MASK             0x7U
  82
  83 #define SQ_CTRL_QUEUE_INFO_SET(val, member)     \
  84         (((u32)(val) & SQ_CTRL_QUEUE_INFO_##member##_MASK) <<   \
  85                         SQ_CTRL_QUEUE_INFO_##member##_SHIFT)
  86
  87 #define SQ_CTRL_QUEUE_INFO_GET(val, member)     \
  88         (((val) >> SQ_CTRL_QUEUE_INFO_##member##_SHIFT) &       \
  89                         SQ_CTRL_QUEUE_INFO_##member##_MASK)
  90
  91 #define SQ_CTRL_QUEUE_INFO_CLEAR(val, member)   \
  92         ((val) & (~(SQ_CTRL_QUEUE_INFO_##member##_MASK << \
  93                         SQ_CTRL_QUEUE_INFO_##member##_SHIFT)))
  94
  95 #define SQ_TASK_INFO0_L2HDR_LEN_SHIFT           0
  96 #define SQ_TASK_INFO0_L4OFFLOAD_SHIFT           8
  97 #define SQ_TASK_INFO0_INNER_L3TYPE_SHIFT        10
  98 #define SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT        12
  99 #define SQ_TASK_INFO0_PARSE_FLAG_SHIFT          13
 100 #define SQ_TASK_INFO0_UFO_AVD_SHIFT             14
 101 #define SQ_TASK_INFO0_TSO_UFO_SHIFT             15
 102 #define SQ_TASK_INFO0_VLAN_TAG_SHIFT            16
 103
 104 #define SQ_TASK_INFO0_L2HDR_LEN_MASK            0xFFU
 105 #define SQ_TASK_INFO0_L4OFFLOAD_MASK            0x3U
 106 #define SQ_TASK_INFO0_INNER_L3TYPE_MASK         0x3U
 107 #define SQ_TASK_INFO0_VLAN_OFFLOAD_MASK         0x1U
 108 #define SQ_TASK_INFO0_PARSE_FLAG_MASK           0x1U
 109 #define SQ_TASK_INFO0_UFO_AVD_MASK              0x1U
 110 #define SQ_TASK_INFO0_TSO_UFO_MASK              0x1U
 111 #define SQ_TASK_INFO0_VLAN_TAG_MASK             0xFFFFU
 112
 113 #define SQ_TASK_INFO0_SET(val, member)                  \
 114         (((u32)(val) & SQ_TASK_INFO0_##member##_MASK) <<        \
 115                         SQ_TASK_INFO0_##member##_SHIFT)
 116
 117 #define SQ_TASK_INFO1_MD_TYPE_SHIFT             8
 118 #define SQ_TASK_INFO1_INNER_L4LEN_SHIFT         16
 119 #define SQ_TASK_INFO1_INNER_L3LEN_SHIFT         24
 120
 121 #define SQ_TASK_INFO1_MD_TYPE_MASK              0xFFU
 122 #define SQ_TASK_INFO1_INNER_L4LEN_MASK          0xFFU
 123 #define SQ_TASK_INFO1_INNER_L3LEN_MASK          0xFFU
 124
 125 #define SQ_TASK_INFO1_SET(val, member)                  \
 126         (((val) & SQ_TASK_INFO1_##member##_MASK) <<     \
 127                         SQ_TASK_INFO1_##member##_SHIFT)
 128
 129 #define SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT        0
 130 #define SQ_TASK_INFO2_OUTER_L3LEN_SHIFT         8
 131 #define SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT       16
 132 #define SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT        24
 133
 134 #define SQ_TASK_INFO2_TUNNEL_L4LEN_MASK         0xFFU
 135 #define SQ_TASK_INFO2_OUTER_L3LEN_MASK          0xFFU
 136 #define SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK        0x7U
 137 #define SQ_TASK_INFO2_OUTER_L3TYPE_MASK         0x3U
 138
 139 #define SQ_TASK_INFO2_SET(val, member)                  \
 140         (((val) & SQ_TASK_INFO2_##member##_MASK) <<     \
 141                         SQ_TASK_INFO2_##member##_SHIFT)
 142
 143 #define SQ_TASK_INFO4_L2TYPE_SHIFT              31
 144
 145 #define SQ_TASK_INFO4_L2TYPE_MASK               0x1U
 146
 147 #define SQ_TASK_INFO4_SET(val, member)          \
 148         (((u32)(val) & SQ_TASK_INFO4_##member##_MASK) << \
 149                         SQ_TASK_INFO4_##member##_SHIFT)
 150
 151 /* SQ_DB */
 152 #define SQ_DB_OFF                               0x00000800
 153 #define SQ_DB_INFO_HI_PI_SHIFT                  0
 154 #define SQ_DB_INFO_QID_SHIFT                    8
 155 #define SQ_DB_INFO_CFLAG_SHIFT                  23
 156 #define SQ_DB_INFO_COS_SHIFT                    24
 157 #define SQ_DB_INFO_TYPE_SHIFT                   27
 158
 159 #define SQ_DB_INFO_HI_PI_MASK                   0xFFU
 160 #define SQ_DB_INFO_QID_MASK                     0x3FFU
 161 #define SQ_DB_INFO_CFLAG_MASK                   0x1U
 162 #define SQ_DB_INFO_COS_MASK                     0x7U
 163 #define SQ_DB_INFO_TYPE_MASK                    0x1FU
 164 #define SQ_DB_INFO_SET(val, member)             \
 165         (((u32)(val) & SQ_DB_INFO_##member##_MASK) <<   \
 166                         SQ_DB_INFO_##member##_SHIFT)
 167
 168 #define SQ_DB                                   1
 169 #define SQ_CFLAG_DP                             0       /* CFLAG_DATA_PATH */
 170
 171 #define SQ_DB_PI_LOW_MASK                       0xFF
 172 #define SQ_DB_PI_LOW(pi)                        ((pi) & SQ_DB_PI_LOW_MASK)
 173 #define SQ_DB_PI_HI_SHIFT                       8
 174 #define SQ_DB_PI_HIGH(pi)                       ((pi) >> SQ_DB_PI_HI_SHIFT)
 175 #define SQ_DB_ADDR(sq, pi)              \
 176         ((u64 *)((u8 __iomem *)((sq)->db_addr) + SQ_DB_OFF) + SQ_DB_PI_LOW(pi))
 177
 178 /* txq wq operations */
 179 #define HINIC_GET_SQ_WQE_MASK(txq)              ((txq)->wq->mask)
 180
 181 #define HINIC_GET_SQ_HW_CI(txq) \
 182         ((be16_to_cpu(*(txq)->cons_idx_addr)) & HINIC_GET_SQ_WQE_MASK(txq))
 183
 184 #define HINIC_GET_SQ_LOCAL_CI(txq)      \
 185         (((txq)->wq->cons_idx) & HINIC_GET_SQ_WQE_MASK(txq))
 186
 187 #define HINIC_UPDATE_SQ_LOCAL_CI(txq, wqebb_cnt)        \
 188         do {                                            \
 189                 (txq)->wq->cons_idx += wqebb_cnt;       \
 190                 (txq)->wq->delta += wqebb_cnt;          \
 191         } while (0)
 192
 193 #define HINIC_GET_SQ_FREE_WQEBBS(txq)   ((txq)->wq->delta - 1)
 194
 195 #define HINIC_IS_SQ_EMPTY(txq)  (((txq)->wq->delta) == ((txq)->q_depth))
 196
 197 #define BUF_DESC_SIZE_SHIFT             4
 198
 199 #define HINIC_SQ_WQE_SIZE(num_sge)              \
 200         (sizeof(struct hinic_sq_ctrl) + sizeof(struct hinic_sq_task) +  \
 201                         (unsigned int)((num_sge) << BUF_DESC_SIZE_SHIFT))
 202
 203 #define HINIC_SQ_WQEBB_CNT(num_sge)     \
 204         (int)(ALIGN(HINIC_SQ_WQE_SIZE((u32)num_sge), \
 205                         HINIC_SQ_WQEBB_SIZE) >> HINIC_SQ_WQEBB_SHIFT)
 206
 207
 208 static inline void hinic_sq_wqe_cpu_to_be32(void *data, int nr_wqebb)
 209 {
 210 #if defined(__X86_64_SSE__)
 211         int i;
 212         __m128i *wqe_line = (__m128i *)data;
 213         __m128i shuf_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10,
 214                                         11, 4, 5, 6, 7, 0, 1, 2, 3);
 215
 216         for (i = 0; i < nr_wqebb; i++) {
 217                 /* convert 64B wqebb using 4 SSE instructions */
 218                 wqe_line[0] = _mm_shuffle_epi8(wqe_line[0], shuf_mask);
 219                 wqe_line[1] = _mm_shuffle_epi8(wqe_line[1], shuf_mask);
 220                 wqe_line[2] = _mm_shuffle_epi8(wqe_line[2], shuf_mask);
 221                 wqe_line[3] = _mm_shuffle_epi8(wqe_line[3], shuf_mask);
 222                 wqe_line += 4;
 223         }
 224 #elif defined(__ARM64_NEON__)
 225         int i;
 226         uint8x16_t *wqe_line = (uint8x16_t *)data;
 227         const uint8x16_t shuf_mask = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10,
 228                                         9, 8, 15, 14, 13, 12};
 229
 230         for (i = 0; i < nr_wqebb; i++) {
 231                 wqe_line[0] = vqtbl1q_u8(wqe_line[0], shuf_mask);
 232                 wqe_line[1] = vqtbl1q_u8(wqe_line[1], shuf_mask);
 233                 wqe_line[2] = vqtbl1q_u8(wqe_line[2], shuf_mask);
 234                 wqe_line[3] = vqtbl1q_u8(wqe_line[3], shuf_mask);
 235                 wqe_line += 4;
 236         }
 237 #else
 238         hinic_cpu_to_be32(data, nr_wqebb * HINIC_SQ_WQEBB_SIZE);
 239 #endif
 240 }
 241
 242 static inline void hinic_sge_cpu_to_be32(void *data, int nr_sge)
 243 {
 244 #if defined(__X86_64_SSE__)
 245         int i;
 246         __m128i *sge_line = (__m128i *)data;
 247         __m128i shuf_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10,
 248                                         11, 4, 5, 6, 7, 0, 1, 2, 3);
 249
 250         for (i = 0; i < nr_sge; i++) {
 251                 /* convert 16B sge using 1 SSE instructions */
 252                 *sge_line = _mm_shuffle_epi8(*sge_line, shuf_mask);
 253                 sge_line++;
 254         }
 255 #elif defined(__ARM64_NEON__)
 256         int i;
 257         uint8x16_t *sge_line = (uint8x16_t *)data;
 258         const uint8x16_t shuf_mask = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10,
 259                                         9, 8, 15, 14, 13, 12};
 260
 261         for (i = 0; i < nr_sge; i++) {
 262                 *sge_line = vqtbl1q_u8(*sge_line, shuf_mask);
 263                 sge_line++;
 264         }
 265 #else
 266         hinic_cpu_to_be32(data, nr_sge * sizeof(struct hinic_sq_bufdesc));
 267 #endif
 268 }
 269
 270 void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats)
 271 {
 272         if (!txq || !stats) {
 273                 PMD_DRV_LOG(ERR, "Txq or stats is NULL");
 274                 return;
 275         }
 276
 277         memcpy(stats, &txq->txq_stats, sizeof(txq->txq_stats));
 278 }
 279
 280 void hinic_txq_stats_reset(struct hinic_txq *txq)
 281 {
 282         struct hinic_txq_stats *txq_stats;
 283
 284         if (txq == NULL)
 285                 return;
 286
 287         txq_stats = &txq->txq_stats;
 288         memset(txq_stats, 0, sizeof(*txq_stats));
 289 }
 290
 291 static inline struct rte_mbuf *hinic_copy_tx_mbuf(struct hinic_nic_dev *nic_dev,
 292                                                   struct rte_mbuf *mbuf,
 293                                                   u16 sge_cnt)
 294 {
 295         struct rte_mbuf *dst_mbuf;
 296         u32 offset = 0;
 297         u16 i;
 298
 299         if (unlikely(!nic_dev->cpy_mpool))
 300                 return NULL;
 301
 302         dst_mbuf = rte_pktmbuf_alloc(nic_dev->cpy_mpool);
 303         if (unlikely(!dst_mbuf))
 304                 return NULL;
 305
 306         dst_mbuf->data_off = 0;
 307         for (i = 0; i < sge_cnt; i++) {
 308                 rte_memcpy((char *)dst_mbuf->buf_addr + offset,
 309                            (char *)mbuf->buf_addr + mbuf->data_off,
 310                            mbuf->data_len);
 311                 dst_mbuf->data_len += mbuf->data_len;
 312                 offset += mbuf->data_len;
 313                 mbuf = mbuf->next;
 314         }
 315
 316         dst_mbuf->pkt_len = dst_mbuf->data_len;
 317
 318         return dst_mbuf;
 319 }
 320
 321 static inline bool hinic_mbuf_dma_map_sge(struct hinic_txq *txq,
 322                                           struct rte_mbuf *mbuf,
 323                                           struct hinic_sq_bufdesc *sges,
 324                                           struct hinic_wqe_info *sqe_info)
 325 {
 326         dma_addr_t dma_addr;
 327         u16 i, around_sges;
 328         u16 nb_segs = sqe_info->sge_cnt - sqe_info->cpy_mbuf_cnt;
 329         u16 real_nb_segs = mbuf->nb_segs;
 330         struct hinic_sq_bufdesc *sge_idx = sges;
 331
 332         if (unlikely(sqe_info->around)) {
 333                 /* parts of wqe is in sq bottom while parts
 334                  * of wqe is in sq head
 335                  */
 336                 i = 0;
 337                 for (sge_idx = sges; (u64)sge_idx <= txq->sq_bot_sge_addr;
 338                      sge_idx++) {
 339                         if (unlikely(mbuf == NULL)) {
 340                                 txq->txq_stats.mbuf_null++;
 341                                 return false;
 342                         }
 343
 344                         dma_addr = rte_mbuf_data_iova(mbuf);
 345                         if (unlikely(mbuf->data_len == 0)) {
 346                                 txq->txq_stats.sge_len0++;
 347                                 return false;
 348                         }
 349                         hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr,
 350                                       mbuf->data_len);
 351                         mbuf = mbuf->next;
 352                         i++;
 353                 }
 354
 355                 around_sges = nb_segs - i;
 356                 sge_idx = (struct hinic_sq_bufdesc *)
 357                                 ((void *)txq->sq_head_addr);
 358                 for (; i < nb_segs; i++) {
 359                         if (unlikely(mbuf == NULL)) {
 360                                 txq->txq_stats.mbuf_null++;
 361                                 return false;
 362                         }
 363
 364                         dma_addr = rte_mbuf_data_iova(mbuf);
 365                         if (unlikely(mbuf->data_len == 0)) {
 366                                 txq->txq_stats.sge_len0++;
 367                                 return false;
 368                         }
 369                         hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr,
 370                                       mbuf->data_len);
 371                         mbuf = mbuf->next;
 372                         sge_idx++;
 373                 }
 374
 375                 /* covert sges at head to big endian */
 376                 hinic_sge_cpu_to_be32((void *)txq->sq_head_addr, around_sges);
 377         } else {
 378                 /* wqe is in continuous space */
 379                 for (i = 0; i < nb_segs; i++) {
 380                         if (unlikely(mbuf == NULL)) {
 381                                 txq->txq_stats.mbuf_null++;
 382                                 return false;
 383                         }
 384
 385                         dma_addr = rte_mbuf_data_iova(mbuf);
 386                         if (unlikely(mbuf->data_len == 0)) {
 387                                 txq->txq_stats.sge_len0++;
 388                                 return false;
 389                         }
 390                         hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr,
 391                                       mbuf->data_len);
 392                         mbuf = mbuf->next;
 393                         sge_idx++;
 394                 }
 395         }
 396
 397         /* for now: support non-tso over 17 sge, copy the last 2 mbuf */
 398         if (unlikely(sqe_info->cpy_mbuf_cnt != 0)) {
 399                 /* copy invalid mbuf segs to a valid buffer, lost performance */
 400                 txq->txq_stats.cpy_pkts += 1;
 401                 mbuf = hinic_copy_tx_mbuf(txq->nic_dev, mbuf,
 402                                           real_nb_segs - nb_segs);
 403                 if (unlikely(!mbuf))
 404                         return false;
 405
 406                 txq->tx_info[sqe_info->pi].cpy_mbuf = mbuf;
 407
 408                 /* deal with the last mbuf */
 409                 dma_addr = rte_mbuf_data_iova(mbuf);
 410                 if (unlikely(mbuf->data_len == 0)) {
 411                         txq->txq_stats.sge_len0++;
 412                         return false;
 413                 }
 414                 hinic_set_sge((struct hinic_sge *)sge_idx, dma_addr,
 415                               mbuf->data_len);
 416                 if (unlikely(sqe_info->around))
 417                         hinic_sge_cpu_to_be32((void *)sge_idx, 1);
 418         }
 419
 420         return true;
 421 }
 422
 423 static inline void hinic_fill_sq_wqe_header(struct hinic_sq_ctrl *ctrl,
 424                                             u32 queue_info, int nr_descs,
 425                                             u8 owner)
 426 {
 427         u32 ctrl_size, task_size, bufdesc_size;
 428
 429         ctrl_size = SIZE_8BYTES(sizeof(struct hinic_sq_ctrl));
 430         task_size = SIZE_8BYTES(sizeof(struct hinic_sq_task));
 431         bufdesc_size = HINIC_BUF_DESC_SIZE(nr_descs);
 432
 433         ctrl->ctrl_fmt = SQ_CTRL_SET(bufdesc_size, BUFDESC_SECT_LEN) |
 434                         SQ_CTRL_SET(task_size, TASKSECT_LEN)    |
 435                         SQ_CTRL_SET(SQ_NORMAL_WQE, DATA_FORMAT) |
 436                         SQ_CTRL_SET(ctrl_size, LEN)             |
 437                         SQ_CTRL_SET(owner, OWNER);
 438
 439         ctrl->queue_info = queue_info;
 440         ctrl->queue_info |= SQ_CTRL_QUEUE_INFO_SET(1U, UC);
 441
 442         if (!SQ_CTRL_QUEUE_INFO_GET(ctrl->queue_info, MSS)) {
 443                 ctrl->queue_info |=
 444                         SQ_CTRL_QUEUE_INFO_SET(TX_MSS_DEFAULT, MSS);
 445         } else if (SQ_CTRL_QUEUE_INFO_GET(ctrl->queue_info, MSS) < TX_MSS_MIN) {
 446                 /* mss should not be less than 80 */
 447                 ctrl->queue_info =
 448                                 SQ_CTRL_QUEUE_INFO_CLEAR(ctrl->queue_info, MSS);
 449                 ctrl->queue_info |= SQ_CTRL_QUEUE_INFO_SET(TX_MSS_MIN, MSS);
 450         }
 451 }
 452
 453 static inline bool hinic_is_tso_sge_valid(struct rte_mbuf *mbuf,
 454                                           struct hinic_tx_offload_info
 455                                           *poff_info,
 456                                           struct hinic_wqe_info *sqe_info)
 457 {
 458         u32 total_len, limit_len, checked_len, left_len;
 459         u32 i, first_mss_sges, left_sges;
 460         struct rte_mbuf *mbuf_head, *mbuf_pre;
 461
 462         left_sges = mbuf->nb_segs;
 463         mbuf_head = mbuf;
 464
 465         /* tso sge number validation */
 466         if (unlikely(left_sges >= HINIC_NONTSO_PKT_MAX_SGE)) {
 467                 checked_len = 0;
 468                 limit_len = mbuf->tso_segsz + poff_info->payload_offset;
 469                 first_mss_sges = HINIC_NONTSO_PKT_MAX_SGE;
 470
 471                 /* each continues 17 mbufs segmust do one check */
 472                 while (left_sges >= HINIC_NONTSO_PKT_MAX_SGE) {
 473                         /* total len of first 16 mbufs must equal
 474                          * or more than limit_len
 475                          */
 476                         total_len = 0;
 477                         for (i = 0; i < first_mss_sges; i++) {
 478                                 total_len += mbuf->data_len;
 479                                 mbuf_pre = mbuf;
 480                                 mbuf = mbuf->next;
 481                                 if (total_len >= limit_len) {
 482                                         limit_len = mbuf_head->tso_segsz;
 483                                         break;
 484                                 }
 485                         }
 486
 487                         checked_len += total_len;
 488
 489                         /* try to copy if not valid */
 490                         if (unlikely(first_mss_sges == i)) {
 491                                 left_sges -= first_mss_sges;
 492                                 checked_len -= mbuf_pre->data_len;
 493
 494                                 left_len = mbuf_head->pkt_len - checked_len;
 495                                 if (left_len > HINIC_COPY_MBUF_SIZE)
 496                                         return false;
 497
 498                                 sqe_info->sge_cnt = mbuf_head->nb_segs -
 499                                                         left_sges;
 500                                 sqe_info->cpy_mbuf_cnt = 1;
 501
 502                                 return true;
 503                         }
 504                         first_mss_sges = (HINIC_NONTSO_PKT_MAX_SGE - 1);
 505
 506                         /* continue next 16 mbufs */
 507                         left_sges -= (i + 1);
 508                 } /* end of while */
 509         }
 510
 511         sqe_info->sge_cnt = mbuf_head->nb_segs;
 512         return true;
 513 }
 514
 515 static inline void
 516 hinic_set_l4_csum_info(struct hinic_sq_task *task,
 517                 u32 *queue_info, struct hinic_tx_offload_info *poff_info)
 518 {
 519         u32 tcp_udp_cs, sctp = 0;
 520         u16 l2hdr_len;
 521
 522         if (unlikely(poff_info->inner_l4_type == SCTP_OFFLOAD_ENABLE))
 523                 sctp = 1;
 524
 525         tcp_udp_cs = poff_info->inner_l4_tcp_udp;
 526
 527         if (poff_info->tunnel_type == TUNNEL_UDP_CSUM ||
 528             poff_info->tunnel_type == TUNNEL_UDP_NO_CSUM) {
 529                 l2hdr_len =  poff_info->outer_l2_len;
 530
 531                 task->pkt_info2 |=
 532                 SQ_TASK_INFO2_SET(poff_info->outer_l3_type, OUTER_L3TYPE) |
 533                 SQ_TASK_INFO2_SET(poff_info->outer_l3_len, OUTER_L3LEN);
 534                 task->pkt_info2 |=
 535                 SQ_TASK_INFO2_SET(poff_info->tunnel_type, TUNNEL_L4TYPE) |
 536                 SQ_TASK_INFO2_SET(poff_info->tunnel_length, TUNNEL_L4LEN);
 537         } else {
 538                 l2hdr_len = poff_info->inner_l2_len;
 539         }
 540
 541         task->pkt_info0 |= SQ_TASK_INFO0_SET(l2hdr_len, L2HDR_LEN);
 542         task->pkt_info1 |=
 543                 SQ_TASK_INFO1_SET(poff_info->inner_l3_len, INNER_L3LEN);
 544         task->pkt_info0 |=
 545                 SQ_TASK_INFO0_SET(poff_info->inner_l3_type, INNER_L3TYPE);
 546         task->pkt_info1 |=
 547                 SQ_TASK_INFO1_SET(poff_info->inner_l4_len, INNER_L4LEN);
 548         task->pkt_info0 |=
 549                 SQ_TASK_INFO0_SET(poff_info->inner_l4_type, L4OFFLOAD);
 550         *queue_info |=
 551                 SQ_CTRL_QUEUE_INFO_SET(poff_info->payload_offset, PLDOFF) |
 552                 SQ_CTRL_QUEUE_INFO_SET(tcp_udp_cs, TCPUDP_CS) |
 553                 SQ_CTRL_QUEUE_INFO_SET(sctp, SCTP);
 554 }
 555
 556 static inline void
 557 hinic_set_tso_info(struct hinic_sq_task *task,
 558                 u32 *queue_info, struct rte_mbuf *mbuf,
 559                 struct hinic_tx_offload_info *poff_info)
 560 {
 561         hinic_set_l4_csum_info(task, queue_info, poff_info);
 562
 563         /* wqe for tso */
 564         task->pkt_info0 |=
 565                 SQ_TASK_INFO0_SET(poff_info->inner_l3_type, INNER_L3TYPE);
 566         task->pkt_info0 |= SQ_TASK_INFO0_SET(TSO_ENABLE, TSO_UFO);
 567         *queue_info |= SQ_CTRL_QUEUE_INFO_SET(TSO_ENABLE, TSO);
 568         /* qsf was initialized in prepare_sq_wqe */
 569         *queue_info = SQ_CTRL_QUEUE_INFO_CLEAR(*queue_info, MSS);
 570         *queue_info |= SQ_CTRL_QUEUE_INFO_SET(mbuf->tso_segsz, MSS);
 571 }
 572
 573 static inline void
 574 hinic_set_vlan_tx_offload(struct hinic_sq_task *task,
 575                         u32 *queue_info, u16 vlan_tag, u16 vlan_pri)
 576 {
 577         task->pkt_info0 |= SQ_TASK_INFO0_SET(vlan_tag, VLAN_TAG) |
 578                                 SQ_TASK_INFO0_SET(1U, VLAN_OFFLOAD);
 579
 580         *queue_info |= SQ_CTRL_QUEUE_INFO_SET(vlan_pri, PRI);
 581 }
 582
 583 static inline void
 584 hinic_fill_tx_offload_info(struct rte_mbuf *mbuf,
 585                 struct hinic_sq_task *task, u32 *queue_info,
 586                 struct hinic_tx_offload_info *tx_off_info)
 587 {
 588         u16 vlan_tag;
 589         uint64_t ol_flags = mbuf->ol_flags;
 590
 591         /* clear DW0~2 of task section for offload */
 592         task->pkt_info0 = 0;
 593         task->pkt_info1 = 0;
 594         task->pkt_info2 = 0;
 595
 596         /* Base VLAN */
 597         if (unlikely(ol_flags & PKT_TX_VLAN_PKT)) {
 598                 vlan_tag = mbuf->vlan_tci;
 599                 hinic_set_vlan_tx_offload(task, queue_info, vlan_tag,
 600                                           vlan_tag >> VLAN_PRIO_SHIFT);
 601         }
 602
 603         /* non checksum or tso */
 604         if (unlikely(!(ol_flags & HINIC_TX_CKSUM_OFFLOAD_MASK)))
 605                 return;
 606
 607         if ((ol_flags & PKT_TX_TCP_SEG))
 608                 /* set tso info for task and qsf */
 609                 hinic_set_tso_info(task, queue_info, mbuf, tx_off_info);
 610         else /* just support l4 checksum offload */
 611                 hinic_set_l4_csum_info(task, queue_info, tx_off_info);
 612 }
 613
 614 static inline void hinic_xmit_mbuf_cleanup(struct hinic_txq *txq)
 615 {
 616         struct hinic_tx_info *tx_info;
 617         struct rte_mbuf *mbuf, *m, *mbuf_free[HINIC_MAX_TX_FREE_BULK];
 618         int i, nb_free = 0;
 619         u16 hw_ci, sw_ci, sq_mask;
 620         int wqebb_cnt = 0;
 621
 622         hw_ci = HINIC_GET_SQ_HW_CI(txq);
 623         sw_ci = HINIC_GET_SQ_LOCAL_CI(txq);
 624         sq_mask = HINIC_GET_SQ_WQE_MASK(txq);
 625
 626         for (i = 0; i < txq->tx_free_thresh; ++i) {
 627                 tx_info = &txq->tx_info[sw_ci];
 628                 if (hw_ci == sw_ci ||
 629                         (((hw_ci - sw_ci) & sq_mask) < tx_info->wqebb_cnt))
 630                         break;
 631
 632                 sw_ci = (sw_ci + tx_info->wqebb_cnt) & sq_mask;
 633
 634                 if (unlikely(tx_info->cpy_mbuf != NULL)) {
 635                         rte_pktmbuf_free(tx_info->cpy_mbuf);
 636                         tx_info->cpy_mbuf = NULL;
 637                 }
 638
 639                 wqebb_cnt += tx_info->wqebb_cnt;
 640                 mbuf = tx_info->mbuf;
 641
 642                 if (likely(mbuf->nb_segs == 1)) {
 643                         m = rte_pktmbuf_prefree_seg(mbuf);
 644                         tx_info->mbuf = NULL;
 645
 646                         if (unlikely(m == NULL))
 647                                 continue;
 648
 649                         mbuf_free[nb_free++] = m;
 650                         if (unlikely(m->pool != mbuf_free[0]->pool ||
 651                                 nb_free >= HINIC_MAX_TX_FREE_BULK)) {
 652                                 rte_mempool_put_bulk(mbuf_free[0]->pool,
 653                                         (void **)mbuf_free, (nb_free - 1));
 654                                 nb_free = 0;
 655                                 mbuf_free[nb_free++] = m;
 656                         }
 657                 } else {
 658                         rte_pktmbuf_free(mbuf);
 659                         tx_info->mbuf = NULL;
 660                 }
 661         }
 662
 663         if (nb_free > 0)
 664                 rte_mempool_put_bulk(mbuf_free[0]->pool, (void **)mbuf_free,
 665                                      nb_free);
 666
 667         HINIC_UPDATE_SQ_LOCAL_CI(txq, wqebb_cnt);
 668 }
 669
 670 static inline struct hinic_sq_wqe *
 671 hinic_get_sq_wqe(struct hinic_txq *txq, int wqebb_cnt,
 672                 struct hinic_wqe_info *wqe_info)
 673 {
 674         u32 cur_pi, end_pi;
 675         u16 remain_wqebbs;
 676         struct hinic_sq *sq = txq->sq;
 677         struct hinic_wq *wq = txq->wq;
 678
 679         /* record current pi */
 680         cur_pi = MASKED_WQE_IDX(wq, wq->prod_idx);
 681         end_pi = cur_pi + wqebb_cnt;
 682
 683         /* update next pi and delta */
 684         wq->prod_idx += wqebb_cnt;
 685         wq->delta -= wqebb_cnt;
 686
 687         /* return current pi and owner */
 688         wqe_info->pi = cur_pi;
 689         wqe_info->owner = sq->owner;
 690         wqe_info->around = 0;
 691         wqe_info->seq_wqebbs = wqebb_cnt;
 692
 693         if (unlikely(end_pi >= txq->q_depth)) {
 694                 /* update owner of next prod_idx */
 695                 sq->owner = !sq->owner;
 696
 697                 /* turn around to head */
 698                 if (unlikely(end_pi > txq->q_depth)) {
 699                         wqe_info->around = 1;
 700                         remain_wqebbs = txq->q_depth - cur_pi;
 701                         wqe_info->seq_wqebbs = remain_wqebbs;
 702                 }
 703         }
 704
 705         return (struct hinic_sq_wqe *)WQ_WQE_ADDR(wq, cur_pi);
 706 }
 707
 708 static inline uint16_t
 709 hinic_ipv4_phdr_cksum(const struct rte_ipv4_hdr *ipv4_hdr, uint64_t ol_flags)
 710 {
 711         struct ipv4_psd_header {
 712                 uint32_t src_addr; /* IP address of source host. */
 713                 uint32_t dst_addr; /* IP address of destination host. */
 714                 uint8_t  zero;     /* zero. */
 715                 uint8_t  proto;    /* L4 protocol type. */
 716                 uint16_t len;      /* L4 length. */
 717         } psd_hdr;
 718         uint8_t ihl;
 719
 720         psd_hdr.src_addr = ipv4_hdr->src_addr;
 721         psd_hdr.dst_addr = ipv4_hdr->dst_addr;
 722         psd_hdr.zero = 0;
 723         psd_hdr.proto = ipv4_hdr->next_proto_id;
 724         if (ol_flags & PKT_TX_TCP_SEG) {
 725                 psd_hdr.len = 0;
 726         } else {
 727                 /* ipv4_hdr->version_ihl is uint8_t big endian, ihl locates
 728                  * lower 4 bits and unit is 4 bytes
 729                  */
 730                 ihl = (ipv4_hdr->version_ihl & 0xF) << 2;
 731                 psd_hdr.len =
 732                 rte_cpu_to_be_16(rte_be_to_cpu_16(ipv4_hdr->total_length) -
 733                                  ihl);
 734         }
 735         return rte_raw_cksum(&psd_hdr, sizeof(psd_hdr));
 736 }
 737
 738 static inline uint16_t
 739 hinic_ipv6_phdr_cksum(const struct rte_ipv6_hdr *ipv6_hdr, uint64_t ol_flags)
 740 {
 741         uint32_t sum;
 742         struct {
 743                 uint32_t len;   /* L4 length. */
 744                 uint32_t proto; /* L4 protocol - top 3 bytes must be zero */
 745         } psd_hdr;
 746
 747         psd_hdr.proto = (ipv6_hdr->proto << 24);
 748         if (ol_flags & PKT_TX_TCP_SEG)
 749                 psd_hdr.len = 0;
 750         else
 751                 psd_hdr.len = ipv6_hdr->payload_len;
 752
 753         sum = __rte_raw_cksum(ipv6_hdr->src_addr,
 754                 sizeof(ipv6_hdr->src_addr) + sizeof(ipv6_hdr->dst_addr), 0);
 755         sum = __rte_raw_cksum(&psd_hdr, sizeof(psd_hdr), sum);
 756         return __rte_raw_cksum_reduce(sum);
 757 }
 758
 759 static inline void
 760 hinic_get_pld_offset(struct rte_mbuf *m, struct hinic_tx_offload_info *off_info,
 761                      int outer_cs_flag)
 762 {
 763         uint64_t ol_flags = m->ol_flags;
 764
 765         if (outer_cs_flag == 1) {
 766                 if ((ol_flags & PKT_TX_UDP_CKSUM) == PKT_TX_UDP_CKSUM) {
 767                         off_info->payload_offset = m->outer_l2_len +
 768                                 m->outer_l3_len + m->l2_len + m->l3_len;
 769                 } else if ((ol_flags & PKT_TX_TCP_CKSUM) ||
 770                                 (ol_flags & PKT_TX_TCP_SEG)) {
 771                         off_info->payload_offset = m->outer_l2_len +
 772                                         m->outer_l3_len + m->l2_len +
 773                                         m->l3_len + m->l4_len;
 774                 }
 775         } else {
 776                 if ((ol_flags & PKT_TX_UDP_CKSUM) == PKT_TX_UDP_CKSUM) {
 777                         off_info->payload_offset = m->l2_len + m->l3_len;
 778                 } else if ((ol_flags & PKT_TX_TCP_CKSUM) ||
 779                         (ol_flags & PKT_TX_TCP_SEG)) {
 780                         off_info->payload_offset = m->l2_len + m->l3_len +
 781                                                    m->l4_len;
 782                 }
 783         }
 784 }
 785
 786 static inline void
 787 hinic_analyze_tx_info(struct rte_mbuf *mbuf,
 788                       struct hinic_tx_offload_info *off_info)
 789 {
 790         struct rte_ether_hdr *eth_hdr;
 791         struct rte_vlan_hdr *vlan_hdr;
 792         struct rte_ipv4_hdr *ip4h;
 793         u16 pkt_type;
 794         u8 *hdr;
 795
 796         hdr = (u8 *)rte_pktmbuf_mtod(mbuf, u8*);
 797         eth_hdr = (struct rte_ether_hdr *)hdr;
 798         pkt_type = rte_be_to_cpu_16(eth_hdr->ether_type);
 799
 800         if (pkt_type == RTE_ETHER_TYPE_VLAN) {
 801                 off_info->outer_l2_len = ETHER_LEN_WITH_VLAN;
 802                 vlan_hdr = (struct rte_vlan_hdr *)(hdr + 1);
 803                 pkt_type = rte_be_to_cpu_16(vlan_hdr->eth_proto);
 804         } else {
 805                 off_info->outer_l2_len = ETHER_LEN_NO_VLAN;
 806         }
 807
 808         if (pkt_type == RTE_ETHER_TYPE_IPV4) {
 809                 ip4h = (struct rte_ipv4_hdr *)(hdr + off_info->outer_l2_len);
 810                 off_info->outer_l3_len = (ip4h->version_ihl & 0xf) <<
 811                                         HEADER_LEN_OFFSET;
 812         } else if (pkt_type == RTE_ETHER_TYPE_IPV6) {
 813                 /* not support ipv6 extension header */
 814                 off_info->outer_l3_len = sizeof(struct rte_ipv6_hdr);
 815         }
 816 }
 817
 818 static inline int
 819 hinic_tx_offload_pkt_prepare(struct rte_mbuf *m,
 820                                 struct hinic_tx_offload_info *off_info)
 821 {
 822         struct rte_ipv4_hdr *ipv4_hdr;
 823         struct rte_ipv6_hdr *ipv6_hdr;
 824         struct rte_tcp_hdr *tcp_hdr;
 825         struct rte_udp_hdr *udp_hdr;
 826         struct rte_ether_hdr *eth_hdr;
 827         struct rte_vlan_hdr *vlan_hdr;
 828         u16 eth_type = 0;
 829         uint64_t inner_l3_offset;
 830         uint64_t ol_flags = m->ol_flags;
 831
 832         /* Check if the packets set available offload flags */
 833         if (!(ol_flags & HINIC_TX_CKSUM_OFFLOAD_MASK))
 834                 return 0;
 835
 836         /* Support only vxlan offload */
 837         if ((ol_flags & PKT_TX_TUNNEL_MASK) &&
 838             !(ol_flags & PKT_TX_TUNNEL_VXLAN))
 839                 return -ENOTSUP;
 840
 841 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
 842         if (rte_validate_tx_offload(m) != 0)
 843                 return -EINVAL;
 844 #endif
 845
 846         if (ol_flags & PKT_TX_TUNNEL_VXLAN) {
 847                 if ((ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
 848                     (ol_flags & PKT_TX_OUTER_IPV6) ||
 849                     (ol_flags & PKT_TX_TCP_SEG)) {
 850                         inner_l3_offset = m->l2_len + m->outer_l2_len +
 851                                 m->outer_l3_len;
 852                         off_info->outer_l2_len = m->outer_l2_len;
 853                         off_info->outer_l3_len = m->outer_l3_len;
 854                         /* just support vxlan tunneling pkt */
 855                         off_info->inner_l2_len = m->l2_len - VXLANLEN -
 856                                 sizeof(*udp_hdr);
 857                         off_info->inner_l3_len = m->l3_len;
 858                         off_info->inner_l4_len = m->l4_len;
 859                         off_info->tunnel_length = m->l2_len;
 860                         off_info->tunnel_type = TUNNEL_UDP_NO_CSUM;
 861
 862                         hinic_get_pld_offset(m, off_info,
 863                                              HINIC_TX_OUTER_CHECKSUM_FLAG_SET);
 864                 } else {
 865                         inner_l3_offset = m->l2_len;
 866                         hinic_analyze_tx_info(m, off_info);
 867                         /* just support vxlan tunneling pkt */
 868                         off_info->inner_l2_len = m->l2_len - VXLANLEN -
 869                                 sizeof(*udp_hdr) - off_info->outer_l2_len -
 870                                 off_info->outer_l3_len;
 871                         off_info->inner_l3_len = m->l3_len;
 872                         off_info->inner_l4_len = m->l4_len;
 873                         off_info->tunnel_length = m->l2_len -
 874                                 off_info->outer_l2_len - off_info->outer_l3_len;
 875                         off_info->tunnel_type = TUNNEL_UDP_NO_CSUM;
 876
 877                         hinic_get_pld_offset(m, off_info,
 878                                 HINIC_TX_OUTER_CHECKSUM_FLAG_NO_SET);
 879                 }
 880         } else {
 881                 inner_l3_offset = m->l2_len;
 882                 off_info->inner_l2_len = m->l2_len;
 883                 off_info->inner_l3_len = m->l3_len;
 884                 off_info->inner_l4_len = m->l4_len;
 885                 off_info->tunnel_type = NOT_TUNNEL;
 886
 887                 hinic_get_pld_offset(m, off_info,
 888                                      HINIC_TX_OUTER_CHECKSUM_FLAG_NO_SET);
 889         }
 890
 891         /* invalid udp or tcp header */
 892         if (unlikely(off_info->payload_offset > MAX_PLD_OFFSET))
 893                 return -EINVAL;
 894
 895         /* Process outter udp pseudo-header checksum */
 896         if ((ol_flags & PKT_TX_TUNNEL_VXLAN) && ((ol_flags & PKT_TX_TCP_SEG) ||
 897                         (ol_flags & PKT_TX_OUTER_IP_CKSUM) ||
 898                         (ol_flags & PKT_TX_OUTER_IPV6))) {
 899
 900                 /* inner_l4_tcp_udp csum should be setted to calculate outter
 901                  * udp checksum when vxlan packets without inner l3 and l4
 902                  */
 903                 off_info->inner_l4_tcp_udp = 1;
 904
 905                 eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
 906                 eth_type = rte_be_to_cpu_16(eth_hdr->ether_type);
 907
 908                 if (eth_type == RTE_ETHER_TYPE_VLAN) {
 909                         vlan_hdr = (struct rte_vlan_hdr *)(eth_hdr + 1);
 910                         eth_type = rte_be_to_cpu_16(vlan_hdr->eth_proto);
 911                 }
 912
 913                 if (eth_type == RTE_ETHER_TYPE_IPV4) {
 914                         ipv4_hdr =
 915                         rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
 916                                                 m->outer_l2_len);
 917                         off_info->outer_l3_type = IPV4_PKT_WITH_CHKSUM_OFFLOAD;
 918                         ipv4_hdr->hdr_checksum = 0;
 919
 920                         udp_hdr = (struct rte_udp_hdr *)((char *)ipv4_hdr +
 921                                                         m->outer_l3_len);
 922                         udp_hdr->dgram_cksum = 0;
 923                 } else if (eth_type == RTE_ETHER_TYPE_IPV6) {
 924                         off_info->outer_l3_type = IPV6_PKT;
 925                         ipv6_hdr =
 926                         rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
 927                                                 m->outer_l2_len);
 928
 929                         udp_hdr =
 930                         rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
 931                                                 (m->outer_l2_len +
 932                                                 m->outer_l3_len));
 933                         udp_hdr->dgram_cksum = 0;
 934                 }
 935         } else if (ol_flags & PKT_TX_OUTER_IPV4) {
 936                 off_info->tunnel_type = TUNNEL_UDP_NO_CSUM;
 937                 off_info->inner_l4_tcp_udp = 1;
 938                 off_info->outer_l3_type = IPV4_PKT_NO_CHKSUM_OFFLOAD;
 939         }
 940
 941         if (ol_flags & PKT_TX_IPV4)
 942                 off_info->inner_l3_type = (ol_flags & PKT_TX_IP_CKSUM) ?
 943                                         IPV4_PKT_WITH_CHKSUM_OFFLOAD :
 944                                         IPV4_PKT_NO_CHKSUM_OFFLOAD;
 945         else if (ol_flags & PKT_TX_IPV6)
 946                 off_info->inner_l3_type = IPV6_PKT;
 947
 948         /* Process the pseudo-header checksum */
 949         if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM) {
 950                 if (ol_flags & PKT_TX_IPV4) {
 951                         ipv4_hdr =
 952                         rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
 953                                                 inner_l3_offset);
 954
 955                         if (ol_flags & PKT_TX_IP_CKSUM)
 956                                 ipv4_hdr->hdr_checksum = 0;
 957
 958                         udp_hdr = (struct rte_udp_hdr *)((char *)ipv4_hdr +
 959                                                                 m->l3_len);
 960                         udp_hdr->dgram_cksum =
 961                                 hinic_ipv4_phdr_cksum(ipv4_hdr, ol_flags);
 962                 } else {
 963                         ipv6_hdr =
 964                         rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
 965                                                 inner_l3_offset);
 966
 967                         udp_hdr =
 968                         rte_pktmbuf_mtod_offset(m, struct rte_udp_hdr *,
 969                                                 (inner_l3_offset + m->l3_len));
 970                         udp_hdr->dgram_cksum =
 971                                 hinic_ipv6_phdr_cksum(ipv6_hdr, ol_flags);
 972                 }
 973
 974                 off_info->inner_l4_type = UDP_OFFLOAD_ENABLE;
 975                 off_info->inner_l4_tcp_udp = 1;
 976         } else if (((ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) ||
 977                         (ol_flags & PKT_TX_TCP_SEG)) {
 978                 if (ol_flags & PKT_TX_IPV4) {
 979                         ipv4_hdr =
 980                         rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
 981                                                 inner_l3_offset);
 982
 983                         if (ol_flags & PKT_TX_IP_CKSUM)
 984                                 ipv4_hdr->hdr_checksum = 0;
 985
 986                         /* non-TSO tcp */
 987                         tcp_hdr = (struct rte_tcp_hdr *)((char *)ipv4_hdr +
 988                                                                 m->l3_len);
 989                         tcp_hdr->cksum =
 990                                 hinic_ipv4_phdr_cksum(ipv4_hdr, ol_flags);
 991                 } else {
 992                         ipv6_hdr =
 993                         rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
 994                                                 inner_l3_offset);
 995                         /* non-TSO tcp */
 996                         tcp_hdr =
 997                         rte_pktmbuf_mtod_offset(m, struct rte_tcp_hdr *,
 998                                                 (inner_l3_offset + m->l3_len));
 999                         tcp_hdr->cksum =
1000                                 hinic_ipv6_phdr_cksum(ipv6_hdr, ol_flags);
1001                 }
1002
1003                 off_info->inner_l4_type = TCP_OFFLOAD_ENABLE;
1004                 off_info->inner_l4_tcp_udp = 1;
1005         } else if ((ol_flags & PKT_TX_L4_MASK) == PKT_TX_SCTP_CKSUM) {
1006                 off_info->inner_l4_type = SCTP_OFFLOAD_ENABLE;
1007                 off_info->inner_l4_tcp_udp = 0;
1008                 off_info->inner_l4_len = sizeof(struct rte_sctp_hdr);
1009         }
1010
1011         return 0;
1012 }
1013
1014 static inline bool hinic_get_sge_txoff_info(struct rte_mbuf *mbuf_pkt,
1015                                             struct hinic_wqe_info *sqe_info,
1016                                             struct hinic_tx_offload_info
1017                                             *off_info)
1018 {
1019         u16  i, total_len, sge_cnt = mbuf_pkt->nb_segs;
1020         struct rte_mbuf *mbuf;
1021         int ret;
1022
1023         memset(off_info, 0, sizeof(*off_info));
1024
1025         ret = hinic_tx_offload_pkt_prepare(mbuf_pkt, off_info);
1026         if (unlikely(ret))
1027                 return false;
1028
1029         sqe_info->cpy_mbuf_cnt = 0;
1030
1031         /* non tso mbuf */
1032         if (likely(!(mbuf_pkt->ol_flags & PKT_TX_TCP_SEG))) {
1033                 if (unlikely(mbuf_pkt->pkt_len > MAX_SINGLE_SGE_SIZE)) {
1034                         /* non tso packet len must less than 64KB */
1035                         return false;
1036                 } else if (unlikely(HINIC_NONTSO_SEG_NUM_INVALID(sge_cnt))) {
1037                         /* non tso packet buffer number must less than 17
1038                          * the mbuf segs more than 17 must copy to one buffer
1039                          */
1040                         total_len = 0;
1041                         mbuf = mbuf_pkt;
1042                         for (i = 0; i < (HINIC_NONTSO_PKT_MAX_SGE - 1) ; i++) {
1043                                 total_len += mbuf->data_len;
1044                                 mbuf = mbuf->next;
1045                         }
1046
1047                         /* default support copy total 4k mbuf segs */
1048                         if ((u32)(total_len + (u16)HINIC_COPY_MBUF_SIZE) <
1049                                   mbuf_pkt->pkt_len)
1050                                 return false;
1051
1052                         sqe_info->sge_cnt = HINIC_NONTSO_PKT_MAX_SGE;
1053                         sqe_info->cpy_mbuf_cnt = 1;
1054                         return true;
1055                 }
1056
1057                 /* valid non tso mbuf */
1058                 sqe_info->sge_cnt = sge_cnt;
1059         } else {
1060                 /* tso mbuf */
1061                 if (unlikely(HINIC_TSO_SEG_NUM_INVALID(sge_cnt)))
1062                         /* too many mbuf segs */
1063                         return false;
1064
1065                 /* check tso mbuf segs are valid or not */
1066                 if (unlikely(!hinic_is_tso_sge_valid(mbuf_pkt,
1067                              off_info, sqe_info)))
1068                         return false;
1069         }
1070
1071         return true;
1072 }
1073
1074 static inline void hinic_sq_write_db(struct hinic_sq *sq, int cos)
1075 {
1076         u16 prod_idx;
1077         u32 hi_prod_idx;
1078         struct hinic_sq_db sq_db;
1079
1080         prod_idx = MASKED_SQ_IDX(sq, sq->wq->prod_idx);
1081         hi_prod_idx = SQ_DB_PI_HIGH(prod_idx);
1082
1083         sq_db.db_info = SQ_DB_INFO_SET(hi_prod_idx, HI_PI) |
1084                         SQ_DB_INFO_SET(SQ_DB, TYPE) |
1085                         SQ_DB_INFO_SET(SQ_CFLAG_DP, CFLAG) |
1086                         SQ_DB_INFO_SET(cos, COS) |
1087                         SQ_DB_INFO_SET(sq->q_id, QID);
1088
1089         /* Data should be written to HW in Big Endian Format */
1090         sq_db.db_info = cpu_to_be32(sq_db.db_info);
1091
1092         /* Write all before the doorbell */
1093         rte_wmb();
1094         writel(sq_db.db_info, SQ_DB_ADDR(sq, prod_idx));
1095 }
1096
1097 u16 hinic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, u16 nb_pkts)
1098 {
1099         int free_wqebb_cnt, wqe_wqebb_cnt;
1100         u32 queue_info, tx_bytes = 0;
1101         u16 nb_tx;
1102         struct hinic_wqe_info sqe_info;
1103         struct hinic_tx_offload_info off_info;
1104         struct rte_mbuf *mbuf_pkt;
1105         struct hinic_txq *txq = tx_queue;
1106         struct hinic_tx_info *tx_info;
1107         struct hinic_sq_wqe *sq_wqe;
1108         struct hinic_sq_task *task;
1109
1110         /* reclaim tx mbuf before xmit new packet */
1111         if (HINIC_GET_SQ_FREE_WQEBBS(txq) < txq->tx_free_thresh)
1112                 hinic_xmit_mbuf_cleanup(txq);
1113
1114         /* tx loop routine */
1115         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1116                 mbuf_pkt = *tx_pkts++;
1117                 queue_info = 0;
1118
1119                 /* 1. parse sge and tx offlod info from mbuf */
1120                 if (unlikely(!hinic_get_sge_txoff_info(mbuf_pkt,
1121                                                        &sqe_info, &off_info))) {
1122                         txq->txq_stats.off_errs++;
1123                         break;
1124                 }
1125
1126                 /* 2. try to get enough wqebb */
1127                 wqe_wqebb_cnt = HINIC_SQ_WQEBB_CNT(sqe_info.sge_cnt);
1128                 free_wqebb_cnt = HINIC_GET_SQ_FREE_WQEBBS(txq);
1129                 if (unlikely(wqe_wqebb_cnt > free_wqebb_cnt)) {
1130                         /* reclaim again */
1131                         hinic_xmit_mbuf_cleanup(txq);
1132                         free_wqebb_cnt = HINIC_GET_SQ_FREE_WQEBBS(txq);
1133                         if (unlikely(wqe_wqebb_cnt > free_wqebb_cnt)) {
1134                                 txq->txq_stats.tx_busy += (nb_pkts - nb_tx);
1135                                 break;
1136                         }
1137                 }
1138
1139                 /* 3. get sq tail wqe address from wqe_page,
1140                  * sq have enough wqebb for this packet
1141                  */
1142                 sq_wqe = hinic_get_sq_wqe(txq, wqe_wqebb_cnt, &sqe_info);
1143
1144                 /* 4. fill sq wqe sge section */
1145                 if (unlikely(!hinic_mbuf_dma_map_sge(txq, mbuf_pkt,
1146                                                      sq_wqe->buf_descs,
1147                                                      &sqe_info))) {
1148                         hinic_return_sq_wqe(txq->nic_dev->hwdev, txq->q_id,
1149                                             wqe_wqebb_cnt, sqe_info.owner);
1150                         txq->txq_stats.off_errs++;
1151                         break;
1152                 }
1153
1154                 /* 5. fill sq wqe task section and queue info */
1155                 task = &sq_wqe->task;
1156
1157                 /* tx packet offload configure */
1158                 hinic_fill_tx_offload_info(mbuf_pkt, task, &queue_info,
1159                                            &off_info);
1160
1161                 /* 6. record tx info */
1162                 tx_info = &txq->tx_info[sqe_info.pi];
1163                 tx_info->mbuf = mbuf_pkt;
1164                 tx_info->wqebb_cnt = wqe_wqebb_cnt;
1165
1166                 /* 7. fill sq wqe header section */
1167                 hinic_fill_sq_wqe_header(&sq_wqe->ctrl, queue_info,
1168                                          sqe_info.sge_cnt, sqe_info.owner);
1169
1170                 /* 8.convert continue or bottom wqe byteorder to big endian */
1171                 hinic_sq_wqe_cpu_to_be32(sq_wqe, sqe_info.seq_wqebbs);
1172
1173                 tx_bytes += mbuf_pkt->pkt_len;
1174         }
1175
1176         /* 9. write sq doorbell in burst mode */
1177         if (nb_tx) {
1178                 hinic_sq_write_db(txq->sq, txq->cos);
1179
1180                 txq->txq_stats.packets += nb_tx;
1181                 txq->txq_stats.bytes += tx_bytes;
1182         }
1183         txq->txq_stats.burst_pkts = nb_tx;
1184
1185         return nb_tx;
1186 }
1187
1188 void hinic_free_all_tx_mbufs(struct hinic_txq *txq)
1189 {
1190         u16 ci;
1191         struct hinic_nic_dev *nic_dev = txq->nic_dev;
1192         struct hinic_tx_info *tx_info;
1193         int free_wqebbs = hinic_get_sq_free_wqebbs(nic_dev->hwdev,
1194                                                    txq->q_id) + 1;
1195
1196         while (free_wqebbs < txq->q_depth) {
1197                 ci = hinic_get_sq_local_ci(nic_dev->hwdev, txq->q_id);
1198
1199                 tx_info = &txq->tx_info[ci];
1200
1201                 if (unlikely(tx_info->cpy_mbuf != NULL)) {
1202                         rte_pktmbuf_free(tx_info->cpy_mbuf);
1203                         tx_info->cpy_mbuf = NULL;
1204                 }
1205
1206                 rte_pktmbuf_free(tx_info->mbuf);
1207                 hinic_update_sq_local_ci(nic_dev->hwdev, txq->q_id,
1208                                          tx_info->wqebb_cnt);
1209
1210                 free_wqebbs += tx_info->wqebb_cnt;
1211                 tx_info->mbuf = NULL;
1212         }
1213 }
1214
1215 void hinic_free_all_tx_resources(struct rte_eth_dev *eth_dev)
1216 {
1217         u16 q_id;
1218         struct hinic_nic_dev *nic_dev =
1219                                 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1220
1221         for (q_id = 0; q_id < nic_dev->num_sq; q_id++) {
1222                 if (eth_dev->data->tx_queues != NULL)
1223                         eth_dev->data->tx_queues[q_id] = NULL;
1224
1225                 if (nic_dev->txqs[q_id] == NULL)
1226                         continue;
1227
1228                 /* stop tx queue free tx mbuf */
1229                 hinic_free_all_tx_mbufs(nic_dev->txqs[q_id]);
1230                 hinic_free_tx_resources(nic_dev->txqs[q_id]);
1231
1232                 /* free txq */
1233                 kfree(nic_dev->txqs[q_id]);
1234                 nic_dev->txqs[q_id] = NULL;
1235         }
1236 }
1237
1238 void hinic_free_all_tx_mbuf(struct rte_eth_dev *eth_dev)
1239 {
1240         u16 q_id;
1241         struct hinic_nic_dev *nic_dev =
1242                                 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);
1243
1244         for (q_id = 0; q_id < nic_dev->num_sq; q_id++)
1245                 /* stop tx queue free tx mbuf */
1246                 hinic_free_all_tx_mbufs(nic_dev->txqs[q_id]);
1247 }
1248
1249 int hinic_setup_tx_resources(struct hinic_txq *txq)
1250 {
1251         u64 tx_info_sz;
1252
1253         tx_info_sz = txq->q_depth * sizeof(*txq->tx_info);
1254         txq->tx_info = rte_zmalloc_socket("tx_info", tx_info_sz,
1255                         RTE_CACHE_LINE_SIZE, txq->socket_id);
1256         if (!txq->tx_info)
1257                 return -ENOMEM;
1258
1259         return HINIC_OK;
1260 }
1261
1262 void hinic_free_tx_resources(struct hinic_txq *txq)
1263 {
1264         if (txq->tx_info == NULL)
1265                 return;
1266
1267         rte_free(txq->tx_info);
1268         txq->tx_info = NULL;
1269 }
1270
1271 int hinic_create_sq(struct hinic_hwdev *hwdev, u16 q_id,
1272                         u16 sq_depth, unsigned int socket_id)
1273 {
1274         int err;
1275         struct hinic_nic_io *nic_io = hwdev->nic_io;
1276         struct hinic_qp *qp = &nic_io->qps[q_id];
1277         struct hinic_sq *sq = &qp->sq;
1278         void __iomem *db_addr;
1279         volatile u32 *ci_addr;
1280
1281         sq->sq_depth = sq_depth;
1282         nic_io->sq_depth = sq_depth;
1283
1284         /* alloc wq */
1285         err = hinic_wq_allocate(nic_io->hwdev, &nic_io->sq_wq[q_id],
1286                                 HINIC_SQ_WQEBB_SHIFT, nic_io->sq_depth,
1287                                 socket_id);
1288         if (err) {
1289                 PMD_DRV_LOG(ERR, "Failed to allocate WQ for SQ");
1290                 return err;
1291         }
1292
1293         /* alloc sq doorbell space */
1294         err = hinic_alloc_db_addr(nic_io->hwdev, &db_addr);
1295         if (err) {
1296                 PMD_DRV_LOG(ERR, "Failed to init db addr");
1297                 goto alloc_db_err;
1298         }
1299
1300         /* clear hardware ci */
1301         ci_addr = (volatile u32 *)HINIC_CI_VADDR(nic_io->ci_vaddr_base, q_id);
1302         *ci_addr = 0;
1303
1304         sq->q_id = q_id;
1305         sq->wq = &nic_io->sq_wq[q_id];
1306         sq->owner = 1;
1307         sq->cons_idx_addr = (volatile u16 *)ci_addr;
1308         sq->db_addr = db_addr;
1309
1310         return HINIC_OK;
1311
1312 alloc_db_err:
1313         hinic_wq_free(nic_io->hwdev, &nic_io->sq_wq[q_id]);
1314
1315         return err;
1316 }
1317
1318 void hinic_destroy_sq(struct hinic_hwdev *hwdev, u16 q_id)
1319 {
1320         struct hinic_nic_io *nic_io;
1321         struct hinic_qp *qp;
1322
1323         nic_io = hwdev->nic_io;
1324         qp = &nic_io->qps[q_id];
1325
1326         if (qp->sq.wq == NULL)
1327                 return;
1328
1329         hinic_free_db_addr(nic_io->hwdev, qp->sq.db_addr);
1330         hinic_wq_free(nic_io->hwdev, qp->sq.wq);
1331         qp->sq.wq = NULL;
1332 }