1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
10 #define HNS3_CMDQ_TX_TIMEOUT 30000
11 #define HNS3_CMDQ_CLEAR_WAIT_TIME 200
12 #define HNS3_CMDQ_RX_INVLD_B 0
13 #define HNS3_CMDQ_RX_OUTVLD_B 1
14 #define HNS3_CMD_DESC_ALIGNMENT 4096
15 #define HNS3_CMD_FLAG_NEXT BIT(2)
19 #define HNS3_CMD_DESC_DATA_NUM 6
20 struct hns3_cmd_desc {
25 uint32_t data[HNS3_CMD_DESC_DATA_NUM];
28 struct hns3_cmq_ring {
29 uint64_t desc_dma_addr;
30 struct hns3_cmd_desc *desc;
34 uint16_t desc_num; /* max number of cmq descriptor */
36 uint32_t next_to_clean;
37 uint8_t ring_type; /* cmq ring type */
38 rte_spinlock_t lock; /* Command queue lock */
40 const void *zone; /* memory zone */
43 enum hns3_cmd_return_status {
44 HNS3_CMD_EXEC_SUCCESS = 0,
46 HNS3_CMD_NOT_SUPPORTED = 2,
47 HNS3_CMD_QUEUE_FULL = 3,
48 HNS3_CMD_NEXT_ERR = 4,
49 HNS3_CMD_UNEXE_ERR = 5,
50 HNS3_CMD_PARA_ERR = 6,
51 HNS3_CMD_RESULT_ERR = 7,
53 HNS3_CMD_HILINK_ERR = 9,
54 HNS3_CMD_QUEUE_ILLEGAL = 10,
55 HNS3_CMD_INVALID = 11,
56 HNS3_CMD_ROH_CHECK_FAIL = 12
59 enum hns3_cmd_status {
60 HNS3_STATUS_SUCCESS = 0,
61 HNS3_ERR_CSQ_FULL = -1,
62 HNS3_ERR_CSQ_TIMEOUT = -2,
63 HNS3_ERR_CSQ_ERROR = -3,
66 struct hns3_misc_vector {
72 struct hns3_cmq_ring csq;
73 struct hns3_cmq_ring crq;
75 enum hns3_cmd_status last_status;
78 enum hns3_opcode_type {
79 /* Generic commands */
80 HNS3_OPC_QUERY_FW_VER = 0x0001,
81 HNS3_OPC_CFG_RST_TRIGGER = 0x0020,
82 HNS3_OPC_GBL_RST_STATUS = 0x0021,
83 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
84 HNS3_OPC_QUERY_PF_RSRC = 0x0023,
85 HNS3_OPC_QUERY_VF_RSRC = 0x0024,
86 HNS3_OPC_GET_CFG_PARAM = 0x0025,
87 HNS3_OPC_PF_RST_DONE = 0x0026,
89 HNS3_OPC_STATS_64_BIT = 0x0030,
90 HNS3_OPC_STATS_32_BIT = 0x0031,
91 HNS3_OPC_STATS_MAC = 0x0032,
92 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,
93 HNS3_OPC_STATS_MAC_ALL = 0x0034,
95 HNS3_OPC_QUERY_REG_NUM = 0x0040,
96 HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
97 HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
98 HNS3_OPC_DFX_BD_NUM = 0x0043,
99 HNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044,
100 HNS3_OPC_DFX_SSU_REG_0 = 0x0045,
101 HNS3_OPC_DFX_SSU_REG_1 = 0x0046,
102 HNS3_OPC_DFX_IGU_EGU_REG = 0x0047,
103 HNS3_OPC_DFX_RPU_REG_0 = 0x0048,
104 HNS3_OPC_DFX_RPU_REG_1 = 0x0049,
105 HNS3_OPC_DFX_NCSI_REG = 0x004A,
106 HNS3_OPC_DFX_RTC_REG = 0x004B,
107 HNS3_OPC_DFX_PPP_REG = 0x004C,
108 HNS3_OPC_DFX_RCB_REG = 0x004D,
109 HNS3_OPC_DFX_TQP_REG = 0x004E,
110 HNS3_OPC_DFX_SSU_REG_2 = 0x004F,
112 HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
114 HNS3_OPC_SSU_DROP_REG = 0x0065,
117 HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
118 HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
119 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
120 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
121 HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310,
122 HNS3_OPC_MAC_TNL_INT_EN = 0x0311,
123 HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312,
124 HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
126 /* PFC/Pause commands */
127 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
128 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,
129 HNS3_OPC_CFG_MAC_PARA = 0x0703,
130 HNS3_OPC_CFG_PFC_PARA = 0x0704,
131 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
132 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
133 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
134 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
135 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,
136 HNS3_OPC_QOS_MAP = 0x070A,
138 /* ETS/scheduler commands */
139 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,
140 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,
141 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,
142 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,
143 HNS3_OPC_TM_PORT_WEIGHT = 0x0808,
144 HNS3_OPC_TM_PG_WEIGHT = 0x0809,
145 HNS3_OPC_TM_QS_WEIGHT = 0x080A,
146 HNS3_OPC_TM_PRI_WEIGHT = 0x080B,
147 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,
148 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,
149 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E,
150 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F,
151 HNS3_OPC_TM_PORT_SHAPPING = 0x0810,
152 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
153 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
154 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
155 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
156 HNS3_OPC_ETS_TC_WEIGHT = 0x0843,
157 HNS3_OPC_QSET_DFX_STS = 0x0844,
158 HNS3_OPC_PRI_DFX_STS = 0x0845,
159 HNS3_OPC_PG_DFX_STS = 0x0846,
160 HNS3_OPC_PORT_DFX_STS = 0x0847,
161 HNS3_OPC_SCH_NQ_CNT = 0x0848,
162 HNS3_OPC_SCH_RQ_CNT = 0x0849,
163 HNS3_OPC_TM_INTERNAL_STS = 0x0850,
164 HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
165 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
168 HNS3_OPC_MBX_VF_TO_PF = 0x2001,
170 /* Packet buffer allocate commands */
171 HNS3_OPC_TX_BUFF_ALLOC = 0x0901,
172 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
173 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,
174 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
175 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
177 /* TQP management command */
178 HNS3_OPC_SET_TQP_MAP = 0x0A01,
181 HNS3_OPC_QUERY_TX_STATUS = 0x0B03,
182 HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
183 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
184 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
185 HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23,
188 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
189 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
192 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,
193 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,
194 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07,
195 HNS3_OPC_RSS_TC_MODE = 0x0D08,
197 /* Promisuous mode command */
198 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01,
200 /* Vlan offload commands */
201 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,
202 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,
205 HNS3_OPC_MAC_VLAN_ADD = 0x1000,
206 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001,
207 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,
208 HNS3_OPC_MAC_VLAN_INSERT = 0x1003,
209 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,
210 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,
213 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100,
214 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,
215 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,
217 /* Flow Director command */
218 HNS3_OPC_FD_MODE_CTRL = 0x1200,
219 HNS3_OPC_FD_GET_ALLOCATION = 0x1201,
220 HNS3_OPC_FD_KEY_CONFIG = 0x1202,
221 HNS3_OPC_FD_TCAM_OP = 0x1203,
222 HNS3_OPC_FD_AD_OP = 0x1204,
223 HNS3_OPC_FD_COUNTER_OP = 0x1205,
225 /* Clear hardware state command */
226 HNS3_OPC_CLEAR_HW_STATE = 0x700B,
228 /* Firmware stats command */
229 HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A,
230 /* Firmware control phy command */
231 HNS3_OPC_PHY_PARAM_CFG = 0x7025,
234 HNS3_OPC_GET_SFP_EEPROM = 0x7100,
235 HNS3_OPC_GET_SFP_EXIST = 0x7101,
236 HNS3_OPC_SFP_GET_SPEED = 0x7104,
238 /* Interrupts commands */
239 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
240 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
242 /* Error INT commands */
243 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E,
244 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829,
245 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989,
246 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C,
247 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40,
248 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41,
249 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42,
250 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505,
251 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
252 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
253 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512,
254 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
255 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
256 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
257 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803,
258 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806,
259 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14,
260 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100,
261 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101,
262 HNS3_OPC_NCSI_INT_EN = 0x2401,
265 #define HNS3_CMD_FLAG_IN BIT(0)
266 #define HNS3_CMD_FLAG_OUT BIT(1)
267 #define HNS3_CMD_FLAG_NEXT BIT(2)
268 #define HNS3_CMD_FLAG_WR BIT(3)
269 #define HNS3_CMD_FLAG_NO_INTR BIT(4)
270 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
272 #define HNS3_MPF_RAS_INT_MIN_BD_NUM 10
273 #define HNS3_PF_RAS_INT_MIN_BD_NUM 4
274 #define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10
275 #define HNS3_PF_MSIX_INT_MIN_BD_NUM 4
277 #define HNS3_BUF_SIZE_UNIT 256
278 #define HNS3_BUF_MUL_BY 2
279 #define HNS3_BUF_DIV_BY 2
280 #define NEED_RESERVE_TC_NUM 2
281 #define BUF_MAX_PERCENT 100
282 #define BUF_RESERVE_PERCENT 90
284 #define HNS3_MAX_TC_NUM 8
285 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
286 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
287 #define HNS3_TX_BUFF_RSV_NUM 8
288 struct hns3_tx_buff_alloc_cmd {
289 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];
290 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];
293 struct hns3_rx_priv_buff_cmd {
294 uint16_t buf_num[HNS3_MAX_TC_NUM];
299 #define HNS3_FW_VERSION_BYTE3_S 24
300 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24)
301 #define HNS3_FW_VERSION_BYTE2_S 16
302 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16)
303 #define HNS3_FW_VERSION_BYTE1_S 8
304 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
305 #define HNS3_FW_VERSION_BYTE0_S 0
306 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
308 enum HNS3_CAPS_BITS {
311 HNS3_CAPS_FD_QUEUE_REGION_B,
314 HNS3_CAPS_SIMPLE_BD_B,
317 HNS3_CAPS_TQP_TXRX_INDEP_B,
320 HNS3_CAPS_UDP_TUNNEL_CSUM_B,
324 HNS3_CAPS_RXD_ADV_LAYOUT_B,
327 enum HNS3_API_CAP_BITS {
328 HNS3_API_CAP_FLEX_RSS_TBL_B,
331 #define HNS3_QUERY_CAP_LENGTH 3
332 struct hns3_query_version_cmd {
336 uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
339 #define HNS3_RX_PRIV_EN_B 15
340 #define HNS3_TC_NUM_ONE_DESC 4
341 struct hns3_priv_wl {
346 struct hns3_rx_priv_wl_buf {
347 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];
350 struct hns3_rx_com_thrd {
351 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];
354 struct hns3_rx_com_wl {
355 struct hns3_priv_wl com_wl;
358 struct hns3_waterline {
363 struct hns3_tc_thrd {
368 struct hns3_priv_buf {
369 struct hns3_waterline wl; /* Waterline for low and high */
370 uint32_t buf_size; /* TC private buffer size */
371 uint32_t tx_buf_size;
372 uint32_t enable; /* Enable TC private buffer or not */
375 struct hns3_shared_buf {
376 struct hns3_waterline self;
377 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];
381 struct hns3_pkt_buf_alloc {
382 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];
383 struct hns3_shared_buf s_buf;
386 #define HNS3_RX_COM_WL_EN_B 15
387 struct hns3_rx_com_wl_buf_cmd {
393 #define HNS3_RX_PKT_EN_B 15
394 struct hns3_rx_pkt_buf_cmd {
400 #define HNS3_PF_STATE_DONE_B 0
401 #define HNS3_PF_STATE_MAIN_B 1
402 #define HNS3_PF_STATE_BOND_B 2
403 #define HNS3_PF_STATE_MAC_N_B 6
404 #define HNS3_PF_MAC_NUM_MASK 0x3
405 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B)
406 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B)
407 #define HNS3_VF_RST_STATE_NUM 4
408 struct hns3_func_status_cmd {
409 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];
413 uint8_t pf_cnt_in_mac;
419 #define HNS3_PF_VEC_NUM_S 0
420 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
421 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */
422 struct hns3_pf_res_cmd {
425 uint16_t msixcap_localid_ba_nic;
426 uint16_t nic_pf_intr_vector_number;
427 uint16_t roce_pf_intr_vector_number;
428 uint16_t pf_own_fun_number;
429 uint16_t tx_buf_size;
430 uint16_t dv_buf_size;
431 /* number of queues that exceed 1024 */
432 uint16_t ext_tqp_num;
433 uint16_t roh_pf_intr_vector_number;
437 #define HNS3_VF_VEC_NUM_S 0
438 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
439 struct hns3_vf_res_cmd {
442 uint16_t msixcap_localid_ba_nic;
443 uint16_t msixcap_localid_ba_rocee;
444 uint16_t vf_intr_vector_number;
448 #define HNS3_UMV_SPC_ALC_B 0
449 struct hns3_umv_spc_alc_cmd {
456 #define HNS3_CFG_OFFSET_S 0
457 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
458 #define HNS3_CFG_RD_LEN_S 24
459 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24)
460 #define HNS3_CFG_RD_LEN_BYTES 16
461 #define HNS3_CFG_RD_LEN_UNIT 4
463 #define HNS3_CFG_VMDQ_S 0
464 #define HNS3_CFG_VMDQ_M GENMASK(7, 0)
465 #define HNS3_CFG_TC_NUM_S 8
466 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
467 #define HNS3_CFG_TQP_DESC_N_S 16
468 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16)
469 #define HNS3_CFG_PHY_ADDR_S 0
470 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0)
471 #define HNS3_CFG_MEDIA_TP_S 8
472 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8)
473 #define HNS3_CFG_RX_BUF_LEN_S 16
474 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16)
475 #define HNS3_CFG_MAC_ADDR_H_S 0
476 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0)
477 #define HNS3_CFG_DEFAULT_SPEED_S 16
478 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
479 #define HNS3_CFG_RSS_SIZE_S 24
480 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24)
481 #define HNS3_CFG_SPEED_ABILITY_S 0
482 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0)
483 #define HNS3_CFG_UMV_TBL_SPACE_S 16
484 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
485 #define HNS3_CFG_EXT_RSS_SIZE_S 0
486 #define HNS3_CFG_EXT_RSS_SIZE_M GENMASK(3, 0)
488 #define HNS3_ACCEPT_TAG1_B 0
489 #define HNS3_ACCEPT_UNTAG1_B 1
490 #define HNS3_PORT_INS_TAG1_EN_B 2
491 #define HNS3_PORT_INS_TAG2_EN_B 3
492 #define HNS3_CFG_NIC_ROCE_SEL_B 4
493 #define HNS3_ACCEPT_TAG2_B 5
494 #define HNS3_ACCEPT_UNTAG2_B 6
495 #define HNS3_TAG_SHIFT_MODE_EN_B 7
497 #define HNS3_REM_TAG1_EN_B 0
498 #define HNS3_REM_TAG2_EN_B 1
499 #define HNS3_SHOW_TAG1_EN_B 2
500 #define HNS3_SHOW_TAG2_EN_B 3
501 #define HNS3_DISCARD_TAG1_EN_B 5
502 #define HNS3_DISCARD_TAG2_EN_B 6
504 /* Factor used to calculate offset and bitmap of VF num */
505 #define HNS3_VF_NUM_PER_CMD 64
506 #define HNS3_VF_NUM_PER_BYTE 8
508 struct hns3_cfg_param_cmd {
514 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8
515 struct hns3_vport_vtag_rx_cfg_cmd {
516 uint8_t vport_vlan_cfg;
519 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];
523 struct hns3_vport_vtag_tx_cfg_cmd {
524 uint8_t vport_vlan_cfg;
527 uint16_t def_vlan_tag1;
528 uint16_t def_vlan_tag2;
529 uint8_t vf_bitmap[8];
534 struct hns3_vlan_filter_ctrl_cmd {
542 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20
543 struct hns3_vlan_filter_pf_cfg_cmd {
547 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];
550 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16
551 struct hns3_vlan_filter_vf_cfg_cmd {
557 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];
560 struct hns3_tx_vlan_type_cfg_cmd {
561 uint16_t ot_vlan_type;
562 uint16_t in_vlan_type;
566 struct hns3_rx_vlan_type_cfg_cmd {
567 uint16_t ot_fst_vlan_type;
568 uint16_t ot_sec_vlan_type;
569 uint16_t in_fst_vlan_type;
570 uint16_t in_sec_vlan_type;
574 #define HNS3_TSO_MSS_MIN_S 0
575 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
577 #define HNS3_TSO_MSS_MAX_S 16
578 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16)
580 struct hns3_cfg_tso_status_cmd {
581 rte_le16_t tso_mss_min;
582 rte_le16_t tso_mss_max;
586 #define HNS3_GRO_EN_B 0
587 struct hns3_cfg_gro_status_cmd {
592 #define HNS3_TSO_MSS_MIN 256
593 #define HNS3_TSO_MSS_MAX 9668
595 #define HNS3_RSS_HASH_KEY_OFFSET_B 4
597 #define HNS3_RSS_CFG_TBL_SIZE 16
598 #define HNS3_RSS_HASH_KEY_NUM 16
599 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
600 struct hns3_rss_generic_config_cmd {
601 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */
604 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];
607 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */
608 struct hns3_rss_input_tuple_cmd {
609 uint64_t tuple_field;
613 #define HNS3_RSS_CFG_TBL_SIZE 16
614 #define HNS3_RSS_CFG_TBL_SIZE_H 4
615 #define HNS3_RSS_CFG_TBL_BW_H 2
616 #define HNS3_RSS_CFG_TBL_BW_L 8
618 /* Configure the indirection table, opcode:0x0D07 */
619 struct hns3_rss_indirection_table_cmd {
620 uint16_t start_table_index; /* Bit3~0 must be 0x0. */
621 uint16_t rss_set_bitmap;
622 uint8_t rss_result_h[HNS3_RSS_CFG_TBL_SIZE_H];
623 uint8_t rss_result_l[HNS3_RSS_CFG_TBL_SIZE];
626 #define HNS3_RSS_TC_OFFSET_S 0
627 #define HNS3_RSS_TC_OFFSET_M GENMASK(10, 0)
628 #define HNS3_RSS_TC_SIZE_MSB_S 11
629 #define HNS3_RSS_TC_SIZE_MSB_OFFSET 3
630 #define HNS3_RSS_TC_SIZE_S 12
631 #define HNS3_RSS_TC_SIZE_M GENMASK(14, 12)
632 #define HNS3_RSS_TC_VALID_B 15
634 /* Configure the tc_size and tc_offset, opcode:0x0D08 */
635 struct hns3_rss_tc_mode_cmd {
636 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM];
640 #define HNS3_LINK_STATUS_UP_B 0
641 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B)
642 struct hns3_link_status_cmd {
647 struct hns3_promisc_param {
652 #define HNS3_PROMISC_TX_EN_B BIT(4)
653 #define HNS3_PROMISC_RX_EN_B BIT(5)
654 #define HNS3_PROMISC_EN_B 1
655 #define HNS3_PROMISC_EN_ALL 0x7
656 #define HNS3_PROMISC_EN_UC 0x1
657 #define HNS3_PROMISC_EN_MC 0x2
658 #define HNS3_PROMISC_EN_BC 0x4
659 struct hns3_promisc_cfg_cmd {
666 enum hns3_promisc_type {
672 #define HNS3_LINK_EVENT_REPORT_EN_B 0
673 #define HNS3_NCSI_ERROR_REPORT_EN_B 1
674 #define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2
675 struct hns3_firmware_compat_cmd {
680 /* Bitmap flags in supported, advertising and lp_advertising */
681 #define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0)
682 #define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1)
683 #define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2)
684 #define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3)
685 #define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6)
686 #define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13)
687 #define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14)
689 #define HNS3_PHY_PARAM_CFG_BD_NUM 2
690 struct hns3_phy_params_bd0_cmd {
692 #define HNS3_PHY_DUPLEX_CFG_B 0
694 #define HNS3_PHY_AUTONEG_CFG_B 0
697 uint8_t eth_tp_mdix_ctrl;
703 uint32_t advertising;
704 uint32_t lp_advertising;
707 struct hns3_phy_params_bd1_cmd {
708 uint8_t master_slave_cfg;
709 uint8_t master_slave_state;
714 #define HNS3_MAC_TX_EN_B 6
715 #define HNS3_MAC_RX_EN_B 7
716 #define HNS3_MAC_PAD_TX_B 11
717 #define HNS3_MAC_PAD_RX_B 12
718 #define HNS3_MAC_1588_TX_B 13
719 #define HNS3_MAC_1588_RX_B 14
720 #define HNS3_MAC_APP_LP_B 15
721 #define HNS3_MAC_LINE_LP_B 16
722 #define HNS3_MAC_FCS_TX_B 17
723 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18
724 #define HNS3_MAC_RX_FCS_STRIP_B 19
725 #define HNS3_MAC_RX_FCS_B 20
726 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21
727 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22
729 struct hns3_config_mac_mode_cmd {
730 uint32_t txrx_pad_fcs_loop_en;
734 #define HNS3_CFG_SPEED_10M 6
735 #define HNS3_CFG_SPEED_100M 7
736 #define HNS3_CFG_SPEED_1G 0
737 #define HNS3_CFG_SPEED_10G 1
738 #define HNS3_CFG_SPEED_25G 2
739 #define HNS3_CFG_SPEED_40G 3
740 #define HNS3_CFG_SPEED_50G 4
741 #define HNS3_CFG_SPEED_100G 5
742 #define HNS3_CFG_SPEED_200G 8
744 #define HNS3_CFG_SPEED_S 0
745 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
746 #define HNS3_CFG_DUPLEX_B 7
747 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B)
749 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0
751 struct hns3_config_mac_speed_dup_cmd {
753 uint8_t mac_change_fec_en;
757 #define HNS3_TQP_ENABLE_B 0
759 #define HNS3_MAC_CFG_AN_EN_B 0
760 #define HNS3_MAC_CFG_AN_INT_EN_B 1
761 #define HNS3_MAC_CFG_AN_INT_MSK_B 2
762 #define HNS3_MAC_CFG_AN_INT_CLR_B 3
763 #define HNS3_MAC_CFG_AN_RST_B 4
765 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B)
767 struct hns3_config_auto_neg_cmd {
768 uint32_t cfg_an_cmd_flag;
772 #define HNS3_MAC_CFG_FEC_AUTO_EN_B 0
773 #define HNS3_MAC_CFG_FEC_MODE_S 1
774 #define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
775 #define HNS3_MAC_FEC_OFF 0
776 #define HNS3_MAC_FEC_BASER 1
777 #define HNS3_MAC_FEC_RS 2
779 #define HNS3_SFP_INFO_BD0_LEN 20UL
780 #define HNS3_SFP_INFO_BDX_LEN 24UL
782 struct hns3_sfp_info_bd0_cmd {
785 uint8_t data[HNS3_SFP_INFO_BD0_LEN];
788 struct hns3_sfp_type {
793 struct hns3_sfp_speed_cmd {
795 uint8_t query_type; /* 0: sfp speed, 1: active fec */
796 uint8_t active_fec; /* current FEC mode */
801 /* Configure FEC mode, opcode:0x031A */
802 struct hns3_config_fec_cmd {
807 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
808 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1)
809 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
810 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc
812 struct hns3_mac_mgr_tbl_entry_cmd {
816 uint32_t mac_addr_hi32;
817 uint16_t mac_addr_lo16;
819 uint16_t ethter_type;
820 uint16_t egress_port;
821 uint16_t egress_queue;
822 uint8_t sw_port_id_aware;
824 uint8_t i_port_bitmap;
825 uint8_t i_port_direction;
829 struct hns3_cfg_com_tqp_queue_cmd {
836 #define HNS3_TQP_MAP_TYPE_PF 0
837 #define HNS3_TQP_MAP_TYPE_VF 1
838 #define HNS3_TQP_MAP_TYPE_B 0
839 #define HNS3_TQP_MAP_EN_B 1
841 struct hns3_tqp_map_cmd {
842 uint16_t tqp_id; /* Absolute tqp id for in this pf */
843 uint8_t tqp_vf; /* VF id */
844 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */
845 uint16_t tqp_vid; /* Virtual id in this pf/vf */
849 enum hns3_ring_type {
854 enum hns3_int_gl_idx {
857 HNS3_RING_GL_IMMEDIATE = 3
860 #define HNS3_RING_GL_IDX_S 0
861 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
863 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10
865 #define HNS3_INT_TYPE_S 0
866 #define HNS3_INT_TYPE_M GENMASK(1, 0)
867 #define HNS3_TQP_ID_S 2
868 #define HNS3_TQP_ID_M GENMASK(12, 2)
869 #define HNS3_INT_GL_IDX_S 13
870 #define HNS3_INT_GL_IDX_M GENMASK(14, 13)
871 #define HNS3_TQP_INT_ID_L_S 0
872 #define HNS3_TQP_INT_ID_L_M GENMASK(7, 0)
873 #define HNS3_TQP_INT_ID_H_S 8
874 #define HNS3_TQP_INT_ID_H_M GENMASK(15, 8)
875 struct hns3_ctrl_vector_chain_cmd {
876 uint8_t int_vector_id; /* the low order of the interrupt id */
877 uint8_t int_cause_num;
878 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
880 uint8_t int_vector_id_h; /* the high order of the interrupt id */
883 struct hns3_config_max_frm_size_cmd {
884 uint16_t max_frm_size;
885 uint8_t min_frm_size;
889 enum hns3_mac_vlan_tbl_opcode {
890 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
891 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */
892 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
893 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
896 enum hns3_mac_vlan_add_resp_code {
897 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
898 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
901 #define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
903 #define HNS3_MAC_VLAN_BIT0_EN_B 0
904 #define HNS3_MAC_VLAN_BIT1_EN_B 1
905 #define HNS3_MAC_EPORT_SW_EN_B 12
906 #define HNS3_MAC_EPORT_TYPE_B 11
907 #define HNS3_MAC_EPORT_VFID_S 3
908 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3)
909 #define HNS3_MAC_EPORT_PFID_S 0
910 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0)
911 struct hns3_mac_vlan_tbl_entry_cmd {
915 uint32_t mac_addr_hi32;
916 uint16_t mac_addr_lo16;
920 uint16_t egress_port;
921 uint16_t egress_queue;
925 #define HNS3_TQP_RESET_B 0
926 struct hns3_reset_tqp_queue_cmd {
929 uint8_t ready_to_reset;
930 uint8_t queue_direction;
934 #define HNS3_CFG_RESET_MAC_B 3
935 #define HNS3_CFG_RESET_FUNC_B 7
936 #define HNS3_CFG_RESET_RCB_B 1
937 struct hns3_reset_cmd {
938 uint8_t mac_func_reset;
939 uint8_t fun_reset_vfid;
940 uint8_t fun_reset_rcb;
942 uint16_t fun_reset_rcb_vqid_start;
943 uint16_t fun_reset_rcb_vqid_num;
944 uint8_t fun_reset_rcb_return_status;
948 #define HNS3_QUERY_DEV_SPECS_BD_NUM 4
949 struct hns3_dev_specs_0_cmd {
951 uint32_t mac_entry_num;
952 uint32_t mng_entry_num;
953 uint16_t rss_ind_tbl_size;
954 uint16_t rss_key_size;
955 uint16_t intr_ql_max;
956 uint8_t max_non_tso_bd_num;
958 uint32_t max_tm_rate;
961 struct hns3_query_rpu_cmd {
962 uint32_t tc_queue_num;
964 uint32_t rpu_rx_pkt_drop_cnt;
968 #define HNS3_OPC_SSU_DROP_REG_NUM 2
970 struct hns3_query_ssu_cmd {
973 uint32_t full_drop_cnt;
974 uint32_t part_drop_cnt;
975 uint32_t oq_drop_cnt;
979 #define HNS3_MAX_TQP_NUM_HIP08_PF 64
980 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
981 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
982 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */
983 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
984 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
986 #define HNS3_TYPE_CRQ 0
987 #define HNS3_TYPE_CSQ 1
989 #define HNS3_NIC_SW_RST_RDY_B 16
990 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B)
991 #define HNS3_NIC_CMQ_DESC_NUM 1024
992 #define HNS3_NIC_CMQ_DESC_NUM_S 3
994 #define HNS3_CMD_SEND_SYNC(flag) \
995 ((flag) & HNS3_CMD_FLAG_NO_INTR)
997 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);
998 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,
999 enum hns3_opcode_type opcode, bool is_read);
1000 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);
1001 int hns3_cmd_init_queue(struct hns3_hw *hw);
1002 int hns3_cmd_init(struct hns3_hw *hw);
1003 void hns3_cmd_destroy_queue(struct hns3_hw *hw);
1004 void hns3_cmd_uninit(struct hns3_hw *hw);
1006 #endif /* _HNS3_CMD_H_ */