1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
10 #define HNS3_CMDQ_TX_TIMEOUT 30000
11 #define HNS3_CMDQ_CLEAR_WAIT_TIME 200
12 #define HNS3_CMDQ_RX_INVLD_B 0
13 #define HNS3_CMDQ_RX_OUTVLD_B 1
14 #define HNS3_CMD_DESC_ALIGNMENT 4096
15 #define HNS3_CMD_FLAG_NEXT BIT(2)
19 #define HNS3_CMD_DESC_DATA_NUM 6
20 struct hns3_cmd_desc {
25 uint32_t data[HNS3_CMD_DESC_DATA_NUM];
28 struct hns3_cmq_ring {
29 uint64_t desc_dma_addr;
30 struct hns3_cmd_desc *desc;
34 uint16_t desc_num; /* max number of cmq descriptor */
36 uint32_t next_to_clean;
37 uint8_t ring_type; /* cmq ring type */
38 rte_spinlock_t lock; /* Command queue lock */
40 const void *zone; /* memory zone */
43 enum hns3_cmd_return_status {
44 HNS3_CMD_EXEC_SUCCESS = 0,
46 HNS3_CMD_NOT_SUPPORTED = 2,
47 HNS3_CMD_QUEUE_FULL = 3,
48 HNS3_CMD_NEXT_ERR = 4,
49 HNS3_CMD_UNEXE_ERR = 5,
50 HNS3_CMD_PARA_ERR = 6,
51 HNS3_CMD_RESULT_ERR = 7,
53 HNS3_CMD_HILINK_ERR = 9,
54 HNS3_CMD_QUEUE_ILLEGAL = 10,
55 HNS3_CMD_INVALID = 11,
56 HNS3_CMD_ROH_CHECK_FAIL = 12
59 enum hns3_cmd_status {
60 HNS3_STATUS_SUCCESS = 0,
61 HNS3_ERR_CSQ_FULL = -1,
62 HNS3_ERR_CSQ_TIMEOUT = -2,
63 HNS3_ERR_CSQ_ERROR = -3,
66 struct hns3_misc_vector {
72 struct hns3_cmq_ring csq;
73 struct hns3_cmq_ring crq;
75 enum hns3_cmd_status last_status;
78 enum hns3_opcode_type {
79 /* Generic commands */
80 HNS3_OPC_QUERY_FW_VER = 0x0001,
81 HNS3_OPC_CFG_RST_TRIGGER = 0x0020,
82 HNS3_OPC_GBL_RST_STATUS = 0x0021,
83 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
84 HNS3_OPC_QUERY_PF_RSRC = 0x0023,
85 HNS3_OPC_QUERY_VF_RSRC = 0x0024,
86 HNS3_OPC_GET_CFG_PARAM = 0x0025,
87 HNS3_OPC_PF_RST_DONE = 0x0026,
89 HNS3_OPC_STATS_64_BIT = 0x0030,
90 HNS3_OPC_STATS_32_BIT = 0x0031,
91 HNS3_OPC_STATS_MAC = 0x0032,
92 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,
93 HNS3_OPC_STATS_MAC_ALL = 0x0034,
95 HNS3_OPC_QUERY_REG_NUM = 0x0040,
96 HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
97 HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
99 HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
102 HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
103 HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
104 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
105 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
106 HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
108 /* PFC/Pause commands */
109 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
110 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,
111 HNS3_OPC_CFG_MAC_PARA = 0x0703,
112 HNS3_OPC_CFG_PFC_PARA = 0x0704,
113 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
114 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
115 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
116 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
117 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,
118 HNS3_OPC_QOS_MAP = 0x070A,
120 /* ETS/scheduler commands */
121 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,
122 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,
123 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,
124 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,
125 HNS3_OPC_TM_PORT_WEIGHT = 0x0808,
126 HNS3_OPC_TM_PG_WEIGHT = 0x0809,
127 HNS3_OPC_TM_QS_WEIGHT = 0x080A,
128 HNS3_OPC_TM_PRI_WEIGHT = 0x080B,
129 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,
130 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,
131 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E,
132 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F,
133 HNS3_OPC_TM_PORT_SHAPPING = 0x0810,
134 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
135 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
136 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
137 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
138 HNS3_OPC_ETS_TC_WEIGHT = 0x0843,
139 HNS3_OPC_QSET_DFX_STS = 0x0844,
140 HNS3_OPC_PRI_DFX_STS = 0x0845,
141 HNS3_OPC_PG_DFX_STS = 0x0846,
142 HNS3_OPC_PORT_DFX_STS = 0x0847,
143 HNS3_OPC_SCH_NQ_CNT = 0x0848,
144 HNS3_OPC_SCH_RQ_CNT = 0x0849,
145 HNS3_OPC_TM_INTERNAL_STS = 0x0850,
146 HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
147 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
150 HNS3_OPC_MBX_VF_TO_PF = 0x2001,
152 /* Packet buffer allocate commands */
153 HNS3_OPC_TX_BUFF_ALLOC = 0x0901,
154 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
155 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,
156 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
157 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
159 /* TQP management command */
160 HNS3_OPC_SET_TQP_MAP = 0x0A01,
163 HNS3_OPC_QUERY_TX_STATUS = 0x0B03,
164 HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
165 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
166 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
167 HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23,
170 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
171 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
174 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,
175 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,
176 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07,
177 HNS3_OPC_RSS_TC_MODE = 0x0D08,
179 /* Promisuous mode command */
180 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01,
182 /* Vlan offload commands */
183 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,
184 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,
187 HNS3_OPC_MAC_VLAN_ADD = 0x1000,
188 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001,
189 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,
190 HNS3_OPC_MAC_VLAN_INSERT = 0x1003,
191 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,
192 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,
195 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100,
196 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,
197 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,
199 /* Flow Director command */
200 HNS3_OPC_FD_MODE_CTRL = 0x1200,
201 HNS3_OPC_FD_GET_ALLOCATION = 0x1201,
202 HNS3_OPC_FD_KEY_CONFIG = 0x1202,
203 HNS3_OPC_FD_TCAM_OP = 0x1203,
204 HNS3_OPC_FD_AD_OP = 0x1204,
205 HNS3_OPC_FD_COUNTER_OP = 0x1205,
207 /* Clear hardware state command */
208 HNS3_OPC_CLEAR_HW_STATE = 0x700B,
210 /* Firmware stats command */
211 HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A,
214 HNS3_OPC_SFP_GET_SPEED = 0x7104,
216 /* Interrupts commands */
217 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
218 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
220 /* Error INT commands */
221 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E,
222 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829,
223 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989,
224 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C,
225 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40,
226 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41,
227 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42,
228 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505,
229 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
230 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
231 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512,
232 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
233 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
234 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
235 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803,
236 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806,
237 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14,
238 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100,
239 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101,
240 HNS3_OPC_NCSI_INT_EN = 0x2401,
243 #define HNS3_CMD_FLAG_IN BIT(0)
244 #define HNS3_CMD_FLAG_OUT BIT(1)
245 #define HNS3_CMD_FLAG_NEXT BIT(2)
246 #define HNS3_CMD_FLAG_WR BIT(3)
247 #define HNS3_CMD_FLAG_NO_INTR BIT(4)
248 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
250 #define HNS3_MPF_RAS_INT_MIN_BD_NUM 10
251 #define HNS3_PF_RAS_INT_MIN_BD_NUM 4
252 #define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10
253 #define HNS3_PF_MSIX_INT_MIN_BD_NUM 4
255 #define HNS3_BUF_SIZE_UNIT 256
256 #define HNS3_BUF_MUL_BY 2
257 #define HNS3_BUF_DIV_BY 2
258 #define NEED_RESERVE_TC_NUM 2
259 #define BUF_MAX_PERCENT 100
260 #define BUF_RESERVE_PERCENT 90
262 #define HNS3_MAX_TC_NUM 8
263 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
264 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
265 #define HNS3_TX_BUFF_RSV_NUM 8
266 struct hns3_tx_buff_alloc_cmd {
267 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];
268 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];
271 struct hns3_rx_priv_buff_cmd {
272 uint16_t buf_num[HNS3_MAX_TC_NUM];
277 #define HNS3_FW_VERSION_BYTE3_S 24
278 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24)
279 #define HNS3_FW_VERSION_BYTE2_S 16
280 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16)
281 #define HNS3_FW_VERSION_BYTE1_S 8
282 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
283 #define HNS3_FW_VERSION_BYTE0_S 0
284 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
286 enum HNS3_CAPS_BITS {
289 HNS3_CAPS_FD_QUEUE_REGION_B,
292 HNS3_CAPS_SIMPLE_BD_B,
295 HNS3_CAPS_TQP_TXRX_INDEP_B,
300 enum HNS3_API_CAP_BITS {
301 HNS3_API_CAP_FLEX_RSS_TBL_B,
304 #define HNS3_QUERY_CAP_LENGTH 3
305 struct hns3_query_version_cmd {
309 uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
312 #define HNS3_RX_PRIV_EN_B 15
313 #define HNS3_TC_NUM_ONE_DESC 4
314 struct hns3_priv_wl {
319 struct hns3_rx_priv_wl_buf {
320 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];
323 struct hns3_rx_com_thrd {
324 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];
327 struct hns3_rx_com_wl {
328 struct hns3_priv_wl com_wl;
331 struct hns3_waterline {
336 struct hns3_tc_thrd {
341 struct hns3_priv_buf {
342 struct hns3_waterline wl; /* Waterline for low and high */
343 uint32_t buf_size; /* TC private buffer size */
344 uint32_t tx_buf_size;
345 uint32_t enable; /* Enable TC private buffer or not */
348 struct hns3_shared_buf {
349 struct hns3_waterline self;
350 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];
354 struct hns3_pkt_buf_alloc {
355 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];
356 struct hns3_shared_buf s_buf;
359 #define HNS3_RX_COM_WL_EN_B 15
360 struct hns3_rx_com_wl_buf_cmd {
366 #define HNS3_RX_PKT_EN_B 15
367 struct hns3_rx_pkt_buf_cmd {
373 #define HNS3_PF_STATE_DONE_B 0
374 #define HNS3_PF_STATE_MAIN_B 1
375 #define HNS3_PF_STATE_BOND_B 2
376 #define HNS3_PF_STATE_MAC_N_B 6
377 #define HNS3_PF_MAC_NUM_MASK 0x3
378 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B)
379 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B)
380 #define HNS3_VF_RST_STATE_NUM 4
381 struct hns3_func_status_cmd {
382 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];
386 uint8_t pf_cnt_in_mac;
392 #define HNS3_PF_VEC_NUM_S 0
393 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
394 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */
395 struct hns3_pf_res_cmd {
398 uint16_t msixcap_localid_ba_nic;
399 uint16_t nic_pf_intr_vector_number;
400 uint16_t roce_pf_intr_vector_number;
401 uint16_t pf_own_fun_number;
402 uint16_t tx_buf_size;
403 uint16_t dv_buf_size;
404 /* number of queues that exceed 1024 */
405 uint16_t ext_tqp_num;
406 uint16_t roh_pf_intr_vector_number;
410 #define HNS3_VF_VEC_NUM_S 0
411 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
412 struct hns3_vf_res_cmd {
415 uint16_t msixcap_localid_ba_nic;
416 uint16_t msixcap_localid_ba_rocee;
417 uint16_t vf_intr_vector_number;
421 #define HNS3_UMV_SPC_ALC_B 0
422 struct hns3_umv_spc_alc_cmd {
429 #define HNS3_CFG_OFFSET_S 0
430 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
431 #define HNS3_CFG_RD_LEN_S 24
432 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24)
433 #define HNS3_CFG_RD_LEN_BYTES 16
434 #define HNS3_CFG_RD_LEN_UNIT 4
436 #define HNS3_CFG_VMDQ_S 0
437 #define HNS3_CFG_VMDQ_M GENMASK(7, 0)
438 #define HNS3_CFG_TC_NUM_S 8
439 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
440 #define HNS3_CFG_TQP_DESC_N_S 16
441 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16)
442 #define HNS3_CFG_PHY_ADDR_S 0
443 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0)
444 #define HNS3_CFG_MEDIA_TP_S 8
445 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8)
446 #define HNS3_CFG_RX_BUF_LEN_S 16
447 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16)
448 #define HNS3_CFG_MAC_ADDR_H_S 0
449 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0)
450 #define HNS3_CFG_DEFAULT_SPEED_S 16
451 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
452 #define HNS3_CFG_RSS_SIZE_S 24
453 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24)
454 #define HNS3_CFG_SPEED_ABILITY_S 0
455 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0)
456 #define HNS3_CFG_UMV_TBL_SPACE_S 16
457 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
458 #define HNS3_CFG_EXT_RSS_SIZE_S 0
459 #define HNS3_CFG_EXT_RSS_SIZE_M GENMASK(3, 0)
461 #define HNS3_ACCEPT_TAG1_B 0
462 #define HNS3_ACCEPT_UNTAG1_B 1
463 #define HNS3_PORT_INS_TAG1_EN_B 2
464 #define HNS3_PORT_INS_TAG2_EN_B 3
465 #define HNS3_CFG_NIC_ROCE_SEL_B 4
466 #define HNS3_ACCEPT_TAG2_B 5
467 #define HNS3_ACCEPT_UNTAG2_B 6
468 #define HNS3_TAG_SHIFT_MODE_EN_B 7
470 #define HNS3_REM_TAG1_EN_B 0
471 #define HNS3_REM_TAG2_EN_B 1
472 #define HNS3_SHOW_TAG1_EN_B 2
473 #define HNS3_SHOW_TAG2_EN_B 3
474 #define HNS3_DISCARD_TAG1_EN_B 5
475 #define HNS3_DISCARD_TAG2_EN_B 6
477 /* Factor used to calculate offset and bitmap of VF num */
478 #define HNS3_VF_NUM_PER_CMD 64
479 #define HNS3_VF_NUM_PER_BYTE 8
481 struct hns3_cfg_param_cmd {
487 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8
488 struct hns3_vport_vtag_rx_cfg_cmd {
489 uint8_t vport_vlan_cfg;
492 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];
496 struct hns3_vport_vtag_tx_cfg_cmd {
497 uint8_t vport_vlan_cfg;
500 uint16_t def_vlan_tag1;
501 uint16_t def_vlan_tag2;
502 uint8_t vf_bitmap[8];
507 struct hns3_vlan_filter_ctrl_cmd {
515 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20
516 struct hns3_vlan_filter_pf_cfg_cmd {
520 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];
523 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16
524 struct hns3_vlan_filter_vf_cfg_cmd {
530 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];
533 struct hns3_tx_vlan_type_cfg_cmd {
534 uint16_t ot_vlan_type;
535 uint16_t in_vlan_type;
539 struct hns3_rx_vlan_type_cfg_cmd {
540 uint16_t ot_fst_vlan_type;
541 uint16_t ot_sec_vlan_type;
542 uint16_t in_fst_vlan_type;
543 uint16_t in_sec_vlan_type;
547 #define HNS3_TSO_MSS_MIN_S 0
548 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
550 #define HNS3_TSO_MSS_MAX_S 16
551 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16)
553 struct hns3_cfg_tso_status_cmd {
554 rte_le16_t tso_mss_min;
555 rte_le16_t tso_mss_max;
559 #define HNS3_GRO_EN_B 0
560 struct hns3_cfg_gro_status_cmd {
565 #define HNS3_TSO_MSS_MIN 256
566 #define HNS3_TSO_MSS_MAX 9668
568 #define HNS3_RSS_HASH_KEY_OFFSET_B 4
570 #define HNS3_RSS_CFG_TBL_SIZE 16
571 #define HNS3_RSS_HASH_KEY_NUM 16
572 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
573 struct hns3_rss_generic_config_cmd {
574 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */
577 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];
580 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */
581 struct hns3_rss_input_tuple_cmd {
582 uint64_t tuple_field;
586 #define HNS3_RSS_CFG_TBL_SIZE 16
587 #define HNS3_RSS_CFG_TBL_SIZE_H 4
588 #define HNS3_RSS_CFG_TBL_BW_H 2
589 #define HNS3_RSS_CFG_TBL_BW_L 8
591 /* Configure the indirection table, opcode:0x0D07 */
592 struct hns3_rss_indirection_table_cmd {
593 uint16_t start_table_index; /* Bit3~0 must be 0x0. */
594 uint16_t rss_set_bitmap;
595 uint8_t rss_result_h[HNS3_RSS_CFG_TBL_SIZE_H];
596 uint8_t rss_result_l[HNS3_RSS_CFG_TBL_SIZE];
599 #define HNS3_RSS_TC_OFFSET_S 0
600 #define HNS3_RSS_TC_OFFSET_M GENMASK(10, 0)
601 #define HNS3_RSS_TC_SIZE_MSB_S 11
602 #define HNS3_RSS_TC_SIZE_MSB_OFFSET 3
603 #define HNS3_RSS_TC_SIZE_S 12
604 #define HNS3_RSS_TC_SIZE_M GENMASK(14, 12)
605 #define HNS3_RSS_TC_VALID_B 15
607 /* Configure the tc_size and tc_offset, opcode:0x0D08 */
608 struct hns3_rss_tc_mode_cmd {
609 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM];
613 #define HNS3_LINK_STATUS_UP_B 0
614 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B)
615 struct hns3_link_status_cmd {
620 struct hns3_promisc_param {
625 #define HNS3_PROMISC_TX_EN_B BIT(4)
626 #define HNS3_PROMISC_RX_EN_B BIT(5)
627 #define HNS3_PROMISC_EN_B 1
628 #define HNS3_PROMISC_EN_ALL 0x7
629 #define HNS3_PROMISC_EN_UC 0x1
630 #define HNS3_PROMISC_EN_MC 0x2
631 #define HNS3_PROMISC_EN_BC 0x4
632 struct hns3_promisc_cfg_cmd {
639 enum hns3_promisc_type {
645 #define HNS3_LINK_EVENT_REPORT_EN_B 0
646 #define HNS3_NCSI_ERROR_REPORT_EN_B 1
647 struct hns3_firmware_compat_cmd {
652 #define HNS3_MAC_TX_EN_B 6
653 #define HNS3_MAC_RX_EN_B 7
654 #define HNS3_MAC_PAD_TX_B 11
655 #define HNS3_MAC_PAD_RX_B 12
656 #define HNS3_MAC_1588_TX_B 13
657 #define HNS3_MAC_1588_RX_B 14
658 #define HNS3_MAC_APP_LP_B 15
659 #define HNS3_MAC_LINE_LP_B 16
660 #define HNS3_MAC_FCS_TX_B 17
661 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18
662 #define HNS3_MAC_RX_FCS_STRIP_B 19
663 #define HNS3_MAC_RX_FCS_B 20
664 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21
665 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22
667 struct hns3_config_mac_mode_cmd {
668 uint32_t txrx_pad_fcs_loop_en;
672 #define HNS3_CFG_SPEED_10M 6
673 #define HNS3_CFG_SPEED_100M 7
674 #define HNS3_CFG_SPEED_1G 0
675 #define HNS3_CFG_SPEED_10G 1
676 #define HNS3_CFG_SPEED_25G 2
677 #define HNS3_CFG_SPEED_40G 3
678 #define HNS3_CFG_SPEED_50G 4
679 #define HNS3_CFG_SPEED_100G 5
680 #define HNS3_CFG_SPEED_200G 8
682 #define HNS3_CFG_SPEED_S 0
683 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
684 #define HNS3_CFG_DUPLEX_B 7
685 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B)
687 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0
689 struct hns3_config_mac_speed_dup_cmd {
691 uint8_t mac_change_fec_en;
695 #define HNS3_TQP_ENABLE_B 0
697 #define HNS3_MAC_CFG_AN_EN_B 0
698 #define HNS3_MAC_CFG_AN_INT_EN_B 1
699 #define HNS3_MAC_CFG_AN_INT_MSK_B 2
700 #define HNS3_MAC_CFG_AN_INT_CLR_B 3
701 #define HNS3_MAC_CFG_AN_RST_B 4
703 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B)
705 struct hns3_config_auto_neg_cmd {
706 uint32_t cfg_an_cmd_flag;
710 #define HNS3_MAC_CFG_FEC_AUTO_EN_B 0
711 #define HNS3_MAC_CFG_FEC_MODE_S 1
712 #define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
713 #define HNS3_MAC_FEC_OFF 0
714 #define HNS3_MAC_FEC_BASER 1
715 #define HNS3_MAC_FEC_RS 2
717 struct hns3_sfp_speed_cmd {
719 uint8_t query_type; /* 0: sfp speed, 1: active fec */
720 uint8_t active_fec; /* current FEC mode */
725 /* Configure FEC mode, opcode:0x031A */
726 struct hns3_config_fec_cmd {
731 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
732 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1)
733 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
734 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc
736 struct hns3_mac_mgr_tbl_entry_cmd {
740 uint32_t mac_addr_hi32;
741 uint16_t mac_addr_lo16;
743 uint16_t ethter_type;
744 uint16_t egress_port;
745 uint16_t egress_queue;
746 uint8_t sw_port_id_aware;
748 uint8_t i_port_bitmap;
749 uint8_t i_port_direction;
753 struct hns3_cfg_com_tqp_queue_cmd {
760 #define HNS3_TQP_MAP_TYPE_PF 0
761 #define HNS3_TQP_MAP_TYPE_VF 1
762 #define HNS3_TQP_MAP_TYPE_B 0
763 #define HNS3_TQP_MAP_EN_B 1
765 struct hns3_tqp_map_cmd {
766 uint16_t tqp_id; /* Absolute tqp id for in this pf */
767 uint8_t tqp_vf; /* VF id */
768 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */
769 uint16_t tqp_vid; /* Virtual id in this pf/vf */
773 enum hns3_ring_type {
778 enum hns3_int_gl_idx {
781 HNS3_RING_GL_IMMEDIATE = 3
784 #define HNS3_RING_GL_IDX_S 0
785 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
787 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10
789 #define HNS3_INT_TYPE_S 0
790 #define HNS3_INT_TYPE_M GENMASK(1, 0)
791 #define HNS3_TQP_ID_S 2
792 #define HNS3_TQP_ID_M GENMASK(12, 2)
793 #define HNS3_INT_GL_IDX_S 13
794 #define HNS3_INT_GL_IDX_M GENMASK(14, 13)
795 #define HNS3_TQP_INT_ID_L_S 0
796 #define HNS3_TQP_INT_ID_L_M GENMASK(7, 0)
797 #define HNS3_TQP_INT_ID_H_S 8
798 #define HNS3_TQP_INT_ID_H_M GENMASK(15, 8)
799 struct hns3_ctrl_vector_chain_cmd {
800 uint8_t int_vector_id; /* the low order of the interrupt id */
801 uint8_t int_cause_num;
802 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
804 uint8_t int_vector_id_h; /* the high order of the interrupt id */
807 struct hns3_config_max_frm_size_cmd {
808 uint16_t max_frm_size;
809 uint8_t min_frm_size;
813 enum hns3_mac_vlan_tbl_opcode {
814 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
815 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */
816 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
817 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
820 enum hns3_mac_vlan_add_resp_code {
821 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
822 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
825 #define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
827 #define HNS3_MAC_VLAN_BIT0_EN_B 0
828 #define HNS3_MAC_VLAN_BIT1_EN_B 1
829 #define HNS3_MAC_EPORT_SW_EN_B 12
830 #define HNS3_MAC_EPORT_TYPE_B 11
831 #define HNS3_MAC_EPORT_VFID_S 3
832 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3)
833 #define HNS3_MAC_EPORT_PFID_S 0
834 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0)
835 struct hns3_mac_vlan_tbl_entry_cmd {
839 uint32_t mac_addr_hi32;
840 uint16_t mac_addr_lo16;
844 uint16_t egress_port;
845 uint16_t egress_queue;
849 #define HNS3_TQP_RESET_B 0
850 struct hns3_reset_tqp_queue_cmd {
853 uint8_t ready_to_reset;
854 uint8_t queue_direction;
858 #define HNS3_CFG_RESET_MAC_B 3
859 #define HNS3_CFG_RESET_FUNC_B 7
860 struct hns3_reset_cmd {
861 uint8_t mac_func_reset;
862 uint8_t fun_reset_vfid;
866 #define HNS3_QUERY_DEV_SPECS_BD_NUM 4
867 struct hns3_dev_specs_0_cmd {
869 uint32_t mac_entry_num;
870 uint32_t mng_entry_num;
871 uint16_t rss_ind_tbl_size;
872 uint16_t rss_key_size;
873 uint16_t intr_ql_max;
874 uint8_t max_non_tso_bd_num;
876 uint32_t max_tm_rate;
879 #define HNS3_MAX_TQP_NUM_HIP08_PF 64
880 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
881 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
882 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */
883 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
884 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
886 #define HNS3_TYPE_CRQ 0
887 #define HNS3_TYPE_CSQ 1
889 #define HNS3_NIC_SW_RST_RDY_B 16
890 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B)
891 #define HNS3_NIC_CMQ_DESC_NUM 1024
892 #define HNS3_NIC_CMQ_DESC_NUM_S 3
894 #define HNS3_CMD_SEND_SYNC(flag) \
895 ((flag) & HNS3_CMD_FLAG_NO_INTR)
897 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);
898 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,
899 enum hns3_opcode_type opcode, bool is_read);
900 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);
901 int hns3_cmd_init_queue(struct hns3_hw *hw);
902 int hns3_cmd_init(struct hns3_hw *hw);
903 void hns3_cmd_destroy_queue(struct hns3_hw *hw);
904 void hns3_cmd_uninit(struct hns3_hw *hw);
906 #endif /* _HNS3_CMD_H_ */