1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_CMDQ_TX_TIMEOUT 30000
9 #define HNS3_CMDQ_RX_INVLD_B 0
10 #define HNS3_CMDQ_RX_OUTVLD_B 1
11 #define HNS3_CMD_DESC_ALIGNMENT 4096
12 #define HNS3_QUEUE_ID_MASK 0x1ff
13 #define HNS3_CMD_FLAG_NEXT BIT(2)
17 #define HNS3_CMD_DESC_DATA_NUM 6
18 struct hns3_cmd_desc {
23 uint32_t data[HNS3_CMD_DESC_DATA_NUM];
26 struct hns3_cmq_ring {
27 uint64_t desc_dma_addr;
28 struct hns3_cmd_desc *desc;
32 uint16_t desc_num; /* max number of cmq descriptor */
34 uint32_t next_to_clean;
35 uint8_t ring_type; /* cmq ring type */
36 rte_spinlock_t lock; /* Command queue lock */
38 const void *zone; /* memory zone */
41 enum hns3_cmd_return_status {
42 HNS3_CMD_EXEC_SUCCESS = 0,
44 HNS3_CMD_NOT_SUPPORTED = 2,
45 HNS3_CMD_QUEUE_FULL = 3,
46 HNS3_CMD_NEXT_ERR = 4,
47 HNS3_CMD_UNEXE_ERR = 5,
48 HNS3_CMD_PARA_ERR = 6,
49 HNS3_CMD_RESULT_ERR = 7,
51 HNS3_CMD_HILINK_ERR = 9,
52 HNS3_CMD_QUEUE_ILLEGAL = 10,
53 HNS3_CMD_INVALID = 11,
56 enum hns3_cmd_status {
57 HNS3_STATUS_SUCCESS = 0,
58 HNS3_ERR_CSQ_FULL = -1,
59 HNS3_ERR_CSQ_TIMEOUT = -2,
60 HNS3_ERR_CSQ_ERROR = -3,
63 struct hns3_misc_vector {
69 struct hns3_cmq_ring csq;
70 struct hns3_cmq_ring crq;
72 enum hns3_cmd_status last_status;
75 enum hns3_opcode_type {
76 /* Generic commands */
77 HNS3_OPC_QUERY_FW_VER = 0x0001,
78 HNS3_OPC_CFG_RST_TRIGGER = 0x0020,
79 HNS3_OPC_GBL_RST_STATUS = 0x0021,
80 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
81 HNS3_OPC_QUERY_PF_RSRC = 0x0023,
82 HNS3_OPC_QUERY_VF_RSRC = 0x0024,
83 HNS3_OPC_GET_CFG_PARAM = 0x0025,
84 HNS3_OPC_PF_RST_DONE = 0x0026,
86 HNS3_OPC_STATS_64_BIT = 0x0030,
87 HNS3_OPC_STATS_32_BIT = 0x0031,
88 HNS3_OPC_STATS_MAC = 0x0032,
89 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,
90 HNS3_OPC_STATS_MAC_ALL = 0x0034,
92 HNS3_OPC_QUERY_REG_NUM = 0x0040,
93 HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
94 HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
96 HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
99 HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
100 HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
101 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
102 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
104 /* PFC/Pause commands */
105 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
106 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,
107 HNS3_OPC_CFG_MAC_PARA = 0x0703,
108 HNS3_OPC_CFG_PFC_PARA = 0x0704,
109 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
110 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
111 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
112 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
113 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,
114 HNS3_OPC_QOS_MAP = 0x070A,
116 /* ETS/scheduler commands */
117 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,
118 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,
119 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,
120 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,
121 HNS3_OPC_TM_PORT_WEIGHT = 0x0808,
122 HNS3_OPC_TM_PG_WEIGHT = 0x0809,
123 HNS3_OPC_TM_QS_WEIGHT = 0x080A,
124 HNS3_OPC_TM_PRI_WEIGHT = 0x080B,
125 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,
126 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,
127 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E,
128 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F,
129 HNS3_OPC_TM_PORT_SHAPPING = 0x0810,
130 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
131 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
132 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
133 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
134 HNS3_OPC_ETS_TC_WEIGHT = 0x0843,
135 HNS3_OPC_QSET_DFX_STS = 0x0844,
136 HNS3_OPC_PRI_DFX_STS = 0x0845,
137 HNS3_OPC_PG_DFX_STS = 0x0846,
138 HNS3_OPC_PORT_DFX_STS = 0x0847,
139 HNS3_OPC_SCH_NQ_CNT = 0x0848,
140 HNS3_OPC_SCH_RQ_CNT = 0x0849,
141 HNS3_OPC_TM_INTERNAL_STS = 0x0850,
142 HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
143 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
146 HNS3_OPC_MBX_VF_TO_PF = 0x2001,
148 /* Packet buffer allocate commands */
149 HNS3_OPC_TX_BUFF_ALLOC = 0x0901,
150 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
151 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,
152 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
153 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
155 /* TQP management command */
156 HNS3_OPC_SET_TQP_MAP = 0x0A01,
159 HNS3_OPC_QUERY_TX_STATUS = 0x0B03,
160 HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
161 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
162 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
165 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
166 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
169 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,
170 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,
171 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07,
172 HNS3_OPC_RSS_TC_MODE = 0x0D08,
174 /* Promisuous mode command */
175 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01,
177 /* Vlan offload commands */
178 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,
179 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,
182 HNS3_OPC_MAC_VLAN_ADD = 0x1000,
183 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001,
184 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,
185 HNS3_OPC_MAC_VLAN_INSERT = 0x1003,
186 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,
187 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,
190 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100,
191 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,
192 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,
194 /* Flow Director command */
195 HNS3_OPC_FD_MODE_CTRL = 0x1200,
196 HNS3_OPC_FD_GET_ALLOCATION = 0x1201,
197 HNS3_OPC_FD_KEY_CONFIG = 0x1202,
198 HNS3_OPC_FD_TCAM_OP = 0x1203,
199 HNS3_OPC_FD_AD_OP = 0x1204,
200 HNS3_OPC_FD_COUNTER_OP = 0x1205,
202 /* Clear hardware state command */
203 HNS3_OPC_CLEAR_HW_STATE = 0x700A,
206 HNS3_OPC_SFP_GET_SPEED = 0x7104,
208 /* Interrupts commands */
209 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
210 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
212 /* Error INT commands */
213 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E,
214 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829,
215 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989,
216 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C,
217 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40,
218 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41,
219 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42,
220 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505,
221 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
222 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
223 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512,
224 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
225 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
226 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
227 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803,
228 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806,
229 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14,
230 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100,
231 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101,
232 HNS3_OPC_NCSI_INT_EN = 0x2401,
235 #define HNS3_CMD_FLAG_IN BIT(0)
236 #define HNS3_CMD_FLAG_OUT BIT(1)
237 #define HNS3_CMD_FLAG_NEXT BIT(2)
238 #define HNS3_CMD_FLAG_WR BIT(3)
239 #define HNS3_CMD_FLAG_NO_INTR BIT(4)
240 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
242 #define HNS3_MPF_RAS_INT_MIN_BD_NUM 10
243 #define HNS3_PF_RAS_INT_MIN_BD_NUM 4
244 #define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10
245 #define HNS3_PF_MSIX_INT_MIN_BD_NUM 4
247 #define HNS3_BUF_SIZE_UNIT 256
248 #define HNS3_BUF_MUL_BY 2
249 #define HNS3_BUF_DIV_BY 2
250 #define NEED_RESERVE_TC_NUM 2
251 #define BUF_MAX_PERCENT 100
252 #define BUF_RESERVE_PERCENT 90
254 #define HNS3_MAX_TC_NUM 8
255 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
256 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
257 #define HNS3_TX_BUFF_RSV_NUM 8
258 struct hns3_tx_buff_alloc_cmd {
259 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];
260 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];
263 struct hns3_rx_priv_buff_cmd {
264 uint16_t buf_num[HNS3_MAX_TC_NUM];
269 #define HNS3_FW_VERSION_BYTE3_S 24
270 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24)
271 #define HNS3_FW_VERSION_BYTE2_S 16
272 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16)
273 #define HNS3_FW_VERSION_BYTE1_S 8
274 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
275 #define HNS3_FW_VERSION_BYTE0_S 0
276 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
278 enum HNS3_CAPS_BITS {
284 HNS3_CAPS_SIMPLE_BD_B,
287 HNS3_CAPS_TQP_TXRX_INDEP_B,
291 #define HNS3_QUERY_CAP_LENGTH 3
292 struct hns3_query_version_cmd {
296 uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
299 #define HNS3_RX_PRIV_EN_B 15
300 #define HNS3_TC_NUM_ONE_DESC 4
301 struct hns3_priv_wl {
306 struct hns3_rx_priv_wl_buf {
307 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];
310 struct hns3_rx_com_thrd {
311 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];
314 struct hns3_rx_com_wl {
315 struct hns3_priv_wl com_wl;
318 struct hns3_waterline {
323 struct hns3_tc_thrd {
328 struct hns3_priv_buf {
329 struct hns3_waterline wl; /* Waterline for low and high */
330 uint32_t buf_size; /* TC private buffer size */
331 uint32_t tx_buf_size;
332 uint32_t enable; /* Enable TC private buffer or not */
335 struct hns3_shared_buf {
336 struct hns3_waterline self;
337 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];
341 struct hns3_pkt_buf_alloc {
342 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];
343 struct hns3_shared_buf s_buf;
346 #define HNS3_RX_COM_WL_EN_B 15
347 struct hns3_rx_com_wl_buf_cmd {
353 #define HNS3_RX_PKT_EN_B 15
354 struct hns3_rx_pkt_buf_cmd {
360 #define HNS3_PF_STATE_DONE_B 0
361 #define HNS3_PF_STATE_MAIN_B 1
362 #define HNS3_PF_STATE_BOND_B 2
363 #define HNS3_PF_STATE_MAC_N_B 6
364 #define HNS3_PF_MAC_NUM_MASK 0x3
365 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B)
366 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B)
367 #define HNS3_VF_RST_STATE_NUM 4
368 struct hns3_func_status_cmd {
369 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];
373 uint8_t pf_cnt_in_mac;
379 #define HNS3_PF_VEC_NUM_S 0
380 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
381 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */
382 struct hns3_pf_res_cmd {
385 uint16_t msixcap_localid_ba_nic;
386 uint16_t nic_pf_intr_vector_number;
387 uint16_t roce_pf_intr_vector_number;
388 uint16_t pf_own_fun_number;
389 uint16_t tx_buf_size;
390 uint16_t dv_buf_size;
391 uint16_t tqp_num_ext;
392 uint16_t roh_pf_intr_vector_number;
396 #define HNS3_VF_VEC_NUM_S 0
397 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
398 struct hns3_vf_res_cmd {
401 uint16_t msixcap_localid_ba_nic;
402 uint16_t msixcap_localid_ba_rocee;
403 uint16_t vf_intr_vector_number;
407 #define HNS3_UMV_SPC_ALC_B 0
408 struct hns3_umv_spc_alc_cmd {
415 #define HNS3_CFG_OFFSET_S 0
416 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
417 #define HNS3_CFG_RD_LEN_S 24
418 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24)
419 #define HNS3_CFG_RD_LEN_BYTES 16
420 #define HNS3_CFG_RD_LEN_UNIT 4
422 #define HNS3_CFG_VMDQ_S 0
423 #define HNS3_CFG_VMDQ_M GENMASK(7, 0)
424 #define HNS3_CFG_TC_NUM_S 8
425 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
426 #define HNS3_CFG_TQP_DESC_N_S 16
427 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16)
428 #define HNS3_CFG_PHY_ADDR_S 0
429 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0)
430 #define HNS3_CFG_MEDIA_TP_S 8
431 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8)
432 #define HNS3_CFG_RX_BUF_LEN_S 16
433 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16)
434 #define HNS3_CFG_MAC_ADDR_H_S 0
435 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0)
436 #define HNS3_CFG_DEFAULT_SPEED_S 16
437 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
438 #define HNS3_CFG_RSS_SIZE_S 24
439 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24)
440 #define HNS3_CFG_SPEED_ABILITY_S 0
441 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0)
442 #define HNS3_CFG_UMV_TBL_SPACE_S 16
443 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
445 #define HNS3_ACCEPT_TAG1_B 0
446 #define HNS3_ACCEPT_UNTAG1_B 1
447 #define HNS3_PORT_INS_TAG1_EN_B 2
448 #define HNS3_PORT_INS_TAG2_EN_B 3
449 #define HNS3_CFG_NIC_ROCE_SEL_B 4
450 #define HNS3_ACCEPT_TAG2_B 5
451 #define HNS3_ACCEPT_UNTAG2_B 6
453 #define HNS3_REM_TAG1_EN_B 0
454 #define HNS3_REM_TAG2_EN_B 1
455 #define HNS3_SHOW_TAG1_EN_B 2
456 #define HNS3_SHOW_TAG2_EN_B 3
458 /* Factor used to calculate offset and bitmap of VF num */
459 #define HNS3_VF_NUM_PER_CMD 64
460 #define HNS3_VF_NUM_PER_BYTE 8
462 struct hns3_cfg_param_cmd {
468 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8
469 struct hns3_vport_vtag_rx_cfg_cmd {
470 uint8_t vport_vlan_cfg;
473 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];
477 struct hns3_vport_vtag_tx_cfg_cmd {
478 uint8_t vport_vlan_cfg;
481 uint16_t def_vlan_tag1;
482 uint16_t def_vlan_tag2;
483 uint8_t vf_bitmap[8];
488 struct hns3_vlan_filter_ctrl_cmd {
496 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20
497 struct hns3_vlan_filter_pf_cfg_cmd {
501 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];
504 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16
505 struct hns3_vlan_filter_vf_cfg_cmd {
511 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];
514 struct hns3_tx_vlan_type_cfg_cmd {
515 uint16_t ot_vlan_type;
516 uint16_t in_vlan_type;
520 struct hns3_rx_vlan_type_cfg_cmd {
521 uint16_t ot_fst_vlan_type;
522 uint16_t ot_sec_vlan_type;
523 uint16_t in_fst_vlan_type;
524 uint16_t in_sec_vlan_type;
528 #define HNS3_TSO_MSS_MIN_S 0
529 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
531 #define HNS3_TSO_MSS_MAX_S 16
532 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16)
534 struct hns3_cfg_tso_status_cmd {
535 rte_le16_t tso_mss_min;
536 rte_le16_t tso_mss_max;
540 #define HNS3_GRO_EN_B 0
541 struct hns3_cfg_gro_status_cmd {
546 #define HNS3_TSO_MSS_MIN 256
547 #define HNS3_TSO_MSS_MAX 9668
549 #define HNS3_RSS_HASH_KEY_OFFSET_B 4
551 #define HNS3_RSS_CFG_TBL_SIZE 16
552 #define HNS3_RSS_HASH_KEY_NUM 16
553 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
554 struct hns3_rss_generic_config_cmd {
555 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */
558 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];
561 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */
562 struct hns3_rss_input_tuple_cmd {
565 uint8_t ipv4_sctp_en;
566 uint8_t ipv4_fragment_en;
569 uint8_t ipv6_sctp_en;
570 uint8_t ipv6_fragment_en;
574 #define HNS3_RSS_CFG_TBL_SIZE 16
576 /* Configure the indirection table, opcode:0x0D07 */
577 struct hns3_rss_indirection_table_cmd {
578 uint16_t start_table_index; /* Bit3~0 must be 0x0. */
579 uint16_t rss_set_bitmap;
581 uint8_t rss_result[HNS3_RSS_CFG_TBL_SIZE];
584 #define HNS3_RSS_TC_OFFSET_S 0
585 #define HNS3_RSS_TC_OFFSET_M (0x3ff << HNS3_RSS_TC_OFFSET_S)
586 #define HNS3_RSS_TC_SIZE_S 12
587 #define HNS3_RSS_TC_SIZE_M (0x7 << HNS3_RSS_TC_SIZE_S)
588 #define HNS3_RSS_TC_VALID_B 15
590 /* Configure the tc_size and tc_offset, opcode:0x0D08 */
591 struct hns3_rss_tc_mode_cmd {
592 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM];
596 #define HNS3_LINK_STATUS_UP_B 0
597 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B)
598 struct hns3_link_status_cmd {
603 struct hns3_promisc_param {
608 #define HNS3_PROMISC_TX_EN_B BIT(4)
609 #define HNS3_PROMISC_RX_EN_B BIT(5)
610 #define HNS3_PROMISC_EN_B 1
611 #define HNS3_PROMISC_EN_ALL 0x7
612 #define HNS3_PROMISC_EN_UC 0x1
613 #define HNS3_PROMISC_EN_MC 0x2
614 #define HNS3_PROMISC_EN_BC 0x4
615 struct hns3_promisc_cfg_cmd {
622 enum hns3_promisc_type {
628 #define HNS3_MAC_TX_EN_B 6
629 #define HNS3_MAC_RX_EN_B 7
630 #define HNS3_MAC_PAD_TX_B 11
631 #define HNS3_MAC_PAD_RX_B 12
632 #define HNS3_MAC_1588_TX_B 13
633 #define HNS3_MAC_1588_RX_B 14
634 #define HNS3_MAC_APP_LP_B 15
635 #define HNS3_MAC_LINE_LP_B 16
636 #define HNS3_MAC_FCS_TX_B 17
637 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18
638 #define HNS3_MAC_RX_FCS_STRIP_B 19
639 #define HNS3_MAC_RX_FCS_B 20
640 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21
641 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22
643 struct hns3_config_mac_mode_cmd {
644 uint32_t txrx_pad_fcs_loop_en;
648 #define HNS3_CFG_SPEED_10M 6
649 #define HNS3_CFG_SPEED_100M 7
650 #define HNS3_CFG_SPEED_1G 0
651 #define HNS3_CFG_SPEED_10G 1
652 #define HNS3_CFG_SPEED_25G 2
653 #define HNS3_CFG_SPEED_40G 3
654 #define HNS3_CFG_SPEED_50G 4
655 #define HNS3_CFG_SPEED_100G 5
656 #define HNS3_CFG_SPEED_200G 8
658 #define HNS3_CFG_SPEED_S 0
659 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
660 #define HNS3_CFG_DUPLEX_B 7
661 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B)
663 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0
665 struct hns3_config_mac_speed_dup_cmd {
667 uint8_t mac_change_fec_en;
671 #define HNS3_RING_ID_MASK GENMASK(9, 0)
672 #define HNS3_TQP_ENABLE_B 0
674 #define HNS3_MAC_CFG_AN_EN_B 0
675 #define HNS3_MAC_CFG_AN_INT_EN_B 1
676 #define HNS3_MAC_CFG_AN_INT_MSK_B 2
677 #define HNS3_MAC_CFG_AN_INT_CLR_B 3
678 #define HNS3_MAC_CFG_AN_RST_B 4
680 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B)
682 struct hns3_config_auto_neg_cmd {
683 uint32_t cfg_an_cmd_flag;
687 struct hns3_sfp_speed_cmd {
692 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
693 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1)
694 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
695 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc
697 struct hns3_mac_mgr_tbl_entry_cmd {
701 uint32_t mac_addr_hi32;
702 uint16_t mac_addr_lo16;
704 uint16_t ethter_type;
705 uint16_t egress_port;
706 uint16_t egress_queue;
707 uint8_t sw_port_id_aware;
709 uint8_t i_port_bitmap;
710 uint8_t i_port_direction;
714 struct hns3_cfg_com_tqp_queue_cmd {
721 #define HNS3_TQP_MAP_TYPE_PF 0
722 #define HNS3_TQP_MAP_TYPE_VF 1
723 #define HNS3_TQP_MAP_TYPE_B 0
724 #define HNS3_TQP_MAP_EN_B 1
726 struct hns3_tqp_map_cmd {
727 uint16_t tqp_id; /* Absolute tqp id for in this pf */
728 uint8_t tqp_vf; /* VF id */
729 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */
730 uint16_t tqp_vid; /* Virtual id in this pf/vf */
734 enum hns3_ring_type {
739 enum hns3_int_gl_idx {
742 HNS3_RING_GL_IMMEDIATE = 3
745 #define HNS3_RING_GL_IDX_S 0
746 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
748 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10
750 #define HNS3_INT_TYPE_S 0
751 #define HNS3_INT_TYPE_M GENMASK(1, 0)
752 #define HNS3_TQP_ID_S 2
753 #define HNS3_TQP_ID_M GENMASK(12, 2)
754 #define HNS3_INT_GL_IDX_S 13
755 #define HNS3_INT_GL_IDX_M GENMASK(14, 13)
756 struct hns3_ctrl_vector_chain_cmd {
757 uint8_t int_vector_id;
758 uint8_t int_cause_num;
759 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
764 struct hns3_config_max_frm_size_cmd {
765 uint16_t max_frm_size;
766 uint8_t min_frm_size;
770 enum hns3_mac_vlan_tbl_opcode {
771 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
772 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */
773 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
774 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
777 enum hns3_mac_vlan_add_resp_code {
778 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
779 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
782 #define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
784 #define HNS3_MAC_VLAN_BIT0_EN_B 0
785 #define HNS3_MAC_VLAN_BIT1_EN_B 1
786 #define HNS3_MAC_EPORT_SW_EN_B 12
787 #define HNS3_MAC_EPORT_TYPE_B 11
788 #define HNS3_MAC_EPORT_VFID_S 3
789 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3)
790 #define HNS3_MAC_EPORT_PFID_S 0
791 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0)
792 struct hns3_mac_vlan_tbl_entry_cmd {
796 uint32_t mac_addr_hi32;
797 uint16_t mac_addr_lo16;
801 uint16_t egress_port;
802 uint16_t egress_queue;
806 #define HNS3_TQP_RESET_B 0
807 struct hns3_reset_tqp_queue_cmd {
810 uint8_t ready_to_reset;
814 #define HNS3_CFG_RESET_MAC_B 3
815 #define HNS3_CFG_RESET_FUNC_B 7
816 struct hns3_reset_cmd {
817 uint8_t mac_func_reset;
818 uint8_t fun_reset_vfid;
822 #define HNS3_QUERY_DEV_SPECS_BD_NUM 4
823 struct hns3_dev_specs_0_cmd {
825 uint32_t mac_entry_num;
826 uint32_t mng_entry_num;
827 uint16_t rss_ind_tbl_size;
828 uint16_t rss_key_size;
829 uint16_t intr_ql_max;
830 uint8_t max_non_tso_bd_num;
832 uint32_t max_tm_rate;
835 #define HNS3_MAX_TQP_NUM_PER_FUNC 64
836 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
837 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
838 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */
839 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
840 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
842 #define HNS3_TYPE_CRQ 0
843 #define HNS3_TYPE_CSQ 1
845 #define HNS3_NIC_SW_RST_RDY_B 16
846 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B)
847 #define HNS3_NIC_CMQ_DESC_NUM 1024
848 #define HNS3_NIC_CMQ_DESC_NUM_S 3
850 #define HNS3_CMD_SEND_SYNC(flag) \
851 ((flag) & HNS3_CMD_FLAG_NO_INTR)
853 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);
854 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,
855 enum hns3_opcode_type opcode, bool is_read);
856 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);
857 int hns3_cmd_init_queue(struct hns3_hw *hw);
858 int hns3_cmd_init(struct hns3_hw *hw);
859 void hns3_cmd_destroy_queue(struct hns3_hw *hw);
860 void hns3_cmd_uninit(struct hns3_hw *hw);
862 #endif /* _HNS3_CMD_H_ */