1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_CMDQ_TX_TIMEOUT 30000
9 #define HNS3_CMDQ_RX_INVLD_B 0
10 #define HNS3_CMDQ_RX_OUTVLD_B 1
11 #define HNS3_CMD_DESC_ALIGNMENT 4096
12 #define HNS3_QUEUE_ID_MASK 0x1ff
13 #define HNS3_CMD_FLAG_NEXT BIT(2)
17 #define HNS3_CMD_DESC_DATA_NUM 6
18 struct hns3_cmd_desc {
23 uint32_t data[HNS3_CMD_DESC_DATA_NUM];
26 struct hns3_cmq_ring {
27 uint64_t desc_dma_addr;
28 struct hns3_cmd_desc *desc;
32 uint16_t desc_num; /* max number of cmq descriptor */
34 uint32_t next_to_clean;
35 uint8_t ring_type; /* cmq ring type */
36 rte_spinlock_t lock; /* Command queue lock */
38 const void *zone; /* memory zone */
41 enum hns3_cmd_return_status {
42 HNS3_CMD_EXEC_SUCCESS = 0,
44 HNS3_CMD_NOT_SUPPORTED = 2,
45 HNS3_CMD_QUEUE_FULL = 3,
46 HNS3_CMD_NEXT_ERR = 4,
47 HNS3_CMD_UNEXE_ERR = 5,
48 HNS3_CMD_PARA_ERR = 6,
49 HNS3_CMD_RESULT_ERR = 7,
51 HNS3_CMD_HILINK_ERR = 9,
52 HNS3_CMD_QUEUE_ILLEGAL = 10,
53 HNS3_CMD_INVALID = 11,
56 enum hns3_cmd_status {
57 HNS3_STATUS_SUCCESS = 0,
58 HNS3_ERR_CSQ_FULL = -1,
59 HNS3_ERR_CSQ_TIMEOUT = -2,
60 HNS3_ERR_CSQ_ERROR = -3,
63 struct hns3_misc_vector {
69 struct hns3_cmq_ring csq;
70 struct hns3_cmq_ring crq;
72 enum hns3_cmd_status last_status;
75 enum hns3_opcode_type {
76 /* Generic commands */
77 HNS3_OPC_QUERY_FW_VER = 0x0001,
78 HNS3_OPC_CFG_RST_TRIGGER = 0x0020,
79 HNS3_OPC_GBL_RST_STATUS = 0x0021,
80 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
81 HNS3_OPC_QUERY_PF_RSRC = 0x0023,
82 HNS3_OPC_QUERY_VF_RSRC = 0x0024,
83 HNS3_OPC_GET_CFG_PARAM = 0x0025,
84 HNS3_OPC_PF_RST_DONE = 0x0026,
86 HNS3_OPC_STATS_64_BIT = 0x0030,
87 HNS3_OPC_STATS_32_BIT = 0x0031,
88 HNS3_OPC_STATS_MAC = 0x0032,
89 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,
90 HNS3_OPC_STATS_MAC_ALL = 0x0034,
92 HNS3_OPC_QUERY_REG_NUM = 0x0040,
93 HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
94 HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
97 HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
98 HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
99 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
100 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
101 HNS3_MAC_COMMON_INT_EN = 0x030E,
103 /* PFC/Pause commands */
104 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
105 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,
106 HNS3_OPC_CFG_MAC_PARA = 0x0703,
107 HNS3_OPC_CFG_PFC_PARA = 0x0704,
108 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
109 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
110 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
111 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
112 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,
113 HNS3_OPC_QOS_MAP = 0x070A,
115 /* ETS/scheduler commands */
116 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,
117 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,
118 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,
119 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,
120 HNS3_OPC_TM_PORT_WEIGHT = 0x0808,
121 HNS3_OPC_TM_PG_WEIGHT = 0x0809,
122 HNS3_OPC_TM_QS_WEIGHT = 0x080A,
123 HNS3_OPC_TM_PRI_WEIGHT = 0x080B,
124 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,
125 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,
126 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E,
127 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F,
128 HNS3_OPC_TM_PORT_SHAPPING = 0x0810,
129 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
130 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
131 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
132 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
133 HNS3_OPC_ETS_TC_WEIGHT = 0x0843,
134 HNS3_OPC_QSET_DFX_STS = 0x0844,
135 HNS3_OPC_PRI_DFX_STS = 0x0845,
136 HNS3_OPC_PG_DFX_STS = 0x0846,
137 HNS3_OPC_PORT_DFX_STS = 0x0847,
138 HNS3_OPC_SCH_NQ_CNT = 0x0848,
139 HNS3_OPC_SCH_RQ_CNT = 0x0849,
140 HNS3_OPC_TM_INTERNAL_STS = 0x0850,
141 HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
142 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
145 HNS3_OPC_MBX_VF_TO_PF = 0x2001,
147 /* Packet buffer allocate commands */
148 HNS3_OPC_TX_BUFF_ALLOC = 0x0901,
149 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
150 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,
151 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
152 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
154 /* SSU module INT commands */
155 HNS3_SSU_ECC_INT_CMD = 0x0989,
156 HNS3_SSU_COMMON_INT_CMD = 0x098C,
158 /* TQP management command */
159 HNS3_OPC_SET_TQP_MAP = 0x0A01,
162 HNS3_OPC_QUERY_TX_STATUS = 0x0B03,
163 HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
164 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
165 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
167 /* PPU module intr commands */
168 HNS3_PPU_MPF_ECC_INT_CMD = 0x0B40,
169 HNS3_PPU_MPF_OTHER_INT_CMD = 0x0B41,
170 HNS3_PPU_PF_OTHER_INT_CMD = 0x0B42,
173 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
174 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
177 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,
178 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,
179 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07,
180 HNS3_OPC_RSS_TC_MODE = 0x0D08,
182 /* Promisuous mode command */
183 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01,
185 /* Vlan offload commands */
186 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,
187 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,
190 HNS3_OPC_MAC_VLAN_ADD = 0x1000,
191 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001,
192 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,
193 HNS3_OPC_MAC_VLAN_INSERT = 0x1003,
194 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,
195 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,
198 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100,
199 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,
200 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,
202 /* Flow Director command */
203 HNS3_OPC_FD_MODE_CTRL = 0x1200,
204 HNS3_OPC_FD_GET_ALLOCATION = 0x1201,
205 HNS3_OPC_FD_KEY_CONFIG = 0x1202,
206 HNS3_OPC_FD_TCAM_OP = 0x1203,
207 HNS3_OPC_FD_AD_OP = 0x1204,
208 HNS3_OPC_FD_COUNTER_OP = 0x1205,
211 HNS3_OPC_SFP_GET_SPEED = 0x7104,
213 /* Interrupts commands */
214 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
215 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
217 /* Error INT commands */
218 HNS3_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
219 HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
220 HNS3_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
222 /* PPP module intr commands */
223 HNS3_PPP_CMD0_INT_CMD = 0x2100,
224 HNS3_PPP_CMD1_INT_CMD = 0x2101,
227 #define HNS3_CMD_FLAG_IN BIT(0)
228 #define HNS3_CMD_FLAG_OUT BIT(1)
229 #define HNS3_CMD_FLAG_NEXT BIT(2)
230 #define HNS3_CMD_FLAG_WR BIT(3)
231 #define HNS3_CMD_FLAG_NO_INTR BIT(4)
232 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
234 #define HNS3_BUF_SIZE_UNIT 256
235 #define HNS3_BUF_MUL_BY 2
236 #define HNS3_BUF_DIV_BY 2
237 #define NEED_RESERVE_TC_NUM 2
238 #define BUF_MAX_PERCENT 100
239 #define BUF_RESERVE_PERCENT 90
241 #define HNS3_MAX_TC_NUM 8
242 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
243 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
244 #define HNS3_TX_BUFF_RSV_NUM 8
245 struct hns3_tx_buff_alloc_cmd {
246 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];
247 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];
250 struct hns3_rx_priv_buff_cmd {
251 uint16_t buf_num[HNS3_MAX_TC_NUM];
256 #define HNS3_FW_VERSION_BYTE3_S 24
257 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24)
258 #define HNS3_FW_VERSION_BYTE2_S 16
259 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16)
260 #define HNS3_FW_VERSION_BYTE1_S 8
261 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
262 #define HNS3_FW_VERSION_BYTE0_S 0
263 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
264 struct hns3_query_version_cmd {
266 uint32_t firmware_rsv[5];
269 #define HNS3_RX_PRIV_EN_B 15
270 #define HNS3_TC_NUM_ONE_DESC 4
271 struct hns3_priv_wl {
276 struct hns3_rx_priv_wl_buf {
277 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];
280 struct hns3_rx_com_thrd {
281 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];
284 struct hns3_rx_com_wl {
285 struct hns3_priv_wl com_wl;
288 struct hns3_waterline {
293 struct hns3_tc_thrd {
298 struct hns3_priv_buf {
299 struct hns3_waterline wl; /* Waterline for low and high */
300 uint32_t buf_size; /* TC private buffer size */
301 uint32_t tx_buf_size;
302 uint32_t enable; /* Enable TC private buffer or not */
305 struct hns3_shared_buf {
306 struct hns3_waterline self;
307 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];
311 struct hns3_pkt_buf_alloc {
312 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];
313 struct hns3_shared_buf s_buf;
316 #define HNS3_RX_COM_WL_EN_B 15
317 struct hns3_rx_com_wl_buf_cmd {
323 #define HNS3_RX_PKT_EN_B 15
324 struct hns3_rx_pkt_buf_cmd {
330 #define HNS3_PF_STATE_DONE_B 0
331 #define HNS3_PF_STATE_MAIN_B 1
332 #define HNS3_PF_STATE_BOND_B 2
333 #define HNS3_PF_STATE_MAC_N_B 6
334 #define HNS3_PF_MAC_NUM_MASK 0x3
335 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B)
336 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B)
337 #define HNS3_VF_RST_STATE_NUM 4
338 struct hns3_func_status_cmd {
339 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];
343 uint8_t pf_cnt_in_mac;
349 #define HNS3_VEC_NUM_S 0
350 #define HNS3_VEC_NUM_M GENMASK(7, 0)
351 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */
352 struct hns3_pf_res_cmd {
355 uint16_t msixcap_localid_ba_nic;
356 uint16_t msixcap_localid_ba_rocee;
357 uint16_t pf_intr_vector_number;
358 uint16_t pf_own_fun_number;
359 uint16_t tx_buf_size;
360 uint16_t dv_buf_size;
364 struct hns3_vf_res_cmd {
367 uint16_t msixcap_localid_ba_nic;
368 uint16_t msixcap_localid_ba_rocee;
369 uint16_t vf_intr_vector_number;
373 #define HNS3_UMV_SPC_ALC_B 0
374 struct hns3_umv_spc_alc_cmd {
381 #define HNS3_CFG_OFFSET_S 0
382 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
383 #define HNS3_CFG_RD_LEN_S 24
384 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24)
385 #define HNS3_CFG_RD_LEN_BYTES 16
386 #define HNS3_CFG_RD_LEN_UNIT 4
388 #define HNS3_CFG_VMDQ_S 0
389 #define HNS3_CFG_VMDQ_M GENMASK(7, 0)
390 #define HNS3_CFG_TC_NUM_S 8
391 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
392 #define HNS3_CFG_TQP_DESC_N_S 16
393 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16)
394 #define HNS3_CFG_PHY_ADDR_S 0
395 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0)
396 #define HNS3_CFG_MEDIA_TP_S 8
397 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8)
398 #define HNS3_CFG_RX_BUF_LEN_S 16
399 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16)
400 #define HNS3_CFG_MAC_ADDR_H_S 0
401 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0)
402 #define HNS3_CFG_DEFAULT_SPEED_S 16
403 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
404 #define HNS3_CFG_RSS_SIZE_S 24
405 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24)
406 #define HNS3_CFG_SPEED_ABILITY_S 0
407 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0)
408 #define HNS3_CFG_UMV_TBL_SPACE_S 16
409 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
411 #define HNS3_ACCEPT_TAG1_B 0
412 #define HNS3_ACCEPT_UNTAG1_B 1
413 #define HNS3_PORT_INS_TAG1_EN_B 2
414 #define HNS3_PORT_INS_TAG2_EN_B 3
415 #define HNS3_CFG_NIC_ROCE_SEL_B 4
416 #define HNS3_ACCEPT_TAG2_B 5
417 #define HNS3_ACCEPT_UNTAG2_B 6
419 #define HNS3_REM_TAG1_EN_B 0
420 #define HNS3_REM_TAG2_EN_B 1
421 #define HNS3_SHOW_TAG1_EN_B 2
422 #define HNS3_SHOW_TAG2_EN_B 3
424 /* Factor used to calculate offset and bitmap of VF num */
425 #define HNS3_VF_NUM_PER_CMD 64
426 #define HNS3_VF_NUM_PER_BYTE 8
428 struct hns3_cfg_param_cmd {
434 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8
435 struct hns3_vport_vtag_rx_cfg_cmd {
436 uint8_t vport_vlan_cfg;
439 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];
443 struct hns3_vport_vtag_tx_cfg_cmd {
444 uint8_t vport_vlan_cfg;
447 uint16_t def_vlan_tag1;
448 uint16_t def_vlan_tag2;
449 uint8_t vf_bitmap[8];
454 struct hns3_vlan_filter_ctrl_cmd {
462 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20
463 struct hns3_vlan_filter_pf_cfg_cmd {
467 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];
470 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16
471 struct hns3_vlan_filter_vf_cfg_cmd {
477 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];
480 struct hns3_tx_vlan_type_cfg_cmd {
481 uint16_t ot_vlan_type;
482 uint16_t in_vlan_type;
486 struct hns3_rx_vlan_type_cfg_cmd {
487 uint16_t ot_fst_vlan_type;
488 uint16_t ot_sec_vlan_type;
489 uint16_t in_fst_vlan_type;
490 uint16_t in_sec_vlan_type;
494 #define HNS3_TSO_MSS_MIN_S 0
495 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
497 #define HNS3_TSO_MSS_MAX_S 16
498 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16)
500 struct hns3_cfg_tso_status_cmd {
501 rte_le16_t tso_mss_min;
502 rte_le16_t tso_mss_max;
506 #define HNS3_GRO_EN_B 0
507 struct hns3_cfg_gro_status_cmd {
512 #define HNS3_TSO_MSS_MIN 256
513 #define HNS3_TSO_MSS_MAX 9668
515 #define HNS3_RSS_HASH_KEY_OFFSET_B 4
517 #define HNS3_RSS_CFG_TBL_SIZE 16
518 #define HNS3_RSS_HASH_KEY_NUM 16
519 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
520 struct hns3_rss_generic_config_cmd {
521 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */
524 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];
527 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */
528 struct hns3_rss_input_tuple_cmd {
531 uint8_t ipv4_sctp_en;
532 uint8_t ipv4_fragment_en;
535 uint8_t ipv6_sctp_en;
536 uint8_t ipv6_fragment_en;
540 #define HNS3_RSS_CFG_TBL_SIZE 16
542 /* Configure the indirection table, opcode:0x0D07 */
543 struct hns3_rss_indirection_table_cmd {
544 uint16_t start_table_index; /* Bit3~0 must be 0x0. */
545 uint16_t rss_set_bitmap;
547 uint8_t rss_result[HNS3_RSS_CFG_TBL_SIZE];
550 #define HNS3_RSS_TC_OFFSET_S 0
551 #define HNS3_RSS_TC_OFFSET_M (0x3ff << HNS3_RSS_TC_OFFSET_S)
552 #define HNS3_RSS_TC_SIZE_S 12
553 #define HNS3_RSS_TC_SIZE_M (0x7 << HNS3_RSS_TC_SIZE_S)
554 #define HNS3_RSS_TC_VALID_B 15
556 /* Configure the tc_size and tc_offset, opcode:0x0D08 */
557 struct hns3_rss_tc_mode_cmd {
558 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM];
562 #define HNS3_LINK_STATUS_UP_B 0
563 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B)
564 struct hns3_link_status_cmd {
569 struct hns3_promisc_param {
574 #define HNS3_PROMISC_TX_EN_B BIT(4)
575 #define HNS3_PROMISC_RX_EN_B BIT(5)
576 #define HNS3_PROMISC_EN_B 1
577 #define HNS3_PROMISC_EN_ALL 0x7
578 #define HNS3_PROMISC_EN_UC 0x1
579 #define HNS3_PROMISC_EN_MC 0x2
580 #define HNS3_PROMISC_EN_BC 0x4
581 struct hns3_promisc_cfg_cmd {
588 enum hns3_promisc_type {
594 #define HNS3_MAC_TX_EN_B 6
595 #define HNS3_MAC_RX_EN_B 7
596 #define HNS3_MAC_PAD_TX_B 11
597 #define HNS3_MAC_PAD_RX_B 12
598 #define HNS3_MAC_1588_TX_B 13
599 #define HNS3_MAC_1588_RX_B 14
600 #define HNS3_MAC_APP_LP_B 15
601 #define HNS3_MAC_LINE_LP_B 16
602 #define HNS3_MAC_FCS_TX_B 17
603 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18
604 #define HNS3_MAC_RX_FCS_STRIP_B 19
605 #define HNS3_MAC_RX_FCS_B 20
606 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21
607 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22
609 struct hns3_config_mac_mode_cmd {
610 uint32_t txrx_pad_fcs_loop_en;
614 #define HNS3_CFG_SPEED_10M 6
615 #define HNS3_CFG_SPEED_100M 7
616 #define HNS3_CFG_SPEED_1G 0
617 #define HNS3_CFG_SPEED_10G 1
618 #define HNS3_CFG_SPEED_25G 2
619 #define HNS3_CFG_SPEED_40G 3
620 #define HNS3_CFG_SPEED_50G 4
621 #define HNS3_CFG_SPEED_100G 5
623 #define HNS3_CFG_SPEED_S 0
624 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
625 #define HNS3_CFG_DUPLEX_B 7
626 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B)
628 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0
630 struct hns3_config_mac_speed_dup_cmd {
632 uint8_t mac_change_fec_en;
636 #define HNS3_RING_ID_MASK GENMASK(9, 0)
637 #define HNS3_TQP_ENABLE_B 0
639 #define HNS3_MAC_CFG_AN_EN_B 0
640 #define HNS3_MAC_CFG_AN_INT_EN_B 1
641 #define HNS3_MAC_CFG_AN_INT_MSK_B 2
642 #define HNS3_MAC_CFG_AN_INT_CLR_B 3
643 #define HNS3_MAC_CFG_AN_RST_B 4
645 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B)
647 struct hns3_config_auto_neg_cmd {
648 uint32_t cfg_an_cmd_flag;
652 struct hns3_sfp_speed_cmd {
657 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
658 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1)
659 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
660 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc
662 struct hns3_mac_mgr_tbl_entry_cmd {
666 uint32_t mac_addr_hi32;
667 uint16_t mac_addr_lo16;
669 uint16_t ethter_type;
670 uint16_t egress_port;
671 uint16_t egress_queue;
672 uint8_t sw_port_id_aware;
674 uint8_t i_port_bitmap;
675 uint8_t i_port_direction;
679 struct hns3_cfg_com_tqp_queue_cmd {
686 #define HNS3_TQP_MAP_TYPE_PF 0
687 #define HNS3_TQP_MAP_TYPE_VF 1
688 #define HNS3_TQP_MAP_TYPE_B 0
689 #define HNS3_TQP_MAP_EN_B 1
691 struct hns3_tqp_map_cmd {
692 uint16_t tqp_id; /* Absolute tqp id for in this pf */
693 uint8_t tqp_vf; /* VF id */
694 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */
695 uint16_t tqp_vid; /* Virtual id in this pf/vf */
699 enum hns3_ring_type {
704 enum hns3_int_gl_idx {
707 HNS3_RING_GL_IMMEDIATE = 3
710 #define HNS3_RING_GL_IDX_S 0
711 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
713 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10
715 #define HNS3_INT_TYPE_S 0
716 #define HNS3_INT_TYPE_M GENMASK(1, 0)
717 #define HNS3_TQP_ID_S 2
718 #define HNS3_TQP_ID_M GENMASK(12, 2)
719 #define HNS3_INT_GL_IDX_S 13
720 #define HNS3_INT_GL_IDX_M GENMASK(14, 13)
721 struct hns3_ctrl_vector_chain_cmd {
722 uint8_t int_vector_id;
723 uint8_t int_cause_num;
724 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
729 struct hns3_config_max_frm_size_cmd {
730 uint16_t max_frm_size;
731 uint8_t min_frm_size;
735 enum hns3_mac_vlan_tbl_opcode {
736 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
737 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */
738 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
739 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
742 enum hns3_mac_vlan_add_resp_code {
743 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
744 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
747 #define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
749 #define HNS3_MAC_VLAN_BIT0_EN_B 0
750 #define HNS3_MAC_VLAN_BIT1_EN_B 1
751 #define HNS3_MAC_EPORT_SW_EN_B 12
752 #define HNS3_MAC_EPORT_TYPE_B 11
753 #define HNS3_MAC_EPORT_VFID_S 3
754 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3)
755 #define HNS3_MAC_EPORT_PFID_S 0
756 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0)
757 struct hns3_mac_vlan_tbl_entry_cmd {
761 uint32_t mac_addr_hi32;
762 uint16_t mac_addr_lo16;
766 uint16_t egress_port;
767 uint16_t egress_queue;
771 #define HNS3_TQP_RESET_B 0
772 struct hns3_reset_tqp_queue_cmd {
775 uint8_t ready_to_reset;
779 #define HNS3_CFG_RESET_MAC_B 3
780 #define HNS3_CFG_RESET_FUNC_B 7
781 struct hns3_reset_cmd {
782 uint8_t mac_func_reset;
783 uint8_t fun_reset_vfid;
787 #define HNS3_MAX_TQP_NUM_PER_FUNC 64
788 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
789 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
790 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */
791 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
792 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
794 #define HNS3_TYPE_CRQ 0
795 #define HNS3_TYPE_CSQ 1
797 #define HNS3_NIC_SW_RST_RDY_B 16
798 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B)
799 #define HNS3_NIC_CMQ_DESC_NUM 1024
800 #define HNS3_NIC_CMQ_DESC_NUM_S 3
802 #define HNS3_CMD_SEND_SYNC(flag) \
803 ((flag) & HNS3_CMD_FLAG_NO_INTR)
805 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);
806 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,
807 enum hns3_opcode_type opcode, bool is_read);
808 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);
809 int hns3_cmd_init_queue(struct hns3_hw *hw);
810 int hns3_cmd_init(struct hns3_hw *hw);
811 void hns3_cmd_destroy_queue(struct hns3_hw *hw);
812 void hns3_cmd_uninit(struct hns3_hw *hw);
814 #endif /* _HNS3_CMD_H_ */