1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
10 #define HNS3_CMDQ_TX_TIMEOUT 30000
11 #define HNS3_CMDQ_RX_INVLD_B 0
12 #define HNS3_CMDQ_RX_OUTVLD_B 1
13 #define HNS3_CMD_DESC_ALIGNMENT 4096
14 #define HNS3_CMD_FLAG_NEXT BIT(2)
18 #define HNS3_CMD_DESC_DATA_NUM 6
19 struct hns3_cmd_desc {
24 uint32_t data[HNS3_CMD_DESC_DATA_NUM];
27 struct hns3_cmq_ring {
28 uint64_t desc_dma_addr;
29 struct hns3_cmd_desc *desc;
33 uint16_t desc_num; /* max number of cmq descriptor */
35 uint32_t next_to_clean;
36 uint8_t ring_type; /* cmq ring type */
37 rte_spinlock_t lock; /* Command queue lock */
39 const void *zone; /* memory zone */
42 enum hns3_cmd_return_status {
43 HNS3_CMD_EXEC_SUCCESS = 0,
45 HNS3_CMD_NOT_SUPPORTED = 2,
46 HNS3_CMD_QUEUE_FULL = 3,
47 HNS3_CMD_NEXT_ERR = 4,
48 HNS3_CMD_UNEXE_ERR = 5,
49 HNS3_CMD_PARA_ERR = 6,
50 HNS3_CMD_RESULT_ERR = 7,
52 HNS3_CMD_HILINK_ERR = 9,
53 HNS3_CMD_QUEUE_ILLEGAL = 10,
54 HNS3_CMD_INVALID = 11,
55 HNS3_CMD_ROH_CHECK_FAIL = 12
58 enum hns3_cmd_status {
59 HNS3_STATUS_SUCCESS = 0,
60 HNS3_ERR_CSQ_FULL = -1,
61 HNS3_ERR_CSQ_TIMEOUT = -2,
62 HNS3_ERR_CSQ_ERROR = -3,
65 struct hns3_misc_vector {
71 struct hns3_cmq_ring csq;
72 struct hns3_cmq_ring crq;
74 enum hns3_cmd_status last_status;
77 enum hns3_opcode_type {
78 /* Generic commands */
79 HNS3_OPC_QUERY_FW_VER = 0x0001,
80 HNS3_OPC_CFG_RST_TRIGGER = 0x0020,
81 HNS3_OPC_GBL_RST_STATUS = 0x0021,
82 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
83 HNS3_OPC_QUERY_PF_RSRC = 0x0023,
84 HNS3_OPC_QUERY_VF_RSRC = 0x0024,
85 HNS3_OPC_GET_CFG_PARAM = 0x0025,
86 HNS3_OPC_PF_RST_DONE = 0x0026,
88 HNS3_OPC_STATS_64_BIT = 0x0030,
89 HNS3_OPC_STATS_32_BIT = 0x0031,
90 HNS3_OPC_STATS_MAC = 0x0032,
91 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,
92 HNS3_OPC_STATS_MAC_ALL = 0x0034,
94 HNS3_OPC_QUERY_REG_NUM = 0x0040,
95 HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
96 HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
98 HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
101 HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
102 HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
103 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
104 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
105 HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
107 /* PFC/Pause commands */
108 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
109 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,
110 HNS3_OPC_CFG_MAC_PARA = 0x0703,
111 HNS3_OPC_CFG_PFC_PARA = 0x0704,
112 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
113 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
114 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
115 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
116 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,
117 HNS3_OPC_QOS_MAP = 0x070A,
119 /* ETS/scheduler commands */
120 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,
121 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,
122 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,
123 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,
124 HNS3_OPC_TM_PORT_WEIGHT = 0x0808,
125 HNS3_OPC_TM_PG_WEIGHT = 0x0809,
126 HNS3_OPC_TM_QS_WEIGHT = 0x080A,
127 HNS3_OPC_TM_PRI_WEIGHT = 0x080B,
128 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,
129 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,
130 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E,
131 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F,
132 HNS3_OPC_TM_PORT_SHAPPING = 0x0810,
133 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
134 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
135 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
136 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
137 HNS3_OPC_ETS_TC_WEIGHT = 0x0843,
138 HNS3_OPC_QSET_DFX_STS = 0x0844,
139 HNS3_OPC_PRI_DFX_STS = 0x0845,
140 HNS3_OPC_PG_DFX_STS = 0x0846,
141 HNS3_OPC_PORT_DFX_STS = 0x0847,
142 HNS3_OPC_SCH_NQ_CNT = 0x0848,
143 HNS3_OPC_SCH_RQ_CNT = 0x0849,
144 HNS3_OPC_TM_INTERNAL_STS = 0x0850,
145 HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
146 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
149 HNS3_OPC_MBX_VF_TO_PF = 0x2001,
151 /* Packet buffer allocate commands */
152 HNS3_OPC_TX_BUFF_ALLOC = 0x0901,
153 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
154 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,
155 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
156 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
158 /* TQP management command */
159 HNS3_OPC_SET_TQP_MAP = 0x0A01,
162 HNS3_OPC_QUERY_TX_STATUS = 0x0B03,
163 HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
164 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
165 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
166 HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23,
169 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
170 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
173 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,
174 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,
175 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07,
176 HNS3_OPC_RSS_TC_MODE = 0x0D08,
178 /* Promisuous mode command */
179 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01,
181 /* Vlan offload commands */
182 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,
183 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,
186 HNS3_OPC_MAC_VLAN_ADD = 0x1000,
187 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001,
188 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,
189 HNS3_OPC_MAC_VLAN_INSERT = 0x1003,
190 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,
191 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,
194 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100,
195 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,
196 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,
198 /* Flow Director command */
199 HNS3_OPC_FD_MODE_CTRL = 0x1200,
200 HNS3_OPC_FD_GET_ALLOCATION = 0x1201,
201 HNS3_OPC_FD_KEY_CONFIG = 0x1202,
202 HNS3_OPC_FD_TCAM_OP = 0x1203,
203 HNS3_OPC_FD_AD_OP = 0x1204,
204 HNS3_OPC_FD_COUNTER_OP = 0x1205,
206 /* Clear hardware state command */
207 HNS3_OPC_CLEAR_HW_STATE = 0x700B,
210 HNS3_OPC_SFP_GET_SPEED = 0x7104,
212 /* Interrupts commands */
213 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
214 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
216 /* Error INT commands */
217 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E,
218 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829,
219 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989,
220 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C,
221 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40,
222 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41,
223 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42,
224 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505,
225 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
226 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
227 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512,
228 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
229 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
230 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
231 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803,
232 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806,
233 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14,
234 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100,
235 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101,
236 HNS3_OPC_NCSI_INT_EN = 0x2401,
239 #define HNS3_CMD_FLAG_IN BIT(0)
240 #define HNS3_CMD_FLAG_OUT BIT(1)
241 #define HNS3_CMD_FLAG_NEXT BIT(2)
242 #define HNS3_CMD_FLAG_WR BIT(3)
243 #define HNS3_CMD_FLAG_NO_INTR BIT(4)
244 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
246 #define HNS3_MPF_RAS_INT_MIN_BD_NUM 10
247 #define HNS3_PF_RAS_INT_MIN_BD_NUM 4
248 #define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10
249 #define HNS3_PF_MSIX_INT_MIN_BD_NUM 4
251 #define HNS3_BUF_SIZE_UNIT 256
252 #define HNS3_BUF_MUL_BY 2
253 #define HNS3_BUF_DIV_BY 2
254 #define NEED_RESERVE_TC_NUM 2
255 #define BUF_MAX_PERCENT 100
256 #define BUF_RESERVE_PERCENT 90
258 #define HNS3_MAX_TC_NUM 8
259 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
260 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
261 #define HNS3_TX_BUFF_RSV_NUM 8
262 struct hns3_tx_buff_alloc_cmd {
263 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];
264 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];
267 struct hns3_rx_priv_buff_cmd {
268 uint16_t buf_num[HNS3_MAX_TC_NUM];
273 #define HNS3_FW_VERSION_BYTE3_S 24
274 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24)
275 #define HNS3_FW_VERSION_BYTE2_S 16
276 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16)
277 #define HNS3_FW_VERSION_BYTE1_S 8
278 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
279 #define HNS3_FW_VERSION_BYTE0_S 0
280 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
282 enum HNS3_CAPS_BITS {
285 HNS3_CAPS_FD_QUEUE_REGION_B,
288 HNS3_CAPS_SIMPLE_BD_B,
291 HNS3_CAPS_TQP_TXRX_INDEP_B,
295 #define HNS3_QUERY_CAP_LENGTH 3
296 struct hns3_query_version_cmd {
300 uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
303 #define HNS3_RX_PRIV_EN_B 15
304 #define HNS3_TC_NUM_ONE_DESC 4
305 struct hns3_priv_wl {
310 struct hns3_rx_priv_wl_buf {
311 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];
314 struct hns3_rx_com_thrd {
315 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];
318 struct hns3_rx_com_wl {
319 struct hns3_priv_wl com_wl;
322 struct hns3_waterline {
327 struct hns3_tc_thrd {
332 struct hns3_priv_buf {
333 struct hns3_waterline wl; /* Waterline for low and high */
334 uint32_t buf_size; /* TC private buffer size */
335 uint32_t tx_buf_size;
336 uint32_t enable; /* Enable TC private buffer or not */
339 struct hns3_shared_buf {
340 struct hns3_waterline self;
341 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];
345 struct hns3_pkt_buf_alloc {
346 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];
347 struct hns3_shared_buf s_buf;
350 #define HNS3_RX_COM_WL_EN_B 15
351 struct hns3_rx_com_wl_buf_cmd {
357 #define HNS3_RX_PKT_EN_B 15
358 struct hns3_rx_pkt_buf_cmd {
364 #define HNS3_PF_STATE_DONE_B 0
365 #define HNS3_PF_STATE_MAIN_B 1
366 #define HNS3_PF_STATE_BOND_B 2
367 #define HNS3_PF_STATE_MAC_N_B 6
368 #define HNS3_PF_MAC_NUM_MASK 0x3
369 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B)
370 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B)
371 #define HNS3_VF_RST_STATE_NUM 4
372 struct hns3_func_status_cmd {
373 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];
377 uint8_t pf_cnt_in_mac;
383 #define HNS3_PF_VEC_NUM_S 0
384 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
385 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */
386 struct hns3_pf_res_cmd {
389 uint16_t msixcap_localid_ba_nic;
390 uint16_t nic_pf_intr_vector_number;
391 uint16_t roce_pf_intr_vector_number;
392 uint16_t pf_own_fun_number;
393 uint16_t tx_buf_size;
394 uint16_t dv_buf_size;
395 /* number of queues that exceed 1024 */
396 uint16_t ext_tqp_num;
397 uint16_t roh_pf_intr_vector_number;
401 #define HNS3_VF_VEC_NUM_S 0
402 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
403 struct hns3_vf_res_cmd {
406 uint16_t msixcap_localid_ba_nic;
407 uint16_t msixcap_localid_ba_rocee;
408 uint16_t vf_intr_vector_number;
412 #define HNS3_UMV_SPC_ALC_B 0
413 struct hns3_umv_spc_alc_cmd {
420 #define HNS3_CFG_OFFSET_S 0
421 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
422 #define HNS3_CFG_RD_LEN_S 24
423 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24)
424 #define HNS3_CFG_RD_LEN_BYTES 16
425 #define HNS3_CFG_RD_LEN_UNIT 4
427 #define HNS3_CFG_VMDQ_S 0
428 #define HNS3_CFG_VMDQ_M GENMASK(7, 0)
429 #define HNS3_CFG_TC_NUM_S 8
430 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
431 #define HNS3_CFG_TQP_DESC_N_S 16
432 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16)
433 #define HNS3_CFG_PHY_ADDR_S 0
434 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0)
435 #define HNS3_CFG_MEDIA_TP_S 8
436 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8)
437 #define HNS3_CFG_RX_BUF_LEN_S 16
438 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16)
439 #define HNS3_CFG_MAC_ADDR_H_S 0
440 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0)
441 #define HNS3_CFG_DEFAULT_SPEED_S 16
442 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
443 #define HNS3_CFG_RSS_SIZE_S 24
444 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24)
445 #define HNS3_CFG_SPEED_ABILITY_S 0
446 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0)
447 #define HNS3_CFG_UMV_TBL_SPACE_S 16
448 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
449 #define HNS3_CFG_EXT_RSS_SIZE_S 0
450 #define HNS3_CFG_EXT_RSS_SIZE_M GENMASK(3, 0)
452 #define HNS3_ACCEPT_TAG1_B 0
453 #define HNS3_ACCEPT_UNTAG1_B 1
454 #define HNS3_PORT_INS_TAG1_EN_B 2
455 #define HNS3_PORT_INS_TAG2_EN_B 3
456 #define HNS3_CFG_NIC_ROCE_SEL_B 4
457 #define HNS3_ACCEPT_TAG2_B 5
458 #define HNS3_ACCEPT_UNTAG2_B 6
459 #define HNS3_TAG_SHIFT_MODE_EN_B 7
461 #define HNS3_REM_TAG1_EN_B 0
462 #define HNS3_REM_TAG2_EN_B 1
463 #define HNS3_SHOW_TAG1_EN_B 2
464 #define HNS3_SHOW_TAG2_EN_B 3
465 #define HNS3_DISCARD_TAG1_EN_B 5
466 #define HNS3_DISCARD_TAG2_EN_B 6
468 /* Factor used to calculate offset and bitmap of VF num */
469 #define HNS3_VF_NUM_PER_CMD 64
470 #define HNS3_VF_NUM_PER_BYTE 8
472 struct hns3_cfg_param_cmd {
478 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8
479 struct hns3_vport_vtag_rx_cfg_cmd {
480 uint8_t vport_vlan_cfg;
483 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];
487 struct hns3_vport_vtag_tx_cfg_cmd {
488 uint8_t vport_vlan_cfg;
491 uint16_t def_vlan_tag1;
492 uint16_t def_vlan_tag2;
493 uint8_t vf_bitmap[8];
498 struct hns3_vlan_filter_ctrl_cmd {
506 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20
507 struct hns3_vlan_filter_pf_cfg_cmd {
511 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];
514 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16
515 struct hns3_vlan_filter_vf_cfg_cmd {
521 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];
524 struct hns3_tx_vlan_type_cfg_cmd {
525 uint16_t ot_vlan_type;
526 uint16_t in_vlan_type;
530 struct hns3_rx_vlan_type_cfg_cmd {
531 uint16_t ot_fst_vlan_type;
532 uint16_t ot_sec_vlan_type;
533 uint16_t in_fst_vlan_type;
534 uint16_t in_sec_vlan_type;
538 #define HNS3_TSO_MSS_MIN_S 0
539 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
541 #define HNS3_TSO_MSS_MAX_S 16
542 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16)
544 struct hns3_cfg_tso_status_cmd {
545 rte_le16_t tso_mss_min;
546 rte_le16_t tso_mss_max;
550 #define HNS3_GRO_EN_B 0
551 struct hns3_cfg_gro_status_cmd {
556 #define HNS3_TSO_MSS_MIN 256
557 #define HNS3_TSO_MSS_MAX 9668
559 #define HNS3_RSS_HASH_KEY_OFFSET_B 4
561 #define HNS3_RSS_CFG_TBL_SIZE 16
562 #define HNS3_RSS_HASH_KEY_NUM 16
563 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
564 struct hns3_rss_generic_config_cmd {
565 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */
568 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];
571 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */
572 struct hns3_rss_input_tuple_cmd {
573 uint64_t tuple_field;
577 #define HNS3_RSS_CFG_TBL_SIZE 16
578 #define HNS3_RSS_CFG_TBL_SIZE_H 4
579 #define HNS3_RSS_CFG_TBL_BW_H 2
580 #define HNS3_RSS_CFG_TBL_BW_L 8
582 /* Configure the indirection table, opcode:0x0D07 */
583 struct hns3_rss_indirection_table_cmd {
584 uint16_t start_table_index; /* Bit3~0 must be 0x0. */
585 uint16_t rss_set_bitmap;
586 uint8_t rss_result_h[HNS3_RSS_CFG_TBL_SIZE_H];
587 uint8_t rss_result_l[HNS3_RSS_CFG_TBL_SIZE];
590 #define HNS3_RSS_TC_OFFSET_S 0
591 #define HNS3_RSS_TC_OFFSET_M GENMASK(10, 0)
592 #define HNS3_RSS_TC_SIZE_MSB_S 11
593 #define HNS3_RSS_TC_SIZE_MSB_OFFSET 3
594 #define HNS3_RSS_TC_SIZE_S 12
595 #define HNS3_RSS_TC_SIZE_M GENMASK(14, 12)
596 #define HNS3_RSS_TC_VALID_B 15
598 /* Configure the tc_size and tc_offset, opcode:0x0D08 */
599 struct hns3_rss_tc_mode_cmd {
600 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM];
604 #define HNS3_LINK_STATUS_UP_B 0
605 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B)
606 struct hns3_link_status_cmd {
611 struct hns3_promisc_param {
616 #define HNS3_PROMISC_TX_EN_B BIT(4)
617 #define HNS3_PROMISC_RX_EN_B BIT(5)
618 #define HNS3_PROMISC_EN_B 1
619 #define HNS3_PROMISC_EN_ALL 0x7
620 #define HNS3_PROMISC_EN_UC 0x1
621 #define HNS3_PROMISC_EN_MC 0x2
622 #define HNS3_PROMISC_EN_BC 0x4
623 struct hns3_promisc_cfg_cmd {
630 enum hns3_promisc_type {
636 #define HNS3_MAC_TX_EN_B 6
637 #define HNS3_MAC_RX_EN_B 7
638 #define HNS3_MAC_PAD_TX_B 11
639 #define HNS3_MAC_PAD_RX_B 12
640 #define HNS3_MAC_1588_TX_B 13
641 #define HNS3_MAC_1588_RX_B 14
642 #define HNS3_MAC_APP_LP_B 15
643 #define HNS3_MAC_LINE_LP_B 16
644 #define HNS3_MAC_FCS_TX_B 17
645 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18
646 #define HNS3_MAC_RX_FCS_STRIP_B 19
647 #define HNS3_MAC_RX_FCS_B 20
648 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21
649 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22
651 struct hns3_config_mac_mode_cmd {
652 uint32_t txrx_pad_fcs_loop_en;
656 #define HNS3_CFG_SPEED_10M 6
657 #define HNS3_CFG_SPEED_100M 7
658 #define HNS3_CFG_SPEED_1G 0
659 #define HNS3_CFG_SPEED_10G 1
660 #define HNS3_CFG_SPEED_25G 2
661 #define HNS3_CFG_SPEED_40G 3
662 #define HNS3_CFG_SPEED_50G 4
663 #define HNS3_CFG_SPEED_100G 5
664 #define HNS3_CFG_SPEED_200G 8
666 #define HNS3_CFG_SPEED_S 0
667 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
668 #define HNS3_CFG_DUPLEX_B 7
669 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B)
671 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0
673 struct hns3_config_mac_speed_dup_cmd {
675 uint8_t mac_change_fec_en;
679 #define HNS3_TQP_ENABLE_B 0
681 #define HNS3_MAC_CFG_AN_EN_B 0
682 #define HNS3_MAC_CFG_AN_INT_EN_B 1
683 #define HNS3_MAC_CFG_AN_INT_MSK_B 2
684 #define HNS3_MAC_CFG_AN_INT_CLR_B 3
685 #define HNS3_MAC_CFG_AN_RST_B 4
687 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B)
689 struct hns3_config_auto_neg_cmd {
690 uint32_t cfg_an_cmd_flag;
694 #define HNS3_MAC_CFG_FEC_AUTO_EN_B 0
695 #define HNS3_MAC_CFG_FEC_MODE_S 1
696 #define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
697 #define HNS3_MAC_FEC_OFF 0
698 #define HNS3_MAC_FEC_BASER 1
699 #define HNS3_MAC_FEC_RS 2
701 struct hns3_sfp_speed_cmd {
703 uint8_t query_type; /* 0: sfp speed, 1: active fec */
704 uint8_t active_fec; /* current FEC mode */
709 /* Configure FEC mode, opcode:0x031A */
710 struct hns3_config_fec_cmd {
715 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
716 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1)
717 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
718 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc
720 struct hns3_mac_mgr_tbl_entry_cmd {
724 uint32_t mac_addr_hi32;
725 uint16_t mac_addr_lo16;
727 uint16_t ethter_type;
728 uint16_t egress_port;
729 uint16_t egress_queue;
730 uint8_t sw_port_id_aware;
732 uint8_t i_port_bitmap;
733 uint8_t i_port_direction;
737 struct hns3_cfg_com_tqp_queue_cmd {
744 #define HNS3_TQP_MAP_TYPE_PF 0
745 #define HNS3_TQP_MAP_TYPE_VF 1
746 #define HNS3_TQP_MAP_TYPE_B 0
747 #define HNS3_TQP_MAP_EN_B 1
749 struct hns3_tqp_map_cmd {
750 uint16_t tqp_id; /* Absolute tqp id for in this pf */
751 uint8_t tqp_vf; /* VF id */
752 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */
753 uint16_t tqp_vid; /* Virtual id in this pf/vf */
757 enum hns3_ring_type {
762 enum hns3_int_gl_idx {
765 HNS3_RING_GL_IMMEDIATE = 3
768 #define HNS3_RING_GL_IDX_S 0
769 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
771 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10
773 #define HNS3_INT_TYPE_S 0
774 #define HNS3_INT_TYPE_M GENMASK(1, 0)
775 #define HNS3_TQP_ID_S 2
776 #define HNS3_TQP_ID_M GENMASK(12, 2)
777 #define HNS3_INT_GL_IDX_S 13
778 #define HNS3_INT_GL_IDX_M GENMASK(14, 13)
779 #define HNS3_TQP_INT_ID_L_S 0
780 #define HNS3_TQP_INT_ID_L_M GENMASK(7, 0)
781 #define HNS3_TQP_INT_ID_H_S 8
782 #define HNS3_TQP_INT_ID_H_M GENMASK(15, 8)
783 struct hns3_ctrl_vector_chain_cmd {
784 uint8_t int_vector_id; /* the low order of the interrupt id */
785 uint8_t int_cause_num;
786 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
788 uint8_t int_vector_id_h; /* the high order of the interrupt id */
791 struct hns3_config_max_frm_size_cmd {
792 uint16_t max_frm_size;
793 uint8_t min_frm_size;
797 enum hns3_mac_vlan_tbl_opcode {
798 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
799 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */
800 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
801 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
804 enum hns3_mac_vlan_add_resp_code {
805 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
806 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
809 #define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
811 #define HNS3_MAC_VLAN_BIT0_EN_B 0
812 #define HNS3_MAC_VLAN_BIT1_EN_B 1
813 #define HNS3_MAC_EPORT_SW_EN_B 12
814 #define HNS3_MAC_EPORT_TYPE_B 11
815 #define HNS3_MAC_EPORT_VFID_S 3
816 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3)
817 #define HNS3_MAC_EPORT_PFID_S 0
818 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0)
819 struct hns3_mac_vlan_tbl_entry_cmd {
823 uint32_t mac_addr_hi32;
824 uint16_t mac_addr_lo16;
828 uint16_t egress_port;
829 uint16_t egress_queue;
833 #define HNS3_TQP_RESET_B 0
834 struct hns3_reset_tqp_queue_cmd {
837 uint8_t ready_to_reset;
838 uint8_t queue_direction;
842 #define HNS3_CFG_RESET_MAC_B 3
843 #define HNS3_CFG_RESET_FUNC_B 7
844 struct hns3_reset_cmd {
845 uint8_t mac_func_reset;
846 uint8_t fun_reset_vfid;
850 #define HNS3_QUERY_DEV_SPECS_BD_NUM 4
851 struct hns3_dev_specs_0_cmd {
853 uint32_t mac_entry_num;
854 uint32_t mng_entry_num;
855 uint16_t rss_ind_tbl_size;
856 uint16_t rss_key_size;
857 uint16_t intr_ql_max;
858 uint8_t max_non_tso_bd_num;
860 uint32_t max_tm_rate;
863 #define HNS3_MAX_TQP_NUM_HIP08_PF 64
864 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
865 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
866 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */
867 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
868 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
870 #define HNS3_TYPE_CRQ 0
871 #define HNS3_TYPE_CSQ 1
873 #define HNS3_NIC_SW_RST_RDY_B 16
874 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B)
875 #define HNS3_NIC_CMQ_DESC_NUM 1024
876 #define HNS3_NIC_CMQ_DESC_NUM_S 3
878 #define HNS3_CMD_SEND_SYNC(flag) \
879 ((flag) & HNS3_CMD_FLAG_NO_INTR)
881 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);
882 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,
883 enum hns3_opcode_type opcode, bool is_read);
884 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);
885 int hns3_cmd_init_queue(struct hns3_hw *hw);
886 int hns3_cmd_init(struct hns3_hw *hw);
887 void hns3_cmd_destroy_queue(struct hns3_hw *hw);
888 void hns3_cmd_uninit(struct hns3_hw *hw);
890 #endif /* _HNS3_CMD_H_ */