1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
10 #define HNS3_CMDQ_TX_TIMEOUT 30000
11 #define HNS3_CMDQ_RX_INVLD_B 0
12 #define HNS3_CMDQ_RX_OUTVLD_B 1
13 #define HNS3_CMD_DESC_ALIGNMENT 4096
14 #define HNS3_CMD_FLAG_NEXT BIT(2)
18 #define HNS3_CMD_DESC_DATA_NUM 6
19 struct hns3_cmd_desc {
24 uint32_t data[HNS3_CMD_DESC_DATA_NUM];
27 struct hns3_cmq_ring {
28 uint64_t desc_dma_addr;
29 struct hns3_cmd_desc *desc;
33 uint16_t desc_num; /* max number of cmq descriptor */
35 uint32_t next_to_clean;
36 uint8_t ring_type; /* cmq ring type */
37 rte_spinlock_t lock; /* Command queue lock */
39 const void *zone; /* memory zone */
42 enum hns3_cmd_return_status {
43 HNS3_CMD_EXEC_SUCCESS = 0,
45 HNS3_CMD_NOT_SUPPORTED = 2,
46 HNS3_CMD_QUEUE_FULL = 3,
47 HNS3_CMD_NEXT_ERR = 4,
48 HNS3_CMD_UNEXE_ERR = 5,
49 HNS3_CMD_PARA_ERR = 6,
50 HNS3_CMD_RESULT_ERR = 7,
52 HNS3_CMD_HILINK_ERR = 9,
53 HNS3_CMD_QUEUE_ILLEGAL = 10,
54 HNS3_CMD_INVALID = 11,
57 enum hns3_cmd_status {
58 HNS3_STATUS_SUCCESS = 0,
59 HNS3_ERR_CSQ_FULL = -1,
60 HNS3_ERR_CSQ_TIMEOUT = -2,
61 HNS3_ERR_CSQ_ERROR = -3,
64 struct hns3_misc_vector {
70 struct hns3_cmq_ring csq;
71 struct hns3_cmq_ring crq;
73 enum hns3_cmd_status last_status;
76 enum hns3_opcode_type {
77 /* Generic commands */
78 HNS3_OPC_QUERY_FW_VER = 0x0001,
79 HNS3_OPC_CFG_RST_TRIGGER = 0x0020,
80 HNS3_OPC_GBL_RST_STATUS = 0x0021,
81 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022,
82 HNS3_OPC_QUERY_PF_RSRC = 0x0023,
83 HNS3_OPC_QUERY_VF_RSRC = 0x0024,
84 HNS3_OPC_GET_CFG_PARAM = 0x0025,
85 HNS3_OPC_PF_RST_DONE = 0x0026,
87 HNS3_OPC_STATS_64_BIT = 0x0030,
88 HNS3_OPC_STATS_32_BIT = 0x0031,
89 HNS3_OPC_STATS_MAC = 0x0032,
90 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033,
91 HNS3_OPC_STATS_MAC_ALL = 0x0034,
93 HNS3_OPC_QUERY_REG_NUM = 0x0040,
94 HNS3_OPC_QUERY_32_BIT_REG = 0x0041,
95 HNS3_OPC_QUERY_64_BIT_REG = 0x0042,
97 HNS3_OPC_QUERY_DEV_SPECS = 0x0050,
100 HNS3_OPC_CONFIG_MAC_MODE = 0x0301,
101 HNS3_OPC_QUERY_LINK_STATUS = 0x0307,
102 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
103 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309,
104 HNS3_OPC_CONFIG_FEC_MODE = 0x031A,
106 /* PFC/Pause commands */
107 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,
108 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,
109 HNS3_OPC_CFG_MAC_PARA = 0x0703,
110 HNS3_OPC_CFG_PFC_PARA = 0x0704,
111 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
112 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
113 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
114 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
115 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709,
116 HNS3_OPC_QOS_MAP = 0x070A,
118 /* ETS/scheduler commands */
119 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804,
120 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805,
121 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806,
122 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807,
123 HNS3_OPC_TM_PORT_WEIGHT = 0x0808,
124 HNS3_OPC_TM_PG_WEIGHT = 0x0809,
125 HNS3_OPC_TM_QS_WEIGHT = 0x080A,
126 HNS3_OPC_TM_PRI_WEIGHT = 0x080B,
127 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C,
128 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D,
129 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E,
130 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F,
131 HNS3_OPC_TM_PORT_SHAPPING = 0x0810,
132 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
133 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
134 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
135 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
136 HNS3_OPC_ETS_TC_WEIGHT = 0x0843,
137 HNS3_OPC_QSET_DFX_STS = 0x0844,
138 HNS3_OPC_PRI_DFX_STS = 0x0845,
139 HNS3_OPC_PG_DFX_STS = 0x0846,
140 HNS3_OPC_PORT_DFX_STS = 0x0847,
141 HNS3_OPC_SCH_NQ_CNT = 0x0848,
142 HNS3_OPC_SCH_RQ_CNT = 0x0849,
143 HNS3_OPC_TM_INTERNAL_STS = 0x0850,
144 HNS3_OPC_TM_INTERNAL_CNT = 0x0851,
145 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
148 HNS3_OPC_MBX_VF_TO_PF = 0x2001,
150 /* Packet buffer allocate commands */
151 HNS3_OPC_TX_BUFF_ALLOC = 0x0901,
152 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
153 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903,
154 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904,
155 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905,
157 /* TQP management command */
158 HNS3_OPC_SET_TQP_MAP = 0x0A01,
161 HNS3_OPC_QUERY_TX_STATUS = 0x0B03,
162 HNS3_OPC_QUERY_RX_STATUS = 0x0B13,
163 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
164 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22,
165 HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23,
168 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01,
169 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10,
172 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01,
173 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02,
174 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07,
175 HNS3_OPC_RSS_TC_MODE = 0x0D08,
177 /* Promisuous mode command */
178 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01,
180 /* Vlan offload commands */
181 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01,
182 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02,
185 HNS3_OPC_MAC_VLAN_ADD = 0x1000,
186 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001,
187 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002,
188 HNS3_OPC_MAC_VLAN_INSERT = 0x1003,
189 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004,
190 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010,
193 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100,
194 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101,
195 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102,
197 /* Flow Director command */
198 HNS3_OPC_FD_MODE_CTRL = 0x1200,
199 HNS3_OPC_FD_GET_ALLOCATION = 0x1201,
200 HNS3_OPC_FD_KEY_CONFIG = 0x1202,
201 HNS3_OPC_FD_TCAM_OP = 0x1203,
202 HNS3_OPC_FD_AD_OP = 0x1204,
203 HNS3_OPC_FD_COUNTER_OP = 0x1205,
205 /* Clear hardware state command */
206 HNS3_OPC_CLEAR_HW_STATE = 0x700B,
209 HNS3_OPC_SFP_GET_SPEED = 0x7104,
211 /* Interrupts commands */
212 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503,
213 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504,
215 /* Error INT commands */
216 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E,
217 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829,
218 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989,
219 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C,
220 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40,
221 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41,
222 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42,
223 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505,
224 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
225 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
226 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512,
227 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
228 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
229 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
230 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803,
231 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806,
232 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14,
233 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100,
234 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101,
235 HNS3_OPC_NCSI_INT_EN = 0x2401,
238 #define HNS3_CMD_FLAG_IN BIT(0)
239 #define HNS3_CMD_FLAG_OUT BIT(1)
240 #define HNS3_CMD_FLAG_NEXT BIT(2)
241 #define HNS3_CMD_FLAG_WR BIT(3)
242 #define HNS3_CMD_FLAG_NO_INTR BIT(4)
243 #define HNS3_CMD_FLAG_ERR_INTR BIT(5)
245 #define HNS3_MPF_RAS_INT_MIN_BD_NUM 10
246 #define HNS3_PF_RAS_INT_MIN_BD_NUM 4
247 #define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10
248 #define HNS3_PF_MSIX_INT_MIN_BD_NUM 4
250 #define HNS3_BUF_SIZE_UNIT 256
251 #define HNS3_BUF_MUL_BY 2
252 #define HNS3_BUF_DIV_BY 2
253 #define NEED_RESERVE_TC_NUM 2
254 #define BUF_MAX_PERCENT 100
255 #define BUF_RESERVE_PERCENT 90
257 #define HNS3_MAX_TC_NUM 8
258 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
259 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
260 #define HNS3_TX_BUFF_RSV_NUM 8
261 struct hns3_tx_buff_alloc_cmd {
262 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM];
263 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM];
266 struct hns3_rx_priv_buff_cmd {
267 uint16_t buf_num[HNS3_MAX_TC_NUM];
272 #define HNS3_FW_VERSION_BYTE3_S 24
273 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24)
274 #define HNS3_FW_VERSION_BYTE2_S 16
275 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16)
276 #define HNS3_FW_VERSION_BYTE1_S 8
277 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
278 #define HNS3_FW_VERSION_BYTE0_S 0
279 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
281 enum HNS3_CAPS_BITS {
284 HNS3_CAPS_FD_QUEUE_REGION_B,
287 HNS3_CAPS_SIMPLE_BD_B,
290 HNS3_CAPS_TQP_TXRX_INDEP_B,
294 #define HNS3_QUERY_CAP_LENGTH 3
295 struct hns3_query_version_cmd {
299 uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
302 #define HNS3_RX_PRIV_EN_B 15
303 #define HNS3_TC_NUM_ONE_DESC 4
304 struct hns3_priv_wl {
309 struct hns3_rx_priv_wl_buf {
310 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC];
313 struct hns3_rx_com_thrd {
314 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC];
317 struct hns3_rx_com_wl {
318 struct hns3_priv_wl com_wl;
321 struct hns3_waterline {
326 struct hns3_tc_thrd {
331 struct hns3_priv_buf {
332 struct hns3_waterline wl; /* Waterline for low and high */
333 uint32_t buf_size; /* TC private buffer size */
334 uint32_t tx_buf_size;
335 uint32_t enable; /* Enable TC private buffer or not */
338 struct hns3_shared_buf {
339 struct hns3_waterline self;
340 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM];
344 struct hns3_pkt_buf_alloc {
345 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM];
346 struct hns3_shared_buf s_buf;
349 #define HNS3_RX_COM_WL_EN_B 15
350 struct hns3_rx_com_wl_buf_cmd {
356 #define HNS3_RX_PKT_EN_B 15
357 struct hns3_rx_pkt_buf_cmd {
363 #define HNS3_PF_STATE_DONE_B 0
364 #define HNS3_PF_STATE_MAIN_B 1
365 #define HNS3_PF_STATE_BOND_B 2
366 #define HNS3_PF_STATE_MAC_N_B 6
367 #define HNS3_PF_MAC_NUM_MASK 0x3
368 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B)
369 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B)
370 #define HNS3_VF_RST_STATE_NUM 4
371 struct hns3_func_status_cmd {
372 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM];
376 uint8_t pf_cnt_in_mac;
382 #define HNS3_PF_VEC_NUM_S 0
383 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0)
384 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */
385 struct hns3_pf_res_cmd {
388 uint16_t msixcap_localid_ba_nic;
389 uint16_t nic_pf_intr_vector_number;
390 uint16_t roce_pf_intr_vector_number;
391 uint16_t pf_own_fun_number;
392 uint16_t tx_buf_size;
393 uint16_t dv_buf_size;
394 /* number of queues that exceed 1024 */
395 uint16_t ext_tqp_num;
396 uint16_t roh_pf_intr_vector_number;
400 #define HNS3_VF_VEC_NUM_S 0
401 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0)
402 struct hns3_vf_res_cmd {
405 uint16_t msixcap_localid_ba_nic;
406 uint16_t msixcap_localid_ba_rocee;
407 uint16_t vf_intr_vector_number;
411 #define HNS3_UMV_SPC_ALC_B 0
412 struct hns3_umv_spc_alc_cmd {
419 #define HNS3_CFG_OFFSET_S 0
420 #define HNS3_CFG_OFFSET_M GENMASK(19, 0)
421 #define HNS3_CFG_RD_LEN_S 24
422 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24)
423 #define HNS3_CFG_RD_LEN_BYTES 16
424 #define HNS3_CFG_RD_LEN_UNIT 4
426 #define HNS3_CFG_VMDQ_S 0
427 #define HNS3_CFG_VMDQ_M GENMASK(7, 0)
428 #define HNS3_CFG_TC_NUM_S 8
429 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8)
430 #define HNS3_CFG_TQP_DESC_N_S 16
431 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16)
432 #define HNS3_CFG_PHY_ADDR_S 0
433 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0)
434 #define HNS3_CFG_MEDIA_TP_S 8
435 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8)
436 #define HNS3_CFG_RX_BUF_LEN_S 16
437 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16)
438 #define HNS3_CFG_MAC_ADDR_H_S 0
439 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0)
440 #define HNS3_CFG_DEFAULT_SPEED_S 16
441 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
442 #define HNS3_CFG_RSS_SIZE_S 24
443 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24)
444 #define HNS3_CFG_SPEED_ABILITY_S 0
445 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0)
446 #define HNS3_CFG_UMV_TBL_SPACE_S 16
447 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
448 #define HNS3_CFG_EXT_RSS_SIZE_S 0
449 #define HNS3_CFG_EXT_RSS_SIZE_M GENMASK(3, 0)
451 #define HNS3_ACCEPT_TAG1_B 0
452 #define HNS3_ACCEPT_UNTAG1_B 1
453 #define HNS3_PORT_INS_TAG1_EN_B 2
454 #define HNS3_PORT_INS_TAG2_EN_B 3
455 #define HNS3_CFG_NIC_ROCE_SEL_B 4
456 #define HNS3_ACCEPT_TAG2_B 5
457 #define HNS3_ACCEPT_UNTAG2_B 6
458 #define HNS3_TAG_SHIFT_MODE_EN_B 7
460 #define HNS3_REM_TAG1_EN_B 0
461 #define HNS3_REM_TAG2_EN_B 1
462 #define HNS3_SHOW_TAG1_EN_B 2
463 #define HNS3_SHOW_TAG2_EN_B 3
464 #define HNS3_DISCARD_TAG1_EN_B 5
465 #define HNS3_DISCARD_TAG2_EN_B 6
467 /* Factor used to calculate offset and bitmap of VF num */
468 #define HNS3_VF_NUM_PER_CMD 64
469 #define HNS3_VF_NUM_PER_BYTE 8
471 struct hns3_cfg_param_cmd {
477 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8
478 struct hns3_vport_vtag_rx_cfg_cmd {
479 uint8_t vport_vlan_cfg;
482 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM];
486 struct hns3_vport_vtag_tx_cfg_cmd {
487 uint8_t vport_vlan_cfg;
490 uint16_t def_vlan_tag1;
491 uint16_t def_vlan_tag2;
492 uint8_t vf_bitmap[8];
497 struct hns3_vlan_filter_ctrl_cmd {
505 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20
506 struct hns3_vlan_filter_pf_cfg_cmd {
510 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM];
513 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16
514 struct hns3_vlan_filter_vf_cfg_cmd {
520 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM];
523 struct hns3_tx_vlan_type_cfg_cmd {
524 uint16_t ot_vlan_type;
525 uint16_t in_vlan_type;
529 struct hns3_rx_vlan_type_cfg_cmd {
530 uint16_t ot_fst_vlan_type;
531 uint16_t ot_sec_vlan_type;
532 uint16_t in_fst_vlan_type;
533 uint16_t in_sec_vlan_type;
537 #define HNS3_TSO_MSS_MIN_S 0
538 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0)
540 #define HNS3_TSO_MSS_MAX_S 16
541 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16)
543 struct hns3_cfg_tso_status_cmd {
544 rte_le16_t tso_mss_min;
545 rte_le16_t tso_mss_max;
549 #define HNS3_GRO_EN_B 0
550 struct hns3_cfg_gro_status_cmd {
555 #define HNS3_TSO_MSS_MIN 256
556 #define HNS3_TSO_MSS_MAX 9668
558 #define HNS3_RSS_HASH_KEY_OFFSET_B 4
560 #define HNS3_RSS_CFG_TBL_SIZE 16
561 #define HNS3_RSS_HASH_KEY_NUM 16
562 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */
563 struct hns3_rss_generic_config_cmd {
564 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */
567 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM];
570 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */
571 struct hns3_rss_input_tuple_cmd {
572 uint64_t tuple_field;
576 #define HNS3_RSS_CFG_TBL_SIZE 16
577 #define HNS3_RSS_CFG_TBL_SIZE_H 4
578 #define HNS3_RSS_CFG_TBL_BW_H 2
579 #define HNS3_RSS_CFG_TBL_BW_L 8
581 /* Configure the indirection table, opcode:0x0D07 */
582 struct hns3_rss_indirection_table_cmd {
583 uint16_t start_table_index; /* Bit3~0 must be 0x0. */
584 uint16_t rss_set_bitmap;
585 uint8_t rss_result_h[HNS3_RSS_CFG_TBL_SIZE_H];
586 uint8_t rss_result_l[HNS3_RSS_CFG_TBL_SIZE];
589 #define HNS3_RSS_TC_OFFSET_S 0
590 #define HNS3_RSS_TC_OFFSET_M GENMASK(10, 0)
591 #define HNS3_RSS_TC_SIZE_MSB_S 11
592 #define HNS3_RSS_TC_SIZE_MSB_OFFSET 3
593 #define HNS3_RSS_TC_SIZE_S 12
594 #define HNS3_RSS_TC_SIZE_M GENMASK(14, 12)
595 #define HNS3_RSS_TC_VALID_B 15
597 /* Configure the tc_size and tc_offset, opcode:0x0D08 */
598 struct hns3_rss_tc_mode_cmd {
599 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM];
603 #define HNS3_LINK_STATUS_UP_B 0
604 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B)
605 struct hns3_link_status_cmd {
610 struct hns3_promisc_param {
615 #define HNS3_PROMISC_TX_EN_B BIT(4)
616 #define HNS3_PROMISC_RX_EN_B BIT(5)
617 #define HNS3_PROMISC_EN_B 1
618 #define HNS3_PROMISC_EN_ALL 0x7
619 #define HNS3_PROMISC_EN_UC 0x1
620 #define HNS3_PROMISC_EN_MC 0x2
621 #define HNS3_PROMISC_EN_BC 0x4
622 struct hns3_promisc_cfg_cmd {
629 enum hns3_promisc_type {
635 #define HNS3_MAC_TX_EN_B 6
636 #define HNS3_MAC_RX_EN_B 7
637 #define HNS3_MAC_PAD_TX_B 11
638 #define HNS3_MAC_PAD_RX_B 12
639 #define HNS3_MAC_1588_TX_B 13
640 #define HNS3_MAC_1588_RX_B 14
641 #define HNS3_MAC_APP_LP_B 15
642 #define HNS3_MAC_LINE_LP_B 16
643 #define HNS3_MAC_FCS_TX_B 17
644 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18
645 #define HNS3_MAC_RX_FCS_STRIP_B 19
646 #define HNS3_MAC_RX_FCS_B 20
647 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21
648 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22
650 struct hns3_config_mac_mode_cmd {
651 uint32_t txrx_pad_fcs_loop_en;
655 #define HNS3_CFG_SPEED_10M 6
656 #define HNS3_CFG_SPEED_100M 7
657 #define HNS3_CFG_SPEED_1G 0
658 #define HNS3_CFG_SPEED_10G 1
659 #define HNS3_CFG_SPEED_25G 2
660 #define HNS3_CFG_SPEED_40G 3
661 #define HNS3_CFG_SPEED_50G 4
662 #define HNS3_CFG_SPEED_100G 5
663 #define HNS3_CFG_SPEED_200G 8
665 #define HNS3_CFG_SPEED_S 0
666 #define HNS3_CFG_SPEED_M GENMASK(5, 0)
667 #define HNS3_CFG_DUPLEX_B 7
668 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B)
670 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0
672 struct hns3_config_mac_speed_dup_cmd {
674 uint8_t mac_change_fec_en;
678 #define HNS3_TQP_ENABLE_B 0
680 #define HNS3_MAC_CFG_AN_EN_B 0
681 #define HNS3_MAC_CFG_AN_INT_EN_B 1
682 #define HNS3_MAC_CFG_AN_INT_MSK_B 2
683 #define HNS3_MAC_CFG_AN_INT_CLR_B 3
684 #define HNS3_MAC_CFG_AN_RST_B 4
686 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B)
688 struct hns3_config_auto_neg_cmd {
689 uint32_t cfg_an_cmd_flag;
693 #define HNS3_MAC_CFG_FEC_AUTO_EN_B 0
694 #define HNS3_MAC_CFG_FEC_MODE_S 1
695 #define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
696 #define HNS3_MAC_FEC_OFF 0
697 #define HNS3_MAC_FEC_BASER 1
698 #define HNS3_MAC_FEC_RS 2
700 struct hns3_sfp_speed_cmd {
702 uint8_t query_type; /* 0: sfp speed, 1: active fec */
703 uint8_t active_fec; /* current FEC mode */
708 /* Configure FEC mode, opcode:0x031A */
709 struct hns3_config_fec_cmd {
714 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0)
715 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1)
716 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
717 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc
719 struct hns3_mac_mgr_tbl_entry_cmd {
723 uint32_t mac_addr_hi32;
724 uint16_t mac_addr_lo16;
726 uint16_t ethter_type;
727 uint16_t egress_port;
728 uint16_t egress_queue;
729 uint8_t sw_port_id_aware;
731 uint8_t i_port_bitmap;
732 uint8_t i_port_direction;
736 struct hns3_cfg_com_tqp_queue_cmd {
743 #define HNS3_TQP_MAP_TYPE_PF 0
744 #define HNS3_TQP_MAP_TYPE_VF 1
745 #define HNS3_TQP_MAP_TYPE_B 0
746 #define HNS3_TQP_MAP_EN_B 1
748 struct hns3_tqp_map_cmd {
749 uint16_t tqp_id; /* Absolute tqp id for in this pf */
750 uint8_t tqp_vf; /* VF id */
751 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */
752 uint16_t tqp_vid; /* Virtual id in this pf/vf */
756 enum hns3_ring_type {
761 enum hns3_int_gl_idx {
764 HNS3_RING_GL_IMMEDIATE = 3
767 #define HNS3_RING_GL_IDX_S 0
768 #define HNS3_RING_GL_IDX_M GENMASK(1, 0)
770 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10
772 #define HNS3_INT_TYPE_S 0
773 #define HNS3_INT_TYPE_M GENMASK(1, 0)
774 #define HNS3_TQP_ID_S 2
775 #define HNS3_TQP_ID_M GENMASK(12, 2)
776 #define HNS3_INT_GL_IDX_S 13
777 #define HNS3_INT_GL_IDX_M GENMASK(14, 13)
778 struct hns3_ctrl_vector_chain_cmd {
779 uint8_t int_vector_id;
780 uint8_t int_cause_num;
781 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD];
786 struct hns3_config_max_frm_size_cmd {
787 uint16_t max_frm_size;
788 uint8_t min_frm_size;
792 enum hns3_mac_vlan_tbl_opcode {
793 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
794 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */
795 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
796 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
799 enum hns3_mac_vlan_add_resp_code {
800 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
801 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
804 #define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3
806 #define HNS3_MAC_VLAN_BIT0_EN_B 0
807 #define HNS3_MAC_VLAN_BIT1_EN_B 1
808 #define HNS3_MAC_EPORT_SW_EN_B 12
809 #define HNS3_MAC_EPORT_TYPE_B 11
810 #define HNS3_MAC_EPORT_VFID_S 3
811 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3)
812 #define HNS3_MAC_EPORT_PFID_S 0
813 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0)
814 struct hns3_mac_vlan_tbl_entry_cmd {
818 uint32_t mac_addr_hi32;
819 uint16_t mac_addr_lo16;
823 uint16_t egress_port;
824 uint16_t egress_queue;
828 #define HNS3_TQP_RESET_B 0
829 struct hns3_reset_tqp_queue_cmd {
832 uint8_t ready_to_reset;
833 uint8_t queue_direction;
837 #define HNS3_CFG_RESET_MAC_B 3
838 #define HNS3_CFG_RESET_FUNC_B 7
839 struct hns3_reset_cmd {
840 uint8_t mac_func_reset;
841 uint8_t fun_reset_vfid;
845 #define HNS3_QUERY_DEV_SPECS_BD_NUM 4
846 struct hns3_dev_specs_0_cmd {
848 uint32_t mac_entry_num;
849 uint32_t mng_entry_num;
850 uint16_t rss_ind_tbl_size;
851 uint16_t rss_key_size;
852 uint16_t intr_ql_max;
853 uint8_t max_non_tso_bd_num;
855 uint32_t max_tm_rate;
858 #define HNS3_MAX_TQP_NUM_HIP08_PF 64
859 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
860 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
861 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */
862 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
863 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
865 #define HNS3_TYPE_CRQ 0
866 #define HNS3_TYPE_CSQ 1
868 #define HNS3_NIC_SW_RST_RDY_B 16
869 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B)
870 #define HNS3_NIC_CMQ_DESC_NUM 1024
871 #define HNS3_NIC_CMQ_DESC_NUM_S 3
873 #define HNS3_CMD_SEND_SYNC(flag) \
874 ((flag) & HNS3_CMD_FLAG_NO_INTR)
876 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read);
877 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc,
878 enum hns3_opcode_type opcode, bool is_read);
879 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num);
880 int hns3_cmd_init_queue(struct hns3_hw *hw);
881 int hns3_cmd_init(struct hns3_hw *hw);
882 void hns3_cmd_destroy_queue(struct hns3_hw *hw);
883 void hns3_cmd_uninit(struct hns3_hw *hw);
885 #endif /* _HNS3_CMD_H_ */