drivers/net/hns3/hns3_dcb.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <rte_io.h>
  11 #include <rte_common.h>
  12 #include <rte_ethdev.h>
  13
  14 #include "hns3_logs.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_ethdev.h"
  17 #include "hns3_dcb.h"
  18
  19 #define HNS3_SHAPER_BS_U_DEF    5
  20 #define HNS3_SHAPER_BS_S_DEF    20
  21 #define BW_MAX_PERCENT          100
  22 #define HNS3_ETHER_MAX_RATE     100000
  23
  24 /*
  25  * hns3_shaper_para_calc: calculate ir parameter for the shaper
  26  * @ir: Rate to be config, its unit is Mbps
  27  * @shaper_level: the shaper level. eg: port, pg, priority, queueset
  28  * @shaper_para: shaper parameter of IR shaper
  29  *
  30  * the formula:
  31  *
  32  *              IR_b * (2 ^ IR_u) * 8
  33  * IR(Mbps) = -------------------------  *  CLOCK(1000Mbps)
  34  *              Tick * (2 ^ IR_s)
  35  *
  36  * @return: 0: calculate sucessful, negative: fail
  37  */
  38 static int
  39 hns3_shaper_para_calc(struct hns3_hw *hw, uint32_t ir, uint8_t shaper_level,
  40                       struct hns3_shaper_parameter *shaper_para)
  41 {
  42 #define SHAPER_DEFAULT_IR_B     126
  43 #define DIVISOR_CLK             (1000 * 8)
  44 #define DIVISOR_IR_B_126        (126 * DIVISOR_CLK)
  45
  46         const uint16_t tick_array[HNS3_SHAPER_LVL_CNT] = {
  47                 6 * 256,    /* Prioriy level */
  48                 6 * 32,     /* Prioriy group level */
  49                 6 * 8,      /* Port level */
  50                 6 * 256     /* Qset level */
  51         };
  52         uint8_t ir_u_calc = 0;
  53         uint8_t ir_s_calc = 0;
  54         uint32_t denominator;
  55         uint32_t ir_calc;
  56         uint32_t tick;
  57
  58         /* Calc tick */
  59         if (shaper_level >= HNS3_SHAPER_LVL_CNT) {
  60                 hns3_err(hw,
  61                          "shaper_level(%d) is greater than HNS3_SHAPER_LVL_CNT(%d)",
  62                          shaper_level, HNS3_SHAPER_LVL_CNT);
  63                 return -EINVAL;
  64         }
  65
  66         if (ir > HNS3_ETHER_MAX_RATE) {
  67                 hns3_err(hw, "rate(%d) exceeds the rate driver supported "
  68                          "HNS3_ETHER_MAX_RATE(%d)", ir, HNS3_ETHER_MAX_RATE);
  69                 return -EINVAL;
  70         }
  71
  72         tick = tick_array[shaper_level];
  73
  74         /*
  75          * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
  76          * the formula is changed to:
  77          *              126 * 1 * 8
  78          * ir_calc = ---------------- * 1000
  79          *              tick * 1
  80          */
  81         ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
  82
  83         if (ir_calc == ir) {
  84                 shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
  85         } else if (ir_calc > ir) {
  86                 /* Increasing the denominator to select ir_s value */
  87                 do {
  88                         ir_s_calc++;
  89                         ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
  90                 } while (ir_calc > ir);
  91
  92                 if (ir_calc == ir)
  93                         shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
  94                 else
  95                         shaper_para->ir_b = (ir * tick * (1 << ir_s_calc) +
  96                                  (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
  97         } else {
  98                 /*
  99                  * Increasing the numerator to select ir_u value. ir_u_calc will
 100                  * get maximum value when ir_calc is minimum and ir is maximum.
 101                  * ir_calc gets minimum value when tick is the maximum value.
 102                  * At the same time, value of ir_u_calc can only be increased up
 103                  * to eight after the while loop if the value of ir is equal
 104                  * to HNS3_ETHER_MAX_RATE.
 105                  */
 106                 uint32_t numerator;
 107                 do {
 108                         ir_u_calc++;
 109                         numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
 110                         ir_calc = (numerator + (tick >> 1)) / tick;
 111                 } while (ir_calc < ir);
 112
 113                 if (ir_calc == ir) {
 114                         shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
 115                 } else {
 116                         --ir_u_calc;
 117
 118                         /*
 119                          * The maximum value of ir_u_calc in this branch is
 120                          * seven in all cases. Thus, value of denominator can
 121                          * not be zero here.
 122                          */
 123                         denominator = DIVISOR_CLK * (1 << ir_u_calc);
 124                         shaper_para->ir_b =
 125                                 (ir * tick + (denominator >> 1)) / denominator;
 126                 }
 127         }
 128
 129         shaper_para->ir_u = ir_u_calc;
 130         shaper_para->ir_s = ir_s_calc;
 131
 132         return 0;
 133 }
 134
 135 static int
 136 hns3_fill_pri_array(struct hns3_hw *hw, uint8_t *pri, uint8_t pri_id)
 137 {
 138 #define HNS3_HALF_BYTE_BIT_OFFSET 4
 139         uint8_t tc = hw->dcb_info.prio_tc[pri_id];
 140
 141         if (tc >= hw->dcb_info.num_tc)
 142                 return -EINVAL;
 143
 144         /*
 145          * The register for priority has four bytes, the first bytes includes
 146          *  priority0 and priority1, the higher 4bit stands for priority1
 147          *  while the lower 4bit stands for priority0, as below:
 148          * first byte:  | pri_1 | pri_0 |
 149          * second byte: | pri_3 | pri_2 |
 150          * third byte:  | pri_5 | pri_4 |
 151          * fourth byte: | pri_7 | pri_6 |
 152          */
 153         pri[pri_id >> 1] |= tc << ((pri_id & 1) * HNS3_HALF_BYTE_BIT_OFFSET);
 154
 155         return 0;
 156 }
 157
 158 static int
 159 hns3_up_to_tc_map(struct hns3_hw *hw)
 160 {
 161         struct hns3_cmd_desc desc;
 162         uint8_t *pri = (uint8_t *)desc.data;
 163         uint8_t pri_id;
 164         int ret;
 165
 166         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PRI_TO_TC_MAPPING, false);
 167
 168         for (pri_id = 0; pri_id < HNS3_MAX_USER_PRIO; pri_id++) {
 169                 ret = hns3_fill_pri_array(hw, pri, pri_id);
 170                 if (ret)
 171                         return ret;
 172         }
 173
 174         return hns3_cmd_send(hw, &desc, 1);
 175 }
 176
 177 static int
 178 hns3_pg_to_pri_map_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t pri_bit_map)
 179 {
 180         struct hns3_pg_to_pri_link_cmd *map;
 181         struct hns3_cmd_desc desc;
 182
 183         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_TO_PRI_LINK, false);
 184
 185         map = (struct hns3_pg_to_pri_link_cmd *)desc.data;
 186
 187         map->pg_id = pg_id;
 188         map->pri_bit_map = pri_bit_map;
 189
 190         return hns3_cmd_send(hw, &desc, 1);
 191 }
 192
 193 static int
 194 hns3_pg_to_pri_map(struct hns3_hw *hw)
 195 {
 196         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 197         struct hns3_pf *pf = &hns->pf;
 198         struct hns3_pg_info *pg_info;
 199         int ret, i;
 200
 201         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 202                 return -EINVAL;
 203
 204         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 205                 /* Cfg pg to priority mapping */
 206                 pg_info = &hw->dcb_info.pg_info[i];
 207                 ret = hns3_pg_to_pri_map_cfg(hw, i, pg_info->tc_bit_map);
 208                 if (ret)
 209                         return ret;
 210         }
 211
 212         return 0;
 213 }
 214
 215 static int
 216 hns3_qs_to_pri_map_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t pri)
 217 {
 218         struct hns3_qs_to_pri_link_cmd *map;
 219         struct hns3_cmd_desc desc;
 220
 221         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_TO_PRI_LINK, false);
 222
 223         map = (struct hns3_qs_to_pri_link_cmd *)desc.data;
 224
 225         map->qs_id = rte_cpu_to_le_16(qs_id);
 226         map->priority = pri;
 227         map->link_vld = HNS3_DCB_QS_PRI_LINK_VLD_MSK;
 228
 229         return hns3_cmd_send(hw, &desc, 1);
 230 }
 231
 232 static int
 233 hns3_dcb_qs_weight_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t dwrr)
 234 {
 235         struct hns3_qs_weight_cmd *weight;
 236         struct hns3_cmd_desc desc;
 237
 238         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_WEIGHT, false);
 239
 240         weight = (struct hns3_qs_weight_cmd *)desc.data;
 241
 242         weight->qs_id = rte_cpu_to_le_16(qs_id);
 243         weight->dwrr = dwrr;
 244
 245         return hns3_cmd_send(hw, &desc, 1);
 246 }
 247
 248 static int
 249 hns3_dcb_ets_tc_dwrr_cfg(struct hns3_hw *hw)
 250 {
 251 #define DEFAULT_TC_WEIGHT       1
 252 #define DEFAULT_TC_OFFSET       14
 253         struct hns3_ets_tc_weight_cmd *ets_weight;
 254         struct hns3_cmd_desc desc;
 255         uint8_t i;
 256
 257         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_ETS_TC_WEIGHT, false);
 258         ets_weight = (struct hns3_ets_tc_weight_cmd *)desc.data;
 259
 260         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 261                 struct hns3_pg_info *pg_info;
 262
 263                 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
 264
 265                 if (!(hw->hw_tc_map & BIT(i)))
 266                         continue;
 267
 268                 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
 269                 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
 270         }
 271
 272         ets_weight->weight_offset = DEFAULT_TC_OFFSET;
 273
 274         return hns3_cmd_send(hw, &desc, 1);
 275 }
 276
 277 static int
 278 hns3_dcb_pri_weight_cfg(struct hns3_hw *hw, uint8_t pri_id, uint8_t dwrr)
 279 {
 280         struct hns3_priority_weight_cmd *weight;
 281         struct hns3_cmd_desc desc;
 282
 283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_WEIGHT, false);
 284
 285         weight = (struct hns3_priority_weight_cmd *)desc.data;
 286
 287         weight->pri_id = pri_id;
 288         weight->dwrr = dwrr;
 289
 290         return hns3_cmd_send(hw, &desc, 1);
 291 }
 292
 293 static int
 294 hns3_dcb_pg_weight_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t dwrr)
 295 {
 296         struct hns3_pg_weight_cmd *weight;
 297         struct hns3_cmd_desc desc;
 298
 299         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_WEIGHT, false);
 300
 301         weight = (struct hns3_pg_weight_cmd *)desc.data;
 302
 303         weight->pg_id = pg_id;
 304         weight->dwrr = dwrr;
 305
 306         return hns3_cmd_send(hw, &desc, 1);
 307 }
 308 static int
 309 hns3_dcb_pg_schd_mode_cfg(struct hns3_hw *hw, uint8_t pg_id)
 310 {
 311         struct hns3_cmd_desc desc;
 312
 313         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_SCH_MODE_CFG, false);
 314
 315         if (hw->dcb_info.pg_info[pg_id].pg_sch_mode == HNS3_SCH_MODE_DWRR)
 316                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 317         else
 318                 desc.data[1] = 0;
 319
 320         desc.data[0] = rte_cpu_to_le_32(pg_id);
 321
 322         return hns3_cmd_send(hw, &desc, 1);
 323 }
 324
 325 static uint32_t
 326 hns3_dcb_get_shapping_para(uint8_t ir_b, uint8_t ir_u, uint8_t ir_s,
 327                            uint8_t bs_b, uint8_t bs_s)
 328 {
 329         uint32_t shapping_para = 0;
 330
 331         hns3_dcb_set_field(shapping_para, IR_B, ir_b);
 332         hns3_dcb_set_field(shapping_para, IR_U, ir_u);
 333         hns3_dcb_set_field(shapping_para, IR_S, ir_s);
 334         hns3_dcb_set_field(shapping_para, BS_B, bs_b);
 335         hns3_dcb_set_field(shapping_para, BS_S, bs_s);
 336
 337         return shapping_para;
 338 }
 339
 340 static int
 341 hns3_dcb_port_shaper_cfg(struct hns3_hw *hw)
 342 {
 343         struct hns3_port_shapping_cmd *shap_cfg_cmd;
 344         struct hns3_shaper_parameter shaper_parameter;
 345         uint32_t shapping_para;
 346         uint32_t ir_u, ir_b, ir_s;
 347         struct hns3_cmd_desc desc;
 348         int ret;
 349
 350         ret = hns3_shaper_para_calc(hw, hw->mac.link_speed,
 351                                     HNS3_SHAPER_LVL_PORT, &shaper_parameter);
 352         if (ret) {
 353                 hns3_err(hw, "calculate shaper parameter failed: %d", ret);
 354                 return ret;
 355         }
 356
 357         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PORT_SHAPPING, false);
 358         shap_cfg_cmd = (struct hns3_port_shapping_cmd *)desc.data;
 359
 360         ir_b = shaper_parameter.ir_b;
 361         ir_u = shaper_parameter.ir_u;
 362         ir_s = shaper_parameter.ir_s;
 363         shapping_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 364                                                    HNS3_SHAPER_BS_U_DEF,
 365                                                    HNS3_SHAPER_BS_S_DEF);
 366
 367         shap_cfg_cmd->port_shapping_para = rte_cpu_to_le_32(shapping_para);
 368
 369         return hns3_cmd_send(hw, &desc, 1);
 370 }
 371
 372 static int
 373 hns3_dcb_pg_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
 374                          uint8_t pg_id, uint32_t shapping_para)
 375 {
 376         struct hns3_pg_shapping_cmd *shap_cfg_cmd;
 377         enum hns3_opcode_type opcode;
 378         struct hns3_cmd_desc desc;
 379
 380         opcode = bucket ? HNS3_OPC_TM_PG_P_SHAPPING :
 381                  HNS3_OPC_TM_PG_C_SHAPPING;
 382         hns3_cmd_setup_basic_desc(&desc, opcode, false);
 383
 384         shap_cfg_cmd = (struct hns3_pg_shapping_cmd *)desc.data;
 385
 386         shap_cfg_cmd->pg_id = pg_id;
 387
 388         shap_cfg_cmd->pg_shapping_para = rte_cpu_to_le_32(shapping_para);
 389
 390         return hns3_cmd_send(hw, &desc, 1);
 391 }
 392
 393 static int
 394 hns3_dcb_pg_shaper_cfg(struct hns3_hw *hw)
 395 {
 396         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 397         struct hns3_shaper_parameter shaper_parameter;
 398         struct hns3_pf *pf = &hns->pf;
 399         uint32_t ir_u, ir_b, ir_s;
 400         uint32_t shaper_para;
 401         uint8_t i;
 402         int ret;
 403
 404         /* Cfg pg schd */
 405         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 406                 return -EINVAL;
 407
 408         /* Pg to pri */
 409         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 410                 /* Calc shaper para */
 411                 ret = hns3_shaper_para_calc(hw,
 412                                             hw->dcb_info.pg_info[i].bw_limit,
 413                                             HNS3_SHAPER_LVL_PG,
 414                                             &shaper_parameter);
 415                 if (ret) {
 416                         hns3_err(hw, "calculate shaper parameter failed: %d",
 417                                  ret);
 418                         return ret;
 419                 }
 420
 421                 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
 422                                                          HNS3_SHAPER_BS_U_DEF,
 423                                                          HNS3_SHAPER_BS_S_DEF);
 424
 425                 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
 426                                                shaper_para);
 427                 if (ret) {
 428                         hns3_err(hw,
 429                                  "config PG CIR shaper parameter failed: %d",
 430                                  ret);
 431                         return ret;
 432                 }
 433
 434                 ir_b = shaper_parameter.ir_b;
 435                 ir_u = shaper_parameter.ir_u;
 436                 ir_s = shaper_parameter.ir_s;
 437                 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 438                                                          HNS3_SHAPER_BS_U_DEF,
 439                                                          HNS3_SHAPER_BS_S_DEF);
 440
 441                 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
 442                                                shaper_para);
 443                 if (ret) {
 444                         hns3_err(hw,
 445                                  "config PG PIR shaper parameter failed: %d",
 446                                  ret);
 447                         return ret;
 448                 }
 449         }
 450
 451         return 0;
 452 }
 453
 454 static int
 455 hns3_dcb_qs_schd_mode_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t mode)
 456 {
 457         struct hns3_cmd_desc desc;
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_SCH_MODE_CFG, false);
 460
 461         if (mode == HNS3_SCH_MODE_DWRR)
 462                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 463         else
 464                 desc.data[1] = 0;
 465
 466         desc.data[0] = rte_cpu_to_le_32(qs_id);
 467
 468         return hns3_cmd_send(hw, &desc, 1);
 469 }
 470
 471 static int
 472 hns3_dcb_pri_schd_mode_cfg(struct hns3_hw *hw, uint8_t pri_id)
 473 {
 474         struct hns3_cmd_desc desc;
 475
 476         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_SCH_MODE_CFG, false);
 477
 478         if (hw->dcb_info.tc_info[pri_id].tc_sch_mode == HNS3_SCH_MODE_DWRR)
 479                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 480         else
 481                 desc.data[1] = 0;
 482
 483         desc.data[0] = rte_cpu_to_le_32(pri_id);
 484
 485         return hns3_cmd_send(hw, &desc, 1);
 486 }
 487
 488 static int
 489 hns3_dcb_pri_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
 490                           uint8_t pri_id, uint32_t shapping_para)
 491 {
 492         struct hns3_pri_shapping_cmd *shap_cfg_cmd;
 493         enum hns3_opcode_type opcode;
 494         struct hns3_cmd_desc desc;
 495
 496         opcode = bucket ? HNS3_OPC_TM_PRI_P_SHAPPING :
 497                  HNS3_OPC_TM_PRI_C_SHAPPING;
 498
 499         hns3_cmd_setup_basic_desc(&desc, opcode, false);
 500
 501         shap_cfg_cmd = (struct hns3_pri_shapping_cmd *)desc.data;
 502
 503         shap_cfg_cmd->pri_id = pri_id;
 504
 505         shap_cfg_cmd->pri_shapping_para = rte_cpu_to_le_32(shapping_para);
 506
 507         return hns3_cmd_send(hw, &desc, 1);
 508 }
 509
 510 static int
 511 hns3_dcb_pri_tc_base_shaper_cfg(struct hns3_hw *hw)
 512 {
 513         struct hns3_shaper_parameter shaper_parameter;
 514         uint32_t ir_u, ir_b, ir_s;
 515         uint32_t shaper_para;
 516         int ret, i;
 517
 518         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 519                 ret = hns3_shaper_para_calc(hw,
 520                                             hw->dcb_info.tc_info[i].bw_limit,
 521                                             HNS3_SHAPER_LVL_PRI,
 522                                             &shaper_parameter);
 523                 if (ret) {
 524                         hns3_err(hw, "calculate shaper parameter failed: %d",
 525                                  ret);
 526                         return ret;
 527                 }
 528
 529                 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
 530                                                          HNS3_SHAPER_BS_U_DEF,
 531                                                          HNS3_SHAPER_BS_S_DEF);
 532
 533                 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
 534                                                 shaper_para);
 535                 if (ret) {
 536                         hns3_err(hw,
 537                                  "config priority CIR shaper parameter failed: %d",
 538                                  ret);
 539                         return ret;
 540                 }
 541
 542                 ir_b = shaper_parameter.ir_b;
 543                 ir_u = shaper_parameter.ir_u;
 544                 ir_s = shaper_parameter.ir_s;
 545                 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 546                                                          HNS3_SHAPER_BS_U_DEF,
 547                                                          HNS3_SHAPER_BS_S_DEF);
 548
 549                 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
 550                                                 shaper_para);
 551                 if (ret) {
 552                         hns3_err(hw,
 553                                  "config priority PIR shaper parameter failed: %d",
 554                                  ret);
 555                         return ret;
 556                 }
 557         }
 558
 559         return 0;
 560 }
 561
 562
 563 static int
 564 hns3_dcb_pri_shaper_cfg(struct hns3_hw *hw)
 565 {
 566         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 567         struct hns3_pf *pf = &hns->pf;
 568         int ret;
 569
 570         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 571                 return -EINVAL;
 572
 573         ret = hns3_dcb_pri_tc_base_shaper_cfg(hw);
 574         if (ret)
 575                 hns3_err(hw, "config port shaper failed: %d", ret);
 576
 577         return ret;
 578 }
 579
 580 void
 581 hns3_tc_queue_mapping_cfg(struct hns3_hw *hw)
 582 {
 583         struct hns3_tc_queue_info *tc_queue;
 584         uint8_t i;
 585
 586         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 587                 tc_queue = &hw->tc_queue[i];
 588                 if (hw->hw_tc_map & BIT(i) && i < hw->num_tc) {
 589                         tc_queue->enable = true;
 590                         tc_queue->tqp_offset = i * hw->alloc_rss_size;
 591                         tc_queue->tqp_count = hw->alloc_rss_size;
 592                         tc_queue->tc = i;
 593                 } else {
 594                         /* Set to default queue if TC is disable */
 595                         tc_queue->enable = false;
 596                         tc_queue->tqp_offset = 0;
 597                         tc_queue->tqp_count = 0;
 598                         tc_queue->tc = 0;
 599                 }
 600         }
 601 }
 602
 603 static void
 604 hns3_dcb_update_tc_queue_mapping(struct hns3_hw *hw, uint16_t queue_num)
 605 {
 606         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 607         struct hns3_pf *pf = &hns->pf;
 608         uint16_t tqpnum_per_tc;
 609         uint16_t alloc_tqps;
 610
 611         alloc_tqps = RTE_MIN(hw->tqps_num, queue_num);
 612         hw->num_tc = RTE_MIN(alloc_tqps, hw->dcb_info.num_tc);
 613         tqpnum_per_tc = RTE_MIN(hw->rss_size_max, alloc_tqps / hw->num_tc);
 614
 615         if (hw->alloc_rss_size != tqpnum_per_tc) {
 616                 PMD_INIT_LOG(INFO, "rss size changes from %d to %d",
 617                              hw->alloc_rss_size, tqpnum_per_tc);
 618                 hw->alloc_rss_size = tqpnum_per_tc;
 619         }
 620         hw->alloc_tqps = hw->num_tc * hw->alloc_rss_size;
 621
 622         hns3_tc_queue_mapping_cfg(hw);
 623
 624         memcpy(pf->prio_tc, hw->dcb_info.prio_tc, HNS3_MAX_USER_PRIO);
 625 }
 626
 627 int
 628 hns3_dcb_info_init(struct hns3_hw *hw)
 629 {
 630         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 631         struct hns3_pf *pf = &hns->pf;
 632         int i, k;
 633
 634         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
 635             hw->dcb_info.num_pg != 1)
 636                 return -EINVAL;
 637
 638         /* Initializing PG information */
 639         memset(hw->dcb_info.pg_info, 0,
 640                sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
 641         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 642                 hw->dcb_info.pg_dwrr[i] = i ? 0 : BW_MAX_PERCENT;
 643                 hw->dcb_info.pg_info[i].pg_id = i;
 644                 hw->dcb_info.pg_info[i].pg_sch_mode = HNS3_SCH_MODE_DWRR;
 645                 hw->dcb_info.pg_info[i].bw_limit = HNS3_ETHER_MAX_RATE;
 646
 647                 if (i != 0)
 648                         continue;
 649
 650                 hw->dcb_info.pg_info[i].tc_bit_map = hw->hw_tc_map;
 651                 for (k = 0; k < hw->dcb_info.num_tc; k++)
 652                         hw->dcb_info.pg_info[i].tc_dwrr[k] = BW_MAX_PERCENT;
 653         }
 654
 655         /* All UPs mapping to TC0 */
 656         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
 657                 hw->dcb_info.prio_tc[i] = 0;
 658
 659         /* Initializing tc information */
 660         memset(hw->dcb_info.tc_info, 0,
 661                sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
 662         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 663                 hw->dcb_info.tc_info[i].tc_id = i;
 664                 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
 665                 hw->dcb_info.tc_info[i].pgid = 0;
 666                 hw->dcb_info.tc_info[i].bw_limit =
 667                         hw->dcb_info.pg_info[0].bw_limit;
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int
 674 hns3_dcb_lvl2_schd_mode_cfg(struct hns3_hw *hw)
 675 {
 676         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 677         struct hns3_pf *pf = &hns->pf;
 678         int ret, i;
 679
 680         /* Only being config on TC-Based scheduler mode */
 681         if (pf->tx_sch_mode == HNS3_FLAG_VNET_BASE_SCH_MODE)
 682                 return -EINVAL;
 683
 684         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 685                 ret = hns3_dcb_pg_schd_mode_cfg(hw, i);
 686                 if (ret)
 687                         return ret;
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int
 694 hns3_dcb_lvl34_schd_mode_cfg(struct hns3_hw *hw)
 695 {
 696         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 697         struct hns3_pf *pf = &hns->pf;
 698         uint8_t i;
 699         int ret;
 700
 701         if (pf->tx_sch_mode == HNS3_FLAG_TC_BASE_SCH_MODE) {
 702                 for (i = 0; i < hw->dcb_info.num_tc; i++) {
 703                         ret = hns3_dcb_pri_schd_mode_cfg(hw, i);
 704                         if (ret)
 705                                 return ret;
 706
 707                         ret = hns3_dcb_qs_schd_mode_cfg(hw, i,
 708                                                         HNS3_SCH_MODE_DWRR);
 709                         if (ret)
 710                                 return ret;
 711                 }
 712         }
 713
 714         return 0;
 715 }
 716
 717 static int
 718 hns3_dcb_schd_mode_cfg(struct hns3_hw *hw)
 719 {
 720         int ret;
 721
 722         ret = hns3_dcb_lvl2_schd_mode_cfg(hw);
 723         if (ret) {
 724                 hns3_err(hw, "config lvl2_schd_mode failed: %d", ret);
 725                 return ret;
 726         }
 727
 728         ret = hns3_dcb_lvl34_schd_mode_cfg(hw);
 729         if (ret) {
 730                 hns3_err(hw, "config lvl34_schd_mode failed: %d", ret);
 731                 return ret;
 732         }
 733
 734         return 0;
 735 }
 736
 737 static int
 738 hns3_dcb_pri_tc_base_dwrr_cfg(struct hns3_hw *hw)
 739 {
 740         struct hns3_pg_info *pg_info;
 741         uint8_t dwrr;
 742         int ret, i;
 743
 744         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 745                 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
 746                 dwrr = pg_info->tc_dwrr[i];
 747
 748                 ret = hns3_dcb_pri_weight_cfg(hw, i, dwrr);
 749                 if (ret) {
 750                         hns3_err(hw, "fail to send priority weight cmd: %d", i);
 751                         return ret;
 752                 }
 753
 754                 ret = hns3_dcb_qs_weight_cfg(hw, i, BW_MAX_PERCENT);
 755                 if (ret) {
 756                         hns3_err(hw, "fail to send qs_weight cmd: %d", i);
 757                         return ret;
 758                 }
 759         }
 760
 761         return 0;
 762 }
 763
 764 static int
 765 hns3_dcb_pri_dwrr_cfg(struct hns3_hw *hw)
 766 {
 767         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 768         struct hns3_pf *pf = &hns->pf;
 769         int ret;
 770
 771         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 772                 return -EINVAL;
 773
 774         ret = hns3_dcb_pri_tc_base_dwrr_cfg(hw);
 775         if (ret)
 776                 return ret;
 777
 778         if (!hns3_dev_dcb_supported(hw))
 779                 return 0;
 780
 781         ret = hns3_dcb_ets_tc_dwrr_cfg(hw);
 782         if (ret == -EOPNOTSUPP) {
 783                 hns3_warn(hw, "fw %08x does't support ets tc weight cmd",
 784                           hw->fw_version);
 785                 ret = 0;
 786         }
 787
 788         return ret;
 789 }
 790
 791 static int
 792 hns3_dcb_pg_dwrr_cfg(struct hns3_hw *hw)
 793 {
 794         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 795         struct hns3_pf *pf = &hns->pf;
 796         int ret, i;
 797
 798         /* Cfg pg schd */
 799         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 800                 return -EINVAL;
 801
 802         /* Cfg pg to prio */
 803         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 804                 /* Cfg dwrr */
 805                 ret = hns3_dcb_pg_weight_cfg(hw, i, hw->dcb_info.pg_dwrr[i]);
 806                 if (ret)
 807                         return ret;
 808         }
 809
 810         return 0;
 811 }
 812
 813 static int
 814 hns3_dcb_dwrr_cfg(struct hns3_hw *hw)
 815 {
 816         int ret;
 817
 818         ret = hns3_dcb_pg_dwrr_cfg(hw);
 819         if (ret) {
 820                 hns3_err(hw, "config pg_dwrr failed: %d", ret);
 821                 return ret;
 822         }
 823
 824         ret = hns3_dcb_pri_dwrr_cfg(hw);
 825         if (ret) {
 826                 hns3_err(hw, "config pri_dwrr failed: %d", ret);
 827                 return ret;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static int
 834 hns3_dcb_shaper_cfg(struct hns3_hw *hw)
 835 {
 836         int ret;
 837
 838         ret = hns3_dcb_port_shaper_cfg(hw);
 839         if (ret) {
 840                 hns3_err(hw, "config port shaper failed: %d", ret);
 841                 return ret;
 842         }
 843
 844         ret = hns3_dcb_pg_shaper_cfg(hw);
 845         if (ret) {
 846                 hns3_err(hw, "config pg shaper failed: %d", ret);
 847                 return ret;
 848         }
 849
 850         return hns3_dcb_pri_shaper_cfg(hw);
 851 }
 852
 853 static int
 854 hns3_q_to_qs_map_cfg(struct hns3_hw *hw, uint16_t q_id, uint16_t qs_id)
 855 {
 856         struct hns3_nq_to_qs_link_cmd *map;
 857         struct hns3_cmd_desc desc;
 858
 859         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_NQ_TO_QS_LINK, false);
 860
 861         map = (struct hns3_nq_to_qs_link_cmd *)desc.data;
 862
 863         map->nq_id = rte_cpu_to_le_16(q_id);
 864         map->qset_id = rte_cpu_to_le_16(qs_id | HNS3_DCB_Q_QS_LINK_VLD_MSK);
 865
 866         return hns3_cmd_send(hw, &desc, 1);
 867 }
 868
 869 static int
 870 hns3_q_to_qs_map(struct hns3_hw *hw)
 871 {
 872         struct hns3_tc_queue_info *tc_queue;
 873         uint16_t q_id;
 874         uint32_t i, j;
 875         int ret;
 876
 877         for (i = 0; i < hw->num_tc; i++) {
 878                 tc_queue = &hw->tc_queue[i];
 879                 for (j = 0; j < tc_queue->tqp_count; j++) {
 880                         q_id = tc_queue->tqp_offset + j;
 881                         ret = hns3_q_to_qs_map_cfg(hw, q_id, i);
 882                         if (ret)
 883                                 return ret;
 884                 }
 885         }
 886
 887         return 0;
 888 }
 889
 890 static int
 891 hns3_pri_q_qs_cfg(struct hns3_hw *hw)
 892 {
 893         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 894         struct hns3_pf *pf = &hns->pf;
 895         uint32_t i;
 896         int ret;
 897
 898         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 899                 return -EINVAL;
 900
 901         /* Cfg qs -> pri mapping */
 902         for (i = 0; i < hw->num_tc; i++) {
 903                 ret = hns3_qs_to_pri_map_cfg(hw, i, i);
 904                 if (ret) {
 905                         hns3_err(hw, "qs_to_pri mapping fail: %d", ret);
 906                         return ret;
 907                 }
 908         }
 909
 910         /* Cfg q -> qs mapping */
 911         ret = hns3_q_to_qs_map(hw);
 912         if (ret) {
 913                 hns3_err(hw, "nq_to_qs mapping fail: %d", ret);
 914                 return ret;
 915         }
 916
 917         return 0;
 918 }
 919
 920 static int
 921 hns3_dcb_map_cfg(struct hns3_hw *hw)
 922 {
 923         int ret;
 924
 925         ret = hns3_up_to_tc_map(hw);
 926         if (ret) {
 927                 hns3_err(hw, "up_to_tc mapping fail: %d", ret);
 928                 return ret;
 929         }
 930
 931         ret = hns3_pg_to_pri_map(hw);
 932         if (ret) {
 933                 hns3_err(hw, "pri_to_pg mapping fail: %d", ret);
 934                 return ret;
 935         }
 936
 937         return hns3_pri_q_qs_cfg(hw);
 938 }
 939
 940 static int
 941 hns3_dcb_schd_setup_hw(struct hns3_hw *hw)
 942 {
 943         int ret;
 944
 945         /* Cfg dcb mapping  */
 946         ret = hns3_dcb_map_cfg(hw);
 947         if (ret)
 948                 return ret;
 949
 950         /* Cfg dcb shaper */
 951         ret = hns3_dcb_shaper_cfg(hw);
 952         if (ret)
 953                 return ret;
 954
 955         /* Cfg dwrr */
 956         ret = hns3_dcb_dwrr_cfg(hw);
 957         if (ret)
 958                 return ret;
 959
 960         /* Cfg schd mode for each level schd */
 961         return hns3_dcb_schd_mode_cfg(hw);
 962 }
 963
 964 static int
 965 hns3_pause_param_cfg(struct hns3_hw *hw, const uint8_t *addr,
 966                      uint8_t pause_trans_gap, uint16_t pause_trans_time)
 967 {
 968         struct hns3_cfg_pause_param_cmd *pause_param;
 969         struct hns3_cmd_desc desc;
 970
 971         pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
 972
 973         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, false);
 974
 975         memcpy(pause_param->mac_addr, addr, RTE_ETHER_ADDR_LEN);
 976         memcpy(pause_param->mac_addr_extra, addr, RTE_ETHER_ADDR_LEN);
 977         pause_param->pause_trans_gap = pause_trans_gap;
 978         pause_param->pause_trans_time = rte_cpu_to_le_16(pause_trans_time);
 979
 980         return hns3_cmd_send(hw, &desc, 1);
 981 }
 982
 983 int
 984 hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr)
 985 {
 986         struct hns3_cfg_pause_param_cmd *pause_param;
 987         struct hns3_cmd_desc desc;
 988         uint16_t trans_time;
 989         uint8_t trans_gap;
 990         int ret;
 991
 992         pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
 993
 994         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, true);
 995
 996         ret = hns3_cmd_send(hw, &desc, 1);
 997         if (ret)
 998                 return ret;
 999
1000         trans_gap = pause_param->pause_trans_gap;
1001         trans_time = rte_le_to_cpu_16(pause_param->pause_trans_time);
1002
1003         return hns3_pause_param_cfg(hw, mac_addr, trans_gap, trans_time);
1004 }
1005
1006 static int
1007 hns3_pause_param_setup_hw(struct hns3_hw *hw, uint16_t pause_time)
1008 {
1009 #define PAUSE_TIME_DIV_BY       2
1010 #define PAUSE_TIME_MIN_VALUE    0x4
1011
1012         struct hns3_mac *mac = &hw->mac;
1013         uint8_t pause_trans_gap;
1014
1015         /*
1016          * Pause transmit gap must be less than "pause_time / 2", otherwise
1017          * the behavior of MAC is undefined.
1018          */
1019         if (pause_time > PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1020                 pause_trans_gap = HNS3_DEFAULT_PAUSE_TRANS_GAP;
1021         else if (pause_time >= PAUSE_TIME_MIN_VALUE &&
1022                  pause_time <= PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1023                 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1024         else {
1025                 hns3_warn(hw, "pause_time(%d) is adjusted to 4", pause_time);
1026                 pause_time = PAUSE_TIME_MIN_VALUE;
1027                 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1028         }
1029
1030         return hns3_pause_param_cfg(hw, mac->mac_addr,
1031                                     pause_trans_gap, pause_time);
1032 }
1033
1034 static int
1035 hns3_mac_pause_en_cfg(struct hns3_hw *hw, bool tx, bool rx)
1036 {
1037         struct hns3_cmd_desc desc;
1038
1039         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PAUSE_EN, false);
1040
1041         desc.data[0] = rte_cpu_to_le_32((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1042                 (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1043
1044         return hns3_cmd_send(hw, &desc, 1);
1045 }
1046
1047 static int
1048 hns3_pfc_pause_en_cfg(struct hns3_hw *hw, uint8_t pfc_bitmap, bool tx, bool rx)
1049 {
1050         struct hns3_cmd_desc desc;
1051         struct hns3_pfc_en_cmd *pfc = (struct hns3_pfc_en_cmd *)desc.data;
1052
1053         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PFC_PAUSE_EN, false);
1054
1055         pfc->tx_rx_en_bitmap = (uint8_t)((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1056                                         (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1057
1058         pfc->pri_en_bitmap = pfc_bitmap;
1059
1060         return hns3_cmd_send(hw, &desc, 1);
1061 }
1062
1063 static int
1064 hns3_qs_bp_cfg(struct hns3_hw *hw, uint8_t tc, uint8_t grp_id, uint32_t bit_map)
1065 {
1066         struct hns3_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
1067         struct hns3_cmd_desc desc;
1068
1069         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_BP_TO_QSET_MAPPING, false);
1070
1071         bp_to_qs_map_cmd = (struct hns3_bp_to_qs_map_cmd *)desc.data;
1072
1073         bp_to_qs_map_cmd->tc_id = tc;
1074         bp_to_qs_map_cmd->qs_group_id = grp_id;
1075         bp_to_qs_map_cmd->qs_bit_map = rte_cpu_to_le_32(bit_map);
1076
1077         return hns3_cmd_send(hw, &desc, 1);
1078 }
1079
1080 static void
1081 hns3_get_rx_tx_en_status(struct hns3_hw *hw, bool *tx_en, bool *rx_en)
1082 {
1083         switch (hw->current_mode) {
1084         case HNS3_FC_NONE:
1085                 *tx_en = false;
1086                 *rx_en = false;
1087                 break;
1088         case HNS3_FC_RX_PAUSE:
1089                 *tx_en = false;
1090                 *rx_en = true;
1091                 break;
1092         case HNS3_FC_TX_PAUSE:
1093                 *tx_en = true;
1094                 *rx_en = false;
1095                 break;
1096         case HNS3_FC_FULL:
1097                 *tx_en = true;
1098                 *rx_en = true;
1099                 break;
1100         default:
1101                 *tx_en = false;
1102                 *rx_en = false;
1103                 break;
1104         }
1105 }
1106
1107 static int
1108 hns3_mac_pause_setup_hw(struct hns3_hw *hw)
1109 {
1110         bool tx_en, rx_en;
1111
1112         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)
1113                 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1114         else {
1115                 tx_en = false;
1116                 rx_en = false;
1117         }
1118
1119         return hns3_mac_pause_en_cfg(hw, tx_en, rx_en);
1120 }
1121
1122 static int
1123 hns3_pfc_setup_hw(struct hns3_hw *hw)
1124 {
1125         bool tx_en, rx_en;
1126
1127         if (hw->current_fc_status == HNS3_FC_STATUS_PFC)
1128                 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1129         else {
1130                 tx_en = false;
1131                 rx_en = false;
1132         }
1133
1134         return hns3_pfc_pause_en_cfg(hw, hw->dcb_info.pfc_en, tx_en, rx_en);
1135 }
1136
1137 /*
1138  * Each Tc has a 1024 queue sets to backpress, it divides to
1139  * 32 group, each group contains 32 queue sets, which can be
1140  * represented by uint32_t bitmap.
1141  */
1142 static int
1143 hns3_bp_setup_hw(struct hns3_hw *hw, uint8_t tc)
1144 {
1145         uint32_t qs_bitmap;
1146         int ret;
1147         int i;
1148
1149         for (i = 0; i < HNS3_BP_GRP_NUM; i++) {
1150                 uint8_t grp, sub_grp;
1151                 qs_bitmap = 0;
1152
1153                 grp = hns3_get_field(tc, HNS3_BP_GRP_ID_M, HNS3_BP_GRP_ID_S);
1154                 sub_grp = hns3_get_field(tc, HNS3_BP_SUB_GRP_ID_M,
1155                                          HNS3_BP_SUB_GRP_ID_S);
1156                 if (i == grp)
1157                         qs_bitmap |= (1 << sub_grp);
1158
1159                 ret = hns3_qs_bp_cfg(hw, tc, i, qs_bitmap);
1160                 if (ret)
1161                         return ret;
1162         }
1163
1164         return 0;
1165 }
1166
1167 static int
1168 hns3_dcb_bp_setup(struct hns3_hw *hw)
1169 {
1170         int ret, i;
1171
1172         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1173                 ret = hns3_bp_setup_hw(hw, i);
1174                 if (ret)
1175                         return ret;
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int
1182 hns3_dcb_pause_setup_hw(struct hns3_hw *hw)
1183 {
1184         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1185         struct hns3_pf *pf = &hns->pf;
1186         int ret;
1187
1188         ret = hns3_pause_param_setup_hw(hw, pf->pause_time);
1189         if (ret) {
1190                 hns3_err(hw, "Fail to set pause parameter. ret = %d", ret);
1191                 return ret;
1192         }
1193
1194         ret = hns3_mac_pause_setup_hw(hw);
1195         if (ret) {
1196                 hns3_err(hw, "Fail to setup MAC pause. ret = %d", ret);
1197                 return ret;
1198         }
1199
1200         /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1201         if (!hns3_dev_dcb_supported(hw))
1202                 return 0;
1203
1204         ret = hns3_pfc_setup_hw(hw);
1205         if (ret) {
1206                 hns3_err(hw, "config pfc failed! ret = %d", ret);
1207                 return ret;
1208         }
1209
1210         return hns3_dcb_bp_setup(hw);
1211 }
1212
1213 static uint8_t
1214 hns3_dcb_undrop_tc_map(struct hns3_hw *hw, uint8_t pfc_en)
1215 {
1216         uint8_t pfc_map = 0;
1217         uint8_t *prio_tc;
1218         uint8_t i, j;
1219
1220         prio_tc = hw->dcb_info.prio_tc;
1221         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1222                 for (j = 0; j < HNS3_MAX_USER_PRIO; j++) {
1223                         if (prio_tc[j] == i && pfc_en & BIT(j)) {
1224                                 pfc_map |= BIT(i);
1225                                 break;
1226                         }
1227                 }
1228         }
1229
1230         return pfc_map;
1231 }
1232
1233 static void
1234 hns3_dcb_cfg_validate(struct hns3_adapter *hns, uint8_t *tc, bool *changed)
1235 {
1236         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1237         struct hns3_hw *hw = &hns->hw;
1238         uint8_t max_tc = 0;
1239         uint8_t pfc_en;
1240         int i;
1241
1242         dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1243         for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1244                 if (dcb_rx_conf->dcb_tc[i] != hw->dcb_info.prio_tc[i])
1245                         *changed = true;
1246
1247                 if (dcb_rx_conf->dcb_tc[i] > max_tc)
1248                         max_tc = dcb_rx_conf->dcb_tc[i];
1249         }
1250         *tc = max_tc + 1;
1251         if (*tc != hw->dcb_info.num_tc)
1252                 *changed = true;
1253
1254         /*
1255          * We ensure that dcb information can be reconfigured
1256          * after the hns3_priority_flow_ctrl_set function called.
1257          */
1258         if (hw->current_mode != HNS3_FC_FULL)
1259                 *changed = true;
1260         pfc_en = RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1261         if (hw->dcb_info.pfc_en != pfc_en)
1262                 *changed = true;
1263 }
1264
1265 static void
1266 hns3_dcb_info_cfg(struct hns3_adapter *hns)
1267 {
1268         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1269         struct hns3_pf *pf = &hns->pf;
1270         struct hns3_hw *hw = &hns->hw;
1271         uint8_t tc_bw, bw_rest;
1272         uint8_t i, j;
1273
1274         dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1275         pf->local_max_tc = (uint8_t)dcb_rx_conf->nb_tcs;
1276         pf->pfc_max = (uint8_t)dcb_rx_conf->nb_tcs;
1277
1278         /* Config pg0 */
1279         memset(hw->dcb_info.pg_info, 0,
1280                sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
1281         hw->dcb_info.pg_dwrr[0] = BW_MAX_PERCENT;
1282         hw->dcb_info.pg_info[0].pg_id = 0;
1283         hw->dcb_info.pg_info[0].pg_sch_mode = HNS3_SCH_MODE_DWRR;
1284         hw->dcb_info.pg_info[0].bw_limit = HNS3_ETHER_MAX_RATE;
1285         hw->dcb_info.pg_info[0].tc_bit_map = hw->hw_tc_map;
1286
1287         /* Each tc has same bw for valid tc by default */
1288         tc_bw = BW_MAX_PERCENT / hw->dcb_info.num_tc;
1289         for (i = 0; i < hw->dcb_info.num_tc; i++)
1290                 hw->dcb_info.pg_info[0].tc_dwrr[i] = tc_bw;
1291         /* To ensure the sum of tc_dwrr is equal to 100 */
1292         bw_rest = BW_MAX_PERCENT % hw->dcb_info.num_tc;
1293         for (j = 0; j < bw_rest; j++)
1294                 hw->dcb_info.pg_info[0].tc_dwrr[j]++;
1295         for (; i < dcb_rx_conf->nb_tcs; i++)
1296                 hw->dcb_info.pg_info[0].tc_dwrr[i] = 0;
1297
1298         /* All tcs map to pg0 */
1299         memset(hw->dcb_info.tc_info, 0,
1300                sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
1301         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1302                 hw->dcb_info.tc_info[i].tc_id = i;
1303                 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
1304                 hw->dcb_info.tc_info[i].pgid = 0;
1305                 hw->dcb_info.tc_info[i].bw_limit =
1306                                         hw->dcb_info.pg_info[0].bw_limit;
1307         }
1308
1309         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
1310                 hw->dcb_info.prio_tc[i] = dcb_rx_conf->dcb_tc[i];
1311
1312         hns3_dcb_update_tc_queue_mapping(hw, hw->data->nb_rx_queues);
1313 }
1314
1315 static void
1316 hns3_dcb_info_update(struct hns3_adapter *hns, uint8_t num_tc)
1317 {
1318         struct hns3_pf *pf = &hns->pf;
1319         struct hns3_hw *hw = &hns->hw;
1320         uint8_t bit_map = 0;
1321         uint8_t i;
1322
1323         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1324             hw->dcb_info.num_pg != 1)
1325                 return;
1326
1327         /* Currently not support uncontinuous tc */
1328         hw->dcb_info.num_tc = num_tc;
1329         for (i = 0; i < hw->dcb_info.num_tc; i++)
1330                 bit_map |= BIT(i);
1331
1332         if (!bit_map) {
1333                 bit_map = 1;
1334                 hw->dcb_info.num_tc = 1;
1335         }
1336
1337         hw->hw_tc_map = bit_map;
1338
1339         hns3_dcb_info_cfg(hns);
1340 }
1341
1342 static int
1343 hns3_dcb_hw_configure(struct hns3_adapter *hns)
1344 {
1345         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1346         struct hns3_pf *pf = &hns->pf;
1347         struct hns3_hw *hw = &hns->hw;
1348         enum hns3_fc_status fc_status = hw->current_fc_status;
1349         enum hns3_fc_mode current_mode = hw->current_mode;
1350         uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1351         int ret, status;
1352
1353         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1354             pf->tx_sch_mode != HNS3_FLAG_VNET_BASE_SCH_MODE)
1355                 return -ENOTSUP;
1356
1357         ret = hns3_dcb_schd_setup_hw(hw);
1358         if (ret) {
1359                 hns3_err(hw, "dcb schdule configure failed! ret = %d", ret);
1360                 return ret;
1361         }
1362
1363         if (hw->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
1364                 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1365                 if (dcb_rx_conf->nb_tcs == 0)
1366                         hw->dcb_info.pfc_en = 1; /* tc0 only */
1367                 else
1368                         hw->dcb_info.pfc_en =
1369                         RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1370
1371                 hw->dcb_info.hw_pfc_map =
1372                                 hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1373
1374                 ret = hns3_buffer_alloc(hw);
1375                 if (ret)
1376                         return ret;
1377
1378                 hw->current_fc_status = HNS3_FC_STATUS_PFC;
1379                 hw->current_mode = HNS3_FC_FULL;
1380                 ret = hns3_dcb_pause_setup_hw(hw);
1381                 if (ret) {
1382                         hns3_err(hw, "setup pfc failed! ret = %d", ret);
1383                         goto pfc_setup_fail;
1384                 }
1385         } else {
1386                 /*
1387                  * Although dcb_capability_en is lack of ETH_DCB_PFC_SUPPORT
1388                  * flag, the DCB information is configured, such as tc numbers.
1389                  * Therefore, refreshing the allocation of packet buffer is
1390                  * necessary.
1391                  */
1392                 ret = hns3_buffer_alloc(hw);
1393                 if (ret)
1394                         return ret;
1395         }
1396
1397         return 0;
1398
1399 pfc_setup_fail:
1400         hw->current_mode = current_mode;
1401         hw->current_fc_status = fc_status;
1402         hw->dcb_info.hw_pfc_map = hw_pfc_map;
1403         status = hns3_buffer_alloc(hw);
1404         if (status)
1405                 hns3_err(hw, "recover packet buffer fail! status = %d", status);
1406
1407         return ret;
1408 }
1409
1410 /*
1411  * hns3_dcb_configure - setup dcb related config
1412  * @hns: pointer to hns3 adapter
1413  * Returns 0 on success, negative value on failure.
1414  */
1415 int
1416 hns3_dcb_configure(struct hns3_adapter *hns)
1417 {
1418         struct hns3_hw *hw = &hns->hw;
1419         bool map_changed = false;
1420         uint8_t num_tc = 0;
1421         int ret;
1422
1423         hns3_dcb_cfg_validate(hns, &num_tc, &map_changed);
1424         if (map_changed || rte_atomic16_read(&hw->reset.resetting)) {
1425                 hns3_dcb_info_update(hns, num_tc);
1426                 ret = hns3_dcb_hw_configure(hns);
1427                 if (ret) {
1428                         hns3_err(hw, "dcb sw configure fails: %d", ret);
1429                         return ret;
1430                 }
1431         }
1432
1433         return 0;
1434 }
1435
1436 int
1437 hns3_dcb_init_hw(struct hns3_hw *hw)
1438 {
1439         int ret;
1440
1441         ret = hns3_dcb_schd_setup_hw(hw);
1442         if (ret) {
1443                 hns3_err(hw, "dcb schedule setup failed: %d", ret);
1444                 return ret;
1445         }
1446
1447         ret = hns3_dcb_pause_setup_hw(hw);
1448         if (ret)
1449                 hns3_err(hw, "PAUSE setup failed: %d", ret);
1450
1451         return ret;
1452 }
1453
1454 int
1455 hns3_dcb_init(struct hns3_hw *hw)
1456 {
1457         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1458         struct hns3_pf *pf = &hns->pf;
1459         int ret;
1460
1461         PMD_INIT_FUNC_TRACE();
1462
1463         /*
1464          * According to the 'adapter_state' identifier, the following branch
1465          * is only executed to initialize default configurations of dcb during
1466          * the initializing driver process. Due to driver saving dcb-related
1467          * information before reset triggered, the reinit dev stage of the
1468          * reset process can not access to the branch, or those information
1469          * will be changed.
1470          */
1471         if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
1472                 hw->requested_mode = HNS3_FC_NONE;
1473                 hw->current_mode = hw->requested_mode;
1474                 pf->pause_time = HNS3_DEFAULT_PAUSE_TRANS_TIME;
1475                 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1476
1477                 ret = hns3_dcb_info_init(hw);
1478                 if (ret) {
1479                         hns3_err(hw, "dcb info init failed: %d", ret);
1480                         return ret;
1481                 }
1482                 hns3_dcb_update_tc_queue_mapping(hw, hw->tqps_num);
1483         }
1484
1485         /*
1486          * DCB hardware will be configured by following the function during
1487          * the initializing driver process and the reset process. However,
1488          * driver will restore directly configurations of dcb hardware based
1489          * on dcb-related information soft maintained when driver
1490          * initialization has finished and reset is coming.
1491          */
1492         ret = hns3_dcb_init_hw(hw);
1493         if (ret) {
1494                 hns3_err(hw, "dcb init hardware failed: %d", ret);
1495                 return ret;
1496         }
1497
1498         return 0;
1499 }
1500
1501 static int
1502 hns3_update_queue_map_configure(struct hns3_adapter *hns)
1503 {
1504         struct hns3_hw *hw = &hns->hw;
1505         uint16_t queue_num = hw->data->nb_rx_queues;
1506         int ret;
1507
1508         hns3_dcb_update_tc_queue_mapping(hw, queue_num);
1509         ret = hns3_q_to_qs_map(hw);
1510         if (ret) {
1511                 hns3_err(hw, "failed to map nq to qs! ret = %d", ret);
1512                 return ret;
1513         }
1514
1515         return 0;
1516 }
1517
1518 int
1519 hns3_dcb_cfg_update(struct hns3_adapter *hns)
1520 {
1521         struct hns3_hw *hw = &hns->hw;
1522         enum rte_eth_rx_mq_mode mq_mode = hw->data->dev_conf.rxmode.mq_mode;
1523         int ret;
1524
1525         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
1526                 ret = hns3_dcb_configure(hns);
1527                 if (ret) {
1528                         hns3_err(hw, "Failed to config dcb: %d", ret);
1529                         return ret;
1530                 }
1531         } else {
1532                 /*
1533                  * Update queue map without PFC configuration,
1534                  * due to queues reconfigured by user.
1535                  */
1536                 ret = hns3_update_queue_map_configure(hns);
1537                 if (ret)
1538                         hns3_err(hw,
1539                                  "Failed to update queue mapping configure: %d",
1540                                  ret);
1541         }
1542
1543         return ret;
1544 }
1545
1546 /*
1547  * hns3_dcb_pfc_enable - Enable priority flow control
1548  * @dev: pointer to ethernet device
1549  *
1550  * Configures the pfc settings for one porority.
1551  */
1552 int
1553 hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
1554 {
1555         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1557         enum hns3_fc_status fc_status = hw->current_fc_status;
1558         enum hns3_fc_mode current_mode = hw->current_mode;
1559         uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1560         uint8_t pfc_en = hw->dcb_info.pfc_en;
1561         uint8_t priority = pfc_conf->priority;
1562         uint16_t pause_time = pf->pause_time;
1563         int ret, status;
1564
1565         pf->pause_time = pfc_conf->fc.pause_time;
1566         hw->current_mode = hw->requested_mode;
1567         hw->current_fc_status = HNS3_FC_STATUS_PFC;
1568         hw->dcb_info.pfc_en |= BIT(priority);
1569         hw->dcb_info.hw_pfc_map =
1570                         hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1571         ret = hns3_buffer_alloc(hw);
1572         if (ret)
1573                 goto pfc_setup_fail;
1574
1575         /*
1576          * The flow control mode of all UPs will be changed based on
1577          * current_mode coming from user.
1578          */
1579         ret = hns3_dcb_pause_setup_hw(hw);
1580         if (ret) {
1581                 hns3_err(hw, "enable pfc failed! ret = %d", ret);
1582                 goto pfc_setup_fail;
1583         }
1584
1585         return 0;
1586
1587 pfc_setup_fail:
1588         hw->current_mode = current_mode;
1589         hw->current_fc_status = fc_status;
1590         pf->pause_time = pause_time;
1591         hw->dcb_info.pfc_en = pfc_en;
1592         hw->dcb_info.hw_pfc_map = hw_pfc_map;
1593         status = hns3_buffer_alloc(hw);
1594         if (status)
1595                 hns3_err(hw, "recover packet buffer fail: %d", status);
1596
1597         return ret;
1598 }
1599
1600 /*
1601  * hns3_fc_enable - Enable MAC pause
1602  * @dev: pointer to ethernet device
1603  *
1604  * Configures the MAC pause settings.
1605  */
1606 int
1607 hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1608 {
1609         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1611         enum hns3_fc_status fc_status = hw->current_fc_status;
1612         enum hns3_fc_mode current_mode = hw->current_mode;
1613         uint16_t pause_time = pf->pause_time;
1614         int ret;
1615
1616         pf->pause_time = fc_conf->pause_time;
1617         hw->current_mode = hw->requested_mode;
1618
1619         /*
1620          * In fact, current_fc_status is HNS3_FC_STATUS_NONE when mode
1621          * of flow control is configured to be HNS3_FC_NONE.
1622          */
1623         if (hw->current_mode == HNS3_FC_NONE)
1624                 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1625         else
1626                 hw->current_fc_status = HNS3_FC_STATUS_MAC_PAUSE;
1627
1628         ret = hns3_dcb_pause_setup_hw(hw);
1629         if (ret) {
1630                 hns3_err(hw, "enable MAC Pause failed! ret = %d", ret);
1631                 goto setup_fc_fail;
1632         }
1633
1634         return 0;
1635
1636 setup_fc_fail:
1637         hw->current_mode = current_mode;
1638         hw->current_fc_status = fc_status;
1639         pf->pause_time = pause_time;
1640
1641         return ret;
1642 }