drivers/net/hns3/hns3_dcb.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <rte_io.h>
  11 #include <rte_common.h>
  12 #include <rte_ethdev.h>
  13
  14 #include "hns3_logs.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_ethdev.h"
  17 #include "hns3_dcb.h"
  18
  19 #define HNS3_SHAPER_BS_U_DEF    5
  20 #define HNS3_SHAPER_BS_S_DEF    20
  21 #define BW_MAX_PERCENT          100
  22 #define HNS3_ETHER_MAX_RATE     100000
  23
  24 /*
  25  * hns3_shaper_para_calc: calculate ir parameter for the shaper
  26  * @ir: Rate to be config, its unit is Mbps
  27  * @shaper_level: the shaper level. eg: port, pg, priority, queueset
  28  * @shaper_para: shaper parameter of IR shaper
  29  *
  30  * the formula:
  31  *
  32  *              IR_b * (2 ^ IR_u) * 8
  33  * IR(Mbps) = -------------------------  *  CLOCK(1000Mbps)
  34  *              Tick * (2 ^ IR_s)
  35  *
  36  * @return: 0: calculate sucessful, negative: fail
  37  */
  38 static int
  39 hns3_shaper_para_calc(struct hns3_hw *hw, uint32_t ir, uint8_t shaper_level,
  40                       struct hns3_shaper_parameter *shaper_para)
  41 {
  42 #define SHAPER_DEFAULT_IR_B     126
  43 #define DIVISOR_CLK             (1000 * 8)
  44 #define DIVISOR_IR_B_126        (126 * DIVISOR_CLK)
  45
  46         const uint16_t tick_array[HNS3_SHAPER_LVL_CNT] = {
  47                 6 * 256,    /* Prioriy level */
  48                 6 * 32,     /* Prioriy group level */
  49                 6 * 8,      /* Port level */
  50                 6 * 256     /* Qset level */
  51         };
  52         uint8_t ir_u_calc = 0;
  53         uint8_t ir_s_calc = 0;
  54         uint32_t denominator;
  55         uint32_t ir_calc;
  56         uint32_t tick;
  57
  58         /* Calc tick */
  59         if (shaper_level >= HNS3_SHAPER_LVL_CNT) {
  60                 hns3_err(hw,
  61                          "shaper_level(%d) is greater than HNS3_SHAPER_LVL_CNT(%d)",
  62                          shaper_level, HNS3_SHAPER_LVL_CNT);
  63                 return -EINVAL;
  64         }
  65
  66         if (ir > HNS3_ETHER_MAX_RATE) {
  67                 hns3_err(hw, "rate(%d) exceeds the rate driver supported "
  68                          "HNS3_ETHER_MAX_RATE(%d)", ir, HNS3_ETHER_MAX_RATE);
  69                 return -EINVAL;
  70         }
  71
  72         tick = tick_array[shaper_level];
  73
  74         /*
  75          * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
  76          * the formula is changed to:
  77          *              126 * 1 * 8
  78          * ir_calc = ---------------- * 1000
  79          *              tick * 1
  80          */
  81         ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
  82
  83         if (ir_calc == ir) {
  84                 shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
  85         } else if (ir_calc > ir) {
  86                 /* Increasing the denominator to select ir_s value */
  87                 do {
  88                         ir_s_calc++;
  89                         ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
  90                 } while (ir_calc > ir);
  91
  92                 if (ir_calc == ir)
  93                         shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
  94                 else
  95                         shaper_para->ir_b = (ir * tick * (1 << ir_s_calc) +
  96                                  (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
  97         } else {
  98                 /*
  99                  * Increasing the numerator to select ir_u value. ir_u_calc will
 100                  * get maximum value when ir_calc is minimum and ir is maximum.
 101                  * ir_calc gets minimum value when tick is the maximum value.
 102                  * At the same time, value of ir_u_calc can only be increased up
 103                  * to eight after the while loop if the value of ir is equal
 104                  * to HNS3_ETHER_MAX_RATE.
 105                  */
 106                 uint32_t numerator;
 107                 do {
 108                         ir_u_calc++;
 109                         numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
 110                         ir_calc = (numerator + (tick >> 1)) / tick;
 111                 } while (ir_calc < ir);
 112
 113                 if (ir_calc == ir) {
 114                         shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
 115                 } else {
 116                         --ir_u_calc;
 117
 118                         /*
 119                          * The maximum value of ir_u_calc in this branch is
 120                          * seven in all cases. Thus, value of denominator can
 121                          * not be zero here.
 122                          */
 123                         denominator = DIVISOR_CLK * (1 << ir_u_calc);
 124                         shaper_para->ir_b =
 125                                 (ir * tick + (denominator >> 1)) / denominator;
 126                 }
 127         }
 128
 129         shaper_para->ir_u = ir_u_calc;
 130         shaper_para->ir_s = ir_s_calc;
 131
 132         return 0;
 133 }
 134
 135 static int
 136 hns3_fill_pri_array(struct hns3_hw *hw, uint8_t *pri, uint8_t pri_id)
 137 {
 138 #define HNS3_HALF_BYTE_BIT_OFFSET 4
 139         uint8_t tc = hw->dcb_info.prio_tc[pri_id];
 140
 141         if (tc >= hw->dcb_info.num_tc)
 142                 return -EINVAL;
 143
 144         /*
 145          * The register for priority has four bytes, the first bytes includes
 146          *  priority0 and priority1, the higher 4bit stands for priority1
 147          *  while the lower 4bit stands for priority0, as below:
 148          * first byte:  | pri_1 | pri_0 |
 149          * second byte: | pri_3 | pri_2 |
 150          * third byte:  | pri_5 | pri_4 |
 151          * fourth byte: | pri_7 | pri_6 |
 152          */
 153         pri[pri_id >> 1] |= tc << ((pri_id & 1) * HNS3_HALF_BYTE_BIT_OFFSET);
 154
 155         return 0;
 156 }
 157
 158 static int
 159 hns3_up_to_tc_map(struct hns3_hw *hw)
 160 {
 161         struct hns3_cmd_desc desc;
 162         uint8_t *pri = (uint8_t *)desc.data;
 163         uint8_t pri_id;
 164         int ret;
 165
 166         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PRI_TO_TC_MAPPING, false);
 167
 168         for (pri_id = 0; pri_id < HNS3_MAX_USER_PRIO; pri_id++) {
 169                 ret = hns3_fill_pri_array(hw, pri, pri_id);
 170                 if (ret)
 171                         return ret;
 172         }
 173
 174         return hns3_cmd_send(hw, &desc, 1);
 175 }
 176
 177 static int
 178 hns3_pg_to_pri_map_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t pri_bit_map)
 179 {
 180         struct hns3_pg_to_pri_link_cmd *map;
 181         struct hns3_cmd_desc desc;
 182
 183         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_TO_PRI_LINK, false);
 184
 185         map = (struct hns3_pg_to_pri_link_cmd *)desc.data;
 186
 187         map->pg_id = pg_id;
 188         map->pri_bit_map = pri_bit_map;
 189
 190         return hns3_cmd_send(hw, &desc, 1);
 191 }
 192
 193 static int
 194 hns3_pg_to_pri_map(struct hns3_hw *hw)
 195 {
 196         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 197         struct hns3_pf *pf = &hns->pf;
 198         struct hns3_pg_info *pg_info;
 199         int ret, i;
 200
 201         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 202                 return -EINVAL;
 203
 204         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 205                 /* Cfg pg to priority mapping */
 206                 pg_info = &hw->dcb_info.pg_info[i];
 207                 ret = hns3_pg_to_pri_map_cfg(hw, i, pg_info->tc_bit_map);
 208                 if (ret)
 209                         return ret;
 210         }
 211
 212         return 0;
 213 }
 214
 215 static int
 216 hns3_qs_to_pri_map_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t pri)
 217 {
 218         struct hns3_qs_to_pri_link_cmd *map;
 219         struct hns3_cmd_desc desc;
 220
 221         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_TO_PRI_LINK, false);
 222
 223         map = (struct hns3_qs_to_pri_link_cmd *)desc.data;
 224
 225         map->qs_id = rte_cpu_to_le_16(qs_id);
 226         map->priority = pri;
 227         map->link_vld = HNS3_DCB_QS_PRI_LINK_VLD_MSK;
 228
 229         return hns3_cmd_send(hw, &desc, 1);
 230 }
 231
 232 static int
 233 hns3_dcb_qs_weight_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t dwrr)
 234 {
 235         struct hns3_qs_weight_cmd *weight;
 236         struct hns3_cmd_desc desc;
 237
 238         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_WEIGHT, false);
 239
 240         weight = (struct hns3_qs_weight_cmd *)desc.data;
 241
 242         weight->qs_id = rte_cpu_to_le_16(qs_id);
 243         weight->dwrr = dwrr;
 244
 245         return hns3_cmd_send(hw, &desc, 1);
 246 }
 247
 248 static int
 249 hns3_dcb_ets_tc_dwrr_cfg(struct hns3_hw *hw)
 250 {
 251 #define DEFAULT_TC_WEIGHT       1
 252 #define DEFAULT_TC_OFFSET       14
 253         struct hns3_ets_tc_weight_cmd *ets_weight;
 254         struct hns3_cmd_desc desc;
 255         uint8_t i;
 256
 257         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_ETS_TC_WEIGHT, false);
 258         ets_weight = (struct hns3_ets_tc_weight_cmd *)desc.data;
 259
 260         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 261                 struct hns3_pg_info *pg_info;
 262
 263                 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
 264
 265                 if (!(hw->hw_tc_map & BIT(i)))
 266                         continue;
 267
 268                 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
 269                 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
 270         }
 271
 272         ets_weight->weight_offset = DEFAULT_TC_OFFSET;
 273
 274         return hns3_cmd_send(hw, &desc, 1);
 275 }
 276
 277 static int
 278 hns3_dcb_pri_weight_cfg(struct hns3_hw *hw, uint8_t pri_id, uint8_t dwrr)
 279 {
 280         struct hns3_priority_weight_cmd *weight;
 281         struct hns3_cmd_desc desc;
 282
 283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_WEIGHT, false);
 284
 285         weight = (struct hns3_priority_weight_cmd *)desc.data;
 286
 287         weight->pri_id = pri_id;
 288         weight->dwrr = dwrr;
 289
 290         return hns3_cmd_send(hw, &desc, 1);
 291 }
 292
 293 static int
 294 hns3_dcb_pg_weight_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t dwrr)
 295 {
 296         struct hns3_pg_weight_cmd *weight;
 297         struct hns3_cmd_desc desc;
 298
 299         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_WEIGHT, false);
 300
 301         weight = (struct hns3_pg_weight_cmd *)desc.data;
 302
 303         weight->pg_id = pg_id;
 304         weight->dwrr = dwrr;
 305
 306         return hns3_cmd_send(hw, &desc, 1);
 307 }
 308 static int
 309 hns3_dcb_pg_schd_mode_cfg(struct hns3_hw *hw, uint8_t pg_id)
 310 {
 311         struct hns3_cmd_desc desc;
 312
 313         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_SCH_MODE_CFG, false);
 314
 315         if (hw->dcb_info.pg_info[pg_id].pg_sch_mode == HNS3_SCH_MODE_DWRR)
 316                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 317         else
 318                 desc.data[1] = 0;
 319
 320         desc.data[0] = rte_cpu_to_le_32(pg_id);
 321
 322         return hns3_cmd_send(hw, &desc, 1);
 323 }
 324
 325 static uint32_t
 326 hns3_dcb_get_shapping_para(uint8_t ir_b, uint8_t ir_u, uint8_t ir_s,
 327                            uint8_t bs_b, uint8_t bs_s)
 328 {
 329         uint32_t shapping_para = 0;
 330
 331         hns3_dcb_set_field(shapping_para, IR_B, ir_b);
 332         hns3_dcb_set_field(shapping_para, IR_U, ir_u);
 333         hns3_dcb_set_field(shapping_para, IR_S, ir_s);
 334         hns3_dcb_set_field(shapping_para, BS_B, bs_b);
 335         hns3_dcb_set_field(shapping_para, BS_S, bs_s);
 336
 337         return shapping_para;
 338 }
 339
 340 static int
 341 hns3_dcb_port_shaper_cfg(struct hns3_hw *hw)
 342 {
 343         struct hns3_port_shapping_cmd *shap_cfg_cmd;
 344         struct hns3_shaper_parameter shaper_parameter;
 345         uint32_t shapping_para;
 346         uint32_t ir_u, ir_b, ir_s;
 347         struct hns3_cmd_desc desc;
 348         int ret;
 349
 350         ret = hns3_shaper_para_calc(hw, hw->mac.link_speed,
 351                                     HNS3_SHAPER_LVL_PORT, &shaper_parameter);
 352         if (ret) {
 353                 hns3_err(hw, "calculate shaper parameter failed: %d", ret);
 354                 return ret;
 355         }
 356
 357         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PORT_SHAPPING, false);
 358         shap_cfg_cmd = (struct hns3_port_shapping_cmd *)desc.data;
 359
 360         ir_b = shaper_parameter.ir_b;
 361         ir_u = shaper_parameter.ir_u;
 362         ir_s = shaper_parameter.ir_s;
 363         shapping_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 364                                                    HNS3_SHAPER_BS_U_DEF,
 365                                                    HNS3_SHAPER_BS_S_DEF);
 366
 367         shap_cfg_cmd->port_shapping_para = rte_cpu_to_le_32(shapping_para);
 368
 369         return hns3_cmd_send(hw, &desc, 1);
 370 }
 371
 372 static int
 373 hns3_dcb_pg_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
 374                          uint8_t pg_id, uint32_t shapping_para)
 375 {
 376         struct hns3_pg_shapping_cmd *shap_cfg_cmd;
 377         enum hns3_opcode_type opcode;
 378         struct hns3_cmd_desc desc;
 379
 380         opcode = bucket ? HNS3_OPC_TM_PG_P_SHAPPING :
 381                  HNS3_OPC_TM_PG_C_SHAPPING;
 382         hns3_cmd_setup_basic_desc(&desc, opcode, false);
 383
 384         shap_cfg_cmd = (struct hns3_pg_shapping_cmd *)desc.data;
 385
 386         shap_cfg_cmd->pg_id = pg_id;
 387
 388         shap_cfg_cmd->pg_shapping_para = rte_cpu_to_le_32(shapping_para);
 389
 390         return hns3_cmd_send(hw, &desc, 1);
 391 }
 392
 393 static int
 394 hns3_dcb_pg_shaper_cfg(struct hns3_hw *hw)
 395 {
 396         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 397         struct hns3_shaper_parameter shaper_parameter;
 398         struct hns3_pf *pf = &hns->pf;
 399         uint32_t ir_u, ir_b, ir_s;
 400         uint32_t shaper_para;
 401         uint8_t i;
 402         int ret;
 403
 404         /* Cfg pg schd */
 405         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 406                 return -EINVAL;
 407
 408         /* Pg to pri */
 409         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 410                 /* Calc shaper para */
 411                 ret = hns3_shaper_para_calc(hw,
 412                                             hw->dcb_info.pg_info[i].bw_limit,
 413                                             HNS3_SHAPER_LVL_PG,
 414                                             &shaper_parameter);
 415                 if (ret) {
 416                         hns3_err(hw, "calculate shaper parameter failed: %d",
 417                                  ret);
 418                         return ret;
 419                 }
 420
 421                 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
 422                                                          HNS3_SHAPER_BS_U_DEF,
 423                                                          HNS3_SHAPER_BS_S_DEF);
 424
 425                 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
 426                                                shaper_para);
 427                 if (ret) {
 428                         hns3_err(hw,
 429                                  "config PG CIR shaper parameter failed: %d",
 430                                  ret);
 431                         return ret;
 432                 }
 433
 434                 ir_b = shaper_parameter.ir_b;
 435                 ir_u = shaper_parameter.ir_u;
 436                 ir_s = shaper_parameter.ir_s;
 437                 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 438                                                          HNS3_SHAPER_BS_U_DEF,
 439                                                          HNS3_SHAPER_BS_S_DEF);
 440
 441                 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
 442                                                shaper_para);
 443                 if (ret) {
 444                         hns3_err(hw,
 445                                  "config PG PIR shaper parameter failed: %d",
 446                                  ret);
 447                         return ret;
 448                 }
 449         }
 450
 451         return 0;
 452 }
 453
 454 static int
 455 hns3_dcb_qs_schd_mode_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t mode)
 456 {
 457         struct hns3_cmd_desc desc;
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_SCH_MODE_CFG, false);
 460
 461         if (mode == HNS3_SCH_MODE_DWRR)
 462                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 463         else
 464                 desc.data[1] = 0;
 465
 466         desc.data[0] = rte_cpu_to_le_32(qs_id);
 467
 468         return hns3_cmd_send(hw, &desc, 1);
 469 }
 470
 471 static int
 472 hns3_dcb_pri_schd_mode_cfg(struct hns3_hw *hw, uint8_t pri_id)
 473 {
 474         struct hns3_cmd_desc desc;
 475
 476         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_SCH_MODE_CFG, false);
 477
 478         if (hw->dcb_info.tc_info[pri_id].tc_sch_mode == HNS3_SCH_MODE_DWRR)
 479                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 480         else
 481                 desc.data[1] = 0;
 482
 483         desc.data[0] = rte_cpu_to_le_32(pri_id);
 484
 485         return hns3_cmd_send(hw, &desc, 1);
 486 }
 487
 488 static int
 489 hns3_dcb_pri_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
 490                           uint8_t pri_id, uint32_t shapping_para)
 491 {
 492         struct hns3_pri_shapping_cmd *shap_cfg_cmd;
 493         enum hns3_opcode_type opcode;
 494         struct hns3_cmd_desc desc;
 495
 496         opcode = bucket ? HNS3_OPC_TM_PRI_P_SHAPPING :
 497                  HNS3_OPC_TM_PRI_C_SHAPPING;
 498
 499         hns3_cmd_setup_basic_desc(&desc, opcode, false);
 500
 501         shap_cfg_cmd = (struct hns3_pri_shapping_cmd *)desc.data;
 502
 503         shap_cfg_cmd->pri_id = pri_id;
 504
 505         shap_cfg_cmd->pri_shapping_para = rte_cpu_to_le_32(shapping_para);
 506
 507         return hns3_cmd_send(hw, &desc, 1);
 508 }
 509
 510 static int
 511 hns3_dcb_pri_tc_base_shaper_cfg(struct hns3_hw *hw)
 512 {
 513         struct hns3_shaper_parameter shaper_parameter;
 514         uint32_t ir_u, ir_b, ir_s;
 515         uint32_t shaper_para;
 516         int ret, i;
 517
 518         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 519                 ret = hns3_shaper_para_calc(hw,
 520                                             hw->dcb_info.tc_info[i].bw_limit,
 521                                             HNS3_SHAPER_LVL_PRI,
 522                                             &shaper_parameter);
 523                 if (ret) {
 524                         hns3_err(hw, "calculate shaper parameter failed: %d",
 525                                  ret);
 526                         return ret;
 527                 }
 528
 529                 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
 530                                                          HNS3_SHAPER_BS_U_DEF,
 531                                                          HNS3_SHAPER_BS_S_DEF);
 532
 533                 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
 534                                                 shaper_para);
 535                 if (ret) {
 536                         hns3_err(hw,
 537                                  "config priority CIR shaper parameter failed: %d",
 538                                  ret);
 539                         return ret;
 540                 }
 541
 542                 ir_b = shaper_parameter.ir_b;
 543                 ir_u = shaper_parameter.ir_u;
 544                 ir_s = shaper_parameter.ir_s;
 545                 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 546                                                          HNS3_SHAPER_BS_U_DEF,
 547                                                          HNS3_SHAPER_BS_S_DEF);
 548
 549                 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
 550                                                 shaper_para);
 551                 if (ret) {
 552                         hns3_err(hw,
 553                                  "config priority PIR shaper parameter failed: %d",
 554                                  ret);
 555                         return ret;
 556                 }
 557         }
 558
 559         return 0;
 560 }
 561
 562
 563 static int
 564 hns3_dcb_pri_shaper_cfg(struct hns3_hw *hw)
 565 {
 566         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 567         struct hns3_pf *pf = &hns->pf;
 568         int ret;
 569
 570         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 571                 return -EINVAL;
 572
 573         ret = hns3_dcb_pri_tc_base_shaper_cfg(hw);
 574         if (ret)
 575                 hns3_err(hw, "config port shaper failed: %d", ret);
 576
 577         return ret;
 578 }
 579
 580 void
 581 hns3_set_rss_size(struct hns3_hw *hw, uint16_t nb_rx_q)
 582 {
 583         uint16_t rx_qnum_per_tc;
 584
 585         rx_qnum_per_tc = nb_rx_q / hw->num_tc;
 586         rx_qnum_per_tc = RTE_MIN(hw->rss_size_max, rx_qnum_per_tc);
 587         if (hw->alloc_rss_size != rx_qnum_per_tc) {
 588                 hns3_info(hw, "rss size changes from %u to %u",
 589                           hw->alloc_rss_size, rx_qnum_per_tc);
 590                 hw->alloc_rss_size = rx_qnum_per_tc;
 591         }
 592         hw->used_rx_queues = hw->num_tc * hw->alloc_rss_size;
 593 }
 594
 595 void
 596 hns3_tc_queue_mapping_cfg(struct hns3_hw *hw, uint16_t nb_queue)
 597 {
 598         struct hns3_tc_queue_info *tc_queue;
 599         uint8_t i;
 600
 601         hw->tx_qnum_per_tc = nb_queue / hw->num_tc;
 602         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 603                 tc_queue = &hw->tc_queue[i];
 604                 if (hw->hw_tc_map & BIT(i) && i < hw->num_tc) {
 605                         tc_queue->enable = true;
 606                         tc_queue->tqp_offset = i * hw->tx_qnum_per_tc;
 607                         tc_queue->tqp_count = hw->tx_qnum_per_tc;
 608                         tc_queue->tc = i;
 609                 } else {
 610                         /* Set to default queue if TC is disable */
 611                         tc_queue->enable = false;
 612                         tc_queue->tqp_offset = 0;
 613                         tc_queue->tqp_count = 0;
 614                         tc_queue->tc = 0;
 615                 }
 616         }
 617         hw->used_tx_queues = hw->num_tc * hw->tx_qnum_per_tc;
 618 }
 619
 620 static void
 621 hns3_dcb_update_tc_queue_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
 622                                  uint16_t nb_tx_q)
 623 {
 624         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 625         struct hns3_pf *pf = &hns->pf;
 626
 627         hw->num_tc = hw->dcb_info.num_tc;
 628         hns3_set_rss_size(hw, nb_rx_q);
 629         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
 630
 631         if (!hns->is_vf)
 632                 memcpy(pf->prio_tc, hw->dcb_info.prio_tc, HNS3_MAX_USER_PRIO);
 633 }
 634
 635 int
 636 hns3_dcb_info_init(struct hns3_hw *hw)
 637 {
 638         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 639         struct hns3_pf *pf = &hns->pf;
 640         int i, k;
 641
 642         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
 643             hw->dcb_info.num_pg != 1)
 644                 return -EINVAL;
 645
 646         /* Initializing PG information */
 647         memset(hw->dcb_info.pg_info, 0,
 648                sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
 649         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 650                 hw->dcb_info.pg_dwrr[i] = i ? 0 : BW_MAX_PERCENT;
 651                 hw->dcb_info.pg_info[i].pg_id = i;
 652                 hw->dcb_info.pg_info[i].pg_sch_mode = HNS3_SCH_MODE_DWRR;
 653                 hw->dcb_info.pg_info[i].bw_limit = HNS3_ETHER_MAX_RATE;
 654
 655                 if (i != 0)
 656                         continue;
 657
 658                 hw->dcb_info.pg_info[i].tc_bit_map = hw->hw_tc_map;
 659                 for (k = 0; k < hw->dcb_info.num_tc; k++)
 660                         hw->dcb_info.pg_info[i].tc_dwrr[k] = BW_MAX_PERCENT;
 661         }
 662
 663         /* All UPs mapping to TC0 */
 664         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
 665                 hw->dcb_info.prio_tc[i] = 0;
 666
 667         /* Initializing tc information */
 668         memset(hw->dcb_info.tc_info, 0,
 669                sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
 670         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 671                 hw->dcb_info.tc_info[i].tc_id = i;
 672                 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
 673                 hw->dcb_info.tc_info[i].pgid = 0;
 674                 hw->dcb_info.tc_info[i].bw_limit =
 675                         hw->dcb_info.pg_info[0].bw_limit;
 676         }
 677
 678         return 0;
 679 }
 680
 681 static int
 682 hns3_dcb_lvl2_schd_mode_cfg(struct hns3_hw *hw)
 683 {
 684         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 685         struct hns3_pf *pf = &hns->pf;
 686         int ret, i;
 687
 688         /* Only being config on TC-Based scheduler mode */
 689         if (pf->tx_sch_mode == HNS3_FLAG_VNET_BASE_SCH_MODE)
 690                 return -EINVAL;
 691
 692         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 693                 ret = hns3_dcb_pg_schd_mode_cfg(hw, i);
 694                 if (ret)
 695                         return ret;
 696         }
 697
 698         return 0;
 699 }
 700
 701 static int
 702 hns3_dcb_lvl34_schd_mode_cfg(struct hns3_hw *hw)
 703 {
 704         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 705         struct hns3_pf *pf = &hns->pf;
 706         uint8_t i;
 707         int ret;
 708
 709         if (pf->tx_sch_mode == HNS3_FLAG_TC_BASE_SCH_MODE) {
 710                 for (i = 0; i < hw->dcb_info.num_tc; i++) {
 711                         ret = hns3_dcb_pri_schd_mode_cfg(hw, i);
 712                         if (ret)
 713                                 return ret;
 714
 715                         ret = hns3_dcb_qs_schd_mode_cfg(hw, i,
 716                                                         HNS3_SCH_MODE_DWRR);
 717                         if (ret)
 718                                 return ret;
 719                 }
 720         }
 721
 722         return 0;
 723 }
 724
 725 static int
 726 hns3_dcb_schd_mode_cfg(struct hns3_hw *hw)
 727 {
 728         int ret;
 729
 730         ret = hns3_dcb_lvl2_schd_mode_cfg(hw);
 731         if (ret) {
 732                 hns3_err(hw, "config lvl2_schd_mode failed: %d", ret);
 733                 return ret;
 734         }
 735
 736         ret = hns3_dcb_lvl34_schd_mode_cfg(hw);
 737         if (ret) {
 738                 hns3_err(hw, "config lvl34_schd_mode failed: %d", ret);
 739                 return ret;
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3_dcb_pri_tc_base_dwrr_cfg(struct hns3_hw *hw)
 747 {
 748         struct hns3_pg_info *pg_info;
 749         uint8_t dwrr;
 750         int ret, i;
 751
 752         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 753                 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
 754                 dwrr = pg_info->tc_dwrr[i];
 755
 756                 ret = hns3_dcb_pri_weight_cfg(hw, i, dwrr);
 757                 if (ret) {
 758                         hns3_err(hw, "fail to send priority weight cmd: %d", i);
 759                         return ret;
 760                 }
 761
 762                 ret = hns3_dcb_qs_weight_cfg(hw, i, BW_MAX_PERCENT);
 763                 if (ret) {
 764                         hns3_err(hw, "fail to send qs_weight cmd: %d", i);
 765                         return ret;
 766                 }
 767         }
 768
 769         return 0;
 770 }
 771
 772 static int
 773 hns3_dcb_pri_dwrr_cfg(struct hns3_hw *hw)
 774 {
 775         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 776         struct hns3_pf *pf = &hns->pf;
 777         int ret;
 778
 779         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 780                 return -EINVAL;
 781
 782         ret = hns3_dcb_pri_tc_base_dwrr_cfg(hw);
 783         if (ret)
 784                 return ret;
 785
 786         if (!hns3_dev_dcb_supported(hw))
 787                 return 0;
 788
 789         ret = hns3_dcb_ets_tc_dwrr_cfg(hw);
 790         if (ret == -EOPNOTSUPP) {
 791                 hns3_warn(hw, "fw %08x does't support ets tc weight cmd",
 792                           hw->fw_version);
 793                 ret = 0;
 794         }
 795
 796         return ret;
 797 }
 798
 799 static int
 800 hns3_dcb_pg_dwrr_cfg(struct hns3_hw *hw)
 801 {
 802         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 803         struct hns3_pf *pf = &hns->pf;
 804         int ret, i;
 805
 806         /* Cfg pg schd */
 807         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 808                 return -EINVAL;
 809
 810         /* Cfg pg to prio */
 811         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 812                 /* Cfg dwrr */
 813                 ret = hns3_dcb_pg_weight_cfg(hw, i, hw->dcb_info.pg_dwrr[i]);
 814                 if (ret)
 815                         return ret;
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int
 822 hns3_dcb_dwrr_cfg(struct hns3_hw *hw)
 823 {
 824         int ret;
 825
 826         ret = hns3_dcb_pg_dwrr_cfg(hw);
 827         if (ret) {
 828                 hns3_err(hw, "config pg_dwrr failed: %d", ret);
 829                 return ret;
 830         }
 831
 832         ret = hns3_dcb_pri_dwrr_cfg(hw);
 833         if (ret) {
 834                 hns3_err(hw, "config pri_dwrr failed: %d", ret);
 835                 return ret;
 836         }
 837
 838         return 0;
 839 }
 840
 841 static int
 842 hns3_dcb_shaper_cfg(struct hns3_hw *hw)
 843 {
 844         int ret;
 845
 846         ret = hns3_dcb_port_shaper_cfg(hw);
 847         if (ret) {
 848                 hns3_err(hw, "config port shaper failed: %d", ret);
 849                 return ret;
 850         }
 851
 852         ret = hns3_dcb_pg_shaper_cfg(hw);
 853         if (ret) {
 854                 hns3_err(hw, "config pg shaper failed: %d", ret);
 855                 return ret;
 856         }
 857
 858         return hns3_dcb_pri_shaper_cfg(hw);
 859 }
 860
 861 static int
 862 hns3_q_to_qs_map_cfg(struct hns3_hw *hw, uint16_t q_id, uint16_t qs_id)
 863 {
 864         struct hns3_nq_to_qs_link_cmd *map;
 865         struct hns3_cmd_desc desc;
 866
 867         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_NQ_TO_QS_LINK, false);
 868
 869         map = (struct hns3_nq_to_qs_link_cmd *)desc.data;
 870
 871         map->nq_id = rte_cpu_to_le_16(q_id);
 872         map->qset_id = rte_cpu_to_le_16(qs_id | HNS3_DCB_Q_QS_LINK_VLD_MSK);
 873
 874         return hns3_cmd_send(hw, &desc, 1);
 875 }
 876
 877 static int
 878 hns3_q_to_qs_map(struct hns3_hw *hw)
 879 {
 880         struct hns3_tc_queue_info *tc_queue;
 881         uint16_t q_id;
 882         uint32_t i, j;
 883         int ret;
 884
 885         for (i = 0; i < hw->num_tc; i++) {
 886                 tc_queue = &hw->tc_queue[i];
 887                 for (j = 0; j < tc_queue->tqp_count; j++) {
 888                         q_id = tc_queue->tqp_offset + j;
 889                         ret = hns3_q_to_qs_map_cfg(hw, q_id, i);
 890                         if (ret)
 891                                 return ret;
 892                 }
 893         }
 894
 895         return 0;
 896 }
 897
 898 static int
 899 hns3_pri_q_qs_cfg(struct hns3_hw *hw)
 900 {
 901         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 902         struct hns3_pf *pf = &hns->pf;
 903         uint32_t i;
 904         int ret;
 905
 906         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 907                 return -EINVAL;
 908
 909         /* Cfg qs -> pri mapping */
 910         for (i = 0; i < hw->num_tc; i++) {
 911                 ret = hns3_qs_to_pri_map_cfg(hw, i, i);
 912                 if (ret) {
 913                         hns3_err(hw, "qs_to_pri mapping fail: %d", ret);
 914                         return ret;
 915                 }
 916         }
 917
 918         /* Cfg q -> qs mapping */
 919         ret = hns3_q_to_qs_map(hw);
 920         if (ret) {
 921                 hns3_err(hw, "nq_to_qs mapping fail: %d", ret);
 922                 return ret;
 923         }
 924
 925         return 0;
 926 }
 927
 928 static int
 929 hns3_dcb_map_cfg(struct hns3_hw *hw)
 930 {
 931         int ret;
 932
 933         ret = hns3_up_to_tc_map(hw);
 934         if (ret) {
 935                 hns3_err(hw, "up_to_tc mapping fail: %d", ret);
 936                 return ret;
 937         }
 938
 939         ret = hns3_pg_to_pri_map(hw);
 940         if (ret) {
 941                 hns3_err(hw, "pri_to_pg mapping fail: %d", ret);
 942                 return ret;
 943         }
 944
 945         return hns3_pri_q_qs_cfg(hw);
 946 }
 947
 948 static int
 949 hns3_dcb_schd_setup_hw(struct hns3_hw *hw)
 950 {
 951         int ret;
 952
 953         /* Cfg dcb mapping  */
 954         ret = hns3_dcb_map_cfg(hw);
 955         if (ret)
 956                 return ret;
 957
 958         /* Cfg dcb shaper */
 959         ret = hns3_dcb_shaper_cfg(hw);
 960         if (ret)
 961                 return ret;
 962
 963         /* Cfg dwrr */
 964         ret = hns3_dcb_dwrr_cfg(hw);
 965         if (ret)
 966                 return ret;
 967
 968         /* Cfg schd mode for each level schd */
 969         return hns3_dcb_schd_mode_cfg(hw);
 970 }
 971
 972 static int
 973 hns3_pause_param_cfg(struct hns3_hw *hw, const uint8_t *addr,
 974                      uint8_t pause_trans_gap, uint16_t pause_trans_time)
 975 {
 976         struct hns3_cfg_pause_param_cmd *pause_param;
 977         struct hns3_cmd_desc desc;
 978
 979         pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
 980
 981         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, false);
 982
 983         memcpy(pause_param->mac_addr, addr, RTE_ETHER_ADDR_LEN);
 984         memcpy(pause_param->mac_addr_extra, addr, RTE_ETHER_ADDR_LEN);
 985         pause_param->pause_trans_gap = pause_trans_gap;
 986         pause_param->pause_trans_time = rte_cpu_to_le_16(pause_trans_time);
 987
 988         return hns3_cmd_send(hw, &desc, 1);
 989 }
 990
 991 int
 992 hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr)
 993 {
 994         struct hns3_cfg_pause_param_cmd *pause_param;
 995         struct hns3_cmd_desc desc;
 996         uint16_t trans_time;
 997         uint8_t trans_gap;
 998         int ret;
 999
1000         pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
1001
1002         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, true);
1003
1004         ret = hns3_cmd_send(hw, &desc, 1);
1005         if (ret)
1006                 return ret;
1007
1008         trans_gap = pause_param->pause_trans_gap;
1009         trans_time = rte_le_to_cpu_16(pause_param->pause_trans_time);
1010
1011         return hns3_pause_param_cfg(hw, mac_addr, trans_gap, trans_time);
1012 }
1013
1014 static int
1015 hns3_pause_param_setup_hw(struct hns3_hw *hw, uint16_t pause_time)
1016 {
1017 #define PAUSE_TIME_DIV_BY       2
1018 #define PAUSE_TIME_MIN_VALUE    0x4
1019
1020         struct hns3_mac *mac = &hw->mac;
1021         uint8_t pause_trans_gap;
1022
1023         /*
1024          * Pause transmit gap must be less than "pause_time / 2", otherwise
1025          * the behavior of MAC is undefined.
1026          */
1027         if (pause_time > PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1028                 pause_trans_gap = HNS3_DEFAULT_PAUSE_TRANS_GAP;
1029         else if (pause_time >= PAUSE_TIME_MIN_VALUE &&
1030                  pause_time <= PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1031                 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1032         else {
1033                 hns3_warn(hw, "pause_time(%d) is adjusted to 4", pause_time);
1034                 pause_time = PAUSE_TIME_MIN_VALUE;
1035                 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1036         }
1037
1038         return hns3_pause_param_cfg(hw, mac->mac_addr,
1039                                     pause_trans_gap, pause_time);
1040 }
1041
1042 static int
1043 hns3_mac_pause_en_cfg(struct hns3_hw *hw, bool tx, bool rx)
1044 {
1045         struct hns3_cmd_desc desc;
1046
1047         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PAUSE_EN, false);
1048
1049         desc.data[0] = rte_cpu_to_le_32((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1050                 (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1051
1052         return hns3_cmd_send(hw, &desc, 1);
1053 }
1054
1055 static int
1056 hns3_pfc_pause_en_cfg(struct hns3_hw *hw, uint8_t pfc_bitmap, bool tx, bool rx)
1057 {
1058         struct hns3_cmd_desc desc;
1059         struct hns3_pfc_en_cmd *pfc = (struct hns3_pfc_en_cmd *)desc.data;
1060
1061         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PFC_PAUSE_EN, false);
1062
1063         pfc->tx_rx_en_bitmap = (uint8_t)((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1064                                         (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1065
1066         pfc->pri_en_bitmap = pfc_bitmap;
1067
1068         return hns3_cmd_send(hw, &desc, 1);
1069 }
1070
1071 static int
1072 hns3_qs_bp_cfg(struct hns3_hw *hw, uint8_t tc, uint8_t grp_id, uint32_t bit_map)
1073 {
1074         struct hns3_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
1075         struct hns3_cmd_desc desc;
1076
1077         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_BP_TO_QSET_MAPPING, false);
1078
1079         bp_to_qs_map_cmd = (struct hns3_bp_to_qs_map_cmd *)desc.data;
1080
1081         bp_to_qs_map_cmd->tc_id = tc;
1082         bp_to_qs_map_cmd->qs_group_id = grp_id;
1083         bp_to_qs_map_cmd->qs_bit_map = rte_cpu_to_le_32(bit_map);
1084
1085         return hns3_cmd_send(hw, &desc, 1);
1086 }
1087
1088 static void
1089 hns3_get_rx_tx_en_status(struct hns3_hw *hw, bool *tx_en, bool *rx_en)
1090 {
1091         switch (hw->current_mode) {
1092         case HNS3_FC_NONE:
1093                 *tx_en = false;
1094                 *rx_en = false;
1095                 break;
1096         case HNS3_FC_RX_PAUSE:
1097                 *tx_en = false;
1098                 *rx_en = true;
1099                 break;
1100         case HNS3_FC_TX_PAUSE:
1101                 *tx_en = true;
1102                 *rx_en = false;
1103                 break;
1104         case HNS3_FC_FULL:
1105                 *tx_en = true;
1106                 *rx_en = true;
1107                 break;
1108         default:
1109                 *tx_en = false;
1110                 *rx_en = false;
1111                 break;
1112         }
1113 }
1114
1115 static int
1116 hns3_mac_pause_setup_hw(struct hns3_hw *hw)
1117 {
1118         bool tx_en, rx_en;
1119
1120         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)
1121                 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1122         else {
1123                 tx_en = false;
1124                 rx_en = false;
1125         }
1126
1127         return hns3_mac_pause_en_cfg(hw, tx_en, rx_en);
1128 }
1129
1130 static int
1131 hns3_pfc_setup_hw(struct hns3_hw *hw)
1132 {
1133         bool tx_en, rx_en;
1134
1135         if (hw->current_fc_status == HNS3_FC_STATUS_PFC)
1136                 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1137         else {
1138                 tx_en = false;
1139                 rx_en = false;
1140         }
1141
1142         return hns3_pfc_pause_en_cfg(hw, hw->dcb_info.pfc_en, tx_en, rx_en);
1143 }
1144
1145 /*
1146  * Each Tc has a 1024 queue sets to backpress, it divides to
1147  * 32 group, each group contains 32 queue sets, which can be
1148  * represented by uint32_t bitmap.
1149  */
1150 static int
1151 hns3_bp_setup_hw(struct hns3_hw *hw, uint8_t tc)
1152 {
1153         uint32_t qs_bitmap;
1154         int ret;
1155         int i;
1156
1157         for (i = 0; i < HNS3_BP_GRP_NUM; i++) {
1158                 uint8_t grp, sub_grp;
1159                 qs_bitmap = 0;
1160
1161                 grp = hns3_get_field(tc, HNS3_BP_GRP_ID_M, HNS3_BP_GRP_ID_S);
1162                 sub_grp = hns3_get_field(tc, HNS3_BP_SUB_GRP_ID_M,
1163                                          HNS3_BP_SUB_GRP_ID_S);
1164                 if (i == grp)
1165                         qs_bitmap |= (1 << sub_grp);
1166
1167                 ret = hns3_qs_bp_cfg(hw, tc, i, qs_bitmap);
1168                 if (ret)
1169                         return ret;
1170         }
1171
1172         return 0;
1173 }
1174
1175 static int
1176 hns3_dcb_bp_setup(struct hns3_hw *hw)
1177 {
1178         int ret, i;
1179
1180         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1181                 ret = hns3_bp_setup_hw(hw, i);
1182                 if (ret)
1183                         return ret;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int
1190 hns3_dcb_pause_setup_hw(struct hns3_hw *hw)
1191 {
1192         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1193         struct hns3_pf *pf = &hns->pf;
1194         int ret;
1195
1196         ret = hns3_pause_param_setup_hw(hw, pf->pause_time);
1197         if (ret) {
1198                 hns3_err(hw, "Fail to set pause parameter. ret = %d", ret);
1199                 return ret;
1200         }
1201
1202         ret = hns3_mac_pause_setup_hw(hw);
1203         if (ret) {
1204                 hns3_err(hw, "Fail to setup MAC pause. ret = %d", ret);
1205                 return ret;
1206         }
1207
1208         /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1209         if (!hns3_dev_dcb_supported(hw))
1210                 return 0;
1211
1212         ret = hns3_pfc_setup_hw(hw);
1213         if (ret) {
1214                 hns3_err(hw, "config pfc failed! ret = %d", ret);
1215                 return ret;
1216         }
1217
1218         return hns3_dcb_bp_setup(hw);
1219 }
1220
1221 static uint8_t
1222 hns3_dcb_undrop_tc_map(struct hns3_hw *hw, uint8_t pfc_en)
1223 {
1224         uint8_t pfc_map = 0;
1225         uint8_t *prio_tc;
1226         uint8_t i, j;
1227
1228         prio_tc = hw->dcb_info.prio_tc;
1229         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1230                 for (j = 0; j < HNS3_MAX_USER_PRIO; j++) {
1231                         if (prio_tc[j] == i && pfc_en & BIT(j)) {
1232                                 pfc_map |= BIT(i);
1233                                 break;
1234                         }
1235                 }
1236         }
1237
1238         return pfc_map;
1239 }
1240
1241 static void
1242 hns3_dcb_cfg_validate(struct hns3_adapter *hns, uint8_t *tc, bool *changed)
1243 {
1244         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1245         struct hns3_hw *hw = &hns->hw;
1246         uint8_t max_tc = 0;
1247         uint8_t pfc_en;
1248         int i;
1249
1250         dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1251         for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1252                 if (dcb_rx_conf->dcb_tc[i] != hw->dcb_info.prio_tc[i])
1253                         *changed = true;
1254
1255                 if (dcb_rx_conf->dcb_tc[i] > max_tc)
1256                         max_tc = dcb_rx_conf->dcb_tc[i];
1257         }
1258         *tc = max_tc + 1;
1259         if (*tc != hw->dcb_info.num_tc)
1260                 *changed = true;
1261
1262         /*
1263          * We ensure that dcb information can be reconfigured
1264          * after the hns3_priority_flow_ctrl_set function called.
1265          */
1266         if (hw->current_mode != HNS3_FC_FULL)
1267                 *changed = true;
1268         pfc_en = RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1269         if (hw->dcb_info.pfc_en != pfc_en)
1270                 *changed = true;
1271 }
1272
1273 static void
1274 hns3_dcb_info_cfg(struct hns3_adapter *hns)
1275 {
1276         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1277         struct hns3_pf *pf = &hns->pf;
1278         struct hns3_hw *hw = &hns->hw;
1279         uint8_t tc_bw, bw_rest;
1280         uint8_t i, j;
1281
1282         dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1283         pf->local_max_tc = (uint8_t)dcb_rx_conf->nb_tcs;
1284         pf->pfc_max = (uint8_t)dcb_rx_conf->nb_tcs;
1285
1286         /* Config pg0 */
1287         memset(hw->dcb_info.pg_info, 0,
1288                sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
1289         hw->dcb_info.pg_dwrr[0] = BW_MAX_PERCENT;
1290         hw->dcb_info.pg_info[0].pg_id = 0;
1291         hw->dcb_info.pg_info[0].pg_sch_mode = HNS3_SCH_MODE_DWRR;
1292         hw->dcb_info.pg_info[0].bw_limit = HNS3_ETHER_MAX_RATE;
1293         hw->dcb_info.pg_info[0].tc_bit_map = hw->hw_tc_map;
1294
1295         /* Each tc has same bw for valid tc by default */
1296         tc_bw = BW_MAX_PERCENT / hw->dcb_info.num_tc;
1297         for (i = 0; i < hw->dcb_info.num_tc; i++)
1298                 hw->dcb_info.pg_info[0].tc_dwrr[i] = tc_bw;
1299         /* To ensure the sum of tc_dwrr is equal to 100 */
1300         bw_rest = BW_MAX_PERCENT % hw->dcb_info.num_tc;
1301         for (j = 0; j < bw_rest; j++)
1302                 hw->dcb_info.pg_info[0].tc_dwrr[j]++;
1303         for (; i < dcb_rx_conf->nb_tcs; i++)
1304                 hw->dcb_info.pg_info[0].tc_dwrr[i] = 0;
1305
1306         /* All tcs map to pg0 */
1307         memset(hw->dcb_info.tc_info, 0,
1308                sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
1309         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1310                 hw->dcb_info.tc_info[i].tc_id = i;
1311                 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
1312                 hw->dcb_info.tc_info[i].pgid = 0;
1313                 hw->dcb_info.tc_info[i].bw_limit =
1314                                         hw->dcb_info.pg_info[0].bw_limit;
1315         }
1316
1317         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
1318                 hw->dcb_info.prio_tc[i] = dcb_rx_conf->dcb_tc[i];
1319
1320         hns3_dcb_update_tc_queue_mapping(hw, hw->data->nb_rx_queues,
1321                                          hw->data->nb_tx_queues);
1322 }
1323
1324 static int
1325 hns3_dcb_info_update(struct hns3_adapter *hns, uint8_t num_tc)
1326 {
1327         struct hns3_pf *pf = &hns->pf;
1328         struct hns3_hw *hw = &hns->hw;
1329         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1330         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1331         uint8_t bit_map = 0;
1332         uint8_t i;
1333
1334         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1335             hw->dcb_info.num_pg != 1)
1336                 return -EINVAL;
1337
1338         if (nb_rx_q < num_tc) {
1339                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1340                          nb_rx_q, num_tc);
1341                 return -EINVAL;
1342         }
1343
1344         if (nb_tx_q < num_tc) {
1345                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1346                          nb_tx_q, num_tc);
1347                 return -EINVAL;
1348         }
1349
1350         /* Currently not support uncontinuous tc */
1351         hw->dcb_info.num_tc = num_tc;
1352         for (i = 0; i < hw->dcb_info.num_tc; i++)
1353                 bit_map |= BIT(i);
1354
1355         if (!bit_map) {
1356                 bit_map = 1;
1357                 hw->dcb_info.num_tc = 1;
1358         }
1359         hw->hw_tc_map = bit_map;
1360         hns3_dcb_info_cfg(hns);
1361
1362         return 0;
1363 }
1364
1365 static int
1366 hns3_dcb_hw_configure(struct hns3_adapter *hns)
1367 {
1368         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1369         struct hns3_pf *pf = &hns->pf;
1370         struct hns3_hw *hw = &hns->hw;
1371         enum hns3_fc_status fc_status = hw->current_fc_status;
1372         enum hns3_fc_mode current_mode = hw->current_mode;
1373         uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1374         int ret, status;
1375
1376         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1377             pf->tx_sch_mode != HNS3_FLAG_VNET_BASE_SCH_MODE)
1378                 return -ENOTSUP;
1379
1380         ret = hns3_dcb_schd_setup_hw(hw);
1381         if (ret) {
1382                 hns3_err(hw, "dcb schdule configure failed! ret = %d", ret);
1383                 return ret;
1384         }
1385
1386         if (hw->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
1387                 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1388                 if (dcb_rx_conf->nb_tcs == 0)
1389                         hw->dcb_info.pfc_en = 1; /* tc0 only */
1390                 else
1391                         hw->dcb_info.pfc_en =
1392                         RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1393
1394                 hw->dcb_info.hw_pfc_map =
1395                                 hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1396
1397                 ret = hns3_buffer_alloc(hw);
1398                 if (ret)
1399                         return ret;
1400
1401                 hw->current_fc_status = HNS3_FC_STATUS_PFC;
1402                 hw->current_mode = HNS3_FC_FULL;
1403                 ret = hns3_dcb_pause_setup_hw(hw);
1404                 if (ret) {
1405                         hns3_err(hw, "setup pfc failed! ret = %d", ret);
1406                         goto pfc_setup_fail;
1407                 }
1408         } else {
1409                 /*
1410                  * Although dcb_capability_en is lack of ETH_DCB_PFC_SUPPORT
1411                  * flag, the DCB information is configured, such as tc numbers.
1412                  * Therefore, refreshing the allocation of packet buffer is
1413                  * necessary.
1414                  */
1415                 ret = hns3_buffer_alloc(hw);
1416                 if (ret)
1417                         return ret;
1418         }
1419
1420         return 0;
1421
1422 pfc_setup_fail:
1423         hw->current_mode = current_mode;
1424         hw->current_fc_status = fc_status;
1425         hw->dcb_info.hw_pfc_map = hw_pfc_map;
1426         status = hns3_buffer_alloc(hw);
1427         if (status)
1428                 hns3_err(hw, "recover packet buffer fail! status = %d", status);
1429
1430         return ret;
1431 }
1432
1433 /*
1434  * hns3_dcb_configure - setup dcb related config
1435  * @hns: pointer to hns3 adapter
1436  * Returns 0 on success, negative value on failure.
1437  */
1438 int
1439 hns3_dcb_configure(struct hns3_adapter *hns)
1440 {
1441         struct hns3_hw *hw = &hns->hw;
1442         bool map_changed = false;
1443         uint8_t num_tc = 0;
1444         int ret;
1445
1446         hns3_dcb_cfg_validate(hns, &num_tc, &map_changed);
1447         if (map_changed || rte_atomic16_read(&hw->reset.resetting)) {
1448                 ret = hns3_dcb_info_update(hns, num_tc);
1449                 if (ret) {
1450                         hns3_err(hw, "dcb info update failed: %d", ret);
1451                         return ret;
1452                 }
1453
1454                 ret = hns3_dcb_hw_configure(hns);
1455                 if (ret) {
1456                         hns3_err(hw, "dcb sw configure failed: %d", ret);
1457                         return ret;
1458                 }
1459         }
1460
1461         return 0;
1462 }
1463
1464 int
1465 hns3_dcb_init_hw(struct hns3_hw *hw)
1466 {
1467         int ret;
1468
1469         ret = hns3_dcb_schd_setup_hw(hw);
1470         if (ret) {
1471                 hns3_err(hw, "dcb schedule setup failed: %d", ret);
1472                 return ret;
1473         }
1474
1475         ret = hns3_dcb_pause_setup_hw(hw);
1476         if (ret)
1477                 hns3_err(hw, "PAUSE setup failed: %d", ret);
1478
1479         return ret;
1480 }
1481
1482 int
1483 hns3_dcb_init(struct hns3_hw *hw)
1484 {
1485         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1486         struct hns3_pf *pf = &hns->pf;
1487         int ret;
1488
1489         PMD_INIT_FUNC_TRACE();
1490
1491         /*
1492          * According to the 'adapter_state' identifier, the following branch
1493          * is only executed to initialize default configurations of dcb during
1494          * the initializing driver process. Due to driver saving dcb-related
1495          * information before reset triggered, the reinit dev stage of the
1496          * reset process can not access to the branch, or those information
1497          * will be changed.
1498          */
1499         if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
1500                 hw->requested_mode = HNS3_FC_NONE;
1501                 hw->current_mode = hw->requested_mode;
1502                 pf->pause_time = HNS3_DEFAULT_PAUSE_TRANS_TIME;
1503                 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1504
1505                 ret = hns3_dcb_info_init(hw);
1506                 if (ret) {
1507                         hns3_err(hw, "dcb info init failed: %d", ret);
1508                         return ret;
1509                 }
1510                 hns3_dcb_update_tc_queue_mapping(hw, hw->tqps_num,
1511                                                  hw->tqps_num);
1512         }
1513
1514         /*
1515          * DCB hardware will be configured by following the function during
1516          * the initializing driver process and the reset process. However,
1517          * driver will restore directly configurations of dcb hardware based
1518          * on dcb-related information soft maintained when driver
1519          * initialization has finished and reset is coming.
1520          */
1521         ret = hns3_dcb_init_hw(hw);
1522         if (ret) {
1523                 hns3_err(hw, "dcb init hardware failed: %d", ret);
1524                 return ret;
1525         }
1526
1527         return 0;
1528 }
1529
1530 static int
1531 hns3_update_queue_map_configure(struct hns3_adapter *hns)
1532 {
1533         struct hns3_hw *hw = &hns->hw;
1534         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1535         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1536         int ret;
1537
1538         hns3_dcb_update_tc_queue_mapping(hw, nb_rx_q, nb_tx_q);
1539         ret = hns3_q_to_qs_map(hw);
1540         if (ret) {
1541                 hns3_err(hw, "failed to map nq to qs! ret = %d", ret);
1542                 return ret;
1543         }
1544
1545         return 0;
1546 }
1547
1548 int
1549 hns3_dcb_cfg_update(struct hns3_adapter *hns)
1550 {
1551         struct hns3_hw *hw = &hns->hw;
1552         enum rte_eth_rx_mq_mode mq_mode = hw->data->dev_conf.rxmode.mq_mode;
1553         int ret;
1554
1555         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
1556                 ret = hns3_dcb_configure(hns);
1557                 if (ret) {
1558                         hns3_err(hw, "Failed to config dcb: %d", ret);
1559                         return ret;
1560                 }
1561         } else {
1562                 /*
1563                  * Update queue map without PFC configuration,
1564                  * due to queues reconfigured by user.
1565                  */
1566                 ret = hns3_update_queue_map_configure(hns);
1567                 if (ret)
1568                         hns3_err(hw,
1569                                  "Failed to update queue mapping configure: %d",
1570                                  ret);
1571         }
1572
1573         return ret;
1574 }
1575
1576 /*
1577  * hns3_dcb_pfc_enable - Enable priority flow control
1578  * @dev: pointer to ethernet device
1579  *
1580  * Configures the pfc settings for one porority.
1581  */
1582 int
1583 hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
1584 {
1585         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1587         enum hns3_fc_status fc_status = hw->current_fc_status;
1588         enum hns3_fc_mode current_mode = hw->current_mode;
1589         uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1590         uint8_t pfc_en = hw->dcb_info.pfc_en;
1591         uint8_t priority = pfc_conf->priority;
1592         uint16_t pause_time = pf->pause_time;
1593         int ret, status;
1594
1595         pf->pause_time = pfc_conf->fc.pause_time;
1596         hw->current_mode = hw->requested_mode;
1597         hw->current_fc_status = HNS3_FC_STATUS_PFC;
1598         hw->dcb_info.pfc_en |= BIT(priority);
1599         hw->dcb_info.hw_pfc_map =
1600                         hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1601         ret = hns3_buffer_alloc(hw);
1602         if (ret)
1603                 goto pfc_setup_fail;
1604
1605         /*
1606          * The flow control mode of all UPs will be changed based on
1607          * current_mode coming from user.
1608          */
1609         ret = hns3_dcb_pause_setup_hw(hw);
1610         if (ret) {
1611                 hns3_err(hw, "enable pfc failed! ret = %d", ret);
1612                 goto pfc_setup_fail;
1613         }
1614
1615         return 0;
1616
1617 pfc_setup_fail:
1618         hw->current_mode = current_mode;
1619         hw->current_fc_status = fc_status;
1620         pf->pause_time = pause_time;
1621         hw->dcb_info.pfc_en = pfc_en;
1622         hw->dcb_info.hw_pfc_map = hw_pfc_map;
1623         status = hns3_buffer_alloc(hw);
1624         if (status)
1625                 hns3_err(hw, "recover packet buffer fail: %d", status);
1626
1627         return ret;
1628 }
1629
1630 /*
1631  * hns3_fc_enable - Enable MAC pause
1632  * @dev: pointer to ethernet device
1633  *
1634  * Configures the MAC pause settings.
1635  */
1636 int
1637 hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1638 {
1639         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1641         enum hns3_fc_status fc_status = hw->current_fc_status;
1642         enum hns3_fc_mode current_mode = hw->current_mode;
1643         uint16_t pause_time = pf->pause_time;
1644         int ret;
1645
1646         pf->pause_time = fc_conf->pause_time;
1647         hw->current_mode = hw->requested_mode;
1648
1649         /*
1650          * In fact, current_fc_status is HNS3_FC_STATUS_NONE when mode
1651          * of flow control is configured to be HNS3_FC_NONE.
1652          */
1653         if (hw->current_mode == HNS3_FC_NONE)
1654                 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1655         else
1656                 hw->current_fc_status = HNS3_FC_STATUS_MAC_PAUSE;
1657
1658         ret = hns3_dcb_pause_setup_hw(hw);
1659         if (ret) {
1660                 hns3_err(hw, "enable MAC Pause failed! ret = %d", ret);
1661                 goto setup_fc_fail;
1662         }
1663
1664         return 0;
1665
1666 setup_fc_fail:
1667         hw->current_mode = current_mode;
1668         hw->current_fc_status = fc_status;
1669         pf->pause_time = pause_time;
1670
1671         return ret;
1672 }