drivers/net/hns3/hns3_dcb.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <rte_io.h>
  11 #include <rte_common.h>
  12 #include <rte_ethdev.h>
  13
  14 #include "hns3_logs.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_ethdev.h"
  17 #include "hns3_dcb.h"
  18
  19 #define HNS3_SHAPER_BS_U_DEF    5
  20 #define HNS3_SHAPER_BS_S_DEF    20
  21 #define BW_MAX_PERCENT          100
  22 #define HNS3_ETHER_MAX_RATE     100000
  23
  24 /*
  25  * hns3_shaper_para_calc: calculate ir parameter for the shaper
  26  * @ir: Rate to be config, its unit is Mbps
  27  * @shaper_level: the shaper level. eg: port, pg, priority, queueset
  28  * @shaper_para: shaper parameter of IR shaper
  29  *
  30  * the formula:
  31  *
  32  *              IR_b * (2 ^ IR_u) * 8
  33  * IR(Mbps) = -------------------------  *  CLOCK(1000Mbps)
  34  *              Tick * (2 ^ IR_s)
  35  *
  36  * @return: 0: calculate sucessful, negative: fail
  37  */
  38 static int
  39 hns3_shaper_para_calc(struct hns3_hw *hw, uint32_t ir, uint8_t shaper_level,
  40                       struct hns3_shaper_parameter *shaper_para)
  41 {
  42 #define SHAPER_DEFAULT_IR_B     126
  43 #define DIVISOR_CLK             (1000 * 8)
  44 #define DIVISOR_IR_B_126        (126 * DIVISOR_CLK)
  45
  46         const uint16_t tick_array[HNS3_SHAPER_LVL_CNT] = {
  47                 6 * 256,    /* Prioriy level */
  48                 6 * 32,     /* Prioriy group level */
  49                 6 * 8,      /* Port level */
  50                 6 * 256     /* Qset level */
  51         };
  52         uint8_t ir_u_calc = 0;
  53         uint8_t ir_s_calc = 0;
  54         uint32_t denominator;
  55         uint32_t ir_calc;
  56         uint32_t tick;
  57
  58         /* Calc tick */
  59         if (shaper_level >= HNS3_SHAPER_LVL_CNT) {
  60                 hns3_err(hw,
  61                          "shaper_level(%d) is greater than HNS3_SHAPER_LVL_CNT(%d)",
  62                          shaper_level, HNS3_SHAPER_LVL_CNT);
  63                 return -EINVAL;
  64         }
  65
  66         if (ir > HNS3_ETHER_MAX_RATE) {
  67                 hns3_err(hw, "rate(%d) exceeds the rate driver supported "
  68                          "HNS3_ETHER_MAX_RATE(%d)", ir, HNS3_ETHER_MAX_RATE);
  69                 return -EINVAL;
  70         }
  71
  72         tick = tick_array[shaper_level];
  73
  74         /*
  75          * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
  76          * the formula is changed to:
  77          *              126 * 1 * 8
  78          * ir_calc = ---------------- * 1000
  79          *              tick * 1
  80          */
  81         ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
  82
  83         if (ir_calc == ir) {
  84                 shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
  85         } else if (ir_calc > ir) {
  86                 /* Increasing the denominator to select ir_s value */
  87                 do {
  88                         ir_s_calc++;
  89                         ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
  90                 } while (ir_calc > ir);
  91
  92                 if (ir_calc == ir)
  93                         shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
  94                 else
  95                         shaper_para->ir_b = (ir * tick * (1 << ir_s_calc) +
  96                                  (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
  97         } else {
  98                 /*
  99                  * Increasing the numerator to select ir_u value. ir_u_calc will
 100                  * get maximum value when ir_calc is minimum and ir is maximum.
 101                  * ir_calc gets minimum value when tick is the maximum value.
 102                  * At the same time, value of ir_u_calc can only be increased up
 103                  * to eight after the while loop if the value of ir is equal
 104                  * to HNS3_ETHER_MAX_RATE.
 105                  */
 106                 uint32_t numerator;
 107                 do {
 108                         ir_u_calc++;
 109                         numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
 110                         ir_calc = (numerator + (tick >> 1)) / tick;
 111                 } while (ir_calc < ir);
 112
 113                 if (ir_calc == ir) {
 114                         shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
 115                 } else {
 116                         --ir_u_calc;
 117
 118                         /*
 119                          * The maximum value of ir_u_calc in this branch is
 120                          * seven in all cases. Thus, value of denominator can
 121                          * not be zero here.
 122                          */
 123                         denominator = DIVISOR_CLK * (1 << ir_u_calc);
 124                         shaper_para->ir_b =
 125                                 (ir * tick + (denominator >> 1)) / denominator;
 126                 }
 127         }
 128
 129         shaper_para->ir_u = ir_u_calc;
 130         shaper_para->ir_s = ir_s_calc;
 131
 132         return 0;
 133 }
 134
 135 static int
 136 hns3_fill_pri_array(struct hns3_hw *hw, uint8_t *pri, uint8_t pri_id)
 137 {
 138 #define HNS3_HALF_BYTE_BIT_OFFSET 4
 139         uint8_t tc = hw->dcb_info.prio_tc[pri_id];
 140
 141         if (tc >= hw->dcb_info.num_tc)
 142                 return -EINVAL;
 143
 144         /*
 145          * The register for priority has four bytes, the first bytes includes
 146          *  priority0 and priority1, the higher 4bit stands for priority1
 147          *  while the lower 4bit stands for priority0, as below:
 148          * first byte:  | pri_1 | pri_0 |
 149          * second byte: | pri_3 | pri_2 |
 150          * third byte:  | pri_5 | pri_4 |
 151          * fourth byte: | pri_7 | pri_6 |
 152          */
 153         pri[pri_id >> 1] |= tc << ((pri_id & 1) * HNS3_HALF_BYTE_BIT_OFFSET);
 154
 155         return 0;
 156 }
 157
 158 static int
 159 hns3_up_to_tc_map(struct hns3_hw *hw)
 160 {
 161         struct hns3_cmd_desc desc;
 162         uint8_t *pri = (uint8_t *)desc.data;
 163         uint8_t pri_id;
 164         int ret;
 165
 166         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PRI_TO_TC_MAPPING, false);
 167
 168         for (pri_id = 0; pri_id < HNS3_MAX_USER_PRIO; pri_id++) {
 169                 ret = hns3_fill_pri_array(hw, pri, pri_id);
 170                 if (ret)
 171                         return ret;
 172         }
 173
 174         return hns3_cmd_send(hw, &desc, 1);
 175 }
 176
 177 static int
 178 hns3_pg_to_pri_map_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t pri_bit_map)
 179 {
 180         struct hns3_pg_to_pri_link_cmd *map;
 181         struct hns3_cmd_desc desc;
 182
 183         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_TO_PRI_LINK, false);
 184
 185         map = (struct hns3_pg_to_pri_link_cmd *)desc.data;
 186
 187         map->pg_id = pg_id;
 188         map->pri_bit_map = pri_bit_map;
 189
 190         return hns3_cmd_send(hw, &desc, 1);
 191 }
 192
 193 static int
 194 hns3_pg_to_pri_map(struct hns3_hw *hw)
 195 {
 196         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 197         struct hns3_pf *pf = &hns->pf;
 198         struct hns3_pg_info *pg_info;
 199         int ret, i;
 200
 201         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 202                 return -EINVAL;
 203
 204         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 205                 /* Cfg pg to priority mapping */
 206                 pg_info = &hw->dcb_info.pg_info[i];
 207                 ret = hns3_pg_to_pri_map_cfg(hw, i, pg_info->tc_bit_map);
 208                 if (ret)
 209                         return ret;
 210         }
 211
 212         return 0;
 213 }
 214
 215 static int
 216 hns3_qs_to_pri_map_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t pri)
 217 {
 218         struct hns3_qs_to_pri_link_cmd *map;
 219         struct hns3_cmd_desc desc;
 220
 221         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_TO_PRI_LINK, false);
 222
 223         map = (struct hns3_qs_to_pri_link_cmd *)desc.data;
 224
 225         map->qs_id = rte_cpu_to_le_16(qs_id);
 226         map->priority = pri;
 227         map->link_vld = HNS3_DCB_QS_PRI_LINK_VLD_MSK;
 228
 229         return hns3_cmd_send(hw, &desc, 1);
 230 }
 231
 232 static int
 233 hns3_dcb_qs_weight_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t dwrr)
 234 {
 235         struct hns3_qs_weight_cmd *weight;
 236         struct hns3_cmd_desc desc;
 237
 238         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_WEIGHT, false);
 239
 240         weight = (struct hns3_qs_weight_cmd *)desc.data;
 241
 242         weight->qs_id = rte_cpu_to_le_16(qs_id);
 243         weight->dwrr = dwrr;
 244
 245         return hns3_cmd_send(hw, &desc, 1);
 246 }
 247
 248 static int
 249 hns3_dcb_ets_tc_dwrr_cfg(struct hns3_hw *hw)
 250 {
 251 #define DEFAULT_TC_WEIGHT       1
 252 #define DEFAULT_TC_OFFSET       14
 253         struct hns3_ets_tc_weight_cmd *ets_weight;
 254         struct hns3_cmd_desc desc;
 255         uint8_t i;
 256
 257         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_ETS_TC_WEIGHT, false);
 258         ets_weight = (struct hns3_ets_tc_weight_cmd *)desc.data;
 259
 260         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 261                 struct hns3_pg_info *pg_info;
 262
 263                 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
 264
 265                 if (!(hw->hw_tc_map & BIT(i)))
 266                         continue;
 267
 268                 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
 269                 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
 270         }
 271
 272         ets_weight->weight_offset = DEFAULT_TC_OFFSET;
 273
 274         return hns3_cmd_send(hw, &desc, 1);
 275 }
 276
 277 static int
 278 hns3_dcb_pri_weight_cfg(struct hns3_hw *hw, uint8_t pri_id, uint8_t dwrr)
 279 {
 280         struct hns3_priority_weight_cmd *weight;
 281         struct hns3_cmd_desc desc;
 282
 283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_WEIGHT, false);
 284
 285         weight = (struct hns3_priority_weight_cmd *)desc.data;
 286
 287         weight->pri_id = pri_id;
 288         weight->dwrr = dwrr;
 289
 290         return hns3_cmd_send(hw, &desc, 1);
 291 }
 292
 293 static int
 294 hns3_dcb_pg_weight_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t dwrr)
 295 {
 296         struct hns3_pg_weight_cmd *weight;
 297         struct hns3_cmd_desc desc;
 298
 299         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_WEIGHT, false);
 300
 301         weight = (struct hns3_pg_weight_cmd *)desc.data;
 302
 303         weight->pg_id = pg_id;
 304         weight->dwrr = dwrr;
 305
 306         return hns3_cmd_send(hw, &desc, 1);
 307 }
 308 static int
 309 hns3_dcb_pg_schd_mode_cfg(struct hns3_hw *hw, uint8_t pg_id)
 310 {
 311         struct hns3_cmd_desc desc;
 312
 313         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_SCH_MODE_CFG, false);
 314
 315         if (hw->dcb_info.pg_info[pg_id].pg_sch_mode == HNS3_SCH_MODE_DWRR)
 316                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 317         else
 318                 desc.data[1] = 0;
 319
 320         desc.data[0] = rte_cpu_to_le_32(pg_id);
 321
 322         return hns3_cmd_send(hw, &desc, 1);
 323 }
 324
 325 static uint32_t
 326 hns3_dcb_get_shapping_para(uint8_t ir_b, uint8_t ir_u, uint8_t ir_s,
 327                            uint8_t bs_b, uint8_t bs_s)
 328 {
 329         uint32_t shapping_para = 0;
 330
 331         hns3_dcb_set_field(shapping_para, IR_B, ir_b);
 332         hns3_dcb_set_field(shapping_para, IR_U, ir_u);
 333         hns3_dcb_set_field(shapping_para, IR_S, ir_s);
 334         hns3_dcb_set_field(shapping_para, BS_B, bs_b);
 335         hns3_dcb_set_field(shapping_para, BS_S, bs_s);
 336
 337         return shapping_para;
 338 }
 339
 340 static int
 341 hns3_dcb_port_shaper_cfg(struct hns3_hw *hw)
 342 {
 343         struct hns3_port_shapping_cmd *shap_cfg_cmd;
 344         struct hns3_shaper_parameter shaper_parameter;
 345         uint32_t shapping_para;
 346         uint32_t ir_u, ir_b, ir_s;
 347         struct hns3_cmd_desc desc;
 348         int ret;
 349
 350         ret = hns3_shaper_para_calc(hw, hw->mac.link_speed,
 351                                     HNS3_SHAPER_LVL_PORT, &shaper_parameter);
 352         if (ret) {
 353                 hns3_err(hw, "calculate shaper parameter failed: %d", ret);
 354                 return ret;
 355         }
 356
 357         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PORT_SHAPPING, false);
 358         shap_cfg_cmd = (struct hns3_port_shapping_cmd *)desc.data;
 359
 360         ir_b = shaper_parameter.ir_b;
 361         ir_u = shaper_parameter.ir_u;
 362         ir_s = shaper_parameter.ir_s;
 363         shapping_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 364                                                    HNS3_SHAPER_BS_U_DEF,
 365                                                    HNS3_SHAPER_BS_S_DEF);
 366
 367         shap_cfg_cmd->port_shapping_para = rte_cpu_to_le_32(shapping_para);
 368
 369         return hns3_cmd_send(hw, &desc, 1);
 370 }
 371
 372 static int
 373 hns3_dcb_pg_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
 374                          uint8_t pg_id, uint32_t shapping_para)
 375 {
 376         struct hns3_pg_shapping_cmd *shap_cfg_cmd;
 377         enum hns3_opcode_type opcode;
 378         struct hns3_cmd_desc desc;
 379
 380         opcode = bucket ? HNS3_OPC_TM_PG_P_SHAPPING :
 381                  HNS3_OPC_TM_PG_C_SHAPPING;
 382         hns3_cmd_setup_basic_desc(&desc, opcode, false);
 383
 384         shap_cfg_cmd = (struct hns3_pg_shapping_cmd *)desc.data;
 385
 386         shap_cfg_cmd->pg_id = pg_id;
 387
 388         shap_cfg_cmd->pg_shapping_para = rte_cpu_to_le_32(shapping_para);
 389
 390         return hns3_cmd_send(hw, &desc, 1);
 391 }
 392
 393 static int
 394 hns3_dcb_pg_shaper_cfg(struct hns3_hw *hw)
 395 {
 396         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 397         struct hns3_shaper_parameter shaper_parameter;
 398         struct hns3_pf *pf = &hns->pf;
 399         uint32_t ir_u, ir_b, ir_s;
 400         uint32_t shaper_para;
 401         uint8_t i;
 402         int ret;
 403
 404         /* Cfg pg schd */
 405         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 406                 return -EINVAL;
 407
 408         /* Pg to pri */
 409         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 410                 /* Calc shaper para */
 411                 ret = hns3_shaper_para_calc(hw,
 412                                             hw->dcb_info.pg_info[i].bw_limit,
 413                                             HNS3_SHAPER_LVL_PG,
 414                                             &shaper_parameter);
 415                 if (ret) {
 416                         hns3_err(hw, "calculate shaper parameter failed: %d",
 417                                  ret);
 418                         return ret;
 419                 }
 420
 421                 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
 422                                                          HNS3_SHAPER_BS_U_DEF,
 423                                                          HNS3_SHAPER_BS_S_DEF);
 424
 425                 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
 426                                                shaper_para);
 427                 if (ret) {
 428                         hns3_err(hw,
 429                                  "config PG CIR shaper parameter failed: %d",
 430                                  ret);
 431                         return ret;
 432                 }
 433
 434                 ir_b = shaper_parameter.ir_b;
 435                 ir_u = shaper_parameter.ir_u;
 436                 ir_s = shaper_parameter.ir_s;
 437                 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 438                                                          HNS3_SHAPER_BS_U_DEF,
 439                                                          HNS3_SHAPER_BS_S_DEF);
 440
 441                 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
 442                                                shaper_para);
 443                 if (ret) {
 444                         hns3_err(hw,
 445                                  "config PG PIR shaper parameter failed: %d",
 446                                  ret);
 447                         return ret;
 448                 }
 449         }
 450
 451         return 0;
 452 }
 453
 454 static int
 455 hns3_dcb_qs_schd_mode_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t mode)
 456 {
 457         struct hns3_cmd_desc desc;
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_SCH_MODE_CFG, false);
 460
 461         if (mode == HNS3_SCH_MODE_DWRR)
 462                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 463         else
 464                 desc.data[1] = 0;
 465
 466         desc.data[0] = rte_cpu_to_le_32(qs_id);
 467
 468         return hns3_cmd_send(hw, &desc, 1);
 469 }
 470
 471 static int
 472 hns3_dcb_pri_schd_mode_cfg(struct hns3_hw *hw, uint8_t pri_id)
 473 {
 474         struct hns3_cmd_desc desc;
 475
 476         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_SCH_MODE_CFG, false);
 477
 478         if (hw->dcb_info.tc_info[pri_id].tc_sch_mode == HNS3_SCH_MODE_DWRR)
 479                 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
 480         else
 481                 desc.data[1] = 0;
 482
 483         desc.data[0] = rte_cpu_to_le_32(pri_id);
 484
 485         return hns3_cmd_send(hw, &desc, 1);
 486 }
 487
 488 static int
 489 hns3_dcb_pri_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
 490                           uint8_t pri_id, uint32_t shapping_para)
 491 {
 492         struct hns3_pri_shapping_cmd *shap_cfg_cmd;
 493         enum hns3_opcode_type opcode;
 494         struct hns3_cmd_desc desc;
 495
 496         opcode = bucket ? HNS3_OPC_TM_PRI_P_SHAPPING :
 497                  HNS3_OPC_TM_PRI_C_SHAPPING;
 498
 499         hns3_cmd_setup_basic_desc(&desc, opcode, false);
 500
 501         shap_cfg_cmd = (struct hns3_pri_shapping_cmd *)desc.data;
 502
 503         shap_cfg_cmd->pri_id = pri_id;
 504
 505         shap_cfg_cmd->pri_shapping_para = rte_cpu_to_le_32(shapping_para);
 506
 507         return hns3_cmd_send(hw, &desc, 1);
 508 }
 509
 510 static int
 511 hns3_dcb_pri_tc_base_shaper_cfg(struct hns3_hw *hw)
 512 {
 513         struct hns3_shaper_parameter shaper_parameter;
 514         uint32_t ir_u, ir_b, ir_s;
 515         uint32_t shaper_para;
 516         int ret, i;
 517
 518         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 519                 ret = hns3_shaper_para_calc(hw,
 520                                             hw->dcb_info.tc_info[i].bw_limit,
 521                                             HNS3_SHAPER_LVL_PRI,
 522                                             &shaper_parameter);
 523                 if (ret) {
 524                         hns3_err(hw, "calculate shaper parameter failed: %d",
 525                                  ret);
 526                         return ret;
 527                 }
 528
 529                 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
 530                                                          HNS3_SHAPER_BS_U_DEF,
 531                                                          HNS3_SHAPER_BS_S_DEF);
 532
 533                 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
 534                                                 shaper_para);
 535                 if (ret) {
 536                         hns3_err(hw,
 537                                  "config priority CIR shaper parameter failed: %d",
 538                                  ret);
 539                         return ret;
 540                 }
 541
 542                 ir_b = shaper_parameter.ir_b;
 543                 ir_u = shaper_parameter.ir_u;
 544                 ir_s = shaper_parameter.ir_s;
 545                 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
 546                                                          HNS3_SHAPER_BS_U_DEF,
 547                                                          HNS3_SHAPER_BS_S_DEF);
 548
 549                 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
 550                                                 shaper_para);
 551                 if (ret) {
 552                         hns3_err(hw,
 553                                  "config priority PIR shaper parameter failed: %d",
 554                                  ret);
 555                         return ret;
 556                 }
 557         }
 558
 559         return 0;
 560 }
 561
 562
 563 static int
 564 hns3_dcb_pri_shaper_cfg(struct hns3_hw *hw)
 565 {
 566         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 567         struct hns3_pf *pf = &hns->pf;
 568         int ret;
 569
 570         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 571                 return -EINVAL;
 572
 573         ret = hns3_dcb_pri_tc_base_shaper_cfg(hw);
 574         if (ret)
 575                 hns3_err(hw, "config port shaper failed: %d", ret);
 576
 577         return ret;
 578 }
 579
 580 void
 581 hns3_set_rss_size(struct hns3_hw *hw, uint16_t nb_rx_q)
 582 {
 583         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 584         uint16_t rx_qnum_per_tc;
 585         int i;
 586
 587         rx_qnum_per_tc = nb_rx_q / hw->num_tc;
 588         rx_qnum_per_tc = RTE_MIN(hw->rss_size_max, rx_qnum_per_tc);
 589         if (hw->alloc_rss_size != rx_qnum_per_tc) {
 590                 hns3_info(hw, "rss size changes from %u to %u",
 591                           hw->alloc_rss_size, rx_qnum_per_tc);
 592                 hw->alloc_rss_size = rx_qnum_per_tc;
 593         }
 594         hw->used_rx_queues = hw->num_tc * hw->alloc_rss_size;
 595
 596         /*
 597          * When rss size is changed, we need to update rss redirection table
 598          * maintained by driver. Besides, during the entire reset process, we
 599          * need to ensure that the rss table information are not overwritten
 600          * and configured directly to the hardware in the RESET_STAGE_RESTORE
 601          * stage of the reset process.
 602          */
 603         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 604                 for (i = 0; i < HNS3_RSS_IND_TBL_SIZE; i++)
 605                         rss_cfg->rss_indirection_tbl[i] =
 606                                                         i % hw->alloc_rss_size;
 607         }
 608 }
 609
 610 void
 611 hns3_tc_queue_mapping_cfg(struct hns3_hw *hw, uint16_t nb_queue)
 612 {
 613         struct hns3_tc_queue_info *tc_queue;
 614         uint8_t i;
 615
 616         hw->tx_qnum_per_tc = nb_queue / hw->num_tc;
 617         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 618                 tc_queue = &hw->tc_queue[i];
 619                 if (hw->hw_tc_map & BIT(i) && i < hw->num_tc) {
 620                         tc_queue->enable = true;
 621                         tc_queue->tqp_offset = i * hw->tx_qnum_per_tc;
 622                         tc_queue->tqp_count = hw->tx_qnum_per_tc;
 623                         tc_queue->tc = i;
 624                 } else {
 625                         /* Set to default queue if TC is disable */
 626                         tc_queue->enable = false;
 627                         tc_queue->tqp_offset = 0;
 628                         tc_queue->tqp_count = 0;
 629                         tc_queue->tc = 0;
 630                 }
 631         }
 632         hw->used_tx_queues = hw->num_tc * hw->tx_qnum_per_tc;
 633 }
 634
 635 static void
 636 hns3_dcb_update_tc_queue_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
 637                                  uint16_t nb_tx_q)
 638 {
 639         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 640         struct hns3_pf *pf = &hns->pf;
 641
 642         hw->num_tc = hw->dcb_info.num_tc;
 643         hns3_set_rss_size(hw, nb_rx_q);
 644         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
 645
 646         if (!hns->is_vf)
 647                 memcpy(pf->prio_tc, hw->dcb_info.prio_tc, HNS3_MAX_USER_PRIO);
 648 }
 649
 650 int
 651 hns3_dcb_info_init(struct hns3_hw *hw)
 652 {
 653         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 654         struct hns3_pf *pf = &hns->pf;
 655         int i, k;
 656
 657         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
 658             hw->dcb_info.num_pg != 1)
 659                 return -EINVAL;
 660
 661         /* Initializing PG information */
 662         memset(hw->dcb_info.pg_info, 0,
 663                sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
 664         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 665                 hw->dcb_info.pg_dwrr[i] = i ? 0 : BW_MAX_PERCENT;
 666                 hw->dcb_info.pg_info[i].pg_id = i;
 667                 hw->dcb_info.pg_info[i].pg_sch_mode = HNS3_SCH_MODE_DWRR;
 668                 hw->dcb_info.pg_info[i].bw_limit = HNS3_ETHER_MAX_RATE;
 669
 670                 if (i != 0)
 671                         continue;
 672
 673                 hw->dcb_info.pg_info[i].tc_bit_map = hw->hw_tc_map;
 674                 for (k = 0; k < hw->dcb_info.num_tc; k++)
 675                         hw->dcb_info.pg_info[i].tc_dwrr[k] = BW_MAX_PERCENT;
 676         }
 677
 678         /* All UPs mapping to TC0 */
 679         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
 680                 hw->dcb_info.prio_tc[i] = 0;
 681
 682         /* Initializing tc information */
 683         memset(hw->dcb_info.tc_info, 0,
 684                sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
 685         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 686                 hw->dcb_info.tc_info[i].tc_id = i;
 687                 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
 688                 hw->dcb_info.tc_info[i].pgid = 0;
 689                 hw->dcb_info.tc_info[i].bw_limit =
 690                         hw->dcb_info.pg_info[0].bw_limit;
 691         }
 692
 693         return 0;
 694 }
 695
 696 static int
 697 hns3_dcb_lvl2_schd_mode_cfg(struct hns3_hw *hw)
 698 {
 699         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 700         struct hns3_pf *pf = &hns->pf;
 701         int ret, i;
 702
 703         /* Only being config on TC-Based scheduler mode */
 704         if (pf->tx_sch_mode == HNS3_FLAG_VNET_BASE_SCH_MODE)
 705                 return -EINVAL;
 706
 707         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 708                 ret = hns3_dcb_pg_schd_mode_cfg(hw, i);
 709                 if (ret)
 710                         return ret;
 711         }
 712
 713         return 0;
 714 }
 715
 716 static int
 717 hns3_dcb_lvl34_schd_mode_cfg(struct hns3_hw *hw)
 718 {
 719         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 720         struct hns3_pf *pf = &hns->pf;
 721         uint8_t i;
 722         int ret;
 723
 724         if (pf->tx_sch_mode == HNS3_FLAG_TC_BASE_SCH_MODE) {
 725                 for (i = 0; i < hw->dcb_info.num_tc; i++) {
 726                         ret = hns3_dcb_pri_schd_mode_cfg(hw, i);
 727                         if (ret)
 728                                 return ret;
 729
 730                         ret = hns3_dcb_qs_schd_mode_cfg(hw, i,
 731                                                         HNS3_SCH_MODE_DWRR);
 732                         if (ret)
 733                                 return ret;
 734                 }
 735         }
 736
 737         return 0;
 738 }
 739
 740 static int
 741 hns3_dcb_schd_mode_cfg(struct hns3_hw *hw)
 742 {
 743         int ret;
 744
 745         ret = hns3_dcb_lvl2_schd_mode_cfg(hw);
 746         if (ret) {
 747                 hns3_err(hw, "config lvl2_schd_mode failed: %d", ret);
 748                 return ret;
 749         }
 750
 751         ret = hns3_dcb_lvl34_schd_mode_cfg(hw);
 752         if (ret)
 753                 hns3_err(hw, "config lvl34_schd_mode failed: %d", ret);
 754
 755         return ret;
 756 }
 757
 758 static int
 759 hns3_dcb_pri_tc_base_dwrr_cfg(struct hns3_hw *hw)
 760 {
 761         struct hns3_pg_info *pg_info;
 762         uint8_t dwrr;
 763         int ret, i;
 764
 765         for (i = 0; i < hw->dcb_info.num_tc; i++) {
 766                 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
 767                 dwrr = pg_info->tc_dwrr[i];
 768
 769                 ret = hns3_dcb_pri_weight_cfg(hw, i, dwrr);
 770                 if (ret) {
 771                         hns3_err(hw, "fail to send priority weight cmd: %d", i);
 772                         return ret;
 773                 }
 774
 775                 ret = hns3_dcb_qs_weight_cfg(hw, i, BW_MAX_PERCENT);
 776                 if (ret) {
 777                         hns3_err(hw, "fail to send qs_weight cmd: %d", i);
 778                         return ret;
 779                 }
 780         }
 781
 782         return 0;
 783 }
 784
 785 static int
 786 hns3_dcb_pri_dwrr_cfg(struct hns3_hw *hw)
 787 {
 788         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 789         struct hns3_pf *pf = &hns->pf;
 790         int ret;
 791
 792         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 793                 return -EINVAL;
 794
 795         ret = hns3_dcb_pri_tc_base_dwrr_cfg(hw);
 796         if (ret)
 797                 return ret;
 798
 799         if (!hns3_dev_dcb_supported(hw))
 800                 return 0;
 801
 802         ret = hns3_dcb_ets_tc_dwrr_cfg(hw);
 803         if (ret == -EOPNOTSUPP) {
 804                 hns3_warn(hw, "fw %08x does't support ets tc weight cmd",
 805                           hw->fw_version);
 806                 ret = 0;
 807         }
 808
 809         return ret;
 810 }
 811
 812 static int
 813 hns3_dcb_pg_dwrr_cfg(struct hns3_hw *hw)
 814 {
 815         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 816         struct hns3_pf *pf = &hns->pf;
 817         int ret, i;
 818
 819         /* Cfg pg schd */
 820         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 821                 return -EINVAL;
 822
 823         /* Cfg pg to prio */
 824         for (i = 0; i < hw->dcb_info.num_pg; i++) {
 825                 /* Cfg dwrr */
 826                 ret = hns3_dcb_pg_weight_cfg(hw, i, hw->dcb_info.pg_dwrr[i]);
 827                 if (ret)
 828                         return ret;
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int
 835 hns3_dcb_dwrr_cfg(struct hns3_hw *hw)
 836 {
 837         int ret;
 838
 839         ret = hns3_dcb_pg_dwrr_cfg(hw);
 840         if (ret) {
 841                 hns3_err(hw, "config pg_dwrr failed: %d", ret);
 842                 return ret;
 843         }
 844
 845         ret = hns3_dcb_pri_dwrr_cfg(hw);
 846         if (ret)
 847                 hns3_err(hw, "config pri_dwrr failed: %d", ret);
 848
 849         return ret;
 850 }
 851
 852 static int
 853 hns3_dcb_shaper_cfg(struct hns3_hw *hw)
 854 {
 855         int ret;
 856
 857         ret = hns3_dcb_port_shaper_cfg(hw);
 858         if (ret) {
 859                 hns3_err(hw, "config port shaper failed: %d", ret);
 860                 return ret;
 861         }
 862
 863         ret = hns3_dcb_pg_shaper_cfg(hw);
 864         if (ret) {
 865                 hns3_err(hw, "config pg shaper failed: %d", ret);
 866                 return ret;
 867         }
 868
 869         return hns3_dcb_pri_shaper_cfg(hw);
 870 }
 871
 872 static int
 873 hns3_q_to_qs_map_cfg(struct hns3_hw *hw, uint16_t q_id, uint16_t qs_id)
 874 {
 875         struct hns3_nq_to_qs_link_cmd *map;
 876         struct hns3_cmd_desc desc;
 877
 878         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_NQ_TO_QS_LINK, false);
 879
 880         map = (struct hns3_nq_to_qs_link_cmd *)desc.data;
 881
 882         map->nq_id = rte_cpu_to_le_16(q_id);
 883         map->qset_id = rte_cpu_to_le_16(qs_id | HNS3_DCB_Q_QS_LINK_VLD_MSK);
 884
 885         return hns3_cmd_send(hw, &desc, 1);
 886 }
 887
 888 static int
 889 hns3_q_to_qs_map(struct hns3_hw *hw)
 890 {
 891         struct hns3_tc_queue_info *tc_queue;
 892         uint16_t q_id;
 893         uint32_t i, j;
 894         int ret;
 895
 896         for (i = 0; i < hw->num_tc; i++) {
 897                 tc_queue = &hw->tc_queue[i];
 898                 for (j = 0; j < tc_queue->tqp_count; j++) {
 899                         q_id = tc_queue->tqp_offset + j;
 900                         ret = hns3_q_to_qs_map_cfg(hw, q_id, i);
 901                         if (ret)
 902                                 return ret;
 903                 }
 904         }
 905
 906         return 0;
 907 }
 908
 909 static int
 910 hns3_pri_q_qs_cfg(struct hns3_hw *hw)
 911 {
 912         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 913         struct hns3_pf *pf = &hns->pf;
 914         uint32_t i;
 915         int ret;
 916
 917         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
 918                 return -EINVAL;
 919
 920         /* Cfg qs -> pri mapping */
 921         for (i = 0; i < hw->num_tc; i++) {
 922                 ret = hns3_qs_to_pri_map_cfg(hw, i, i);
 923                 if (ret) {
 924                         hns3_err(hw, "qs_to_pri mapping fail: %d", ret);
 925                         return ret;
 926                 }
 927         }
 928
 929         /* Cfg q -> qs mapping */
 930         ret = hns3_q_to_qs_map(hw);
 931         if (ret)
 932                 hns3_err(hw, "nq_to_qs mapping fail: %d", ret);
 933
 934         return ret;
 935 }
 936
 937 static int
 938 hns3_dcb_map_cfg(struct hns3_hw *hw)
 939 {
 940         int ret;
 941
 942         ret = hns3_up_to_tc_map(hw);
 943         if (ret) {
 944                 hns3_err(hw, "up_to_tc mapping fail: %d", ret);
 945                 return ret;
 946         }
 947
 948         ret = hns3_pg_to_pri_map(hw);
 949         if (ret) {
 950                 hns3_err(hw, "pri_to_pg mapping fail: %d", ret);
 951                 return ret;
 952         }
 953
 954         return hns3_pri_q_qs_cfg(hw);
 955 }
 956
 957 static int
 958 hns3_dcb_schd_setup_hw(struct hns3_hw *hw)
 959 {
 960         int ret;
 961
 962         /* Cfg dcb mapping  */
 963         ret = hns3_dcb_map_cfg(hw);
 964         if (ret)
 965                 return ret;
 966
 967         /* Cfg dcb shaper */
 968         ret = hns3_dcb_shaper_cfg(hw);
 969         if (ret)
 970                 return ret;
 971
 972         /* Cfg dwrr */
 973         ret = hns3_dcb_dwrr_cfg(hw);
 974         if (ret)
 975                 return ret;
 976
 977         /* Cfg schd mode for each level schd */
 978         return hns3_dcb_schd_mode_cfg(hw);
 979 }
 980
 981 static int
 982 hns3_pause_param_cfg(struct hns3_hw *hw, const uint8_t *addr,
 983                      uint8_t pause_trans_gap, uint16_t pause_trans_time)
 984 {
 985         struct hns3_cfg_pause_param_cmd *pause_param;
 986         struct hns3_cmd_desc desc;
 987
 988         pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
 989
 990         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, false);
 991
 992         memcpy(pause_param->mac_addr, addr, RTE_ETHER_ADDR_LEN);
 993         memcpy(pause_param->mac_addr_extra, addr, RTE_ETHER_ADDR_LEN);
 994         pause_param->pause_trans_gap = pause_trans_gap;
 995         pause_param->pause_trans_time = rte_cpu_to_le_16(pause_trans_time);
 996
 997         return hns3_cmd_send(hw, &desc, 1);
 998 }
 999
1000 int
1001 hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr)
1002 {
1003         struct hns3_cfg_pause_param_cmd *pause_param;
1004         struct hns3_cmd_desc desc;
1005         uint16_t trans_time;
1006         uint8_t trans_gap;
1007         int ret;
1008
1009         pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
1010
1011         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, true);
1012
1013         ret = hns3_cmd_send(hw, &desc, 1);
1014         if (ret)
1015                 return ret;
1016
1017         trans_gap = pause_param->pause_trans_gap;
1018         trans_time = rte_le_to_cpu_16(pause_param->pause_trans_time);
1019
1020         return hns3_pause_param_cfg(hw, mac_addr, trans_gap, trans_time);
1021 }
1022
1023 static int
1024 hns3_pause_param_setup_hw(struct hns3_hw *hw, uint16_t pause_time)
1025 {
1026 #define PAUSE_TIME_DIV_BY       2
1027 #define PAUSE_TIME_MIN_VALUE    0x4
1028
1029         struct hns3_mac *mac = &hw->mac;
1030         uint8_t pause_trans_gap;
1031
1032         /*
1033          * Pause transmit gap must be less than "pause_time / 2", otherwise
1034          * the behavior of MAC is undefined.
1035          */
1036         if (pause_time > PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1037                 pause_trans_gap = HNS3_DEFAULT_PAUSE_TRANS_GAP;
1038         else if (pause_time >= PAUSE_TIME_MIN_VALUE &&
1039                  pause_time <= PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1040                 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1041         else {
1042                 hns3_warn(hw, "pause_time(%d) is adjusted to 4", pause_time);
1043                 pause_time = PAUSE_TIME_MIN_VALUE;
1044                 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1045         }
1046
1047         return hns3_pause_param_cfg(hw, mac->mac_addr,
1048                                     pause_trans_gap, pause_time);
1049 }
1050
1051 static int
1052 hns3_mac_pause_en_cfg(struct hns3_hw *hw, bool tx, bool rx)
1053 {
1054         struct hns3_cmd_desc desc;
1055
1056         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PAUSE_EN, false);
1057
1058         desc.data[0] = rte_cpu_to_le_32((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1059                 (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1060
1061         return hns3_cmd_send(hw, &desc, 1);
1062 }
1063
1064 static int
1065 hns3_pfc_pause_en_cfg(struct hns3_hw *hw, uint8_t pfc_bitmap, bool tx, bool rx)
1066 {
1067         struct hns3_cmd_desc desc;
1068         struct hns3_pfc_en_cmd *pfc = (struct hns3_pfc_en_cmd *)desc.data;
1069
1070         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PFC_PAUSE_EN, false);
1071
1072         pfc->tx_rx_en_bitmap = (uint8_t)((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1073                                         (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1074
1075         pfc->pri_en_bitmap = pfc_bitmap;
1076
1077         return hns3_cmd_send(hw, &desc, 1);
1078 }
1079
1080 static int
1081 hns3_qs_bp_cfg(struct hns3_hw *hw, uint8_t tc, uint8_t grp_id, uint32_t bit_map)
1082 {
1083         struct hns3_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
1084         struct hns3_cmd_desc desc;
1085
1086         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_BP_TO_QSET_MAPPING, false);
1087
1088         bp_to_qs_map_cmd = (struct hns3_bp_to_qs_map_cmd *)desc.data;
1089
1090         bp_to_qs_map_cmd->tc_id = tc;
1091         bp_to_qs_map_cmd->qs_group_id = grp_id;
1092         bp_to_qs_map_cmd->qs_bit_map = rte_cpu_to_le_32(bit_map);
1093
1094         return hns3_cmd_send(hw, &desc, 1);
1095 }
1096
1097 static void
1098 hns3_get_rx_tx_en_status(struct hns3_hw *hw, bool *tx_en, bool *rx_en)
1099 {
1100         switch (hw->current_mode) {
1101         case HNS3_FC_NONE:
1102                 *tx_en = false;
1103                 *rx_en = false;
1104                 break;
1105         case HNS3_FC_RX_PAUSE:
1106                 *tx_en = false;
1107                 *rx_en = true;
1108                 break;
1109         case HNS3_FC_TX_PAUSE:
1110                 *tx_en = true;
1111                 *rx_en = false;
1112                 break;
1113         case HNS3_FC_FULL:
1114                 *tx_en = true;
1115                 *rx_en = true;
1116                 break;
1117         default:
1118                 *tx_en = false;
1119                 *rx_en = false;
1120                 break;
1121         }
1122 }
1123
1124 static int
1125 hns3_mac_pause_setup_hw(struct hns3_hw *hw)
1126 {
1127         bool tx_en, rx_en;
1128
1129         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)
1130                 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1131         else {
1132                 tx_en = false;
1133                 rx_en = false;
1134         }
1135
1136         return hns3_mac_pause_en_cfg(hw, tx_en, rx_en);
1137 }
1138
1139 static int
1140 hns3_pfc_setup_hw(struct hns3_hw *hw)
1141 {
1142         bool tx_en, rx_en;
1143
1144         if (hw->current_fc_status == HNS3_FC_STATUS_PFC)
1145                 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1146         else {
1147                 tx_en = false;
1148                 rx_en = false;
1149         }
1150
1151         return hns3_pfc_pause_en_cfg(hw, hw->dcb_info.pfc_en, tx_en, rx_en);
1152 }
1153
1154 /*
1155  * Each Tc has a 1024 queue sets to backpress, it divides to
1156  * 32 group, each group contains 32 queue sets, which can be
1157  * represented by uint32_t bitmap.
1158  */
1159 static int
1160 hns3_bp_setup_hw(struct hns3_hw *hw, uint8_t tc)
1161 {
1162         uint32_t qs_bitmap;
1163         int ret;
1164         int i;
1165
1166         for (i = 0; i < HNS3_BP_GRP_NUM; i++) {
1167                 uint8_t grp, sub_grp;
1168                 qs_bitmap = 0;
1169
1170                 grp = hns3_get_field(tc, HNS3_BP_GRP_ID_M, HNS3_BP_GRP_ID_S);
1171                 sub_grp = hns3_get_field(tc, HNS3_BP_SUB_GRP_ID_M,
1172                                          HNS3_BP_SUB_GRP_ID_S);
1173                 if (i == grp)
1174                         qs_bitmap |= (1 << sub_grp);
1175
1176                 ret = hns3_qs_bp_cfg(hw, tc, i, qs_bitmap);
1177                 if (ret)
1178                         return ret;
1179         }
1180
1181         return 0;
1182 }
1183
1184 static int
1185 hns3_dcb_bp_setup(struct hns3_hw *hw)
1186 {
1187         int ret, i;
1188
1189         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1190                 ret = hns3_bp_setup_hw(hw, i);
1191                 if (ret)
1192                         return ret;
1193         }
1194
1195         return 0;
1196 }
1197
1198 static int
1199 hns3_dcb_pause_setup_hw(struct hns3_hw *hw)
1200 {
1201         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1202         struct hns3_pf *pf = &hns->pf;
1203         int ret;
1204
1205         ret = hns3_pause_param_setup_hw(hw, pf->pause_time);
1206         if (ret) {
1207                 hns3_err(hw, "Fail to set pause parameter. ret = %d", ret);
1208                 return ret;
1209         }
1210
1211         ret = hns3_mac_pause_setup_hw(hw);
1212         if (ret) {
1213                 hns3_err(hw, "Fail to setup MAC pause. ret = %d", ret);
1214                 return ret;
1215         }
1216
1217         /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1218         if (!hns3_dev_dcb_supported(hw))
1219                 return 0;
1220
1221         ret = hns3_pfc_setup_hw(hw);
1222         if (ret) {
1223                 hns3_err(hw, "config pfc failed! ret = %d", ret);
1224                 return ret;
1225         }
1226
1227         return hns3_dcb_bp_setup(hw);
1228 }
1229
1230 static uint8_t
1231 hns3_dcb_undrop_tc_map(struct hns3_hw *hw, uint8_t pfc_en)
1232 {
1233         uint8_t pfc_map = 0;
1234         uint8_t *prio_tc;
1235         uint8_t i, j;
1236
1237         prio_tc = hw->dcb_info.prio_tc;
1238         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1239                 for (j = 0; j < HNS3_MAX_USER_PRIO; j++) {
1240                         if (prio_tc[j] == i && pfc_en & BIT(j)) {
1241                                 pfc_map |= BIT(i);
1242                                 break;
1243                         }
1244                 }
1245         }
1246
1247         return pfc_map;
1248 }
1249
1250 static void
1251 hns3_dcb_cfg_validate(struct hns3_adapter *hns, uint8_t *tc, bool *changed)
1252 {
1253         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1254         struct hns3_hw *hw = &hns->hw;
1255         uint8_t max_tc = 0;
1256         uint8_t pfc_en;
1257         int i;
1258
1259         dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1260         for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1261                 if (dcb_rx_conf->dcb_tc[i] != hw->dcb_info.prio_tc[i])
1262                         *changed = true;
1263
1264                 if (dcb_rx_conf->dcb_tc[i] > max_tc)
1265                         max_tc = dcb_rx_conf->dcb_tc[i];
1266         }
1267         *tc = max_tc + 1;
1268         if (*tc != hw->dcb_info.num_tc)
1269                 *changed = true;
1270
1271         /*
1272          * We ensure that dcb information can be reconfigured
1273          * after the hns3_priority_flow_ctrl_set function called.
1274          */
1275         if (hw->current_mode != HNS3_FC_FULL)
1276                 *changed = true;
1277         pfc_en = RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1278         if (hw->dcb_info.pfc_en != pfc_en)
1279                 *changed = true;
1280 }
1281
1282 static void
1283 hns3_dcb_info_cfg(struct hns3_adapter *hns)
1284 {
1285         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1286         struct hns3_pf *pf = &hns->pf;
1287         struct hns3_hw *hw = &hns->hw;
1288         uint8_t tc_bw, bw_rest;
1289         uint8_t i, j;
1290
1291         dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1292         pf->local_max_tc = (uint8_t)dcb_rx_conf->nb_tcs;
1293         pf->pfc_max = (uint8_t)dcb_rx_conf->nb_tcs;
1294
1295         /* Config pg0 */
1296         memset(hw->dcb_info.pg_info, 0,
1297                sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
1298         hw->dcb_info.pg_dwrr[0] = BW_MAX_PERCENT;
1299         hw->dcb_info.pg_info[0].pg_id = 0;
1300         hw->dcb_info.pg_info[0].pg_sch_mode = HNS3_SCH_MODE_DWRR;
1301         hw->dcb_info.pg_info[0].bw_limit = HNS3_ETHER_MAX_RATE;
1302         hw->dcb_info.pg_info[0].tc_bit_map = hw->hw_tc_map;
1303
1304         /* Each tc has same bw for valid tc by default */
1305         tc_bw = BW_MAX_PERCENT / hw->dcb_info.num_tc;
1306         for (i = 0; i < hw->dcb_info.num_tc; i++)
1307                 hw->dcb_info.pg_info[0].tc_dwrr[i] = tc_bw;
1308         /* To ensure the sum of tc_dwrr is equal to 100 */
1309         bw_rest = BW_MAX_PERCENT % hw->dcb_info.num_tc;
1310         for (j = 0; j < bw_rest; j++)
1311                 hw->dcb_info.pg_info[0].tc_dwrr[j]++;
1312         for (; i < dcb_rx_conf->nb_tcs; i++)
1313                 hw->dcb_info.pg_info[0].tc_dwrr[i] = 0;
1314
1315         /* All tcs map to pg0 */
1316         memset(hw->dcb_info.tc_info, 0,
1317                sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
1318         for (i = 0; i < hw->dcb_info.num_tc; i++) {
1319                 hw->dcb_info.tc_info[i].tc_id = i;
1320                 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
1321                 hw->dcb_info.tc_info[i].pgid = 0;
1322                 hw->dcb_info.tc_info[i].bw_limit =
1323                                         hw->dcb_info.pg_info[0].bw_limit;
1324         }
1325
1326         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
1327                 hw->dcb_info.prio_tc[i] = dcb_rx_conf->dcb_tc[i];
1328
1329         hns3_dcb_update_tc_queue_mapping(hw, hw->data->nb_rx_queues,
1330                                          hw->data->nb_tx_queues);
1331 }
1332
1333 static int
1334 hns3_dcb_info_update(struct hns3_adapter *hns, uint8_t num_tc)
1335 {
1336         struct hns3_pf *pf = &hns->pf;
1337         struct hns3_hw *hw = &hns->hw;
1338         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1339         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1340         uint8_t bit_map = 0;
1341         uint8_t i;
1342
1343         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1344             hw->dcb_info.num_pg != 1)
1345                 return -EINVAL;
1346
1347         if (nb_rx_q < num_tc) {
1348                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1349                          nb_rx_q, num_tc);
1350                 return -EINVAL;
1351         }
1352
1353         if (nb_tx_q < num_tc) {
1354                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1355                          nb_tx_q, num_tc);
1356                 return -EINVAL;
1357         }
1358
1359         /* Currently not support uncontinuous tc */
1360         hw->dcb_info.num_tc = num_tc;
1361         for (i = 0; i < hw->dcb_info.num_tc; i++)
1362                 bit_map |= BIT(i);
1363
1364         if (!bit_map) {
1365                 bit_map = 1;
1366                 hw->dcb_info.num_tc = 1;
1367         }
1368         hw->hw_tc_map = bit_map;
1369         hns3_dcb_info_cfg(hns);
1370
1371         return 0;
1372 }
1373
1374 static int
1375 hns3_dcb_hw_configure(struct hns3_adapter *hns)
1376 {
1377         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1378         struct hns3_pf *pf = &hns->pf;
1379         struct hns3_hw *hw = &hns->hw;
1380         enum hns3_fc_status fc_status = hw->current_fc_status;
1381         enum hns3_fc_mode current_mode = hw->current_mode;
1382         uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1383         int ret, status;
1384
1385         if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1386             pf->tx_sch_mode != HNS3_FLAG_VNET_BASE_SCH_MODE)
1387                 return -ENOTSUP;
1388
1389         ret = hns3_dcb_schd_setup_hw(hw);
1390         if (ret) {
1391                 hns3_err(hw, "dcb schdule configure failed! ret = %d", ret);
1392                 return ret;
1393         }
1394
1395         if (hw->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
1396                 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1397                 if (dcb_rx_conf->nb_tcs == 0)
1398                         hw->dcb_info.pfc_en = 1; /* tc0 only */
1399                 else
1400                         hw->dcb_info.pfc_en =
1401                         RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1402
1403                 hw->dcb_info.hw_pfc_map =
1404                                 hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1405
1406                 ret = hns3_buffer_alloc(hw);
1407                 if (ret)
1408                         return ret;
1409
1410                 hw->current_fc_status = HNS3_FC_STATUS_PFC;
1411                 hw->current_mode = HNS3_FC_FULL;
1412                 ret = hns3_dcb_pause_setup_hw(hw);
1413                 if (ret) {
1414                         hns3_err(hw, "setup pfc failed! ret = %d", ret);
1415                         goto pfc_setup_fail;
1416                 }
1417         } else {
1418                 /*
1419                  * Although dcb_capability_en is lack of ETH_DCB_PFC_SUPPORT
1420                  * flag, the DCB information is configured, such as tc numbers.
1421                  * Therefore, refreshing the allocation of packet buffer is
1422                  * necessary.
1423                  */
1424                 ret = hns3_buffer_alloc(hw);
1425                 if (ret)
1426                         return ret;
1427         }
1428
1429         return 0;
1430
1431 pfc_setup_fail:
1432         hw->current_mode = current_mode;
1433         hw->current_fc_status = fc_status;
1434         hw->dcb_info.hw_pfc_map = hw_pfc_map;
1435         status = hns3_buffer_alloc(hw);
1436         if (status)
1437                 hns3_err(hw, "recover packet buffer fail! status = %d", status);
1438
1439         return ret;
1440 }
1441
1442 /*
1443  * hns3_dcb_configure - setup dcb related config
1444  * @hns: pointer to hns3 adapter
1445  * Returns 0 on success, negative value on failure.
1446  */
1447 int
1448 hns3_dcb_configure(struct hns3_adapter *hns)
1449 {
1450         struct hns3_hw *hw = &hns->hw;
1451         bool map_changed = false;
1452         uint8_t num_tc = 0;
1453         int ret;
1454
1455         hns3_dcb_cfg_validate(hns, &num_tc, &map_changed);
1456         if (map_changed || rte_atomic16_read(&hw->reset.resetting)) {
1457                 ret = hns3_dcb_info_update(hns, num_tc);
1458                 if (ret) {
1459                         hns3_err(hw, "dcb info update failed: %d", ret);
1460                         return ret;
1461                 }
1462
1463                 ret = hns3_dcb_hw_configure(hns);
1464                 if (ret) {
1465                         hns3_err(hw, "dcb sw configure failed: %d", ret);
1466                         return ret;
1467                 }
1468         }
1469
1470         return 0;
1471 }
1472
1473 int
1474 hns3_dcb_init_hw(struct hns3_hw *hw)
1475 {
1476         int ret;
1477
1478         ret = hns3_dcb_schd_setup_hw(hw);
1479         if (ret) {
1480                 hns3_err(hw, "dcb schedule setup failed: %d", ret);
1481                 return ret;
1482         }
1483
1484         ret = hns3_dcb_pause_setup_hw(hw);
1485         if (ret)
1486                 hns3_err(hw, "PAUSE setup failed: %d", ret);
1487
1488         return ret;
1489 }
1490
1491 int
1492 hns3_dcb_init(struct hns3_hw *hw)
1493 {
1494         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1495         struct hns3_pf *pf = &hns->pf;
1496         int ret;
1497
1498         PMD_INIT_FUNC_TRACE();
1499
1500         /*
1501          * According to the 'adapter_state' identifier, the following branch
1502          * is only executed to initialize default configurations of dcb during
1503          * the initializing driver process. Due to driver saving dcb-related
1504          * information before reset triggered, the reinit dev stage of the
1505          * reset process can not access to the branch, or those information
1506          * will be changed.
1507          */
1508         if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
1509                 hw->requested_mode = HNS3_FC_NONE;
1510                 hw->current_mode = hw->requested_mode;
1511                 pf->pause_time = HNS3_DEFAULT_PAUSE_TRANS_TIME;
1512                 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1513
1514                 ret = hns3_dcb_info_init(hw);
1515                 if (ret) {
1516                         hns3_err(hw, "dcb info init failed: %d", ret);
1517                         return ret;
1518                 }
1519                 hns3_dcb_update_tc_queue_mapping(hw, hw->tqps_num,
1520                                                  hw->tqps_num);
1521         }
1522
1523         /*
1524          * DCB hardware will be configured by following the function during
1525          * the initializing driver process and the reset process. However,
1526          * driver will restore directly configurations of dcb hardware based
1527          * on dcb-related information soft maintained when driver
1528          * initialization has finished and reset is coming.
1529          */
1530         ret = hns3_dcb_init_hw(hw);
1531         if (ret) {
1532                 hns3_err(hw, "dcb init hardware failed: %d", ret);
1533                 return ret;
1534         }
1535
1536         return 0;
1537 }
1538
1539 static int
1540 hns3_update_queue_map_configure(struct hns3_adapter *hns)
1541 {
1542         struct hns3_hw *hw = &hns->hw;
1543         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1544         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1545         int ret;
1546
1547         hns3_dcb_update_tc_queue_mapping(hw, nb_rx_q, nb_tx_q);
1548         ret = hns3_q_to_qs_map(hw);
1549         if (ret)
1550                 hns3_err(hw, "failed to map nq to qs! ret = %d", ret);
1551
1552         return ret;
1553 }
1554
1555 int
1556 hns3_dcb_cfg_update(struct hns3_adapter *hns)
1557 {
1558         struct hns3_hw *hw = &hns->hw;
1559         enum rte_eth_rx_mq_mode mq_mode = hw->data->dev_conf.rxmode.mq_mode;
1560         int ret;
1561
1562         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
1563                 ret = hns3_dcb_configure(hns);
1564                 if (ret)
1565                         hns3_err(hw, "Failed to config dcb: %d", ret);
1566         } else {
1567                 /*
1568                  * Update queue map without PFC configuration,
1569                  * due to queues reconfigured by user.
1570                  */
1571                 ret = hns3_update_queue_map_configure(hns);
1572                 if (ret)
1573                         hns3_err(hw,
1574                                  "Failed to update queue mapping configure: %d",
1575                                  ret);
1576         }
1577
1578         return ret;
1579 }
1580
1581 /*
1582  * hns3_dcb_pfc_enable - Enable priority flow control
1583  * @dev: pointer to ethernet device
1584  *
1585  * Configures the pfc settings for one porority.
1586  */
1587 int
1588 hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
1589 {
1590         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1591         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1592         enum hns3_fc_status fc_status = hw->current_fc_status;
1593         enum hns3_fc_mode current_mode = hw->current_mode;
1594         uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1595         uint8_t pfc_en = hw->dcb_info.pfc_en;
1596         uint8_t priority = pfc_conf->priority;
1597         uint16_t pause_time = pf->pause_time;
1598         int ret, status;
1599
1600         pf->pause_time = pfc_conf->fc.pause_time;
1601         hw->current_mode = hw->requested_mode;
1602         hw->current_fc_status = HNS3_FC_STATUS_PFC;
1603         hw->dcb_info.pfc_en |= BIT(priority);
1604         hw->dcb_info.hw_pfc_map =
1605                         hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1606         ret = hns3_buffer_alloc(hw);
1607         if (ret)
1608                 goto pfc_setup_fail;
1609
1610         /*
1611          * The flow control mode of all UPs will be changed based on
1612          * current_mode coming from user.
1613          */
1614         ret = hns3_dcb_pause_setup_hw(hw);
1615         if (ret) {
1616                 hns3_err(hw, "enable pfc failed! ret = %d", ret);
1617                 goto pfc_setup_fail;
1618         }
1619
1620         return 0;
1621
1622 pfc_setup_fail:
1623         hw->current_mode = current_mode;
1624         hw->current_fc_status = fc_status;
1625         pf->pause_time = pause_time;
1626         hw->dcb_info.pfc_en = pfc_en;
1627         hw->dcb_info.hw_pfc_map = hw_pfc_map;
1628         status = hns3_buffer_alloc(hw);
1629         if (status)
1630                 hns3_err(hw, "recover packet buffer fail: %d", status);
1631
1632         return ret;
1633 }
1634
1635 /*
1636  * hns3_fc_enable - Enable MAC pause
1637  * @dev: pointer to ethernet device
1638  *
1639  * Configures the MAC pause settings.
1640  */
1641 int
1642 hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1643 {
1644         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1646         enum hns3_fc_status fc_status = hw->current_fc_status;
1647         enum hns3_fc_mode current_mode = hw->current_mode;
1648         uint16_t pause_time = pf->pause_time;
1649         int ret;
1650
1651         pf->pause_time = fc_conf->pause_time;
1652         hw->current_mode = hw->requested_mode;
1653
1654         /*
1655          * In fact, current_fc_status is HNS3_FC_STATUS_NONE when mode
1656          * of flow control is configured to be HNS3_FC_NONE.
1657          */
1658         if (hw->current_mode == HNS3_FC_NONE)
1659                 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1660         else
1661                 hw->current_fc_status = HNS3_FC_STATUS_MAC_PAUSE;
1662
1663         ret = hns3_dcb_pause_setup_hw(hw);
1664         if (ret) {
1665                 hns3_err(hw, "enable MAC Pause failed! ret = %d", ret);
1666                 goto setup_fc_fail;
1667         }
1668
1669         return 0;
1670
1671 setup_fc_fail:
1672         hw->current_mode = current_mode;
1673         hw->current_fc_status = fc_status;
1674         pf->pause_time = pause_time;
1675
1676         return ret;
1677 }