1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
6 #include <rte_ethdev.h>
9 #include "hns3_ethdev.h"
12 #define HNS3_SHAPER_BS_U_DEF 5
13 #define HNS3_SHAPER_BS_S_DEF 20
14 #define BW_MAX_PERCENT 100
17 * hns3_shaper_para_calc: calculate ir parameter for the shaper
18 * @ir: Rate to be config, its unit is Mbps
19 * @shaper_level: the shaper level. eg: port, pg, priority, queueset
20 * @shaper_para: shaper parameter of IR shaper
24 * IR_b * (2 ^ IR_u) * 8
25 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps)
28 * @return: 0: calculate sucessful, negative: fail
31 hns3_shaper_para_calc(struct hns3_hw *hw, uint32_t ir, uint8_t shaper_level,
32 struct hns3_shaper_parameter *shaper_para)
34 #define SHAPER_DEFAULT_IR_B 126
35 #define DIVISOR_CLK (1000 * 8)
36 #define DIVISOR_IR_B_126 (126 * DIVISOR_CLK)
38 const uint16_t tick_array[HNS3_SHAPER_LVL_CNT] = {
39 6 * 256, /* Prioriy level */
40 6 * 32, /* Prioriy group level */
41 6 * 8, /* Port level */
42 6 * 256 /* Qset level */
44 uint8_t ir_u_calc = 0;
45 uint8_t ir_s_calc = 0;
51 if (shaper_level >= HNS3_SHAPER_LVL_CNT) {
53 "shaper_level(%u) is greater than HNS3_SHAPER_LVL_CNT(%d)",
54 shaper_level, HNS3_SHAPER_LVL_CNT);
58 if (ir > hw->max_tm_rate) {
59 hns3_err(hw, "rate(%u) exceeds the max rate(%u) driver "
60 "supported.", ir, hw->max_tm_rate);
64 tick = tick_array[shaper_level];
67 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
68 * the formula is changed to:
70 * ir_calc = ---------------- * 1000
73 ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
76 shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
77 } else if (ir_calc > ir) {
78 /* Increasing the denominator to select ir_s value */
79 while (ir_calc >= ir && ir) {
81 ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
84 shaper_para->ir_b = (ir * tick * (1 << ir_s_calc) +
85 (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
88 * Increasing the numerator to select ir_u value. ir_u_calc will
89 * get maximum value when ir_calc is minimum and ir is maximum.
90 * ir_calc gets minimum value when tick is the maximum value.
91 * At the same time, value of ir_u_calc can only be increased up
92 * to eight after the while loop if the value of ir is equal
98 numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
99 ir_calc = (numerator + (tick >> 1)) / tick;
100 } while (ir_calc < ir);
103 shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
108 * The maximum value of ir_u_calc in this branch is
109 * seven in all cases. Thus, value of denominator can
112 denominator = DIVISOR_CLK * (1 << ir_u_calc);
114 (ir * tick + (denominator >> 1)) / denominator;
118 shaper_para->ir_u = ir_u_calc;
119 shaper_para->ir_s = ir_s_calc;
125 hns3_fill_pri_array(struct hns3_hw *hw, uint8_t *pri, uint8_t pri_id)
127 #define HNS3_HALF_BYTE_BIT_OFFSET 4
128 uint8_t tc = hw->dcb_info.prio_tc[pri_id];
130 if (tc >= hw->dcb_info.num_tc)
134 * The register for priority has four bytes, the first bytes includes
135 * priority0 and priority1, the higher 4bit stands for priority1
136 * while the lower 4bit stands for priority0, as below:
137 * first byte: | pri_1 | pri_0 |
138 * second byte: | pri_3 | pri_2 |
139 * third byte: | pri_5 | pri_4 |
140 * fourth byte: | pri_7 | pri_6 |
142 pri[pri_id >> 1] |= tc << ((pri_id & 1) * HNS3_HALF_BYTE_BIT_OFFSET);
148 hns3_up_to_tc_map(struct hns3_hw *hw)
150 struct hns3_cmd_desc desc;
151 uint8_t *pri = (uint8_t *)desc.data;
155 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PRI_TO_TC_MAPPING, false);
157 for (pri_id = 0; pri_id < HNS3_MAX_USER_PRIO; pri_id++) {
158 ret = hns3_fill_pri_array(hw, pri, pri_id);
163 return hns3_cmd_send(hw, &desc, 1);
167 hns3_pg_to_pri_map_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t pri_bit_map)
169 struct hns3_pg_to_pri_link_cmd *map;
170 struct hns3_cmd_desc desc;
172 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_TO_PRI_LINK, false);
174 map = (struct hns3_pg_to_pri_link_cmd *)desc.data;
177 map->pri_bit_map = pri_bit_map;
179 return hns3_cmd_send(hw, &desc, 1);
183 hns3_pg_to_pri_map(struct hns3_hw *hw)
185 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
186 struct hns3_pf *pf = &hns->pf;
187 struct hns3_pg_info *pg_info;
190 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
193 for (i = 0; i < hw->dcb_info.num_pg; i++) {
194 /* Cfg pg to priority mapping */
195 pg_info = &hw->dcb_info.pg_info[i];
196 ret = hns3_pg_to_pri_map_cfg(hw, i, pg_info->tc_bit_map);
205 hns3_qs_to_pri_map_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t pri)
207 struct hns3_qs_to_pri_link_cmd *map;
208 struct hns3_cmd_desc desc;
210 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_TO_PRI_LINK, false);
212 map = (struct hns3_qs_to_pri_link_cmd *)desc.data;
214 map->qs_id = rte_cpu_to_le_16(qs_id);
216 map->link_vld = HNS3_DCB_QS_PRI_LINK_VLD_MSK;
218 return hns3_cmd_send(hw, &desc, 1);
222 hns3_dcb_qs_weight_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t dwrr)
224 struct hns3_qs_weight_cmd *weight;
225 struct hns3_cmd_desc desc;
227 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_WEIGHT, false);
229 weight = (struct hns3_qs_weight_cmd *)desc.data;
231 weight->qs_id = rte_cpu_to_le_16(qs_id);
234 return hns3_cmd_send(hw, &desc, 1);
238 hns3_dcb_ets_tc_dwrr_cfg(struct hns3_hw *hw)
240 #define DEFAULT_TC_WEIGHT 1
241 #define DEFAULT_TC_OFFSET 14
242 struct hns3_ets_tc_weight_cmd *ets_weight;
243 struct hns3_cmd_desc desc;
246 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_ETS_TC_WEIGHT, false);
247 ets_weight = (struct hns3_ets_tc_weight_cmd *)desc.data;
249 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
250 struct hns3_pg_info *pg_info;
252 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
254 if (!(hw->hw_tc_map & BIT(i)))
257 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
258 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
261 ets_weight->weight_offset = DEFAULT_TC_OFFSET;
263 return hns3_cmd_send(hw, &desc, 1);
267 hns3_dcb_pri_weight_cfg(struct hns3_hw *hw, uint8_t pri_id, uint8_t dwrr)
269 struct hns3_priority_weight_cmd *weight;
270 struct hns3_cmd_desc desc;
272 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_WEIGHT, false);
274 weight = (struct hns3_priority_weight_cmd *)desc.data;
276 weight->pri_id = pri_id;
279 return hns3_cmd_send(hw, &desc, 1);
283 hns3_dcb_pg_weight_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t dwrr)
285 struct hns3_pg_weight_cmd *weight;
286 struct hns3_cmd_desc desc;
288 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_WEIGHT, false);
290 weight = (struct hns3_pg_weight_cmd *)desc.data;
292 weight->pg_id = pg_id;
295 return hns3_cmd_send(hw, &desc, 1);
298 hns3_dcb_pg_schd_mode_cfg(struct hns3_hw *hw, uint8_t pg_id)
300 struct hns3_cmd_desc desc;
302 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_SCH_MODE_CFG, false);
304 if (hw->dcb_info.pg_info[pg_id].pg_sch_mode == HNS3_SCH_MODE_DWRR)
305 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
309 desc.data[0] = rte_cpu_to_le_32(pg_id);
311 return hns3_cmd_send(hw, &desc, 1);
315 hns3_dcb_get_shapping_para(uint8_t ir_b, uint8_t ir_u, uint8_t ir_s,
316 uint8_t bs_b, uint8_t bs_s)
318 uint32_t shapping_para = 0;
320 /* If ir_b is zero it means IR is 0Mbps, return zero of shapping_para */
322 return shapping_para;
324 hns3_dcb_set_field(shapping_para, IR_B, ir_b);
325 hns3_dcb_set_field(shapping_para, IR_U, ir_u);
326 hns3_dcb_set_field(shapping_para, IR_S, ir_s);
327 hns3_dcb_set_field(shapping_para, BS_B, bs_b);
328 hns3_dcb_set_field(shapping_para, BS_S, bs_s);
330 return shapping_para;
334 hns3_dcb_port_shaper_cfg(struct hns3_hw *hw)
336 struct hns3_port_shapping_cmd *shap_cfg_cmd;
337 struct hns3_shaper_parameter shaper_parameter;
338 uint32_t shapping_para;
339 uint32_t ir_u, ir_b, ir_s;
340 struct hns3_cmd_desc desc;
343 ret = hns3_shaper_para_calc(hw, hw->mac.link_speed,
344 HNS3_SHAPER_LVL_PORT, &shaper_parameter);
346 hns3_err(hw, "calculate shaper parameter failed: %d", ret);
350 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PORT_SHAPPING, false);
351 shap_cfg_cmd = (struct hns3_port_shapping_cmd *)desc.data;
353 ir_b = shaper_parameter.ir_b;
354 ir_u = shaper_parameter.ir_u;
355 ir_s = shaper_parameter.ir_s;
356 shapping_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
357 HNS3_SHAPER_BS_U_DEF,
358 HNS3_SHAPER_BS_S_DEF);
360 shap_cfg_cmd->port_shapping_para = rte_cpu_to_le_32(shapping_para);
363 * Configure the port_rate and set bit HNS3_TM_RATE_VLD_B of flag
364 * field in hns3_port_shapping_cmd to require firmware to recalculate
365 * shapping parameters. And whether the parameters are recalculated
366 * depends on the firmware version. But driver still needs to
367 * calculate it and configure to firmware for better compatibility.
369 shap_cfg_cmd->port_rate = rte_cpu_to_le_32(hw->mac.link_speed);
370 hns3_set_bit(shap_cfg_cmd->flag, HNS3_TM_RATE_VLD_B, 1);
372 return hns3_cmd_send(hw, &desc, 1);
376 hns3_dcb_pg_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
377 uint8_t pg_id, uint32_t shapping_para, uint32_t rate)
379 struct hns3_pg_shapping_cmd *shap_cfg_cmd;
380 enum hns3_opcode_type opcode;
381 struct hns3_cmd_desc desc;
383 opcode = bucket ? HNS3_OPC_TM_PG_P_SHAPPING :
384 HNS3_OPC_TM_PG_C_SHAPPING;
385 hns3_cmd_setup_basic_desc(&desc, opcode, false);
387 shap_cfg_cmd = (struct hns3_pg_shapping_cmd *)desc.data;
389 shap_cfg_cmd->pg_id = pg_id;
391 shap_cfg_cmd->pg_shapping_para = rte_cpu_to_le_32(shapping_para);
394 * Configure the pg_rate and set bit HNS3_TM_RATE_VLD_B of flag field in
395 * hns3_pg_shapping_cmd to require firmware to recalculate shapping
396 * parameters. And whether parameters are recalculated depends on
397 * the firmware version. But driver still needs to calculate it and
398 * configure to firmware for better compatibility.
400 shap_cfg_cmd->pg_rate = rte_cpu_to_le_32(rate);
401 hns3_set_bit(shap_cfg_cmd->flag, HNS3_TM_RATE_VLD_B, 1);
403 return hns3_cmd_send(hw, &desc, 1);
407 hns3_pg_shaper_rate_cfg(struct hns3_hw *hw, uint8_t pg_id, uint32_t rate)
409 struct hns3_shaper_parameter shaper_parameter;
410 uint32_t ir_u, ir_b, ir_s;
411 uint32_t shaper_para;
414 /* Calc shaper para */
415 ret = hns3_shaper_para_calc(hw, rate, HNS3_SHAPER_LVL_PG,
418 hns3_err(hw, "calculate shaper parameter fail, ret = %d.",
423 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
424 HNS3_SHAPER_BS_U_DEF,
425 HNS3_SHAPER_BS_S_DEF);
427 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, pg_id,
430 hns3_err(hw, "config PG CIR shaper parameter fail, ret = %d.",
435 ir_b = shaper_parameter.ir_b;
436 ir_u = shaper_parameter.ir_u;
437 ir_s = shaper_parameter.ir_s;
438 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
439 HNS3_SHAPER_BS_U_DEF,
440 HNS3_SHAPER_BS_S_DEF);
442 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, pg_id,
445 hns3_err(hw, "config PG PIR shaper parameter fail, ret = %d.",
454 hns3_dcb_pg_shaper_cfg(struct hns3_hw *hw)
456 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
462 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
466 for (i = 0; i < hw->dcb_info.num_pg; i++) {
467 rate = hw->dcb_info.pg_info[i].bw_limit;
468 ret = hns3_pg_shaper_rate_cfg(hw, i, rate);
477 hns3_dcb_qs_schd_mode_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t mode)
479 struct hns3_cmd_desc desc;
481 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_SCH_MODE_CFG, false);
483 if (mode == HNS3_SCH_MODE_DWRR)
484 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
488 desc.data[0] = rte_cpu_to_le_32(qs_id);
490 return hns3_cmd_send(hw, &desc, 1);
494 hns3_dcb_pri_schd_mode_cfg(struct hns3_hw *hw, uint8_t pri_id)
496 struct hns3_cmd_desc desc;
498 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_SCH_MODE_CFG, false);
500 if (hw->dcb_info.tc_info[pri_id].tc_sch_mode == HNS3_SCH_MODE_DWRR)
501 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
505 desc.data[0] = rte_cpu_to_le_32(pri_id);
507 return hns3_cmd_send(hw, &desc, 1);
511 hns3_dcb_pri_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
512 uint8_t pri_id, uint32_t shapping_para, uint32_t rate)
514 struct hns3_pri_shapping_cmd *shap_cfg_cmd;
515 enum hns3_opcode_type opcode;
516 struct hns3_cmd_desc desc;
518 opcode = bucket ? HNS3_OPC_TM_PRI_P_SHAPPING :
519 HNS3_OPC_TM_PRI_C_SHAPPING;
521 hns3_cmd_setup_basic_desc(&desc, opcode, false);
523 shap_cfg_cmd = (struct hns3_pri_shapping_cmd *)desc.data;
525 shap_cfg_cmd->pri_id = pri_id;
527 shap_cfg_cmd->pri_shapping_para = rte_cpu_to_le_32(shapping_para);
530 * Configure the pri_rate and set bit HNS3_TM_RATE_VLD_B of flag
531 * field in hns3_pri_shapping_cmd to require firmware to recalculate
532 * shapping parameters. And whether the parameters are recalculated
533 * depends on the firmware version. But driver still needs to
534 * calculate it and configure to firmware for better compatibility.
536 shap_cfg_cmd->pri_rate = rte_cpu_to_le_32(rate);
537 hns3_set_bit(shap_cfg_cmd->flag, HNS3_TM_RATE_VLD_B, 1);
539 return hns3_cmd_send(hw, &desc, 1);
543 hns3_pri_shaper_rate_cfg(struct hns3_hw *hw, uint8_t tc_no, uint32_t rate)
545 struct hns3_shaper_parameter shaper_parameter;
546 uint32_t ir_u, ir_b, ir_s;
547 uint32_t shaper_para;
550 ret = hns3_shaper_para_calc(hw, rate, HNS3_SHAPER_LVL_PRI,
553 hns3_err(hw, "calculate shaper parameter failed: %d.",
558 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
559 HNS3_SHAPER_BS_U_DEF,
560 HNS3_SHAPER_BS_S_DEF);
562 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, tc_no,
566 "config priority CIR shaper parameter failed: %d.",
571 ir_b = shaper_parameter.ir_b;
572 ir_u = shaper_parameter.ir_u;
573 ir_s = shaper_parameter.ir_s;
574 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
575 HNS3_SHAPER_BS_U_DEF,
576 HNS3_SHAPER_BS_S_DEF);
578 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, tc_no,
582 "config priority PIR shaper parameter failed: %d.",
591 hns3_dcb_pri_shaper_cfg(struct hns3_hw *hw)
593 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
598 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
601 for (i = 0; i < hw->dcb_info.num_tc; i++) {
602 rate = hw->dcb_info.tc_info[i].bw_limit;
603 ret = hns3_pri_shaper_rate_cfg(hw, i, rate);
605 hns3_err(hw, "config pri shaper failed: %d.", ret);
614 hns3_set_rss_size(struct hns3_hw *hw, uint16_t nb_rx_q)
616 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
617 uint16_t rx_qnum_per_tc;
618 uint16_t used_rx_queues;
621 rx_qnum_per_tc = nb_rx_q / hw->num_tc;
622 if (rx_qnum_per_tc > hw->rss_size_max) {
623 hns3_err(hw, "rx queue number of per tc (%u) is greater than "
624 "value (%u) hardware supported.",
625 rx_qnum_per_tc, hw->rss_size_max);
629 used_rx_queues = hw->num_tc * rx_qnum_per_tc;
630 if (used_rx_queues != nb_rx_q) {
631 hns3_err(hw, "rx queue number (%u) configured must be an "
632 "integral multiple of valid tc number (%u).",
633 nb_rx_q, hw->num_tc);
636 hw->alloc_rss_size = rx_qnum_per_tc;
637 hw->used_rx_queues = used_rx_queues;
640 * When rss size is changed, we need to update rss redirection table
641 * maintained by driver. Besides, during the entire reset process, we
642 * need to ensure that the rss table information are not overwritten
643 * and configured directly to the hardware in the RESET_STAGE_RESTORE
644 * stage of the reset process.
646 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
647 for (i = 0; i < hw->rss_ind_tbl_size; i++)
648 rss_cfg->rss_indirection_tbl[i] =
649 i % hw->alloc_rss_size;
656 hns3_tc_queue_mapping_cfg(struct hns3_hw *hw, uint16_t nb_tx_q)
658 struct hns3_tc_queue_info *tc_queue;
659 uint16_t used_tx_queues;
660 uint16_t tx_qnum_per_tc;
663 tx_qnum_per_tc = nb_tx_q / hw->num_tc;
664 used_tx_queues = hw->num_tc * tx_qnum_per_tc;
665 if (used_tx_queues != nb_tx_q) {
666 hns3_err(hw, "tx queue number (%u) configured must be an "
667 "integral multiple of valid tc number (%u).",
668 nb_tx_q, hw->num_tc);
672 hw->used_tx_queues = used_tx_queues;
673 hw->tx_qnum_per_tc = tx_qnum_per_tc;
674 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
675 tc_queue = &hw->tc_queue[i];
676 if (hw->hw_tc_map & BIT(i) && i < hw->num_tc) {
677 tc_queue->enable = true;
678 tc_queue->tqp_offset = i * hw->tx_qnum_per_tc;
679 tc_queue->tqp_count = hw->tx_qnum_per_tc;
682 /* Set to default queue if TC is disable */
683 tc_queue->enable = false;
684 tc_queue->tqp_offset = 0;
685 tc_queue->tqp_count = 0;
694 hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no)
696 struct hns3_tc_queue_info *tc_queue;
699 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
700 tc_queue = &hw->tc_queue[i];
701 if (!tc_queue->enable)
704 if (txq_no >= tc_queue->tqp_offset &&
705 txq_no < tc_queue->tqp_offset + tc_queue->tqp_count)
709 /* return TC0 in default case */
714 hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q, uint16_t nb_tx_q)
718 ret = hns3_set_rss_size(hw, nb_rx_q);
722 return hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
726 hns3_dcb_update_tc_queue_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
729 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
730 struct hns3_pf *pf = &hns->pf;
733 hw->num_tc = hw->dcb_info.num_tc;
734 ret = hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
739 memcpy(pf->prio_tc, hw->dcb_info.prio_tc, HNS3_MAX_USER_PRIO);
745 hns3_dcb_info_init(struct hns3_hw *hw)
747 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
748 struct hns3_pf *pf = &hns->pf;
751 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
752 hw->dcb_info.num_pg != 1)
755 /* Initializing PG information */
756 memset(hw->dcb_info.pg_info, 0,
757 sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
758 for (i = 0; i < hw->dcb_info.num_pg; i++) {
759 hw->dcb_info.pg_dwrr[i] = i ? 0 : BW_MAX_PERCENT;
760 hw->dcb_info.pg_info[i].pg_id = i;
761 hw->dcb_info.pg_info[i].pg_sch_mode = HNS3_SCH_MODE_DWRR;
762 hw->dcb_info.pg_info[i].bw_limit = hw->max_tm_rate;
767 hw->dcb_info.pg_info[i].tc_bit_map = hw->hw_tc_map;
768 for (k = 0; k < hw->dcb_info.num_tc; k++)
769 hw->dcb_info.pg_info[i].tc_dwrr[k] = BW_MAX_PERCENT;
772 /* All UPs mapping to TC0 */
773 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
774 hw->dcb_info.prio_tc[i] = 0;
776 /* Initializing tc information */
777 memset(hw->dcb_info.tc_info, 0,
778 sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
779 for (i = 0; i < hw->dcb_info.num_tc; i++) {
780 hw->dcb_info.tc_info[i].tc_id = i;
781 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
782 hw->dcb_info.tc_info[i].pgid = 0;
783 hw->dcb_info.tc_info[i].bw_limit =
784 hw->dcb_info.pg_info[0].bw_limit;
791 hns3_dcb_lvl2_schd_mode_cfg(struct hns3_hw *hw)
793 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
794 struct hns3_pf *pf = &hns->pf;
797 /* Only being config on TC-Based scheduler mode */
798 if (pf->tx_sch_mode == HNS3_FLAG_VNET_BASE_SCH_MODE)
801 for (i = 0; i < hw->dcb_info.num_pg; i++) {
802 ret = hns3_dcb_pg_schd_mode_cfg(hw, i);
811 hns3_dcb_lvl34_schd_mode_cfg(struct hns3_hw *hw)
813 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
814 struct hns3_pf *pf = &hns->pf;
818 if (pf->tx_sch_mode == HNS3_FLAG_TC_BASE_SCH_MODE) {
819 for (i = 0; i < hw->dcb_info.num_tc; i++) {
820 ret = hns3_dcb_pri_schd_mode_cfg(hw, i);
824 ret = hns3_dcb_qs_schd_mode_cfg(hw, i,
835 hns3_dcb_schd_mode_cfg(struct hns3_hw *hw)
839 ret = hns3_dcb_lvl2_schd_mode_cfg(hw);
841 hns3_err(hw, "config lvl2_schd_mode failed: %d", ret);
845 ret = hns3_dcb_lvl34_schd_mode_cfg(hw);
847 hns3_err(hw, "config lvl34_schd_mode failed: %d", ret);
853 hns3_dcb_pri_tc_base_dwrr_cfg(struct hns3_hw *hw)
855 struct hns3_pg_info *pg_info;
859 for (i = 0; i < hw->dcb_info.num_tc; i++) {
860 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
861 dwrr = pg_info->tc_dwrr[i];
863 ret = hns3_dcb_pri_weight_cfg(hw, i, dwrr);
866 "fail to send priority weight cmd: %d, ret = %d",
871 ret = hns3_dcb_qs_weight_cfg(hw, i, BW_MAX_PERCENT);
873 hns3_err(hw, "fail to send qs_weight cmd: %d, ret = %d",
883 hns3_dcb_pri_dwrr_cfg(struct hns3_hw *hw)
885 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
886 struct hns3_pf *pf = &hns->pf;
890 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
893 ret = hns3_dcb_pri_tc_base_dwrr_cfg(hw);
897 if (!hns3_dev_dcb_supported(hw))
900 ret = hns3_dcb_ets_tc_dwrr_cfg(hw);
901 if (ret == -EOPNOTSUPP) {
902 version = hw->fw_version;
904 "fw %lu.%lu.%lu.%lu doesn't support ets tc weight cmd",
905 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
906 HNS3_FW_VERSION_BYTE3_S),
907 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
908 HNS3_FW_VERSION_BYTE2_S),
909 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
910 HNS3_FW_VERSION_BYTE1_S),
911 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
912 HNS3_FW_VERSION_BYTE0_S));
920 hns3_dcb_pg_dwrr_cfg(struct hns3_hw *hw)
922 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
923 struct hns3_pf *pf = &hns->pf;
927 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
931 for (i = 0; i < hw->dcb_info.num_pg; i++) {
933 ret = hns3_dcb_pg_weight_cfg(hw, i, hw->dcb_info.pg_dwrr[i]);
942 hns3_dcb_dwrr_cfg(struct hns3_hw *hw)
946 ret = hns3_dcb_pg_dwrr_cfg(hw);
948 hns3_err(hw, "config pg_dwrr failed: %d", ret);
952 ret = hns3_dcb_pri_dwrr_cfg(hw);
954 hns3_err(hw, "config pri_dwrr failed: %d", ret);
960 hns3_dcb_shaper_cfg(struct hns3_hw *hw)
964 ret = hns3_dcb_port_shaper_cfg(hw);
966 hns3_err(hw, "config port shaper failed: %d", ret);
970 ret = hns3_dcb_pg_shaper_cfg(hw);
972 hns3_err(hw, "config pg shaper failed: %d", ret);
976 return hns3_dcb_pri_shaper_cfg(hw);
980 hns3_q_to_qs_map_cfg(struct hns3_hw *hw, uint16_t q_id, uint16_t qs_id)
982 struct hns3_nq_to_qs_link_cmd *map;
983 struct hns3_cmd_desc desc;
984 uint16_t tmp_qs_id = 0;
988 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_NQ_TO_QS_LINK, false);
990 map = (struct hns3_nq_to_qs_link_cmd *)desc.data;
992 map->nq_id = rte_cpu_to_le_16(q_id);
995 * Network engine with revision_id 0x21 uses 0~9 bit of qs_id to
996 * configure qset_id. So we need to convert qs_id to the follow
997 * format to support qset_id > 1024.
998 * qs_id: | 15 | 14 ~ 10 | 9 ~ 0 |
1001 * qset_id: | 15 ~ 11 | 10 | 9 ~ 0 |
1002 * | qs_id_h | vld | qs_id_l |
1004 qs_id_l = hns3_get_field(qs_id, HNS3_DCB_QS_ID_L_MSK,
1005 HNS3_DCB_QS_ID_L_S);
1006 qs_id_h = hns3_get_field(qs_id, HNS3_DCB_QS_ID_H_MSK,
1007 HNS3_DCB_QS_ID_H_S);
1008 hns3_set_field(tmp_qs_id, HNS3_DCB_QS_ID_L_MSK, HNS3_DCB_QS_ID_L_S,
1010 hns3_set_field(tmp_qs_id, HNS3_DCB_QS_ID_H_EXT_MSK,
1011 HNS3_DCB_QS_ID_H_EXT_S, qs_id_h);
1012 map->qset_id = rte_cpu_to_le_16(tmp_qs_id | HNS3_DCB_Q_QS_LINK_VLD_MSK);
1014 return hns3_cmd_send(hw, &desc, 1);
1018 hns3_q_to_qs_map(struct hns3_hw *hw)
1020 struct hns3_tc_queue_info *tc_queue;
1025 for (i = 0; i < hw->num_tc; i++) {
1026 tc_queue = &hw->tc_queue[i];
1027 for (j = 0; j < tc_queue->tqp_count; j++) {
1028 q_id = tc_queue->tqp_offset + j;
1029 ret = hns3_q_to_qs_map_cfg(hw, q_id, i);
1039 hns3_pri_q_qs_cfg(struct hns3_hw *hw)
1041 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1042 struct hns3_pf *pf = &hns->pf;
1046 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
1049 /* Cfg qs -> pri mapping */
1050 for (i = 0; i < hw->num_tc; i++) {
1051 ret = hns3_qs_to_pri_map_cfg(hw, i, i);
1053 hns3_err(hw, "qs_to_pri mapping fail: %d", ret);
1058 /* Cfg q -> qs mapping */
1059 ret = hns3_q_to_qs_map(hw);
1061 hns3_err(hw, "nq_to_qs mapping fail: %d", ret);
1067 hns3_dcb_map_cfg(struct hns3_hw *hw)
1071 ret = hns3_up_to_tc_map(hw);
1073 hns3_err(hw, "up_to_tc mapping fail: %d", ret);
1077 ret = hns3_pg_to_pri_map(hw);
1079 hns3_err(hw, "pri_to_pg mapping fail: %d", ret);
1083 return hns3_pri_q_qs_cfg(hw);
1087 hns3_dcb_schd_setup_hw(struct hns3_hw *hw)
1091 /* Cfg dcb mapping */
1092 ret = hns3_dcb_map_cfg(hw);
1096 /* Cfg dcb shaper */
1097 ret = hns3_dcb_shaper_cfg(hw);
1102 ret = hns3_dcb_dwrr_cfg(hw);
1106 /* Cfg schd mode for each level schd */
1107 return hns3_dcb_schd_mode_cfg(hw);
1111 hns3_pause_param_cfg(struct hns3_hw *hw, const uint8_t *addr,
1112 uint8_t pause_trans_gap, uint16_t pause_trans_time)
1114 struct hns3_cfg_pause_param_cmd *pause_param;
1115 struct hns3_cmd_desc desc;
1117 pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
1119 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, false);
1121 memcpy(pause_param->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1122 memcpy(pause_param->mac_addr_extra, addr, RTE_ETHER_ADDR_LEN);
1123 pause_param->pause_trans_gap = pause_trans_gap;
1124 pause_param->pause_trans_time = rte_cpu_to_le_16(pause_trans_time);
1126 return hns3_cmd_send(hw, &desc, 1);
1130 hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr)
1132 struct hns3_cfg_pause_param_cmd *pause_param;
1133 struct hns3_cmd_desc desc;
1134 uint16_t trans_time;
1138 pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
1140 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, true);
1142 ret = hns3_cmd_send(hw, &desc, 1);
1146 trans_gap = pause_param->pause_trans_gap;
1147 trans_time = rte_le_to_cpu_16(pause_param->pause_trans_time);
1149 return hns3_pause_param_cfg(hw, mac_addr, trans_gap, trans_time);
1153 hns3_pause_param_setup_hw(struct hns3_hw *hw, uint16_t pause_time)
1155 #define PAUSE_TIME_DIV_BY 2
1156 #define PAUSE_TIME_MIN_VALUE 0x4
1158 struct hns3_mac *mac = &hw->mac;
1159 uint8_t pause_trans_gap;
1162 * Pause transmit gap must be less than "pause_time / 2", otherwise
1163 * the behavior of MAC is undefined.
1165 if (pause_time > PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1166 pause_trans_gap = HNS3_DEFAULT_PAUSE_TRANS_GAP;
1167 else if (pause_time >= PAUSE_TIME_MIN_VALUE &&
1168 pause_time <= PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1169 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1171 hns3_warn(hw, "pause_time(%u) is adjusted to 4", pause_time);
1172 pause_time = PAUSE_TIME_MIN_VALUE;
1173 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1176 return hns3_pause_param_cfg(hw, mac->mac_addr,
1177 pause_trans_gap, pause_time);
1181 hns3_mac_pause_en_cfg(struct hns3_hw *hw, bool tx, bool rx)
1183 struct hns3_cmd_desc desc;
1185 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PAUSE_EN, false);
1187 desc.data[0] = rte_cpu_to_le_32((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1188 (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1190 return hns3_cmd_send(hw, &desc, 1);
1194 hns3_pfc_pause_en_cfg(struct hns3_hw *hw, uint8_t pfc_bitmap, bool tx, bool rx)
1196 struct hns3_cmd_desc desc;
1197 struct hns3_pfc_en_cmd *pfc = (struct hns3_pfc_en_cmd *)desc.data;
1199 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PFC_PAUSE_EN, false);
1201 pfc->tx_rx_en_bitmap = (uint8_t)((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1202 (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1204 pfc->pri_en_bitmap = pfc_bitmap;
1206 return hns3_cmd_send(hw, &desc, 1);
1210 hns3_qs_bp_cfg(struct hns3_hw *hw, uint8_t tc, uint8_t grp_id, uint32_t bit_map)
1212 struct hns3_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
1213 struct hns3_cmd_desc desc;
1215 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_BP_TO_QSET_MAPPING, false);
1217 bp_to_qs_map_cmd = (struct hns3_bp_to_qs_map_cmd *)desc.data;
1219 bp_to_qs_map_cmd->tc_id = tc;
1220 bp_to_qs_map_cmd->qs_group_id = grp_id;
1221 bp_to_qs_map_cmd->qs_bit_map = rte_cpu_to_le_32(bit_map);
1223 return hns3_cmd_send(hw, &desc, 1);
1227 hns3_get_rx_tx_en_status(struct hns3_hw *hw, bool *tx_en, bool *rx_en)
1229 switch (hw->current_mode) {
1234 case HNS3_FC_RX_PAUSE:
1238 case HNS3_FC_TX_PAUSE:
1254 hns3_mac_pause_setup_hw(struct hns3_hw *hw)
1258 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)
1259 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1265 return hns3_mac_pause_en_cfg(hw, tx_en, rx_en);
1269 hns3_pfc_setup_hw(struct hns3_hw *hw)
1273 if (hw->current_fc_status == HNS3_FC_STATUS_PFC)
1274 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1280 return hns3_pfc_pause_en_cfg(hw, hw->dcb_info.pfc_en, tx_en, rx_en);
1284 * Each Tc has a 1024 queue sets to backpress, it divides to
1285 * 32 group, each group contains 32 queue sets, which can be
1286 * represented by uint32_t bitmap.
1289 hns3_bp_setup_hw(struct hns3_hw *hw, uint8_t tc)
1295 for (i = 0; i < HNS3_BP_GRP_NUM; i++) {
1296 uint8_t grp, sub_grp;
1299 grp = hns3_get_field(tc, HNS3_BP_GRP_ID_M, HNS3_BP_GRP_ID_S);
1300 sub_grp = hns3_get_field(tc, HNS3_BP_SUB_GRP_ID_M,
1301 HNS3_BP_SUB_GRP_ID_S);
1303 qs_bitmap |= (1 << sub_grp);
1305 ret = hns3_qs_bp_cfg(hw, tc, i, qs_bitmap);
1314 hns3_dcb_bp_setup(struct hns3_hw *hw)
1318 for (i = 0; i < hw->dcb_info.num_tc; i++) {
1319 ret = hns3_bp_setup_hw(hw, i);
1328 hns3_dcb_pause_setup_hw(struct hns3_hw *hw)
1330 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1331 struct hns3_pf *pf = &hns->pf;
1334 ret = hns3_pause_param_setup_hw(hw, pf->pause_time);
1336 hns3_err(hw, "Fail to set pause parameter. ret = %d", ret);
1340 ret = hns3_mac_pause_setup_hw(hw);
1342 hns3_err(hw, "Fail to setup MAC pause. ret = %d", ret);
1346 /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1347 if (!hns3_dev_dcb_supported(hw))
1350 ret = hns3_pfc_setup_hw(hw);
1352 hns3_err(hw, "config pfc failed! ret = %d", ret);
1356 return hns3_dcb_bp_setup(hw);
1360 hns3_dcb_undrop_tc_map(struct hns3_hw *hw, uint8_t pfc_en)
1362 uint8_t pfc_map = 0;
1366 prio_tc = hw->dcb_info.prio_tc;
1367 for (i = 0; i < hw->dcb_info.num_tc; i++) {
1368 for (j = 0; j < HNS3_MAX_USER_PRIO; j++) {
1369 if (prio_tc[j] == i && pfc_en & BIT(j)) {
1380 hns3_dcb_cfg_validate(struct hns3_adapter *hns, uint8_t *tc, bool *changed)
1382 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1383 struct hns3_hw *hw = &hns->hw;
1384 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1385 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1390 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1391 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1392 if (dcb_rx_conf->dcb_tc[i] != hw->dcb_info.prio_tc[i])
1395 if (dcb_rx_conf->dcb_tc[i] > max_tc)
1396 max_tc = dcb_rx_conf->dcb_tc[i];
1399 if (*tc != hw->dcb_info.num_tc)
1403 * We ensure that dcb information can be reconfigured
1404 * after the hns3_priority_flow_ctrl_set function called.
1406 if (hw->current_mode != HNS3_FC_FULL)
1408 pfc_en = RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1409 if (hw->dcb_info.pfc_en != pfc_en)
1412 /* tx/rx queue number is reconfigured. */
1413 if (nb_rx_q != hw->used_rx_queues || nb_tx_q != hw->used_tx_queues)
1418 hns3_dcb_info_cfg(struct hns3_adapter *hns)
1420 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1421 struct hns3_pf *pf = &hns->pf;
1422 struct hns3_hw *hw = &hns->hw;
1423 uint8_t tc_bw, bw_rest;
1427 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1428 pf->local_max_tc = (uint8_t)dcb_rx_conf->nb_tcs;
1429 pf->pfc_max = (uint8_t)dcb_rx_conf->nb_tcs;
1432 memset(hw->dcb_info.pg_info, 0,
1433 sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
1434 hw->dcb_info.pg_dwrr[0] = BW_MAX_PERCENT;
1435 hw->dcb_info.pg_info[0].pg_id = 0;
1436 hw->dcb_info.pg_info[0].pg_sch_mode = HNS3_SCH_MODE_DWRR;
1437 hw->dcb_info.pg_info[0].bw_limit = hw->max_tm_rate;
1438 hw->dcb_info.pg_info[0].tc_bit_map = hw->hw_tc_map;
1440 /* Each tc has same bw for valid tc by default */
1441 tc_bw = BW_MAX_PERCENT / hw->dcb_info.num_tc;
1442 for (i = 0; i < hw->dcb_info.num_tc; i++)
1443 hw->dcb_info.pg_info[0].tc_dwrr[i] = tc_bw;
1444 /* To ensure the sum of tc_dwrr is equal to 100 */
1445 bw_rest = BW_MAX_PERCENT % hw->dcb_info.num_tc;
1446 for (j = 0; j < bw_rest; j++)
1447 hw->dcb_info.pg_info[0].tc_dwrr[j]++;
1448 for (; i < dcb_rx_conf->nb_tcs; i++)
1449 hw->dcb_info.pg_info[0].tc_dwrr[i] = 0;
1451 /* All tcs map to pg0 */
1452 memset(hw->dcb_info.tc_info, 0,
1453 sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
1454 for (i = 0; i < hw->dcb_info.num_tc; i++) {
1455 hw->dcb_info.tc_info[i].tc_id = i;
1456 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
1457 hw->dcb_info.tc_info[i].pgid = 0;
1458 hw->dcb_info.tc_info[i].bw_limit =
1459 hw->dcb_info.pg_info[0].bw_limit;
1462 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
1463 hw->dcb_info.prio_tc[i] = dcb_rx_conf->dcb_tc[i];
1465 ret = hns3_dcb_update_tc_queue_mapping(hw, hw->data->nb_rx_queues,
1466 hw->data->nb_tx_queues);
1468 hns3_err(hw, "update tc queue mapping failed, ret = %d.", ret);
1474 hns3_dcb_info_update(struct hns3_adapter *hns, uint8_t num_tc)
1476 struct hns3_pf *pf = &hns->pf;
1477 struct hns3_hw *hw = &hns->hw;
1478 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1479 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1480 uint8_t bit_map = 0;
1483 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1484 hw->dcb_info.num_pg != 1)
1487 if (nb_rx_q < num_tc) {
1488 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).",
1493 if (nb_tx_q < num_tc) {
1494 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).",
1499 /* Currently not support uncontinuous tc */
1500 hw->dcb_info.num_tc = num_tc;
1501 for (i = 0; i < hw->dcb_info.num_tc; i++)
1506 hw->dcb_info.num_tc = 1;
1508 hw->hw_tc_map = bit_map;
1510 return hns3_dcb_info_cfg(hns);
1514 hns3_dcb_hw_configure(struct hns3_adapter *hns)
1516 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1517 struct hns3_pf *pf = &hns->pf;
1518 struct hns3_hw *hw = &hns->hw;
1519 enum hns3_fc_status fc_status = hw->current_fc_status;
1520 enum hns3_fc_mode current_mode = hw->current_mode;
1521 uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1524 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1525 pf->tx_sch_mode != HNS3_FLAG_VNET_BASE_SCH_MODE)
1528 ret = hns3_dcb_schd_setup_hw(hw);
1530 hns3_err(hw, "dcb schdule configure failed! ret = %d", ret);
1534 if (hw->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
1535 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1536 if (dcb_rx_conf->nb_tcs == 0)
1537 hw->dcb_info.pfc_en = 1; /* tc0 only */
1539 hw->dcb_info.pfc_en =
1540 RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1542 hw->dcb_info.hw_pfc_map =
1543 hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1545 ret = hns3_buffer_alloc(hw);
1549 hw->current_fc_status = HNS3_FC_STATUS_PFC;
1550 hw->current_mode = HNS3_FC_FULL;
1551 ret = hns3_dcb_pause_setup_hw(hw);
1553 hns3_err(hw, "setup pfc failed! ret = %d", ret);
1554 goto pfc_setup_fail;
1558 * Although dcb_capability_en is lack of ETH_DCB_PFC_SUPPORT
1559 * flag, the DCB information is configured, such as tc numbers.
1560 * Therefore, refreshing the allocation of packet buffer is
1563 ret = hns3_buffer_alloc(hw);
1571 hw->current_mode = current_mode;
1572 hw->current_fc_status = fc_status;
1573 hw->dcb_info.hw_pfc_map = hw_pfc_map;
1574 status = hns3_buffer_alloc(hw);
1576 hns3_err(hw, "recover packet buffer fail! status = %d", status);
1582 * hns3_dcb_configure - setup dcb related config
1583 * @hns: pointer to hns3 adapter
1584 * Returns 0 on success, negative value on failure.
1587 hns3_dcb_configure(struct hns3_adapter *hns)
1589 struct hns3_hw *hw = &hns->hw;
1590 bool map_changed = false;
1594 hns3_dcb_cfg_validate(hns, &num_tc, &map_changed);
1596 __atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1597 ret = hns3_dcb_info_update(hns, num_tc);
1599 hns3_err(hw, "dcb info update failed: %d", ret);
1603 ret = hns3_dcb_hw_configure(hns);
1605 hns3_err(hw, "dcb sw configure failed: %d", ret);
1614 hns3_dcb_init_hw(struct hns3_hw *hw)
1618 ret = hns3_dcb_schd_setup_hw(hw);
1620 hns3_err(hw, "dcb schedule setup failed: %d", ret);
1624 ret = hns3_dcb_pause_setup_hw(hw);
1626 hns3_err(hw, "PAUSE setup failed: %d", ret);
1632 hns3_dcb_init(struct hns3_hw *hw)
1634 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1635 struct hns3_pf *pf = &hns->pf;
1636 uint16_t default_tqp_num;
1639 PMD_INIT_FUNC_TRACE();
1642 * According to the 'adapter_state' identifier, the following branch
1643 * is only executed to initialize default configurations of dcb during
1644 * the initializing driver process. Due to driver saving dcb-related
1645 * information before reset triggered, the reinit dev stage of the
1646 * reset process can not access to the branch, or those information
1649 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
1650 hw->requested_mode = HNS3_FC_NONE;
1651 hw->current_mode = hw->requested_mode;
1652 pf->pause_time = HNS3_DEFAULT_PAUSE_TRANS_TIME;
1653 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1655 ret = hns3_dcb_info_init(hw);
1657 hns3_err(hw, "dcb info init failed, ret = %d.", ret);
1662 * The number of queues configured by default cannot exceed
1663 * the maximum number of queues for a single TC.
1665 default_tqp_num = RTE_MIN(hw->rss_size_max,
1666 hw->tqps_num / hw->dcb_info.num_tc);
1667 ret = hns3_dcb_update_tc_queue_mapping(hw, default_tqp_num,
1671 "update tc queue mapping failed, ret = %d.",
1678 * DCB hardware will be configured by following the function during
1679 * the initializing driver process and the reset process. However,
1680 * driver will restore directly configurations of dcb hardware based
1681 * on dcb-related information soft maintained when driver
1682 * initialization has finished and reset is coming.
1684 ret = hns3_dcb_init_hw(hw);
1686 hns3_err(hw, "dcb init hardware failed, ret = %d.", ret);
1694 hns3_update_queue_map_configure(struct hns3_adapter *hns)
1696 struct hns3_hw *hw = &hns->hw;
1697 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1698 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1701 ret = hns3_dcb_update_tc_queue_mapping(hw, nb_rx_q, nb_tx_q);
1703 hns3_err(hw, "failed to update tc queue mapping, ret = %d.",
1707 ret = hns3_q_to_qs_map(hw);
1709 hns3_err(hw, "failed to map nq to qs, ret = %d.", ret);
1715 hns3_dcb_cfg_update(struct hns3_adapter *hns)
1717 struct hns3_hw *hw = &hns->hw;
1718 enum rte_eth_rx_mq_mode mq_mode = hw->data->dev_conf.rxmode.mq_mode;
1721 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
1722 ret = hns3_dcb_configure(hns);
1724 hns3_err(hw, "Failed to config dcb: %d", ret);
1727 * Update queue map without PFC configuration,
1728 * due to queues reconfigured by user.
1730 ret = hns3_update_queue_map_configure(hns);
1733 "Failed to update queue mapping configure: %d",
1741 * hns3_dcb_pfc_enable - Enable priority flow control
1742 * @dev: pointer to ethernet device
1744 * Configures the pfc settings for one porority.
1747 hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
1749 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1751 enum hns3_fc_status fc_status = hw->current_fc_status;
1752 enum hns3_fc_mode current_mode = hw->current_mode;
1753 uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1754 uint8_t pfc_en = hw->dcb_info.pfc_en;
1755 uint8_t priority = pfc_conf->priority;
1756 uint16_t pause_time = pf->pause_time;
1759 pf->pause_time = pfc_conf->fc.pause_time;
1760 hw->current_mode = hw->requested_mode;
1761 hw->current_fc_status = HNS3_FC_STATUS_PFC;
1762 hw->dcb_info.pfc_en |= BIT(priority);
1763 hw->dcb_info.hw_pfc_map =
1764 hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1765 ret = hns3_buffer_alloc(hw);
1767 goto pfc_setup_fail;
1770 * The flow control mode of all UPs will be changed based on
1771 * current_mode coming from user.
1773 ret = hns3_dcb_pause_setup_hw(hw);
1775 hns3_err(hw, "enable pfc failed! ret = %d", ret);
1776 goto pfc_setup_fail;
1782 hw->current_mode = current_mode;
1783 hw->current_fc_status = fc_status;
1784 pf->pause_time = pause_time;
1785 hw->dcb_info.pfc_en = pfc_en;
1786 hw->dcb_info.hw_pfc_map = hw_pfc_map;
1787 status = hns3_buffer_alloc(hw);
1789 hns3_err(hw, "recover packet buffer fail: %d", status);
1795 * hns3_fc_enable - Enable MAC pause
1796 * @dev: pointer to ethernet device
1798 * Configures the MAC pause settings.
1801 hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1803 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1805 enum hns3_fc_status fc_status = hw->current_fc_status;
1806 enum hns3_fc_mode current_mode = hw->current_mode;
1807 uint16_t pause_time = pf->pause_time;
1810 pf->pause_time = fc_conf->pause_time;
1811 hw->current_mode = hw->requested_mode;
1814 * In fact, current_fc_status is HNS3_FC_STATUS_NONE when mode
1815 * of flow control is configured to be HNS3_FC_NONE.
1817 if (hw->current_mode == HNS3_FC_NONE)
1818 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1820 hw->current_fc_status = HNS3_FC_STATUS_MAC_PAUSE;
1822 ret = hns3_dcb_pause_setup_hw(hw);
1824 hns3_err(hw, "enable MAC Pause failed! ret = %d", ret);
1831 hw->current_mode = current_mode;
1832 hw->current_fc_status = fc_status;
1833 pf->pause_time = pause_time;