1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
11 #include <rte_common.h>
12 #include <rte_ethdev.h>
14 #include "hns3_logs.h"
15 #include "hns3_regs.h"
16 #include "hns3_ethdev.h"
19 #define HNS3_SHAPER_BS_U_DEF 5
20 #define HNS3_SHAPER_BS_S_DEF 20
21 #define BW_MAX_PERCENT 100
22 #define HNS3_ETHER_MAX_RATE 100000
25 * hns3_shaper_para_calc: calculate ir parameter for the shaper
26 * @ir: Rate to be config, its unit is Mbps
27 * @shaper_level: the shaper level. eg: port, pg, priority, queueset
28 * @shaper_para: shaper parameter of IR shaper
32 * IR_b * (2 ^ IR_u) * 8
33 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps)
36 * @return: 0: calculate sucessful, negative: fail
39 hns3_shaper_para_calc(struct hns3_hw *hw, uint32_t ir, uint8_t shaper_level,
40 struct hns3_shaper_parameter *shaper_para)
42 #define SHAPER_DEFAULT_IR_B 126
43 #define DIVISOR_CLK (1000 * 8)
44 #define DIVISOR_IR_B_126 (126 * DIVISOR_CLK)
46 const uint16_t tick_array[HNS3_SHAPER_LVL_CNT] = {
47 6 * 256, /* Prioriy level */
48 6 * 32, /* Prioriy group level */
49 6 * 8, /* Port level */
50 6 * 256 /* Qset level */
52 uint8_t ir_u_calc = 0;
53 uint8_t ir_s_calc = 0;
59 if (shaper_level >= HNS3_SHAPER_LVL_CNT) {
61 "shaper_level(%d) is greater than HNS3_SHAPER_LVL_CNT(%d)",
62 shaper_level, HNS3_SHAPER_LVL_CNT);
66 if (ir > HNS3_ETHER_MAX_RATE) {
67 hns3_err(hw, "rate(%d) exceeds the rate driver supported "
68 "HNS3_ETHER_MAX_RATE(%d)", ir, HNS3_ETHER_MAX_RATE);
72 tick = tick_array[shaper_level];
75 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
76 * the formula is changed to:
78 * ir_calc = ---------------- * 1000
81 ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
84 shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
85 } else if (ir_calc > ir) {
86 /* Increasing the denominator to select ir_s value */
89 ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
90 } while (ir_calc > ir);
93 shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
95 shaper_para->ir_b = (ir * tick * (1 << ir_s_calc) +
96 (DIVISOR_CLK >> 1)) / DIVISOR_CLK;
99 * Increasing the numerator to select ir_u value. ir_u_calc will
100 * get maximum value when ir_calc is minimum and ir is maximum.
101 * ir_calc gets minimum value when tick is the maximum value.
102 * At the same time, value of ir_u_calc can only be increased up
103 * to eight after the while loop if the value of ir is equal
104 * to HNS3_ETHER_MAX_RATE.
109 numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
110 ir_calc = (numerator + (tick >> 1)) / tick;
111 } while (ir_calc < ir);
114 shaper_para->ir_b = SHAPER_DEFAULT_IR_B;
119 * The maximum value of ir_u_calc in this branch is
120 * seven in all cases. Thus, value of denominator can
123 denominator = DIVISOR_CLK * (1 << ir_u_calc);
125 (ir * tick + (denominator >> 1)) / denominator;
129 shaper_para->ir_u = ir_u_calc;
130 shaper_para->ir_s = ir_s_calc;
136 hns3_fill_pri_array(struct hns3_hw *hw, uint8_t *pri, uint8_t pri_id)
138 #define HNS3_HALF_BYTE_BIT_OFFSET 4
139 uint8_t tc = hw->dcb_info.prio_tc[pri_id];
141 if (tc >= hw->dcb_info.num_tc)
145 * The register for priority has four bytes, the first bytes includes
146 * priority0 and priority1, the higher 4bit stands for priority1
147 * while the lower 4bit stands for priority0, as below:
148 * first byte: | pri_1 | pri_0 |
149 * second byte: | pri_3 | pri_2 |
150 * third byte: | pri_5 | pri_4 |
151 * fourth byte: | pri_7 | pri_6 |
153 pri[pri_id >> 1] |= tc << ((pri_id & 1) * HNS3_HALF_BYTE_BIT_OFFSET);
159 hns3_up_to_tc_map(struct hns3_hw *hw)
161 struct hns3_cmd_desc desc;
162 uint8_t *pri = (uint8_t *)desc.data;
166 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PRI_TO_TC_MAPPING, false);
168 for (pri_id = 0; pri_id < HNS3_MAX_USER_PRIO; pri_id++) {
169 ret = hns3_fill_pri_array(hw, pri, pri_id);
174 return hns3_cmd_send(hw, &desc, 1);
178 hns3_pg_to_pri_map_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t pri_bit_map)
180 struct hns3_pg_to_pri_link_cmd *map;
181 struct hns3_cmd_desc desc;
183 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_TO_PRI_LINK, false);
185 map = (struct hns3_pg_to_pri_link_cmd *)desc.data;
188 map->pri_bit_map = pri_bit_map;
190 return hns3_cmd_send(hw, &desc, 1);
194 hns3_pg_to_pri_map(struct hns3_hw *hw)
196 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
197 struct hns3_pf *pf = &hns->pf;
198 struct hns3_pg_info *pg_info;
201 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
204 for (i = 0; i < hw->dcb_info.num_pg; i++) {
205 /* Cfg pg to priority mapping */
206 pg_info = &hw->dcb_info.pg_info[i];
207 ret = hns3_pg_to_pri_map_cfg(hw, i, pg_info->tc_bit_map);
216 hns3_qs_to_pri_map_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t pri)
218 struct hns3_qs_to_pri_link_cmd *map;
219 struct hns3_cmd_desc desc;
221 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_TO_PRI_LINK, false);
223 map = (struct hns3_qs_to_pri_link_cmd *)desc.data;
225 map->qs_id = rte_cpu_to_le_16(qs_id);
227 map->link_vld = HNS3_DCB_QS_PRI_LINK_VLD_MSK;
229 return hns3_cmd_send(hw, &desc, 1);
233 hns3_dcb_qs_weight_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t dwrr)
235 struct hns3_qs_weight_cmd *weight;
236 struct hns3_cmd_desc desc;
238 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_WEIGHT, false);
240 weight = (struct hns3_qs_weight_cmd *)desc.data;
242 weight->qs_id = rte_cpu_to_le_16(qs_id);
245 return hns3_cmd_send(hw, &desc, 1);
249 hns3_dcb_ets_tc_dwrr_cfg(struct hns3_hw *hw)
251 #define DEFAULT_TC_WEIGHT 1
252 #define DEFAULT_TC_OFFSET 14
253 struct hns3_ets_tc_weight_cmd *ets_weight;
254 struct hns3_cmd_desc desc;
257 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_ETS_TC_WEIGHT, false);
258 ets_weight = (struct hns3_ets_tc_weight_cmd *)desc.data;
260 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
261 struct hns3_pg_info *pg_info;
263 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
265 if (!(hw->hw_tc_map & BIT(i)))
268 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
269 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
272 ets_weight->weight_offset = DEFAULT_TC_OFFSET;
274 return hns3_cmd_send(hw, &desc, 1);
278 hns3_dcb_pri_weight_cfg(struct hns3_hw *hw, uint8_t pri_id, uint8_t dwrr)
280 struct hns3_priority_weight_cmd *weight;
281 struct hns3_cmd_desc desc;
283 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_WEIGHT, false);
285 weight = (struct hns3_priority_weight_cmd *)desc.data;
287 weight->pri_id = pri_id;
290 return hns3_cmd_send(hw, &desc, 1);
294 hns3_dcb_pg_weight_cfg(struct hns3_hw *hw, uint8_t pg_id, uint8_t dwrr)
296 struct hns3_pg_weight_cmd *weight;
297 struct hns3_cmd_desc desc;
299 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_WEIGHT, false);
301 weight = (struct hns3_pg_weight_cmd *)desc.data;
303 weight->pg_id = pg_id;
306 return hns3_cmd_send(hw, &desc, 1);
309 hns3_dcb_pg_schd_mode_cfg(struct hns3_hw *hw, uint8_t pg_id)
311 struct hns3_cmd_desc desc;
313 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PG_SCH_MODE_CFG, false);
315 if (hw->dcb_info.pg_info[pg_id].pg_sch_mode == HNS3_SCH_MODE_DWRR)
316 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
320 desc.data[0] = rte_cpu_to_le_32(pg_id);
322 return hns3_cmd_send(hw, &desc, 1);
326 hns3_dcb_get_shapping_para(uint8_t ir_b, uint8_t ir_u, uint8_t ir_s,
327 uint8_t bs_b, uint8_t bs_s)
329 uint32_t shapping_para = 0;
331 hns3_dcb_set_field(shapping_para, IR_B, ir_b);
332 hns3_dcb_set_field(shapping_para, IR_U, ir_u);
333 hns3_dcb_set_field(shapping_para, IR_S, ir_s);
334 hns3_dcb_set_field(shapping_para, BS_B, bs_b);
335 hns3_dcb_set_field(shapping_para, BS_S, bs_s);
337 return shapping_para;
341 hns3_dcb_port_shaper_cfg(struct hns3_hw *hw)
343 struct hns3_port_shapping_cmd *shap_cfg_cmd;
344 struct hns3_shaper_parameter shaper_parameter;
345 uint32_t shapping_para;
346 uint32_t ir_u, ir_b, ir_s;
347 struct hns3_cmd_desc desc;
350 ret = hns3_shaper_para_calc(hw, hw->mac.link_speed,
351 HNS3_SHAPER_LVL_PORT, &shaper_parameter);
353 hns3_err(hw, "calculate shaper parameter failed: %d", ret);
357 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PORT_SHAPPING, false);
358 shap_cfg_cmd = (struct hns3_port_shapping_cmd *)desc.data;
360 ir_b = shaper_parameter.ir_b;
361 ir_u = shaper_parameter.ir_u;
362 ir_s = shaper_parameter.ir_s;
363 shapping_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
364 HNS3_SHAPER_BS_U_DEF,
365 HNS3_SHAPER_BS_S_DEF);
367 shap_cfg_cmd->port_shapping_para = rte_cpu_to_le_32(shapping_para);
369 return hns3_cmd_send(hw, &desc, 1);
373 hns3_dcb_pg_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
374 uint8_t pg_id, uint32_t shapping_para)
376 struct hns3_pg_shapping_cmd *shap_cfg_cmd;
377 enum hns3_opcode_type opcode;
378 struct hns3_cmd_desc desc;
380 opcode = bucket ? HNS3_OPC_TM_PG_P_SHAPPING :
381 HNS3_OPC_TM_PG_C_SHAPPING;
382 hns3_cmd_setup_basic_desc(&desc, opcode, false);
384 shap_cfg_cmd = (struct hns3_pg_shapping_cmd *)desc.data;
386 shap_cfg_cmd->pg_id = pg_id;
388 shap_cfg_cmd->pg_shapping_para = rte_cpu_to_le_32(shapping_para);
390 return hns3_cmd_send(hw, &desc, 1);
394 hns3_dcb_pg_shaper_cfg(struct hns3_hw *hw)
396 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
397 struct hns3_shaper_parameter shaper_parameter;
398 struct hns3_pf *pf = &hns->pf;
399 uint32_t ir_u, ir_b, ir_s;
400 uint32_t shaper_para;
405 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
409 for (i = 0; i < hw->dcb_info.num_pg; i++) {
410 /* Calc shaper para */
411 ret = hns3_shaper_para_calc(hw,
412 hw->dcb_info.pg_info[i].bw_limit,
416 hns3_err(hw, "calculate shaper parameter failed: %d",
421 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
422 HNS3_SHAPER_BS_U_DEF,
423 HNS3_SHAPER_BS_S_DEF);
425 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
429 "config PG CIR shaper parameter failed: %d",
434 ir_b = shaper_parameter.ir_b;
435 ir_u = shaper_parameter.ir_u;
436 ir_s = shaper_parameter.ir_s;
437 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
438 HNS3_SHAPER_BS_U_DEF,
439 HNS3_SHAPER_BS_S_DEF);
441 ret = hns3_dcb_pg_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
445 "config PG PIR shaper parameter failed: %d",
455 hns3_dcb_qs_schd_mode_cfg(struct hns3_hw *hw, uint16_t qs_id, uint8_t mode)
457 struct hns3_cmd_desc desc;
459 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QS_SCH_MODE_CFG, false);
461 if (mode == HNS3_SCH_MODE_DWRR)
462 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
466 desc.data[0] = rte_cpu_to_le_32(qs_id);
468 return hns3_cmd_send(hw, &desc, 1);
472 hns3_dcb_pri_schd_mode_cfg(struct hns3_hw *hw, uint8_t pri_id)
474 struct hns3_cmd_desc desc;
476 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_PRI_SCH_MODE_CFG, false);
478 if (hw->dcb_info.tc_info[pri_id].tc_sch_mode == HNS3_SCH_MODE_DWRR)
479 desc.data[1] = rte_cpu_to_le_32(HNS3_DCB_TX_SCHD_DWRR_MSK);
483 desc.data[0] = rte_cpu_to_le_32(pri_id);
485 return hns3_cmd_send(hw, &desc, 1);
489 hns3_dcb_pri_shapping_cfg(struct hns3_hw *hw, enum hns3_shap_bucket bucket,
490 uint8_t pri_id, uint32_t shapping_para)
492 struct hns3_pri_shapping_cmd *shap_cfg_cmd;
493 enum hns3_opcode_type opcode;
494 struct hns3_cmd_desc desc;
496 opcode = bucket ? HNS3_OPC_TM_PRI_P_SHAPPING :
497 HNS3_OPC_TM_PRI_C_SHAPPING;
499 hns3_cmd_setup_basic_desc(&desc, opcode, false);
501 shap_cfg_cmd = (struct hns3_pri_shapping_cmd *)desc.data;
503 shap_cfg_cmd->pri_id = pri_id;
505 shap_cfg_cmd->pri_shapping_para = rte_cpu_to_le_32(shapping_para);
507 return hns3_cmd_send(hw, &desc, 1);
511 hns3_dcb_pri_tc_base_shaper_cfg(struct hns3_hw *hw)
513 struct hns3_shaper_parameter shaper_parameter;
514 uint32_t ir_u, ir_b, ir_s;
515 uint32_t shaper_para;
518 for (i = 0; i < hw->dcb_info.num_tc; i++) {
519 ret = hns3_shaper_para_calc(hw,
520 hw->dcb_info.tc_info[i].bw_limit,
524 hns3_err(hw, "calculate shaper parameter failed: %d",
529 shaper_para = hns3_dcb_get_shapping_para(0, 0, 0,
530 HNS3_SHAPER_BS_U_DEF,
531 HNS3_SHAPER_BS_S_DEF);
533 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_C_BUCKET, i,
537 "config priority CIR shaper parameter failed: %d",
542 ir_b = shaper_parameter.ir_b;
543 ir_u = shaper_parameter.ir_u;
544 ir_s = shaper_parameter.ir_s;
545 shaper_para = hns3_dcb_get_shapping_para(ir_b, ir_u, ir_s,
546 HNS3_SHAPER_BS_U_DEF,
547 HNS3_SHAPER_BS_S_DEF);
549 ret = hns3_dcb_pri_shapping_cfg(hw, HNS3_DCB_SHAP_P_BUCKET, i,
553 "config priority PIR shaper parameter failed: %d",
564 hns3_dcb_pri_shaper_cfg(struct hns3_hw *hw)
566 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
567 struct hns3_pf *pf = &hns->pf;
570 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
573 ret = hns3_dcb_pri_tc_base_shaper_cfg(hw);
575 hns3_err(hw, "config port shaper failed: %d", ret);
581 hns3_set_rss_size(struct hns3_hw *hw, uint16_t nb_rx_q)
583 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
584 uint16_t rx_qnum_per_tc;
587 rx_qnum_per_tc = nb_rx_q / hw->num_tc;
588 rx_qnum_per_tc = RTE_MIN(hw->rss_size_max, rx_qnum_per_tc);
589 if (hw->alloc_rss_size != rx_qnum_per_tc) {
590 hns3_info(hw, "rss size changes from %u to %u",
591 hw->alloc_rss_size, rx_qnum_per_tc);
592 hw->alloc_rss_size = rx_qnum_per_tc;
594 hw->used_rx_queues = hw->num_tc * hw->alloc_rss_size;
597 * When rss size is changed, we need to update rss redirection table
598 * maintained by driver. Besides, during the entire reset process, we
599 * need to ensure that the rss table information are not overwritten
600 * and configured directly to the hardware in the RESET_STAGE_RESTORE
601 * stage of the reset process.
603 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
604 for (i = 0; i < HNS3_RSS_IND_TBL_SIZE; i++)
605 rss_cfg->rss_indirection_tbl[i] =
606 i % hw->alloc_rss_size;
611 hns3_tc_queue_mapping_cfg(struct hns3_hw *hw, uint16_t nb_queue)
613 struct hns3_tc_queue_info *tc_queue;
616 hw->tx_qnum_per_tc = nb_queue / hw->num_tc;
617 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
618 tc_queue = &hw->tc_queue[i];
619 if (hw->hw_tc_map & BIT(i) && i < hw->num_tc) {
620 tc_queue->enable = true;
621 tc_queue->tqp_offset = i * hw->tx_qnum_per_tc;
622 tc_queue->tqp_count = hw->tx_qnum_per_tc;
625 /* Set to default queue if TC is disable */
626 tc_queue->enable = false;
627 tc_queue->tqp_offset = 0;
628 tc_queue->tqp_count = 0;
632 hw->used_tx_queues = hw->num_tc * hw->tx_qnum_per_tc;
636 hns3_dcb_update_tc_queue_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
639 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
640 struct hns3_pf *pf = &hns->pf;
642 hw->num_tc = hw->dcb_info.num_tc;
643 hns3_set_rss_size(hw, nb_rx_q);
644 hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
647 memcpy(pf->prio_tc, hw->dcb_info.prio_tc, HNS3_MAX_USER_PRIO);
651 hns3_dcb_info_init(struct hns3_hw *hw)
653 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
654 struct hns3_pf *pf = &hns->pf;
657 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
658 hw->dcb_info.num_pg != 1)
661 /* Initializing PG information */
662 memset(hw->dcb_info.pg_info, 0,
663 sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
664 for (i = 0; i < hw->dcb_info.num_pg; i++) {
665 hw->dcb_info.pg_dwrr[i] = i ? 0 : BW_MAX_PERCENT;
666 hw->dcb_info.pg_info[i].pg_id = i;
667 hw->dcb_info.pg_info[i].pg_sch_mode = HNS3_SCH_MODE_DWRR;
668 hw->dcb_info.pg_info[i].bw_limit = HNS3_ETHER_MAX_RATE;
673 hw->dcb_info.pg_info[i].tc_bit_map = hw->hw_tc_map;
674 for (k = 0; k < hw->dcb_info.num_tc; k++)
675 hw->dcb_info.pg_info[i].tc_dwrr[k] = BW_MAX_PERCENT;
678 /* All UPs mapping to TC0 */
679 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
680 hw->dcb_info.prio_tc[i] = 0;
682 /* Initializing tc information */
683 memset(hw->dcb_info.tc_info, 0,
684 sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
685 for (i = 0; i < hw->dcb_info.num_tc; i++) {
686 hw->dcb_info.tc_info[i].tc_id = i;
687 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
688 hw->dcb_info.tc_info[i].pgid = 0;
689 hw->dcb_info.tc_info[i].bw_limit =
690 hw->dcb_info.pg_info[0].bw_limit;
697 hns3_dcb_lvl2_schd_mode_cfg(struct hns3_hw *hw)
699 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
700 struct hns3_pf *pf = &hns->pf;
703 /* Only being config on TC-Based scheduler mode */
704 if (pf->tx_sch_mode == HNS3_FLAG_VNET_BASE_SCH_MODE)
707 for (i = 0; i < hw->dcb_info.num_pg; i++) {
708 ret = hns3_dcb_pg_schd_mode_cfg(hw, i);
717 hns3_dcb_lvl34_schd_mode_cfg(struct hns3_hw *hw)
719 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
720 struct hns3_pf *pf = &hns->pf;
724 if (pf->tx_sch_mode == HNS3_FLAG_TC_BASE_SCH_MODE) {
725 for (i = 0; i < hw->dcb_info.num_tc; i++) {
726 ret = hns3_dcb_pri_schd_mode_cfg(hw, i);
730 ret = hns3_dcb_qs_schd_mode_cfg(hw, i,
741 hns3_dcb_schd_mode_cfg(struct hns3_hw *hw)
745 ret = hns3_dcb_lvl2_schd_mode_cfg(hw);
747 hns3_err(hw, "config lvl2_schd_mode failed: %d", ret);
751 ret = hns3_dcb_lvl34_schd_mode_cfg(hw);
753 hns3_err(hw, "config lvl34_schd_mode failed: %d", ret);
761 hns3_dcb_pri_tc_base_dwrr_cfg(struct hns3_hw *hw)
763 struct hns3_pg_info *pg_info;
767 for (i = 0; i < hw->dcb_info.num_tc; i++) {
768 pg_info = &hw->dcb_info.pg_info[hw->dcb_info.tc_info[i].pgid];
769 dwrr = pg_info->tc_dwrr[i];
771 ret = hns3_dcb_pri_weight_cfg(hw, i, dwrr);
773 hns3_err(hw, "fail to send priority weight cmd: %d", i);
777 ret = hns3_dcb_qs_weight_cfg(hw, i, BW_MAX_PERCENT);
779 hns3_err(hw, "fail to send qs_weight cmd: %d", i);
788 hns3_dcb_pri_dwrr_cfg(struct hns3_hw *hw)
790 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
791 struct hns3_pf *pf = &hns->pf;
794 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
797 ret = hns3_dcb_pri_tc_base_dwrr_cfg(hw);
801 if (!hns3_dev_dcb_supported(hw))
804 ret = hns3_dcb_ets_tc_dwrr_cfg(hw);
805 if (ret == -EOPNOTSUPP) {
806 hns3_warn(hw, "fw %08x does't support ets tc weight cmd",
815 hns3_dcb_pg_dwrr_cfg(struct hns3_hw *hw)
817 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
818 struct hns3_pf *pf = &hns->pf;
822 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
826 for (i = 0; i < hw->dcb_info.num_pg; i++) {
828 ret = hns3_dcb_pg_weight_cfg(hw, i, hw->dcb_info.pg_dwrr[i]);
837 hns3_dcb_dwrr_cfg(struct hns3_hw *hw)
841 ret = hns3_dcb_pg_dwrr_cfg(hw);
843 hns3_err(hw, "config pg_dwrr failed: %d", ret);
847 ret = hns3_dcb_pri_dwrr_cfg(hw);
849 hns3_err(hw, "config pri_dwrr failed: %d", ret);
857 hns3_dcb_shaper_cfg(struct hns3_hw *hw)
861 ret = hns3_dcb_port_shaper_cfg(hw);
863 hns3_err(hw, "config port shaper failed: %d", ret);
867 ret = hns3_dcb_pg_shaper_cfg(hw);
869 hns3_err(hw, "config pg shaper failed: %d", ret);
873 return hns3_dcb_pri_shaper_cfg(hw);
877 hns3_q_to_qs_map_cfg(struct hns3_hw *hw, uint16_t q_id, uint16_t qs_id)
879 struct hns3_nq_to_qs_link_cmd *map;
880 struct hns3_cmd_desc desc;
882 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_NQ_TO_QS_LINK, false);
884 map = (struct hns3_nq_to_qs_link_cmd *)desc.data;
886 map->nq_id = rte_cpu_to_le_16(q_id);
887 map->qset_id = rte_cpu_to_le_16(qs_id | HNS3_DCB_Q_QS_LINK_VLD_MSK);
889 return hns3_cmd_send(hw, &desc, 1);
893 hns3_q_to_qs_map(struct hns3_hw *hw)
895 struct hns3_tc_queue_info *tc_queue;
900 for (i = 0; i < hw->num_tc; i++) {
901 tc_queue = &hw->tc_queue[i];
902 for (j = 0; j < tc_queue->tqp_count; j++) {
903 q_id = tc_queue->tqp_offset + j;
904 ret = hns3_q_to_qs_map_cfg(hw, q_id, i);
914 hns3_pri_q_qs_cfg(struct hns3_hw *hw)
916 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
917 struct hns3_pf *pf = &hns->pf;
921 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE)
924 /* Cfg qs -> pri mapping */
925 for (i = 0; i < hw->num_tc; i++) {
926 ret = hns3_qs_to_pri_map_cfg(hw, i, i);
928 hns3_err(hw, "qs_to_pri mapping fail: %d", ret);
933 /* Cfg q -> qs mapping */
934 ret = hns3_q_to_qs_map(hw);
936 hns3_err(hw, "nq_to_qs mapping fail: %d", ret);
944 hns3_dcb_map_cfg(struct hns3_hw *hw)
948 ret = hns3_up_to_tc_map(hw);
950 hns3_err(hw, "up_to_tc mapping fail: %d", ret);
954 ret = hns3_pg_to_pri_map(hw);
956 hns3_err(hw, "pri_to_pg mapping fail: %d", ret);
960 return hns3_pri_q_qs_cfg(hw);
964 hns3_dcb_schd_setup_hw(struct hns3_hw *hw)
968 /* Cfg dcb mapping */
969 ret = hns3_dcb_map_cfg(hw);
974 ret = hns3_dcb_shaper_cfg(hw);
979 ret = hns3_dcb_dwrr_cfg(hw);
983 /* Cfg schd mode for each level schd */
984 return hns3_dcb_schd_mode_cfg(hw);
988 hns3_pause_param_cfg(struct hns3_hw *hw, const uint8_t *addr,
989 uint8_t pause_trans_gap, uint16_t pause_trans_time)
991 struct hns3_cfg_pause_param_cmd *pause_param;
992 struct hns3_cmd_desc desc;
994 pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
996 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, false);
998 memcpy(pause_param->mac_addr, addr, RTE_ETHER_ADDR_LEN);
999 memcpy(pause_param->mac_addr_extra, addr, RTE_ETHER_ADDR_LEN);
1000 pause_param->pause_trans_gap = pause_trans_gap;
1001 pause_param->pause_trans_time = rte_cpu_to_le_16(pause_trans_time);
1003 return hns3_cmd_send(hw, &desc, 1);
1007 hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr)
1009 struct hns3_cfg_pause_param_cmd *pause_param;
1010 struct hns3_cmd_desc desc;
1011 uint16_t trans_time;
1015 pause_param = (struct hns3_cfg_pause_param_cmd *)desc.data;
1017 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PARA, true);
1019 ret = hns3_cmd_send(hw, &desc, 1);
1023 trans_gap = pause_param->pause_trans_gap;
1024 trans_time = rte_le_to_cpu_16(pause_param->pause_trans_time);
1026 return hns3_pause_param_cfg(hw, mac_addr, trans_gap, trans_time);
1030 hns3_pause_param_setup_hw(struct hns3_hw *hw, uint16_t pause_time)
1032 #define PAUSE_TIME_DIV_BY 2
1033 #define PAUSE_TIME_MIN_VALUE 0x4
1035 struct hns3_mac *mac = &hw->mac;
1036 uint8_t pause_trans_gap;
1039 * Pause transmit gap must be less than "pause_time / 2", otherwise
1040 * the behavior of MAC is undefined.
1042 if (pause_time > PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1043 pause_trans_gap = HNS3_DEFAULT_PAUSE_TRANS_GAP;
1044 else if (pause_time >= PAUSE_TIME_MIN_VALUE &&
1045 pause_time <= PAUSE_TIME_DIV_BY * HNS3_DEFAULT_PAUSE_TRANS_GAP)
1046 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1048 hns3_warn(hw, "pause_time(%d) is adjusted to 4", pause_time);
1049 pause_time = PAUSE_TIME_MIN_VALUE;
1050 pause_trans_gap = pause_time / PAUSE_TIME_DIV_BY - 1;
1053 return hns3_pause_param_cfg(hw, mac->mac_addr,
1054 pause_trans_gap, pause_time);
1058 hns3_mac_pause_en_cfg(struct hns3_hw *hw, bool tx, bool rx)
1060 struct hns3_cmd_desc desc;
1062 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_MAC_PAUSE_EN, false);
1064 desc.data[0] = rte_cpu_to_le_32((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1065 (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1067 return hns3_cmd_send(hw, &desc, 1);
1071 hns3_pfc_pause_en_cfg(struct hns3_hw *hw, uint8_t pfc_bitmap, bool tx, bool rx)
1073 struct hns3_cmd_desc desc;
1074 struct hns3_pfc_en_cmd *pfc = (struct hns3_pfc_en_cmd *)desc.data;
1076 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PFC_PAUSE_EN, false);
1078 pfc->tx_rx_en_bitmap = (uint8_t)((tx ? HNS3_TX_MAC_PAUSE_EN_MSK : 0) |
1079 (rx ? HNS3_RX_MAC_PAUSE_EN_MSK : 0));
1081 pfc->pri_en_bitmap = pfc_bitmap;
1083 return hns3_cmd_send(hw, &desc, 1);
1087 hns3_qs_bp_cfg(struct hns3_hw *hw, uint8_t tc, uint8_t grp_id, uint32_t bit_map)
1089 struct hns3_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
1090 struct hns3_cmd_desc desc;
1092 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_BP_TO_QSET_MAPPING, false);
1094 bp_to_qs_map_cmd = (struct hns3_bp_to_qs_map_cmd *)desc.data;
1096 bp_to_qs_map_cmd->tc_id = tc;
1097 bp_to_qs_map_cmd->qs_group_id = grp_id;
1098 bp_to_qs_map_cmd->qs_bit_map = rte_cpu_to_le_32(bit_map);
1100 return hns3_cmd_send(hw, &desc, 1);
1104 hns3_get_rx_tx_en_status(struct hns3_hw *hw, bool *tx_en, bool *rx_en)
1106 switch (hw->current_mode) {
1111 case HNS3_FC_RX_PAUSE:
1115 case HNS3_FC_TX_PAUSE:
1131 hns3_mac_pause_setup_hw(struct hns3_hw *hw)
1135 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)
1136 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1142 return hns3_mac_pause_en_cfg(hw, tx_en, rx_en);
1146 hns3_pfc_setup_hw(struct hns3_hw *hw)
1150 if (hw->current_fc_status == HNS3_FC_STATUS_PFC)
1151 hns3_get_rx_tx_en_status(hw, &tx_en, &rx_en);
1157 return hns3_pfc_pause_en_cfg(hw, hw->dcb_info.pfc_en, tx_en, rx_en);
1161 * Each Tc has a 1024 queue sets to backpress, it divides to
1162 * 32 group, each group contains 32 queue sets, which can be
1163 * represented by uint32_t bitmap.
1166 hns3_bp_setup_hw(struct hns3_hw *hw, uint8_t tc)
1172 for (i = 0; i < HNS3_BP_GRP_NUM; i++) {
1173 uint8_t grp, sub_grp;
1176 grp = hns3_get_field(tc, HNS3_BP_GRP_ID_M, HNS3_BP_GRP_ID_S);
1177 sub_grp = hns3_get_field(tc, HNS3_BP_SUB_GRP_ID_M,
1178 HNS3_BP_SUB_GRP_ID_S);
1180 qs_bitmap |= (1 << sub_grp);
1182 ret = hns3_qs_bp_cfg(hw, tc, i, qs_bitmap);
1191 hns3_dcb_bp_setup(struct hns3_hw *hw)
1195 for (i = 0; i < hw->dcb_info.num_tc; i++) {
1196 ret = hns3_bp_setup_hw(hw, i);
1205 hns3_dcb_pause_setup_hw(struct hns3_hw *hw)
1207 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1208 struct hns3_pf *pf = &hns->pf;
1211 ret = hns3_pause_param_setup_hw(hw, pf->pause_time);
1213 hns3_err(hw, "Fail to set pause parameter. ret = %d", ret);
1217 ret = hns3_mac_pause_setup_hw(hw);
1219 hns3_err(hw, "Fail to setup MAC pause. ret = %d", ret);
1223 /* Only DCB-supported dev supports qset back pressure and pfc cmd */
1224 if (!hns3_dev_dcb_supported(hw))
1227 ret = hns3_pfc_setup_hw(hw);
1229 hns3_err(hw, "config pfc failed! ret = %d", ret);
1233 return hns3_dcb_bp_setup(hw);
1237 hns3_dcb_undrop_tc_map(struct hns3_hw *hw, uint8_t pfc_en)
1239 uint8_t pfc_map = 0;
1243 prio_tc = hw->dcb_info.prio_tc;
1244 for (i = 0; i < hw->dcb_info.num_tc; i++) {
1245 for (j = 0; j < HNS3_MAX_USER_PRIO; j++) {
1246 if (prio_tc[j] == i && pfc_en & BIT(j)) {
1257 hns3_dcb_cfg_validate(struct hns3_adapter *hns, uint8_t *tc, bool *changed)
1259 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1260 struct hns3_hw *hw = &hns->hw;
1265 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1266 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1267 if (dcb_rx_conf->dcb_tc[i] != hw->dcb_info.prio_tc[i])
1270 if (dcb_rx_conf->dcb_tc[i] > max_tc)
1271 max_tc = dcb_rx_conf->dcb_tc[i];
1274 if (*tc != hw->dcb_info.num_tc)
1278 * We ensure that dcb information can be reconfigured
1279 * after the hns3_priority_flow_ctrl_set function called.
1281 if (hw->current_mode != HNS3_FC_FULL)
1283 pfc_en = RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1284 if (hw->dcb_info.pfc_en != pfc_en)
1289 hns3_dcb_info_cfg(struct hns3_adapter *hns)
1291 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1292 struct hns3_pf *pf = &hns->pf;
1293 struct hns3_hw *hw = &hns->hw;
1294 uint8_t tc_bw, bw_rest;
1297 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1298 pf->local_max_tc = (uint8_t)dcb_rx_conf->nb_tcs;
1299 pf->pfc_max = (uint8_t)dcb_rx_conf->nb_tcs;
1302 memset(hw->dcb_info.pg_info, 0,
1303 sizeof(struct hns3_pg_info) * HNS3_PG_NUM);
1304 hw->dcb_info.pg_dwrr[0] = BW_MAX_PERCENT;
1305 hw->dcb_info.pg_info[0].pg_id = 0;
1306 hw->dcb_info.pg_info[0].pg_sch_mode = HNS3_SCH_MODE_DWRR;
1307 hw->dcb_info.pg_info[0].bw_limit = HNS3_ETHER_MAX_RATE;
1308 hw->dcb_info.pg_info[0].tc_bit_map = hw->hw_tc_map;
1310 /* Each tc has same bw for valid tc by default */
1311 tc_bw = BW_MAX_PERCENT / hw->dcb_info.num_tc;
1312 for (i = 0; i < hw->dcb_info.num_tc; i++)
1313 hw->dcb_info.pg_info[0].tc_dwrr[i] = tc_bw;
1314 /* To ensure the sum of tc_dwrr is equal to 100 */
1315 bw_rest = BW_MAX_PERCENT % hw->dcb_info.num_tc;
1316 for (j = 0; j < bw_rest; j++)
1317 hw->dcb_info.pg_info[0].tc_dwrr[j]++;
1318 for (; i < dcb_rx_conf->nb_tcs; i++)
1319 hw->dcb_info.pg_info[0].tc_dwrr[i] = 0;
1321 /* All tcs map to pg0 */
1322 memset(hw->dcb_info.tc_info, 0,
1323 sizeof(struct hns3_tc_info) * HNS3_MAX_TC_NUM);
1324 for (i = 0; i < hw->dcb_info.num_tc; i++) {
1325 hw->dcb_info.tc_info[i].tc_id = i;
1326 hw->dcb_info.tc_info[i].tc_sch_mode = HNS3_SCH_MODE_DWRR;
1327 hw->dcb_info.tc_info[i].pgid = 0;
1328 hw->dcb_info.tc_info[i].bw_limit =
1329 hw->dcb_info.pg_info[0].bw_limit;
1332 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
1333 hw->dcb_info.prio_tc[i] = dcb_rx_conf->dcb_tc[i];
1335 hns3_dcb_update_tc_queue_mapping(hw, hw->data->nb_rx_queues,
1336 hw->data->nb_tx_queues);
1340 hns3_dcb_info_update(struct hns3_adapter *hns, uint8_t num_tc)
1342 struct hns3_pf *pf = &hns->pf;
1343 struct hns3_hw *hw = &hns->hw;
1344 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1345 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1346 uint8_t bit_map = 0;
1349 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1350 hw->dcb_info.num_pg != 1)
1353 if (nb_rx_q < num_tc) {
1354 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1359 if (nb_tx_q < num_tc) {
1360 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1365 /* Currently not support uncontinuous tc */
1366 hw->dcb_info.num_tc = num_tc;
1367 for (i = 0; i < hw->dcb_info.num_tc; i++)
1372 hw->dcb_info.num_tc = 1;
1374 hw->hw_tc_map = bit_map;
1375 hns3_dcb_info_cfg(hns);
1381 hns3_dcb_hw_configure(struct hns3_adapter *hns)
1383 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1384 struct hns3_pf *pf = &hns->pf;
1385 struct hns3_hw *hw = &hns->hw;
1386 enum hns3_fc_status fc_status = hw->current_fc_status;
1387 enum hns3_fc_mode current_mode = hw->current_mode;
1388 uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1391 if (pf->tx_sch_mode != HNS3_FLAG_TC_BASE_SCH_MODE &&
1392 pf->tx_sch_mode != HNS3_FLAG_VNET_BASE_SCH_MODE)
1395 ret = hns3_dcb_schd_setup_hw(hw);
1397 hns3_err(hw, "dcb schdule configure failed! ret = %d", ret);
1401 if (hw->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
1402 dcb_rx_conf = &hw->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1403 if (dcb_rx_conf->nb_tcs == 0)
1404 hw->dcb_info.pfc_en = 1; /* tc0 only */
1406 hw->dcb_info.pfc_en =
1407 RTE_LEN2MASK((uint8_t)dcb_rx_conf->nb_tcs, uint8_t);
1409 hw->dcb_info.hw_pfc_map =
1410 hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1412 ret = hns3_buffer_alloc(hw);
1416 hw->current_fc_status = HNS3_FC_STATUS_PFC;
1417 hw->current_mode = HNS3_FC_FULL;
1418 ret = hns3_dcb_pause_setup_hw(hw);
1420 hns3_err(hw, "setup pfc failed! ret = %d", ret);
1421 goto pfc_setup_fail;
1425 * Although dcb_capability_en is lack of ETH_DCB_PFC_SUPPORT
1426 * flag, the DCB information is configured, such as tc numbers.
1427 * Therefore, refreshing the allocation of packet buffer is
1430 ret = hns3_buffer_alloc(hw);
1438 hw->current_mode = current_mode;
1439 hw->current_fc_status = fc_status;
1440 hw->dcb_info.hw_pfc_map = hw_pfc_map;
1441 status = hns3_buffer_alloc(hw);
1443 hns3_err(hw, "recover packet buffer fail! status = %d", status);
1449 * hns3_dcb_configure - setup dcb related config
1450 * @hns: pointer to hns3 adapter
1451 * Returns 0 on success, negative value on failure.
1454 hns3_dcb_configure(struct hns3_adapter *hns)
1456 struct hns3_hw *hw = &hns->hw;
1457 bool map_changed = false;
1461 hns3_dcb_cfg_validate(hns, &num_tc, &map_changed);
1462 if (map_changed || rte_atomic16_read(&hw->reset.resetting)) {
1463 ret = hns3_dcb_info_update(hns, num_tc);
1465 hns3_err(hw, "dcb info update failed: %d", ret);
1469 ret = hns3_dcb_hw_configure(hns);
1471 hns3_err(hw, "dcb sw configure failed: %d", ret);
1480 hns3_dcb_init_hw(struct hns3_hw *hw)
1484 ret = hns3_dcb_schd_setup_hw(hw);
1486 hns3_err(hw, "dcb schedule setup failed: %d", ret);
1490 ret = hns3_dcb_pause_setup_hw(hw);
1492 hns3_err(hw, "PAUSE setup failed: %d", ret);
1498 hns3_dcb_init(struct hns3_hw *hw)
1500 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1501 struct hns3_pf *pf = &hns->pf;
1504 PMD_INIT_FUNC_TRACE();
1507 * According to the 'adapter_state' identifier, the following branch
1508 * is only executed to initialize default configurations of dcb during
1509 * the initializing driver process. Due to driver saving dcb-related
1510 * information before reset triggered, the reinit dev stage of the
1511 * reset process can not access to the branch, or those information
1514 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) {
1515 hw->requested_mode = HNS3_FC_NONE;
1516 hw->current_mode = hw->requested_mode;
1517 pf->pause_time = HNS3_DEFAULT_PAUSE_TRANS_TIME;
1518 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1520 ret = hns3_dcb_info_init(hw);
1522 hns3_err(hw, "dcb info init failed: %d", ret);
1525 hns3_dcb_update_tc_queue_mapping(hw, hw->tqps_num,
1530 * DCB hardware will be configured by following the function during
1531 * the initializing driver process and the reset process. However,
1532 * driver will restore directly configurations of dcb hardware based
1533 * on dcb-related information soft maintained when driver
1534 * initialization has finished and reset is coming.
1536 ret = hns3_dcb_init_hw(hw);
1538 hns3_err(hw, "dcb init hardware failed: %d", ret);
1546 hns3_update_queue_map_configure(struct hns3_adapter *hns)
1548 struct hns3_hw *hw = &hns->hw;
1549 uint16_t nb_rx_q = hw->data->nb_rx_queues;
1550 uint16_t nb_tx_q = hw->data->nb_tx_queues;
1553 hns3_dcb_update_tc_queue_mapping(hw, nb_rx_q, nb_tx_q);
1554 ret = hns3_q_to_qs_map(hw);
1556 hns3_err(hw, "failed to map nq to qs! ret = %d", ret);
1564 hns3_dcb_cfg_update(struct hns3_adapter *hns)
1566 struct hns3_hw *hw = &hns->hw;
1567 enum rte_eth_rx_mq_mode mq_mode = hw->data->dev_conf.rxmode.mq_mode;
1570 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
1571 ret = hns3_dcb_configure(hns);
1573 hns3_err(hw, "Failed to config dcb: %d", ret);
1578 * Update queue map without PFC configuration,
1579 * due to queues reconfigured by user.
1581 ret = hns3_update_queue_map_configure(hns);
1584 "Failed to update queue mapping configure: %d",
1592 * hns3_dcb_pfc_enable - Enable priority flow control
1593 * @dev: pointer to ethernet device
1595 * Configures the pfc settings for one porority.
1598 hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
1600 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1601 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1602 enum hns3_fc_status fc_status = hw->current_fc_status;
1603 enum hns3_fc_mode current_mode = hw->current_mode;
1604 uint8_t hw_pfc_map = hw->dcb_info.hw_pfc_map;
1605 uint8_t pfc_en = hw->dcb_info.pfc_en;
1606 uint8_t priority = pfc_conf->priority;
1607 uint16_t pause_time = pf->pause_time;
1610 pf->pause_time = pfc_conf->fc.pause_time;
1611 hw->current_mode = hw->requested_mode;
1612 hw->current_fc_status = HNS3_FC_STATUS_PFC;
1613 hw->dcb_info.pfc_en |= BIT(priority);
1614 hw->dcb_info.hw_pfc_map =
1615 hns3_dcb_undrop_tc_map(hw, hw->dcb_info.pfc_en);
1616 ret = hns3_buffer_alloc(hw);
1618 goto pfc_setup_fail;
1621 * The flow control mode of all UPs will be changed based on
1622 * current_mode coming from user.
1624 ret = hns3_dcb_pause_setup_hw(hw);
1626 hns3_err(hw, "enable pfc failed! ret = %d", ret);
1627 goto pfc_setup_fail;
1633 hw->current_mode = current_mode;
1634 hw->current_fc_status = fc_status;
1635 pf->pause_time = pause_time;
1636 hw->dcb_info.pfc_en = pfc_en;
1637 hw->dcb_info.hw_pfc_map = hw_pfc_map;
1638 status = hns3_buffer_alloc(hw);
1640 hns3_err(hw, "recover packet buffer fail: %d", status);
1646 * hns3_fc_enable - Enable MAC pause
1647 * @dev: pointer to ethernet device
1649 * Configures the MAC pause settings.
1652 hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1654 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1656 enum hns3_fc_status fc_status = hw->current_fc_status;
1657 enum hns3_fc_mode current_mode = hw->current_mode;
1658 uint16_t pause_time = pf->pause_time;
1661 pf->pause_time = fc_conf->pause_time;
1662 hw->current_mode = hw->requested_mode;
1665 * In fact, current_fc_status is HNS3_FC_STATUS_NONE when mode
1666 * of flow control is configured to be HNS3_FC_NONE.
1668 if (hw->current_mode == HNS3_FC_NONE)
1669 hw->current_fc_status = HNS3_FC_STATUS_NONE;
1671 hw->current_fc_status = HNS3_FC_STATUS_MAC_PAUSE;
1673 ret = hns3_dcb_pause_setup_hw(hw);
1675 hns3_err(hw, "enable MAC Pause failed! ret = %d", ret);
1682 hw->current_mode = current_mode;
1683 hw->current_fc_status = fc_status;
1684 pf->pause_time = pause_time;