1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
8 #define HNS3_ETHER_MAX_RATE 100000
11 #define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
12 #define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
14 #define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18
15 #define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
18 #define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0)
19 #define HNS3_DCB_TX_SCHD_SP_MSK (0xFE)
21 enum hns3_shap_bucket {
22 HNS3_DCB_SHAP_C_BUCKET = 0,
23 HNS3_DCB_SHAP_P_BUCKET,
26 struct hns3_priority_weight_cmd {
31 struct hns3_qs_weight_cmd {
36 struct hns3_pg_weight_cmd {
41 struct hns3_ets_tc_weight_cmd {
42 uint8_t tc_weight[HNS3_MAX_TC_NUM];
43 uint8_t weight_offset;
47 struct hns3_qs_to_pri_link_cmd {
51 #define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
55 struct hns3_nq_to_qs_link_cmd {
58 #define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
62 #define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
63 #define HNS3_DCB_SHAP_IR_B_LSH 0
64 #define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
65 #define HNS3_DCB_SHAP_IR_U_LSH 8
66 #define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
67 #define HNS3_DCB_SHAP_IR_S_LSH 12
68 #define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
69 #define HNS3_DCB_SHAP_BS_B_LSH 16
70 #define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
71 #define HNS3_DCB_SHAP_BS_S_LSH 21
73 struct hns3_pri_shapping_cmd {
76 uint32_t pri_shapping_para;
79 struct hns3_pg_shapping_cmd {
82 uint32_t pg_shapping_para;
85 #define HNS3_BP_GRP_NUM 32
86 #define HNS3_BP_SUB_GRP_ID_S 0
87 #define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
88 #define HNS3_BP_GRP_ID_S 5
89 #define HNS3_BP_GRP_ID_M GENMASK(9, 5)
90 struct hns3_bp_to_qs_map_cmd {
98 struct hns3_pfc_en_cmd {
99 uint8_t tx_rx_en_bitmap;
100 uint8_t pri_en_bitmap;
103 struct hns3_port_shapping_cmd {
104 uint32_t port_shapping_para;
107 struct hns3_cfg_pause_param_cmd {
108 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
109 uint8_t pause_trans_gap;
111 uint16_t pause_trans_time;
113 /* extra mac address to do double check for pause frame */
114 uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN];
118 struct hns3_pg_to_pri_link_cmd {
124 enum hns3_shaper_level {
125 HNS3_SHAPER_LVL_PRI = 0,
126 HNS3_SHAPER_LVL_PG = 1,
127 HNS3_SHAPER_LVL_PORT = 2,
128 HNS3_SHAPER_LVL_QSET = 3,
129 HNS3_SHAPER_LVL_CNT = 4,
130 HNS3_SHAPER_LVL_VF = 0,
131 HNS3_SHAPER_LVL_PF = 1,
134 struct hns3_shaper_parameter {
135 uint32_t ir_b; /* IR_B parameter of IR shaper */
136 uint32_t ir_u; /* IR_U parameter of IR shaper */
137 uint32_t ir_s; /* IR_S parameter of IR shaper */
140 #define hns3_dcb_set_field(dest, string, val) \
141 hns3_set_field((dest), \
142 (HNS3_DCB_SHAP_##string##_MSK), \
143 (HNS3_DCB_SHAP_##string##_LSH), val)
144 #define hns3_dcb_get_field(src, string) \
145 hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \
146 (HNS3_DCB_SHAP_##string##_LSH))
148 int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr);
150 int hns3_dcb_configure(struct hns3_adapter *hns);
152 int hns3_dcb_init(struct hns3_hw *hw);
154 int hns3_dcb_init_hw(struct hns3_hw *hw);
156 int hns3_dcb_info_init(struct hns3_hw *hw);
159 hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
162 hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf);
164 void hns3_set_rss_size(struct hns3_hw *hw, uint16_t nb_rx_q);
166 void hns3_tc_queue_mapping_cfg(struct hns3_hw *hw, uint16_t nb_queue);
168 int hns3_dcb_cfg_update(struct hns3_adapter *hns);
170 #endif /* _HNS3_DCB_H_ */