1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
9 #define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
10 #define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
12 #define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18
13 #define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
16 #define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0)
17 #define HNS3_DCB_TX_SCHD_SP_MSK (0xFE)
19 enum hns3_shap_bucket {
20 HNS3_DCB_SHAP_C_BUCKET = 0,
21 HNS3_DCB_SHAP_P_BUCKET,
24 struct hns3_priority_weight_cmd {
29 struct hns3_qs_weight_cmd {
34 struct hns3_pg_weight_cmd {
39 struct hns3_ets_tc_weight_cmd {
40 uint8_t tc_weight[HNS3_MAX_TC_NUM];
41 uint8_t weight_offset;
45 struct hns3_qs_to_pri_link_cmd {
49 #define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
53 struct hns3_nq_to_qs_link_cmd {
56 #define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
60 #define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
61 #define HNS3_DCB_SHAP_IR_B_LSH 0
62 #define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
63 #define HNS3_DCB_SHAP_IR_U_LSH 8
64 #define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
65 #define HNS3_DCB_SHAP_IR_S_LSH 12
66 #define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
67 #define HNS3_DCB_SHAP_BS_B_LSH 16
68 #define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
69 #define HNS3_DCB_SHAP_BS_S_LSH 21
71 struct hns3_pri_shapping_cmd {
74 uint32_t pri_shapping_para;
77 struct hns3_pg_shapping_cmd {
80 uint32_t pg_shapping_para;
83 #define HNS3_BP_GRP_NUM 32
84 #define HNS3_BP_SUB_GRP_ID_S 0
85 #define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
86 #define HNS3_BP_GRP_ID_S 5
87 #define HNS3_BP_GRP_ID_M GENMASK(9, 5)
88 struct hns3_bp_to_qs_map_cmd {
96 struct hns3_pfc_en_cmd {
97 uint8_t tx_rx_en_bitmap;
98 uint8_t pri_en_bitmap;
101 struct hns3_port_shapping_cmd {
102 uint32_t port_shapping_para;
105 struct hns3_cfg_pause_param_cmd {
106 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
107 uint8_t pause_trans_gap;
109 uint16_t pause_trans_time;
111 /* extra mac address to do double check for pause frame */
112 uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN];
116 struct hns3_pg_to_pri_link_cmd {
122 enum hns3_shaper_level {
123 HNS3_SHAPER_LVL_PRI = 0,
124 HNS3_SHAPER_LVL_PG = 1,
125 HNS3_SHAPER_LVL_PORT = 2,
126 HNS3_SHAPER_LVL_QSET = 3,
127 HNS3_SHAPER_LVL_CNT = 4,
128 HNS3_SHAPER_LVL_VF = 0,
129 HNS3_SHAPER_LVL_PF = 1,
132 struct hns3_shaper_parameter {
133 uint32_t ir_b; /* IR_B parameter of IR shaper */
134 uint32_t ir_u; /* IR_U parameter of IR shaper */
135 uint32_t ir_s; /* IR_S parameter of IR shaper */
138 #define hns3_dcb_set_field(dest, string, val) \
139 hns3_set_field((dest), \
140 (HNS3_DCB_SHAP_##string##_MSK), \
141 (HNS3_DCB_SHAP_##string##_LSH), val)
142 #define hns3_dcb_get_field(src, string) \
143 hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \
144 (HNS3_DCB_SHAP_##string##_LSH))
146 int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr);
148 int hns3_dcb_configure(struct hns3_adapter *hns);
150 int hns3_dcb_init(struct hns3_hw *hw);
152 int hns3_dcb_init_hw(struct hns3_hw *hw);
154 int hns3_dcb_info_init(struct hns3_hw *hw);
157 hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
160 hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf);
162 void hns3_set_rss_size(struct hns3_hw *hw, uint16_t nb_rx_q);
164 void hns3_tc_queue_mapping_cfg(struct hns3_hw *hw, uint16_t nb_queue);
166 int hns3_dcb_cfg_update(struct hns3_adapter *hns);
168 #endif /* _HNS3_DCB_H_ */