1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
12 #define HNS3_ETHER_MAX_RATE 100000
15 #define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0)
16 #define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1)
18 #define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18
19 #define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
22 #define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0)
23 #define HNS3_DCB_TX_SCHD_SP_MSK 0xFE
25 enum hns3_shap_bucket {
26 HNS3_DCB_SHAP_C_BUCKET = 0,
27 HNS3_DCB_SHAP_P_BUCKET,
30 struct hns3_priority_weight_cmd {
36 struct hns3_qs_weight_cmd {
42 struct hns3_pg_weight_cmd {
48 struct hns3_ets_tc_weight_cmd {
49 uint8_t tc_weight[HNS3_MAX_TC_NUM];
50 uint8_t weight_offset;
54 struct hns3_qs_to_pri_link_cmd {
58 #define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0)
59 #define HNS3_DCB_QS_ID_L_MSK GENMASK(9, 0)
60 #define HNS3_DCB_QS_ID_L_S 0
61 #define HNS3_DCB_QS_ID_H_MSK GENMASK(14, 10)
62 #define HNS3_DCB_QS_ID_H_S 10
63 #define HNS3_DCB_QS_ID_H_EXT_S 11
64 #define HNS3_DCB_QS_ID_H_EXT_MSK GENMASK(15, 11)
69 struct hns3_nq_to_qs_link_cmd {
72 #define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10)
77 #define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0)
78 #define HNS3_DCB_SHAP_IR_B_LSH 0
79 #define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8)
80 #define HNS3_DCB_SHAP_IR_U_LSH 8
81 #define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12)
82 #define HNS3_DCB_SHAP_IR_S_LSH 12
83 #define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16)
84 #define HNS3_DCB_SHAP_BS_B_LSH 16
85 #define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21)
86 #define HNS3_DCB_SHAP_BS_S_LSH 21
89 * For more flexible selection of shapping algorithm in different network
90 * engine, the algorithm calculating shapping parameter is moved to firmware to
91 * execute. Bit HNS3_TM_RATE_VLD_B of flag field in hns3_pri_shapping_cmd,
92 * hns3_pg_shapping_cmd or hns3_port_shapping_cmd is set to 1 to require
93 * firmware to recalculate shapping parameters. However, whether the parameters
94 * are recalculated depends on the firmware version. If firmware doesn't support
95 * the calculation of shapping parameters, such as on network engine with
96 * revision id 0x21, the value driver calculated will be used to configure to
97 * hardware. On the contrary, firmware ignores configuration of driver
98 * and recalculates the parameter.
100 #define HNS3_TM_RATE_VLD_B 0
102 struct hns3_pri_shapping_cmd {
105 uint32_t pri_shapping_para;
108 uint32_t pri_rate; /* Unit Mbps */
112 struct hns3_pg_shapping_cmd {
115 uint32_t pg_shapping_para;
118 uint32_t pg_rate; /* Unit Mbps */
122 struct hns3_port_shapping_cmd {
123 uint32_t port_shapping_para;
126 uint32_t port_rate; /* Unit Mbps */
130 #define HNS3_BP_GRP_NUM 32
131 #define HNS3_BP_SUB_GRP_ID_S 0
132 #define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0)
133 #define HNS3_BP_GRP_ID_S 5
134 #define HNS3_BP_GRP_ID_M GENMASK(9, 5)
136 struct hns3_bp_to_qs_map_cmd {
144 struct hns3_pfc_en_cmd {
145 uint8_t tx_rx_en_bitmap;
146 uint8_t pri_en_bitmap;
150 struct hns3_cfg_pause_param_cmd {
151 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
152 uint8_t pause_trans_gap;
154 uint16_t pause_trans_time;
156 /* extra mac address to do double check for pause frame */
157 uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN];
161 struct hns3_pg_to_pri_link_cmd {
168 enum hns3_shaper_level {
169 HNS3_SHAPER_LVL_PRI = 0,
170 HNS3_SHAPER_LVL_PG = 1,
171 HNS3_SHAPER_LVL_PORT = 2,
172 HNS3_SHAPER_LVL_QSET = 3,
173 HNS3_SHAPER_LVL_CNT = 4,
174 HNS3_SHAPER_LVL_VF = 0,
175 HNS3_SHAPER_LVL_PF = 1,
178 struct hns3_shaper_parameter {
179 uint32_t ir_b; /* IR_B parameter of IR shaper */
180 uint32_t ir_u; /* IR_U parameter of IR shaper */
181 uint32_t ir_s; /* IR_S parameter of IR shaper */
184 #define hns3_dcb_set_field(dest, string, val) \
185 hns3_set_field((dest), \
186 (HNS3_DCB_SHAP_##string##_MSK), \
187 (HNS3_DCB_SHAP_##string##_LSH), val)
188 #define hns3_dcb_get_field(src, string) \
189 hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \
190 (HNS3_DCB_SHAP_##string##_LSH))
192 int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr);
194 int hns3_dcb_configure(struct hns3_adapter *hns);
196 int hns3_dcb_init(struct hns3_hw *hw);
198 int hns3_dcb_init_hw(struct hns3_hw *hw);
200 int hns3_dcb_info_init(struct hns3_hw *hw);
202 int hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
204 int hns3_dcb_pfc_enable(struct rte_eth_dev *dev,
205 struct rte_eth_pfc_conf *pfc_conf);
207 int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
210 int hns3_update_queue_map_configure(struct hns3_adapter *hns);
211 int hns3_port_shaper_update(struct hns3_hw *hw, uint32_t speed);
212 uint8_t hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no);
214 #endif /* _HNS3_DCB_H_ */