drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <rte_ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_INVALID_PVID               0xFFFF
  24
  25 #define HNS3_FILTER_TYPE_VF             0
  26 #define HNS3_FILTER_TYPE_PORT           1
  27 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  28 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  29 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  30 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  31 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  32 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  34 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  35                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  36
  37 /* Reset related Registers */
  38 #define HNS3_GLOBAL_RESET_BIT           0
  39 #define HNS3_CORE_RESET_BIT             1
  40 #define HNS3_IMP_RESET_BIT              2
  41 #define HNS3_FUN_RST_ING_B              0
  42
  43 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  45 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  47
  48 #define HNS3_RESET_WAIT_MS      100
  49 #define HNS3_RESET_WAIT_CNT     200
  50
  51 /* FEC mode order defined in HNS3 hardware */
  52 #define HNS3_HW_FEC_MODE_NOFEC  0
  53 #define HNS3_HW_FEC_MODE_BASER  1
  54 #define HNS3_HW_FEC_MODE_RS     2
  55
  56 enum hns3_evt_cause {
  57         HNS3_VECTOR0_EVENT_RST,
  58         HNS3_VECTOR0_EVENT_MBX,
  59         HNS3_VECTOR0_EVENT_ERR,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  97
  98 static int hns3_add_mc_addr(struct hns3_hw *hw,
  99                             struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 101                             struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct rte_eth_dev *dev);
 104
 105 static void
 106 hns3_pf_disable_irq0(struct hns3_hw *hw)
 107 {
 108         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 109 }
 110
 111 static void
 112 hns3_pf_enable_irq0(struct hns3_hw *hw)
 113 {
 114         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 115 }
 116
 117 static enum hns3_evt_cause
 118 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 119 {
 120         struct hns3_hw *hw = &hns->hw;
 121         uint32_t vector0_int_stats;
 122         uint32_t cmdq_src_val;
 123         uint32_t hw_err_src_reg;
 124         uint32_t val;
 125         enum hns3_evt_cause ret;
 126
 127         /* fetch the events from their corresponding regs */
 128         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 129         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 130         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 131
 132         /*
 133          * Assumption: If by any chance reset and mailbox events are reported
 134          * together then we will only process reset event and defer the
 135          * processing of the mailbox events. Since, we would have not cleared
 136          * RX CMDQ event this time we would receive again another interrupt
 137          * from H/W just for the mailbox.
 138          */
 139         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 140                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 141                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 142                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 143                 if (clearval) {
 144                         hw->reset.stats.imp_cnt++;
 145                         hns3_warn(hw, "IMP reset detected, clear reset status");
 146                 } else {
 147                         hns3_schedule_delayed_reset(hns);
 148                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 149                 }
 150
 151                 ret = HNS3_VECTOR0_EVENT_RST;
 152                 goto out;
 153         }
 154
 155         /* Global reset */
 156         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 157                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 158                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 159                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 160                 if (clearval) {
 161                         hw->reset.stats.global_cnt++;
 162                         hns3_warn(hw, "Global reset detected, clear reset status");
 163                 } else {
 164                         hns3_schedule_delayed_reset(hns);
 165                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 166                 }
 167
 168                 ret = HNS3_VECTOR0_EVENT_RST;
 169                 goto out;
 170         }
 171
 172         /* check for vector0 msix event source */
 173         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 174             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 175                 val = vector0_int_stats | hw_err_src_reg;
 176                 ret = HNS3_VECTOR0_EVENT_ERR;
 177                 goto out;
 178         }
 179
 180         /* check for vector0 mailbox(=CMDQ RX) event source */
 181         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 182                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 183                 val = cmdq_src_val;
 184                 ret = HNS3_VECTOR0_EVENT_MBX;
 185                 goto out;
 186         }
 187
 188         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 189                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 190                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 191         val = vector0_int_stats;
 192         ret = HNS3_VECTOR0_EVENT_OTHER;
 193 out:
 194
 195         if (clearval)
 196                 *clearval = val;
 197         return ret;
 198 }
 199
 200 static void
 201 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 202 {
 203         if (event_type == HNS3_VECTOR0_EVENT_RST)
 204                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 205         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 206                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 207 }
 208
 209 static void
 210 hns3_clear_all_event_cause(struct hns3_hw *hw)
 211 {
 212         uint32_t vector0_int_stats;
 213         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 214
 215         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 216                 hns3_warn(hw, "Probe during IMP reset interrupt");
 217
 218         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 219                 hns3_warn(hw, "Probe during Global reset interrupt");
 220
 221         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 222                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 223                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 224                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 225         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 226 }
 227
 228 static void
 229 hns3_interrupt_handler(void *param)
 230 {
 231         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 232         struct hns3_adapter *hns = dev->data->dev_private;
 233         struct hns3_hw *hw = &hns->hw;
 234         enum hns3_evt_cause event_cause;
 235         uint32_t clearval = 0;
 236
 237         /* Disable interrupt */
 238         hns3_pf_disable_irq0(hw);
 239
 240         event_cause = hns3_check_event_cause(hns, &clearval);
 241         /* vector 0 interrupt is shared with reset and mailbox source events. */
 242         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 243                 hns3_warn(hw, "Received err interrupt");
 244                 hns3_handle_msix_error(hns, &hw->reset.request);
 245                 hns3_handle_ras_error(hns, &hw->reset.request);
 246                 hns3_schedule_reset(hns);
 247         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 248                 hns3_warn(hw, "Received reset interrupt");
 249                 hns3_schedule_reset(hns);
 250         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 251                 hns3_dev_handle_mbx_msg(hw);
 252         else
 253                 hns3_err(hw, "Received unknown event");
 254
 255         hns3_clear_event_cause(hw, event_cause, clearval);
 256         /* Enable interrupt if it is not cause by reset */
 257         hns3_pf_enable_irq0(hw);
 258 }
 259
 260 static int
 261 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 262 {
 263 #define HNS3_VLAN_ID_OFFSET_STEP        160
 264 #define HNS3_VLAN_BYTE_SIZE             8
 265         struct hns3_vlan_filter_pf_cfg_cmd *req;
 266         struct hns3_hw *hw = &hns->hw;
 267         uint8_t vlan_offset_byte_val;
 268         struct hns3_cmd_desc desc;
 269         uint8_t vlan_offset_byte;
 270         uint8_t vlan_offset_base;
 271         int ret;
 272
 273         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 274
 275         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 276         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 277                            HNS3_VLAN_BYTE_SIZE;
 278         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 279
 280         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 281         req->vlan_offset = vlan_offset_base;
 282         req->vlan_cfg = on ? 0 : 1;
 283         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 284
 285         ret = hns3_cmd_send(hw, &desc, 1);
 286         if (ret)
 287                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 288                          vlan_id, ret);
 289
 290         return ret;
 291 }
 292
 293 static void
 294 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 295 {
 296         struct hns3_user_vlan_table *vlan_entry;
 297         struct hns3_pf *pf = &hns->pf;
 298
 299         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 300                 if (vlan_entry->vlan_id == vlan_id) {
 301                         if (vlan_entry->hd_tbl_status)
 302                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 303                         LIST_REMOVE(vlan_entry, next);
 304                         rte_free(vlan_entry);
 305                         break;
 306                 }
 307         }
 308 }
 309
 310 static void
 311 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 312                         bool writen_to_tbl)
 313 {
 314         struct hns3_user_vlan_table *vlan_entry;
 315         struct hns3_hw *hw = &hns->hw;
 316         struct hns3_pf *pf = &hns->pf;
 317
 318         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 319                 if (vlan_entry->vlan_id == vlan_id)
 320                         return;
 321         }
 322
 323         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 324         if (vlan_entry == NULL) {
 325                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 326                 return;
 327         }
 328
 329         vlan_entry->hd_tbl_status = writen_to_tbl;
 330         vlan_entry->vlan_id = vlan_id;
 331
 332         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 333 }
 334
 335 static int
 336 hns3_restore_vlan_table(struct hns3_adapter *hns)
 337 {
 338         struct hns3_user_vlan_table *vlan_entry;
 339         struct hns3_hw *hw = &hns->hw;
 340         struct hns3_pf *pf = &hns->pf;
 341         uint16_t vlan_id;
 342         int ret = 0;
 343
 344         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 345                 return hns3_vlan_pvid_configure(hns,
 346                                                 hw->port_base_vlan_cfg.pvid, 1);
 347
 348         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 349                 if (vlan_entry->hd_tbl_status) {
 350                         vlan_id = vlan_entry->vlan_id;
 351                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 352                         if (ret)
 353                                 break;
 354                 }
 355         }
 356
 357         return ret;
 358 }
 359
 360 static int
 361 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 362 {
 363         struct hns3_hw *hw = &hns->hw;
 364         bool writen_to_tbl = false;
 365         int ret = 0;
 366
 367         /*
 368          * When vlan filter is enabled, hardware regards packets without vlan
 369          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 370          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 371          */
 372         if (on == 0 && vlan_id == 0)
 373                 return 0;
 374
 375         /*
 376          * When port base vlan enabled, we use port base vlan as the vlan
 377          * filter condition. In this case, we don't update vlan filter table
 378          * when user add new vlan or remove exist vlan, just update the
 379          * vlan list. The vlan id in vlan list will be writen in vlan filter
 380          * table until port base vlan disabled
 381          */
 382         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 383                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 384                 writen_to_tbl = true;
 385         }
 386
 387         if (ret == 0) {
 388                 if (on)
 389                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 390                 else
 391                         hns3_rm_dev_vlan_table(hns, vlan_id);
 392         }
 393         return ret;
 394 }
 395
 396 static int
 397 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 398 {
 399         struct hns3_adapter *hns = dev->data->dev_private;
 400         struct hns3_hw *hw = &hns->hw;
 401         int ret;
 402
 403         rte_spinlock_lock(&hw->lock);
 404         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 405         rte_spinlock_unlock(&hw->lock);
 406         return ret;
 407 }
 408
 409 static int
 410 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 411                          uint16_t tpid)
 412 {
 413         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 414         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 415         struct hns3_hw *hw = &hns->hw;
 416         struct hns3_cmd_desc desc;
 417         int ret;
 418
 419         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 420              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 421                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 422                 return -EINVAL;
 423         }
 424
 425         if (tpid != RTE_ETHER_TYPE_VLAN) {
 426                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 427                 return -EINVAL;
 428         }
 429
 430         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 431         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 432
 433         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 434                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 435                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 436         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 437                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 438                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 439                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 440                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 441         }
 442
 443         ret = hns3_cmd_send(hw, &desc, 1);
 444         if (ret) {
 445                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 446                          ret);
 447                 return ret;
 448         }
 449
 450         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 451
 452         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 453         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 454         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 455
 456         ret = hns3_cmd_send(hw, &desc, 1);
 457         if (ret)
 458                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 459                          ret);
 460         return ret;
 461 }
 462
 463 static int
 464 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 465                    uint16_t tpid)
 466 {
 467         struct hns3_adapter *hns = dev->data->dev_private;
 468         struct hns3_hw *hw = &hns->hw;
 469         int ret;
 470
 471         rte_spinlock_lock(&hw->lock);
 472         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 473         rte_spinlock_unlock(&hw->lock);
 474         return ret;
 475 }
 476
 477 static int
 478 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 479                              struct hns3_rx_vtag_cfg *vcfg)
 480 {
 481         struct hns3_vport_vtag_rx_cfg_cmd *req;
 482         struct hns3_hw *hw = &hns->hw;
 483         struct hns3_cmd_desc desc;
 484         uint16_t vport_id;
 485         uint8_t bitmap;
 486         int ret;
 487
 488         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 489
 490         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 491         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 492                      vcfg->strip_tag1_en ? 1 : 0);
 493         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 494                      vcfg->strip_tag2_en ? 1 : 0);
 495         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 496                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 497         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 498                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 499
 500         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 501         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 502                      vcfg->strip_tag1_discard_en ? 1 : 0);
 503         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 504                      vcfg->strip_tag2_discard_en ? 1 : 0);
 505         /*
 506          * In current version VF is not supported when PF is driven by DPDK
 507          * driver, just need to configure parameters for PF vport.
 508          */
 509         vport_id = HNS3_PF_FUNC_ID;
 510         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 511         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 512         req->vf_bitmap[req->vf_offset] = bitmap;
 513
 514         ret = hns3_cmd_send(hw, &desc, 1);
 515         if (ret)
 516                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 517         return ret;
 518 }
 519
 520 static void
 521 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 522                            struct hns3_rx_vtag_cfg *vcfg)
 523 {
 524         struct hns3_pf *pf = &hns->pf;
 525         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 526 }
 527
 528 static void
 529 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 530                            struct hns3_tx_vtag_cfg *vcfg)
 531 {
 532         struct hns3_pf *pf = &hns->pf;
 533         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 534 }
 535
 536 static int
 537 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 538 {
 539         struct hns3_rx_vtag_cfg rxvlan_cfg;
 540         struct hns3_hw *hw = &hns->hw;
 541         int ret;
 542
 543         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 544                 rxvlan_cfg.strip_tag1_en = false;
 545                 rxvlan_cfg.strip_tag2_en = enable;
 546                 rxvlan_cfg.strip_tag2_discard_en = false;
 547         } else {
 548                 rxvlan_cfg.strip_tag1_en = enable;
 549                 rxvlan_cfg.strip_tag2_en = true;
 550                 rxvlan_cfg.strip_tag2_discard_en = true;
 551         }
 552
 553         rxvlan_cfg.strip_tag1_discard_en = false;
 554         rxvlan_cfg.vlan1_vlan_prionly = false;
 555         rxvlan_cfg.vlan2_vlan_prionly = false;
 556         rxvlan_cfg.rx_vlan_offload_en = enable;
 557
 558         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 559         if (ret) {
 560                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 561                 return ret;
 562         }
 563
 564         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 565
 566         return ret;
 567 }
 568
 569 static int
 570 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 571                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 572 {
 573         struct hns3_vlan_filter_ctrl_cmd *req;
 574         struct hns3_cmd_desc desc;
 575         int ret;
 576
 577         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 578
 579         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 580         req->vlan_type = vlan_type;
 581         req->vlan_fe = filter_en ? fe_type : 0;
 582         req->vf_id = vf_id;
 583
 584         ret = hns3_cmd_send(hw, &desc, 1);
 585         if (ret)
 586                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 587
 588         return ret;
 589 }
 590
 591 static int
 592 hns3_vlan_filter_init(struct hns3_adapter *hns)
 593 {
 594         struct hns3_hw *hw = &hns->hw;
 595         int ret;
 596
 597         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 598                                         HNS3_FILTER_FE_EGRESS, false,
 599                                         HNS3_PF_FUNC_ID);
 600         if (ret) {
 601                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 602                 return ret;
 603         }
 604
 605         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 606                                         HNS3_FILTER_FE_INGRESS, false,
 607                                         HNS3_PF_FUNC_ID);
 608         if (ret)
 609                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 610
 611         return ret;
 612 }
 613
 614 static int
 615 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 616 {
 617         struct hns3_hw *hw = &hns->hw;
 618         int ret;
 619
 620         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 621                                         HNS3_FILTER_FE_INGRESS, enable,
 622                                         HNS3_PF_FUNC_ID);
 623         if (ret)
 624                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 625                          enable ? "enable" : "disable", ret);
 626
 627         return ret;
 628 }
 629
 630 static int
 631 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 632 {
 633         struct hns3_adapter *hns = dev->data->dev_private;
 634         struct hns3_hw *hw = &hns->hw;
 635         struct rte_eth_rxmode *rxmode;
 636         unsigned int tmp_mask;
 637         bool enable;
 638         int ret = 0;
 639
 640         rte_spinlock_lock(&hw->lock);
 641         rxmode = &dev->data->dev_conf.rxmode;
 642         tmp_mask = (unsigned int)mask;
 643         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 644                 /* ignore vlan filter configuration during promiscuous mode */
 645                 if (!dev->data->promiscuous) {
 646                         /* Enable or disable VLAN filter */
 647                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 648                                  true : false;
 649
 650                         ret = hns3_enable_vlan_filter(hns, enable);
 651                         if (ret) {
 652                                 rte_spinlock_unlock(&hw->lock);
 653                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 654                                          enable ? "enable" : "disable", ret);
 655                                 return ret;
 656                         }
 657                 }
 658         }
 659
 660         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 661                 /* Enable or disable VLAN stripping */
 662                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 663                     true : false;
 664
 665                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 666                 if (ret) {
 667                         rte_spinlock_unlock(&hw->lock);
 668                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 669                                  enable ? "enable" : "disable", ret);
 670                         return ret;
 671                 }
 672         }
 673
 674         rte_spinlock_unlock(&hw->lock);
 675
 676         return ret;
 677 }
 678
 679 static int
 680 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 681                              struct hns3_tx_vtag_cfg *vcfg)
 682 {
 683         struct hns3_vport_vtag_tx_cfg_cmd *req;
 684         struct hns3_cmd_desc desc;
 685         struct hns3_hw *hw = &hns->hw;
 686         uint16_t vport_id;
 687         uint8_t bitmap;
 688         int ret;
 689
 690         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 691
 692         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 693         req->def_vlan_tag1 = vcfg->default_tag1;
 694         req->def_vlan_tag2 = vcfg->default_tag2;
 695         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 696                      vcfg->accept_tag1 ? 1 : 0);
 697         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 698                      vcfg->accept_untag1 ? 1 : 0);
 699         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 700                      vcfg->accept_tag2 ? 1 : 0);
 701         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 702                      vcfg->accept_untag2 ? 1 : 0);
 703         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 704                      vcfg->insert_tag1_en ? 1 : 0);
 705         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 706                      vcfg->insert_tag2_en ? 1 : 0);
 707         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 708
 709         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 710         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 711                      vcfg->tag_shift_mode_en ? 1 : 0);
 712
 713         /*
 714          * In current version VF is not supported when PF is driven by DPDK
 715          * driver, just need to configure parameters for PF vport.
 716          */
 717         vport_id = HNS3_PF_FUNC_ID;
 718         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 719         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 720         req->vf_bitmap[req->vf_offset] = bitmap;
 721
 722         ret = hns3_cmd_send(hw, &desc, 1);
 723         if (ret)
 724                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 725
 726         return ret;
 727 }
 728
 729 static int
 730 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 731                      uint16_t pvid)
 732 {
 733         struct hns3_hw *hw = &hns->hw;
 734         struct hns3_tx_vtag_cfg txvlan_cfg;
 735         int ret;
 736
 737         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 738                 txvlan_cfg.accept_tag1 = true;
 739                 txvlan_cfg.insert_tag1_en = false;
 740                 txvlan_cfg.default_tag1 = 0;
 741         } else {
 742                 txvlan_cfg.accept_tag1 =
 743                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 744                 txvlan_cfg.insert_tag1_en = true;
 745                 txvlan_cfg.default_tag1 = pvid;
 746         }
 747
 748         txvlan_cfg.accept_untag1 = true;
 749         txvlan_cfg.accept_tag2 = true;
 750         txvlan_cfg.accept_untag2 = true;
 751         txvlan_cfg.insert_tag2_en = false;
 752         txvlan_cfg.default_tag2 = 0;
 753         txvlan_cfg.tag_shift_mode_en = true;
 754
 755         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 756         if (ret) {
 757                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 758                          ret);
 759                 return ret;
 760         }
 761
 762         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 763         return ret;
 764 }
 765
 766
 767 static void
 768 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 769 {
 770         struct hns3_user_vlan_table *vlan_entry;
 771         struct hns3_pf *pf = &hns->pf;
 772
 773         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 774                 if (vlan_entry->hd_tbl_status) {
 775                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 776                         vlan_entry->hd_tbl_status = false;
 777                 }
 778         }
 779
 780         if (is_del_list) {
 781                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 782                 while (vlan_entry) {
 783                         LIST_REMOVE(vlan_entry, next);
 784                         rte_free(vlan_entry);
 785                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 786                 }
 787         }
 788 }
 789
 790 static void
 791 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 792 {
 793         struct hns3_user_vlan_table *vlan_entry;
 794         struct hns3_pf *pf = &hns->pf;
 795
 796         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 797                 if (!vlan_entry->hd_tbl_status) {
 798                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 799                         vlan_entry->hd_tbl_status = true;
 800                 }
 801         }
 802 }
 803
 804 static void
 805 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 806 {
 807         struct hns3_hw *hw = &hns->hw;
 808         int ret;
 809
 810         hns3_rm_all_vlan_table(hns, true);
 811         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 812                 ret = hns3_set_port_vlan_filter(hns,
 813                                                 hw->port_base_vlan_cfg.pvid, 0);
 814                 if (ret) {
 815                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 816                                  ret);
 817                         return;
 818                 }
 819         }
 820 }
 821
 822 static int
 823 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 824                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 825 {
 826         struct hns3_hw *hw = &hns->hw;
 827         uint16_t old_pvid;
 828         int ret;
 829
 830         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 831                 old_pvid = hw->port_base_vlan_cfg.pvid;
 832                 if (old_pvid != HNS3_INVALID_PVID) {
 833                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 834                         if (ret) {
 835                                 hns3_err(hw, "failed to remove old pvid %u, "
 836                                                 "ret = %d", old_pvid, ret);
 837                                 return ret;
 838                         }
 839                 }
 840
 841                 hns3_rm_all_vlan_table(hns, false);
 842                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 843                 if (ret) {
 844                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 845                                         new_pvid, ret);
 846                         return ret;
 847                 }
 848         } else {
 849                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 850                 if (ret) {
 851                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 852                                         new_pvid, ret);
 853                         return ret;
 854                 }
 855
 856                 hns3_add_all_vlan_table(hns);
 857         }
 858         return 0;
 859 }
 860
 861 static int
 862 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 863 {
 864         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 865         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 866         bool rx_strip_en;
 867         int ret;
 868
 869         rx_strip_en = old_cfg->rx_vlan_offload_en;
 870         if (on) {
 871                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 872                 rx_vlan_cfg.strip_tag2_en = true;
 873                 rx_vlan_cfg.strip_tag2_discard_en = true;
 874         } else {
 875                 rx_vlan_cfg.strip_tag1_en = false;
 876                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 877                 rx_vlan_cfg.strip_tag2_discard_en = false;
 878         }
 879         rx_vlan_cfg.strip_tag1_discard_en = false;
 880         rx_vlan_cfg.vlan1_vlan_prionly = false;
 881         rx_vlan_cfg.vlan2_vlan_prionly = false;
 882         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 883
 884         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 885         if (ret)
 886                 return ret;
 887
 888         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 889         return ret;
 890 }
 891
 892 static int
 893 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 894 {
 895         struct hns3_hw *hw = &hns->hw;
 896         uint16_t port_base_vlan_state;
 897         int ret;
 898
 899         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 900                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 901                         hns3_warn(hw, "Invalid operation! As current pvid set "
 902                                   "is %u, disable pvid %u is invalid",
 903                                   hw->port_base_vlan_cfg.pvid, pvid);
 904                 return 0;
 905         }
 906
 907         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 908                                     HNS3_PORT_BASE_VLAN_DISABLE;
 909         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 910         if (ret) {
 911                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 912                          ret);
 913                 return ret;
 914         }
 915
 916         ret = hns3_en_pvid_strip(hns, on);
 917         if (ret) {
 918                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 919                          "ret = %d", ret);
 920                 return ret;
 921         }
 922
 923         if (pvid == HNS3_INVALID_PVID)
 924                 goto out;
 925         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 926         if (ret) {
 927                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 928                          ret);
 929                 return ret;
 930         }
 931
 932 out:
 933         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 934         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 935         return ret;
 936 }
 937
 938 static int
 939 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 940 {
 941         struct hns3_adapter *hns = dev->data->dev_private;
 942         struct hns3_hw *hw = &hns->hw;
 943         bool pvid_en_state_change;
 944         uint16_t pvid_state;
 945         int ret;
 946
 947         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 948                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 949                          RTE_ETHER_MAX_VLAN_ID);
 950                 return -EINVAL;
 951         }
 952
 953         /*
 954          * If PVID configuration state change, should refresh the PVID
 955          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 956          */
 957         pvid_state = hw->port_base_vlan_cfg.state;
 958         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 959             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 960                 pvid_en_state_change = false;
 961         else
 962                 pvid_en_state_change = true;
 963
 964         rte_spinlock_lock(&hw->lock);
 965         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 966         rte_spinlock_unlock(&hw->lock);
 967         if (ret)
 968                 return ret;
 969         /*
 970          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
 971          * need be processed by PMD driver.
 972          */
 973         if (pvid_en_state_change &&
 974             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
 975                 hns3_update_all_queues_pvid_proc_en(hw);
 976
 977         return 0;
 978 }
 979
 980 static int
 981 hns3_default_vlan_config(struct hns3_adapter *hns)
 982 {
 983         struct hns3_hw *hw = &hns->hw;
 984         int ret;
 985
 986         /*
 987          * When vlan filter is enabled, hardware regards packets without vlan
 988          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
 989          * table, packets without vlan won't be received. So, add vlan 0 as
 990          * the default vlan.
 991          */
 992         ret = hns3_vlan_filter_configure(hns, 0, 1);
 993         if (ret)
 994                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 995         return ret;
 996 }
 997
 998 static int
 999 hns3_init_vlan_config(struct hns3_adapter *hns)
1000 {
1001         struct hns3_hw *hw = &hns->hw;
1002         int ret;
1003
1004         /*
1005          * This function can be called in the initialization and reset process,
1006          * when in reset process, it means that hardware had been reseted
1007          * successfully and we need to restore the hardware configuration to
1008          * ensure that the hardware configuration remains unchanged before and
1009          * after reset.
1010          */
1011         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1012                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1013                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1014         }
1015
1016         ret = hns3_vlan_filter_init(hns);
1017         if (ret) {
1018                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1019                 return ret;
1020         }
1021
1022         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1023                                        RTE_ETHER_TYPE_VLAN);
1024         if (ret) {
1025                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1026                 return ret;
1027         }
1028
1029         /*
1030          * When in the reinit dev stage of the reset process, the following
1031          * vlan-related configurations may differ from those at initialization,
1032          * we will restore configurations to hardware in hns3_restore_vlan_table
1033          * and hns3_restore_vlan_conf later.
1034          */
1035         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1036                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1037                 if (ret) {
1038                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1039                         return ret;
1040                 }
1041
1042                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1043                 if (ret) {
1044                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1045                                  ret);
1046                         return ret;
1047                 }
1048         }
1049
1050         return hns3_default_vlan_config(hns);
1051 }
1052
1053 static int
1054 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1055 {
1056         struct hns3_pf *pf = &hns->pf;
1057         struct hns3_hw *hw = &hns->hw;
1058         uint64_t offloads;
1059         bool enable;
1060         int ret;
1061
1062         if (!hw->data->promiscuous) {
1063                 /* restore vlan filter states */
1064                 offloads = hw->data->dev_conf.rxmode.offloads;
1065                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1066                 ret = hns3_enable_vlan_filter(hns, enable);
1067                 if (ret) {
1068                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1069                                  "ret = %d", ret);
1070                         return ret;
1071                 }
1072         }
1073
1074         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1075         if (ret) {
1076                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1077                 return ret;
1078         }
1079
1080         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1081         if (ret)
1082                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1083
1084         return ret;
1085 }
1086
1087 static int
1088 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1089 {
1090         struct hns3_adapter *hns = dev->data->dev_private;
1091         struct rte_eth_dev_data *data = dev->data;
1092         struct rte_eth_txmode *txmode;
1093         struct hns3_hw *hw = &hns->hw;
1094         int mask;
1095         int ret;
1096
1097         txmode = &data->dev_conf.txmode;
1098         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1099                 hns3_warn(hw,
1100                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1101                           "configuration is not supported! Ignore these two "
1102                           "parameters: hw_vlan_reject_tagged(%u), "
1103                           "hw_vlan_reject_untagged(%u)",
1104                           txmode->hw_vlan_reject_tagged,
1105                           txmode->hw_vlan_reject_untagged);
1106
1107         /* Apply vlan offload setting */
1108         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1109         ret = hns3_vlan_offload_set(dev, mask);
1110         if (ret) {
1111                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1112                          ret);
1113                 return ret;
1114         }
1115
1116         /*
1117          * If pvid config is not set in rte_eth_conf, driver needn't to set
1118          * VLAN pvid related configuration to hardware.
1119          */
1120         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1121                 return 0;
1122
1123         /* Apply pvid setting */
1124         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1125                                  txmode->hw_vlan_insert_pvid);
1126         if (ret)
1127                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1128                          txmode->pvid, ret);
1129
1130         return ret;
1131 }
1132
1133 static int
1134 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1135                 unsigned int tso_mss_max)
1136 {
1137         struct hns3_cfg_tso_status_cmd *req;
1138         struct hns3_cmd_desc desc;
1139         uint16_t tso_mss;
1140
1141         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1142
1143         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1144
1145         tso_mss = 0;
1146         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1147                        tso_mss_min);
1148         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1149
1150         tso_mss = 0;
1151         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1152                        tso_mss_max);
1153         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1154
1155         return hns3_cmd_send(hw, &desc, 1);
1156 }
1157
1158 static int
1159 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1160                    uint16_t *allocated_size, bool is_alloc)
1161 {
1162         struct hns3_umv_spc_alc_cmd *req;
1163         struct hns3_cmd_desc desc;
1164         int ret;
1165
1166         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1167         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1168         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1169         req->space_size = rte_cpu_to_le_32(space_size);
1170
1171         ret = hns3_cmd_send(hw, &desc, 1);
1172         if (ret) {
1173                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1174                              is_alloc ? "allocate" : "free", ret);
1175                 return ret;
1176         }
1177
1178         if (is_alloc && allocated_size)
1179                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1180
1181         return 0;
1182 }
1183
1184 static int
1185 hns3_init_umv_space(struct hns3_hw *hw)
1186 {
1187         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1188         struct hns3_pf *pf = &hns->pf;
1189         uint16_t allocated_size = 0;
1190         int ret;
1191
1192         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1193                                  true);
1194         if (ret)
1195                 return ret;
1196
1197         if (allocated_size < pf->wanted_umv_size)
1198                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1199                              pf->wanted_umv_size, allocated_size);
1200
1201         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1202                                                 pf->wanted_umv_size;
1203         pf->used_umv_size = 0;
1204         return 0;
1205 }
1206
1207 static int
1208 hns3_uninit_umv_space(struct hns3_hw *hw)
1209 {
1210         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1211         struct hns3_pf *pf = &hns->pf;
1212         int ret;
1213
1214         if (pf->max_umv_size == 0)
1215                 return 0;
1216
1217         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1218         if (ret)
1219                 return ret;
1220
1221         pf->max_umv_size = 0;
1222
1223         return 0;
1224 }
1225
1226 static bool
1227 hns3_is_umv_space_full(struct hns3_hw *hw)
1228 {
1229         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1230         struct hns3_pf *pf = &hns->pf;
1231         bool is_full;
1232
1233         is_full = (pf->used_umv_size >= pf->max_umv_size);
1234
1235         return is_full;
1236 }
1237
1238 static void
1239 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1240 {
1241         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1242         struct hns3_pf *pf = &hns->pf;
1243
1244         if (is_free) {
1245                 if (pf->used_umv_size > 0)
1246                         pf->used_umv_size--;
1247         } else
1248                 pf->used_umv_size++;
1249 }
1250
1251 static void
1252 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1253                       const uint8_t *addr, bool is_mc)
1254 {
1255         const unsigned char *mac_addr = addr;
1256         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1257                             ((uint32_t)mac_addr[2] << 16) |
1258                             ((uint32_t)mac_addr[1] << 8) |
1259                             (uint32_t)mac_addr[0];
1260         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1261
1262         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1263         if (is_mc) {
1264                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1265                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1266                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1267         }
1268
1269         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1270         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1271 }
1272
1273 static int
1274 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1275                              uint8_t resp_code,
1276                              enum hns3_mac_vlan_tbl_opcode op)
1277 {
1278         if (cmdq_resp) {
1279                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1280                          cmdq_resp);
1281                 return -EIO;
1282         }
1283
1284         if (op == HNS3_MAC_VLAN_ADD) {
1285                 if (resp_code == 0 || resp_code == 1) {
1286                         return 0;
1287                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1288                         hns3_err(hw, "add mac addr failed for uc_overflow");
1289                         return -ENOSPC;
1290                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1291                         hns3_err(hw, "add mac addr failed for mc_overflow");
1292                         return -ENOSPC;
1293                 }
1294
1295                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1296                          resp_code);
1297                 return -EIO;
1298         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1299                 if (resp_code == 0) {
1300                         return 0;
1301                 } else if (resp_code == 1) {
1302                         hns3_dbg(hw, "remove mac addr failed for miss");
1303                         return -ENOENT;
1304                 }
1305
1306                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1307                          resp_code);
1308                 return -EIO;
1309         } else if (op == HNS3_MAC_VLAN_LKUP) {
1310                 if (resp_code == 0) {
1311                         return 0;
1312                 } else if (resp_code == 1) {
1313                         hns3_dbg(hw, "lookup mac addr failed for miss");
1314                         return -ENOENT;
1315                 }
1316
1317                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1318                          resp_code);
1319                 return -EIO;
1320         }
1321
1322         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1323                  op);
1324
1325         return -EINVAL;
1326 }
1327
1328 static int
1329 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1330                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1331                          struct hns3_cmd_desc *desc, bool is_mc)
1332 {
1333         uint8_t resp_code;
1334         uint16_t retval;
1335         int ret;
1336
1337         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1338         if (is_mc) {
1339                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1340                 memcpy(desc[0].data, req,
1341                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1342                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1343                                           true);
1344                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1345                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1346                                           true);
1347                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1348         } else {
1349                 memcpy(desc[0].data, req,
1350                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1351                 ret = hns3_cmd_send(hw, desc, 1);
1352         }
1353         if (ret) {
1354                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1355                          ret);
1356                 return ret;
1357         }
1358         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1359         retval = rte_le_to_cpu_16(desc[0].retval);
1360
1361         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1362                                             HNS3_MAC_VLAN_LKUP);
1363 }
1364
1365 static int
1366 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1367                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1368                       struct hns3_cmd_desc *mc_desc)
1369 {
1370         uint8_t resp_code;
1371         uint16_t retval;
1372         int cfg_status;
1373         int ret;
1374
1375         if (mc_desc == NULL) {
1376                 struct hns3_cmd_desc desc;
1377
1378                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1379                 memcpy(desc.data, req,
1380                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1381                 ret = hns3_cmd_send(hw, &desc, 1);
1382                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1383                 retval = rte_le_to_cpu_16(desc.retval);
1384
1385                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1386                                                           HNS3_MAC_VLAN_ADD);
1387         } else {
1388                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1389                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1390                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1391                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1392                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1393                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1394                 memcpy(mc_desc[0].data, req,
1395                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1396                 mc_desc[0].retval = 0;
1397                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1398                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1399                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1400
1401                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1402                                                           HNS3_MAC_VLAN_ADD);
1403         }
1404
1405         if (ret) {
1406                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1407                 return ret;
1408         }
1409
1410         return cfg_status;
1411 }
1412
1413 static int
1414 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1415                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1416 {
1417         struct hns3_cmd_desc desc;
1418         uint8_t resp_code;
1419         uint16_t retval;
1420         int ret;
1421
1422         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1423
1424         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1425
1426         ret = hns3_cmd_send(hw, &desc, 1);
1427         if (ret) {
1428                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1429                 return ret;
1430         }
1431         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1432         retval = rte_le_to_cpu_16(desc.retval);
1433
1434         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1435                                             HNS3_MAC_VLAN_REMOVE);
1436 }
1437
1438 static int
1439 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1440 {
1441         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1442         struct hns3_mac_vlan_tbl_entry_cmd req;
1443         struct hns3_pf *pf = &hns->pf;
1444         struct hns3_cmd_desc desc[3];
1445         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1446         uint16_t egress_port = 0;
1447         uint8_t vf_id;
1448         int ret;
1449
1450         /* check if mac addr is valid */
1451         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1452                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1453                                       mac_addr);
1454                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1455                          mac_str);
1456                 return -EINVAL;
1457         }
1458
1459         memset(&req, 0, sizeof(req));
1460
1461         /*
1462          * In current version VF is not supported when PF is driven by DPDK
1463          * driver, just need to configure parameters for PF vport.
1464          */
1465         vf_id = HNS3_PF_FUNC_ID;
1466         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1467                        HNS3_MAC_EPORT_VFID_S, vf_id);
1468
1469         req.egress_port = rte_cpu_to_le_16(egress_port);
1470
1471         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1472
1473         /*
1474          * Lookup the mac address in the mac_vlan table, and add
1475          * it if the entry is inexistent. Repeated unicast entry
1476          * is not allowed in the mac vlan table.
1477          */
1478         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1479         if (ret == -ENOENT) {
1480                 if (!hns3_is_umv_space_full(hw)) {
1481                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1482                         if (!ret)
1483                                 hns3_update_umv_space(hw, false);
1484                         return ret;
1485                 }
1486
1487                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1488
1489                 return -ENOSPC;
1490         }
1491
1492         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1493
1494         /* check if we just hit the duplicate */
1495         if (ret == 0) {
1496                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1497                 return 0;
1498         }
1499
1500         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1501                  mac_str);
1502
1503         return ret;
1504 }
1505
1506 static int
1507 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1508 {
1509         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1510         struct rte_ether_addr *addr;
1511         int ret;
1512         int i;
1513
1514         for (i = 0; i < hw->mc_addrs_num; i++) {
1515                 addr = &hw->mc_addrs[i];
1516                 /* Check if there are duplicate addresses */
1517                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1518                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1519                                               addr);
1520                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1521                                  "(%s) is added by the set_mc_mac_addr_list "
1522                                  "API", mac_str);
1523                         return -EINVAL;
1524                 }
1525         }
1526
1527         ret = hns3_add_mc_addr(hw, mac_addr);
1528         if (ret) {
1529                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1530                                       mac_addr);
1531                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1532                          mac_str, ret);
1533         }
1534         return ret;
1535 }
1536
1537 static int
1538 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 {
1540         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1541         int ret;
1542
1543         ret = hns3_remove_mc_addr(hw, mac_addr);
1544         if (ret) {
1545                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1546                                       mac_addr);
1547                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1548                          mac_str, ret);
1549         }
1550         return ret;
1551 }
1552
1553 static int
1554 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1555                   uint32_t idx, __rte_unused uint32_t pool)
1556 {
1557         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1558         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1559         int ret;
1560
1561         rte_spinlock_lock(&hw->lock);
1562
1563         /*
1564          * In hns3 network engine adding UC and MC mac address with different
1565          * commands with firmware. We need to determine whether the input
1566          * address is a UC or a MC address to call different commands.
1567          * By the way, it is recommended calling the API function named
1568          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1569          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1570          * may affect the specifications of UC mac addresses.
1571          */
1572         if (rte_is_multicast_ether_addr(mac_addr))
1573                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1574         else
1575                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1576
1577         if (ret) {
1578                 rte_spinlock_unlock(&hw->lock);
1579                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1580                                       mac_addr);
1581                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1582                          ret);
1583                 return ret;
1584         }
1585
1586         if (idx == 0)
1587                 hw->mac.default_addr_setted = true;
1588         rte_spinlock_unlock(&hw->lock);
1589
1590         return ret;
1591 }
1592
1593 static int
1594 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1595 {
1596         struct hns3_mac_vlan_tbl_entry_cmd req;
1597         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1598         int ret;
1599
1600         /* check if mac addr is valid */
1601         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1602                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1603                                       mac_addr);
1604                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1605                          mac_str);
1606                 return -EINVAL;
1607         }
1608
1609         memset(&req, 0, sizeof(req));
1610         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1611         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1612         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1613         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1614                 return 0;
1615         else if (ret == 0)
1616                 hns3_update_umv_space(hw, true);
1617
1618         return ret;
1619 }
1620
1621 static void
1622 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1623 {
1624         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625         /* index will be checked by upper level rte interface */
1626         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1627         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1628         int ret;
1629
1630         rte_spinlock_lock(&hw->lock);
1631
1632         if (rte_is_multicast_ether_addr(mac_addr))
1633                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1634         else
1635                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1636         rte_spinlock_unlock(&hw->lock);
1637         if (ret) {
1638                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1639                                       mac_addr);
1640                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1641                          ret);
1642         }
1643 }
1644
1645 static int
1646 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1647                           struct rte_ether_addr *mac_addr)
1648 {
1649         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         struct rte_ether_addr *oaddr;
1651         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1652         bool default_addr_setted;
1653         bool rm_succes = false;
1654         int ret, ret_val;
1655
1656         /*
1657          * It has been guaranteed that input parameter named mac_addr is valid
1658          * address in the rte layer of DPDK framework.
1659          */
1660         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1661         default_addr_setted = hw->mac.default_addr_setted;
1662         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1663                 return 0;
1664
1665         rte_spinlock_lock(&hw->lock);
1666         if (default_addr_setted) {
1667                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1668                 if (ret) {
1669                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1670                                               oaddr);
1671                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1672                                   mac_str, ret);
1673                         rm_succes = false;
1674                 } else
1675                         rm_succes = true;
1676         }
1677
1678         ret = hns3_add_uc_addr_common(hw, mac_addr);
1679         if (ret) {
1680                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1681                                       mac_addr);
1682                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1683                 goto err_add_uc_addr;
1684         }
1685
1686         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1687         if (ret) {
1688                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1689                 goto err_pause_addr_cfg;
1690         }
1691
1692         rte_ether_addr_copy(mac_addr,
1693                             (struct rte_ether_addr *)hw->mac.mac_addr);
1694         hw->mac.default_addr_setted = true;
1695         rte_spinlock_unlock(&hw->lock);
1696
1697         return 0;
1698
1699 err_pause_addr_cfg:
1700         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1701         if (ret_val) {
1702                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1703                                       mac_addr);
1704                 hns3_warn(hw,
1705                           "Failed to roll back to del setted mac addr(%s): %d",
1706                           mac_str, ret_val);
1707         }
1708
1709 err_add_uc_addr:
1710         if (rm_succes) {
1711                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1712                 if (ret_val) {
1713                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1714                                               oaddr);
1715                         hns3_warn(hw,
1716                                   "Failed to restore old uc mac addr(%s): %d",
1717                                   mac_str, ret_val);
1718                         hw->mac.default_addr_setted = false;
1719                 }
1720         }
1721         rte_spinlock_unlock(&hw->lock);
1722
1723         return ret;
1724 }
1725
1726 static int
1727 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1728 {
1729         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1730         struct hns3_hw *hw = &hns->hw;
1731         struct rte_ether_addr *addr;
1732         int err = 0;
1733         int ret;
1734         int i;
1735
1736         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1737                 addr = &hw->data->mac_addrs[i];
1738                 if (rte_is_zero_ether_addr(addr))
1739                         continue;
1740                 if (rte_is_multicast_ether_addr(addr))
1741                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1742                               hns3_add_mc_addr(hw, addr);
1743                 else
1744                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1745                               hns3_add_uc_addr_common(hw, addr);
1746
1747                 if (ret) {
1748                         err = ret;
1749                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1750                                               addr);
1751                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1752                                  "ret = %d.", del ? "remove" : "restore",
1753                                  mac_str, i, ret);
1754                 }
1755         }
1756         return err;
1757 }
1758
1759 static void
1760 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1761 {
1762 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1763         uint8_t word_num;
1764         uint8_t bit_num;
1765
1766         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1767                 word_num = vfid / 32;
1768                 bit_num = vfid % 32;
1769                 if (clr)
1770                         desc[1].data[word_num] &=
1771                             rte_cpu_to_le_32(~(1UL << bit_num));
1772                 else
1773                         desc[1].data[word_num] |=
1774                             rte_cpu_to_le_32(1UL << bit_num);
1775         } else {
1776                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1777                 bit_num = vfid % 32;
1778                 if (clr)
1779                         desc[2].data[word_num] &=
1780                             rte_cpu_to_le_32(~(1UL << bit_num));
1781                 else
1782                         desc[2].data[word_num] |=
1783                             rte_cpu_to_le_32(1UL << bit_num);
1784         }
1785 }
1786
1787 static int
1788 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1789 {
1790         struct hns3_mac_vlan_tbl_entry_cmd req;
1791         struct hns3_cmd_desc desc[3];
1792         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1793         uint8_t vf_id;
1794         int ret;
1795
1796         /* Check if mac addr is valid */
1797         if (!rte_is_multicast_ether_addr(mac_addr)) {
1798                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1799                                       mac_addr);
1800                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1801                          mac_str);
1802                 return -EINVAL;
1803         }
1804
1805         memset(&req, 0, sizeof(req));
1806         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1807         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1808         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1809         if (ret) {
1810                 /* This mac addr do not exist, add new entry for it */
1811                 memset(desc[0].data, 0, sizeof(desc[0].data));
1812                 memset(desc[1].data, 0, sizeof(desc[0].data));
1813                 memset(desc[2].data, 0, sizeof(desc[0].data));
1814         }
1815
1816         /*
1817          * In current version VF is not supported when PF is driven by DPDK
1818          * driver, just need to configure parameters for PF vport.
1819          */
1820         vf_id = HNS3_PF_FUNC_ID;
1821         hns3_update_desc_vfid(desc, vf_id, false);
1822         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1823         if (ret) {
1824                 if (ret == -ENOSPC)
1825                         hns3_err(hw, "mc mac vlan table is full");
1826                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1827                                       mac_addr);
1828                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1829         }
1830
1831         return ret;
1832 }
1833
1834 static int
1835 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1836 {
1837         struct hns3_mac_vlan_tbl_entry_cmd req;
1838         struct hns3_cmd_desc desc[3];
1839         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1840         uint8_t vf_id;
1841         int ret;
1842
1843         /* Check if mac addr is valid */
1844         if (!rte_is_multicast_ether_addr(mac_addr)) {
1845                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1846                                       mac_addr);
1847                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1848                          mac_str);
1849                 return -EINVAL;
1850         }
1851
1852         memset(&req, 0, sizeof(req));
1853         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1854         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1855         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1856         if (ret == 0) {
1857                 /*
1858                  * This mac addr exist, remove this handle's VFID for it.
1859                  * In current version VF is not supported when PF is driven by
1860                  * DPDK driver, just need to configure parameters for PF vport.
1861                  */
1862                 vf_id = HNS3_PF_FUNC_ID;
1863                 hns3_update_desc_vfid(desc, vf_id, true);
1864
1865                 /* All the vfid is zero, so need to delete this entry */
1866                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1867         } else if (ret == -ENOENT) {
1868                 /* This mac addr doesn't exist. */
1869                 return 0;
1870         }
1871
1872         if (ret) {
1873                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1874                                       mac_addr);
1875                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1876         }
1877
1878         return ret;
1879 }
1880
1881 static int
1882 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1883                            struct rte_ether_addr *mc_addr_set,
1884                            uint32_t nb_mc_addr)
1885 {
1886         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1887         struct rte_ether_addr *addr;
1888         uint32_t i;
1889         uint32_t j;
1890
1891         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1892                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1893                          "invalid. valid range: 0~%d",
1894                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1895                 return -EINVAL;
1896         }
1897
1898         /* Check if input mac addresses are valid */
1899         for (i = 0; i < nb_mc_addr; i++) {
1900                 addr = &mc_addr_set[i];
1901                 if (!rte_is_multicast_ether_addr(addr)) {
1902                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1903                                               addr);
1904                         hns3_err(hw,
1905                                  "failed to set mc mac addr, addr(%s) invalid.",
1906                                  mac_str);
1907                         return -EINVAL;
1908                 }
1909
1910                 /* Check if there are duplicate addresses */
1911                 for (j = i + 1; j < nb_mc_addr; j++) {
1912                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1913                                 rte_ether_format_addr(mac_str,
1914                                                       RTE_ETHER_ADDR_FMT_SIZE,
1915                                                       addr);
1916                                 hns3_err(hw, "failed to set mc mac addr, "
1917                                          "addrs invalid. two same addrs(%s).",
1918                                          mac_str);
1919                                 return -EINVAL;
1920                         }
1921                 }
1922
1923                 /*
1924                  * Check if there are duplicate addresses between mac_addrs
1925                  * and mc_addr_set
1926                  */
1927                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1928                         if (rte_is_same_ether_addr(addr,
1929                                                    &hw->data->mac_addrs[j])) {
1930                                 rte_ether_format_addr(mac_str,
1931                                                       RTE_ETHER_ADDR_FMT_SIZE,
1932                                                       addr);
1933                                 hns3_err(hw, "failed to set mc mac addr, "
1934                                          "addrs invalid. addrs(%s) has already "
1935                                          "configured in mac_addr add API",
1936                                          mac_str);
1937                                 return -EINVAL;
1938                         }
1939                 }
1940         }
1941
1942         return 0;
1943 }
1944
1945 static void
1946 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1947                            struct rte_ether_addr *mc_addr_set,
1948                            int mc_addr_num,
1949                            struct rte_ether_addr *reserved_addr_list,
1950                            int *reserved_addr_num,
1951                            struct rte_ether_addr *add_addr_list,
1952                            int *add_addr_num,
1953                            struct rte_ether_addr *rm_addr_list,
1954                            int *rm_addr_num)
1955 {
1956         struct rte_ether_addr *addr;
1957         int current_addr_num;
1958         int reserved_num = 0;
1959         int add_num = 0;
1960         int rm_num = 0;
1961         int num;
1962         int i;
1963         int j;
1964         bool same_addr;
1965
1966         /* Calculate the mc mac address list that should be removed */
1967         current_addr_num = hw->mc_addrs_num;
1968         for (i = 0; i < current_addr_num; i++) {
1969                 addr = &hw->mc_addrs[i];
1970                 same_addr = false;
1971                 for (j = 0; j < mc_addr_num; j++) {
1972                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1973                                 same_addr = true;
1974                                 break;
1975                         }
1976                 }
1977
1978                 if (!same_addr) {
1979                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1980                         rm_num++;
1981                 } else {
1982                         rte_ether_addr_copy(addr,
1983                                             &reserved_addr_list[reserved_num]);
1984                         reserved_num++;
1985                 }
1986         }
1987
1988         /* Calculate the mc mac address list that should be added */
1989         for (i = 0; i < mc_addr_num; i++) {
1990                 addr = &mc_addr_set[i];
1991                 same_addr = false;
1992                 for (j = 0; j < current_addr_num; j++) {
1993                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1994                                 same_addr = true;
1995                                 break;
1996                         }
1997                 }
1998
1999                 if (!same_addr) {
2000                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2001                         add_num++;
2002                 }
2003         }
2004
2005         /* Reorder the mc mac address list maintained by driver */
2006         for (i = 0; i < reserved_num; i++)
2007                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2008
2009         for (i = 0; i < rm_num; i++) {
2010                 num = reserved_num + i;
2011                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2012         }
2013
2014         *reserved_addr_num = reserved_num;
2015         *add_addr_num = add_num;
2016         *rm_addr_num = rm_num;
2017 }
2018
2019 static int
2020 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2021                           struct rte_ether_addr *mc_addr_set,
2022                           uint32_t nb_mc_addr)
2023 {
2024         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2026         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2027         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2028         struct rte_ether_addr *addr;
2029         int reserved_addr_num;
2030         int add_addr_num;
2031         int rm_addr_num;
2032         int mc_addr_num;
2033         int num;
2034         int ret;
2035         int i;
2036
2037         /* Check if input parameters are valid */
2038         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2039         if (ret)
2040                 return ret;
2041
2042         rte_spinlock_lock(&hw->lock);
2043
2044         /*
2045          * Calculate the mc mac address lists those should be removed and be
2046          * added, Reorder the mc mac address list maintained by driver.
2047          */
2048         mc_addr_num = (int)nb_mc_addr;
2049         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2050                                    reserved_addr_list, &reserved_addr_num,
2051                                    add_addr_list, &add_addr_num,
2052                                    rm_addr_list, &rm_addr_num);
2053
2054         /* Remove mc mac addresses */
2055         for (i = 0; i < rm_addr_num; i++) {
2056                 num = rm_addr_num - i - 1;
2057                 addr = &rm_addr_list[num];
2058                 ret = hns3_remove_mc_addr(hw, addr);
2059                 if (ret) {
2060                         rte_spinlock_unlock(&hw->lock);
2061                         return ret;
2062                 }
2063                 hw->mc_addrs_num--;
2064         }
2065
2066         /* Add mc mac addresses */
2067         for (i = 0; i < add_addr_num; i++) {
2068                 addr = &add_addr_list[i];
2069                 ret = hns3_add_mc_addr(hw, addr);
2070                 if (ret) {
2071                         rte_spinlock_unlock(&hw->lock);
2072                         return ret;
2073                 }
2074
2075                 num = reserved_addr_num + i;
2076                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2077                 hw->mc_addrs_num++;
2078         }
2079         rte_spinlock_unlock(&hw->lock);
2080
2081         return 0;
2082 }
2083
2084 static int
2085 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2086 {
2087         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2088         struct hns3_hw *hw = &hns->hw;
2089         struct rte_ether_addr *addr;
2090         int err = 0;
2091         int ret;
2092         int i;
2093
2094         for (i = 0; i < hw->mc_addrs_num; i++) {
2095                 addr = &hw->mc_addrs[i];
2096                 if (!rte_is_multicast_ether_addr(addr))
2097                         continue;
2098                 if (del)
2099                         ret = hns3_remove_mc_addr(hw, addr);
2100                 else
2101                         ret = hns3_add_mc_addr(hw, addr);
2102                 if (ret) {
2103                         err = ret;
2104                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2105                                               addr);
2106                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2107                                  del ? "Remove" : "Restore", mac_str, ret);
2108                 }
2109         }
2110         return err;
2111 }
2112
2113 static int
2114 hns3_check_mq_mode(struct rte_eth_dev *dev)
2115 {
2116         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2117         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2118         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2119         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2120         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2121         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2122         uint8_t num_tc;
2123         int max_tc = 0;
2124         int i;
2125
2126         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2127         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2128
2129         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2130                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2131                          "rx_mq_mode = %d", rx_mq_mode);
2132                 return -EINVAL;
2133         }
2134
2135         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2136             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2137                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2138                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2139                          rx_mq_mode, tx_mq_mode);
2140                 return -EINVAL;
2141         }
2142
2143         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2144                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2145                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2146                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2147                         return -EINVAL;
2148                 }
2149
2150                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2151                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2152                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2153                                  "nb_tcs(%d) != %d or %d in rx direction.",
2154                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2155                         return -EINVAL;
2156                 }
2157
2158                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2159                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2160                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2161                         return -EINVAL;
2162                 }
2163
2164                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2165                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2166                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2167                                          "is not equal to one in tx direction.",
2168                                          i, dcb_rx_conf->dcb_tc[i]);
2169                                 return -EINVAL;
2170                         }
2171                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2172                                 max_tc = dcb_rx_conf->dcb_tc[i];
2173                 }
2174
2175                 num_tc = max_tc + 1;
2176                 if (num_tc > dcb_rx_conf->nb_tcs) {
2177                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2178                                  num_tc, dcb_rx_conf->nb_tcs);
2179                         return -EINVAL;
2180                 }
2181         }
2182
2183         return 0;
2184 }
2185
2186 static int
2187 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2188 {
2189         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190
2191         if (!hns3_dev_dcb_supported(hw)) {
2192                 hns3_err(hw, "this port does not support dcb configurations.");
2193                 return -EOPNOTSUPP;
2194         }
2195
2196         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2197                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2198                 return -EOPNOTSUPP;
2199         }
2200
2201         /* Check multiple queue mode */
2202         return hns3_check_mq_mode(dev);
2203 }
2204
2205 static int
2206 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2207                            enum hns3_ring_type queue_type, uint16_t queue_id)
2208 {
2209         struct hns3_cmd_desc desc;
2210         struct hns3_ctrl_vector_chain_cmd *req =
2211                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2212         enum hns3_cmd_status status;
2213         enum hns3_opcode_type op;
2214         uint16_t tqp_type_and_id = 0;
2215         const char *op_str;
2216         uint16_t type;
2217         uint16_t gl;
2218
2219         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2220         hns3_cmd_setup_basic_desc(&desc, op, false);
2221         req->int_vector_id = vector_id;
2222
2223         if (queue_type == HNS3_RING_TYPE_RX)
2224                 gl = HNS3_RING_GL_RX;
2225         else
2226                 gl = HNS3_RING_GL_TX;
2227
2228         type = queue_type;
2229
2230         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2231                        type);
2232         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2233         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2234                        gl);
2235         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2236         req->int_cause_num = 1;
2237         op_str = mmap ? "Map" : "Unmap";
2238         status = hns3_cmd_send(hw, &desc, 1);
2239         if (status) {
2240                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2241                          op_str, queue_id, req->int_vector_id, status);
2242                 return status;
2243         }
2244
2245         return 0;
2246 }
2247
2248 static int
2249 hns3_init_ring_with_vector(struct hns3_hw *hw)
2250 {
2251         uint16_t vec;
2252         int ret;
2253         int i;
2254
2255         /*
2256          * In hns3 network engine, vector 0 is always the misc interrupt of this
2257          * function, vector 1~N can be used respectively for the queues of the
2258          * function. Tx and Rx queues with the same number share the interrupt
2259          * vector. In the initialization clearing the all hardware mapping
2260          * relationship configurations between queues and interrupt vectors is
2261          * needed, so some error caused by the residual configurations, such as
2262          * the unexpected Tx interrupt, can be avoid.
2263          */
2264         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2265         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2266                 vec = vec - 1; /* the last interrupt is reserved */
2267         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2268         for (i = 0; i < hw->intr_tqps_num; i++) {
2269                 /*
2270                  * Set gap limiter/rate limiter/quanity limiter algorithm
2271                  * configuration for interrupt coalesce of queue's interrupt.
2272                  */
2273                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2274                                        HNS3_TQP_INTR_GL_DEFAULT);
2275                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2276                                        HNS3_TQP_INTR_GL_DEFAULT);
2277                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2278                 /*
2279                  * QL(quantity limiter) is not used currently, just set 0 to
2280                  * close it.
2281                  */
2282                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2283
2284                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2285                                                  HNS3_RING_TYPE_TX, i);
2286                 if (ret) {
2287                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2288                                           "vector: %u, ret=%d", i, vec, ret);
2289                         return ret;
2290                 }
2291
2292                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2293                                                  HNS3_RING_TYPE_RX, i);
2294                 if (ret) {
2295                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2296                                           "vector: %u, ret=%d", i, vec, ret);
2297                         return ret;
2298                 }
2299         }
2300
2301         return 0;
2302 }
2303
2304 static int
2305 hns3_dev_configure(struct rte_eth_dev *dev)
2306 {
2307         struct hns3_adapter *hns = dev->data->dev_private;
2308         struct rte_eth_conf *conf = &dev->data->dev_conf;
2309         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2310         struct hns3_hw *hw = &hns->hw;
2311         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2312         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2313         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2314         struct rte_eth_rss_conf rss_conf;
2315         uint16_t mtu;
2316         bool gro_en;
2317         int ret;
2318
2319         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2320
2321         /*
2322          * Some versions of hardware network engine does not support
2323          * individually enable/disable/reset the Tx or Rx queue. These devices
2324          * must enable/disable/reset Tx and Rx queues at the same time. When the
2325          * numbers of Tx queues allocated by upper applications are not equal to
2326          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2327          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2328          * work as usual. But these fake queues are imperceptible, and can not
2329          * be used by upper applications.
2330          */
2331         if (!hns3_dev_indep_txrx_supported(hw)) {
2332                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2333                 if (ret) {
2334                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2335                                  ret);
2336                         return ret;
2337                 }
2338         }
2339
2340         hw->adapter_state = HNS3_NIC_CONFIGURING;
2341         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2342                 hns3_err(hw, "setting link speed/duplex not supported");
2343                 ret = -EINVAL;
2344                 goto cfg_err;
2345         }
2346
2347         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2348                 ret = hns3_check_dcb_cfg(dev);
2349                 if (ret)
2350                         goto cfg_err;
2351         }
2352
2353         /* When RSS is not configured, redirect the packet queue 0 */
2354         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2355                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2356                 rss_conf = conf->rx_adv_conf.rss_conf;
2357                 hw->rss_dis_flag = false;
2358                 if (rss_conf.rss_key == NULL) {
2359                         rss_conf.rss_key = rss_cfg->key;
2360                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2361                 }
2362
2363                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2364                 if (ret)
2365                         goto cfg_err;
2366         }
2367
2368         /*
2369          * If jumbo frames are enabled, MTU needs to be refreshed
2370          * according to the maximum RX packet length.
2371          */
2372         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2373                 /*
2374                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2375                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2376                  * can safely assign to "uint16_t" type variable.
2377                  */
2378                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2379                 ret = hns3_dev_mtu_set(dev, mtu);
2380                 if (ret)
2381                         goto cfg_err;
2382                 dev->data->mtu = mtu;
2383         }
2384
2385         ret = hns3_dev_configure_vlan(dev);
2386         if (ret)
2387                 goto cfg_err;
2388
2389         /* config hardware GRO */
2390         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2391         ret = hns3_config_gro(hw, gro_en);
2392         if (ret)
2393                 goto cfg_err;
2394
2395         hns->rx_simple_allowed = true;
2396         hns->rx_vec_allowed = true;
2397         hns->tx_simple_allowed = true;
2398         hns->tx_vec_allowed = true;
2399
2400         hns3_init_rx_ptype_tble(dev);
2401         hw->adapter_state = HNS3_NIC_CONFIGURED;
2402
2403         return 0;
2404
2405 cfg_err:
2406         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2407         hw->adapter_state = HNS3_NIC_INITIALIZED;
2408
2409         return ret;
2410 }
2411
2412 static int
2413 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2414 {
2415         struct hns3_config_max_frm_size_cmd *req;
2416         struct hns3_cmd_desc desc;
2417
2418         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2419
2420         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2421         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2422         req->min_frm_size = RTE_ETHER_MIN_LEN;
2423
2424         return hns3_cmd_send(hw, &desc, 1);
2425 }
2426
2427 static int
2428 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2429 {
2430         int ret;
2431
2432         ret = hns3_set_mac_mtu(hw, mps);
2433         if (ret) {
2434                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2435                 return ret;
2436         }
2437
2438         ret = hns3_buffer_alloc(hw);
2439         if (ret)
2440                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2441
2442         return ret;
2443 }
2444
2445 static int
2446 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2447 {
2448         struct hns3_adapter *hns = dev->data->dev_private;
2449         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2450         struct hns3_hw *hw = &hns->hw;
2451         bool is_jumbo_frame;
2452         int ret;
2453
2454         if (dev->data->dev_started) {
2455                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2456                          "before configuration", dev->data->port_id);
2457                 return -EBUSY;
2458         }
2459
2460         rte_spinlock_lock(&hw->lock);
2461         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2462         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2463
2464         /*
2465          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2466          * assign to "uint16_t" type variable.
2467          */
2468         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2469         if (ret) {
2470                 rte_spinlock_unlock(&hw->lock);
2471                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2472                          dev->data->port_id, mtu, ret);
2473                 return ret;
2474         }
2475         hns->pf.mps = (uint16_t)frame_size;
2476         if (is_jumbo_frame)
2477                 dev->data->dev_conf.rxmode.offloads |=
2478                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2479         else
2480                 dev->data->dev_conf.rxmode.offloads &=
2481                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2482         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2483         rte_spinlock_unlock(&hw->lock);
2484
2485         return 0;
2486 }
2487
2488 static int
2489 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2490 {
2491         struct hns3_adapter *hns = eth_dev->data->dev_private;
2492         struct hns3_hw *hw = &hns->hw;
2493         uint16_t queue_num = hw->tqps_num;
2494
2495         /*
2496          * In interrupt mode, 'max_rx_queues' is set based on the number of
2497          * MSI-X interrupt resources of the hardware.
2498          */
2499         if (hw->data->dev_conf.intr_conf.rxq == 1)
2500                 queue_num = hw->intr_tqps_num;
2501
2502         info->max_rx_queues = queue_num;
2503         info->max_tx_queues = hw->tqps_num;
2504         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2505         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2506         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2507         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2508         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2509         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2510                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2511                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2512                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2513                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2514                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2515                                  DEV_RX_OFFLOAD_KEEP_CRC |
2516                                  DEV_RX_OFFLOAD_SCATTER |
2517                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2518                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2519                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2520                                  DEV_RX_OFFLOAD_RSS_HASH |
2521                                  DEV_RX_OFFLOAD_TCP_LRO);
2522         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2523                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2524                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2525                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2526                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2527                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2528                                  DEV_TX_OFFLOAD_TCP_TSO |
2529                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2530                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2531                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2532                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2533                                  hns3_txvlan_cap_get(hw));
2534
2535         if (hns3_dev_indep_txrx_supported(hw))
2536                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2537                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2538
2539         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2540                 .nb_max = HNS3_MAX_RING_DESC,
2541                 .nb_min = HNS3_MIN_RING_DESC,
2542                 .nb_align = HNS3_ALIGN_RING_DESC,
2543         };
2544
2545         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2546                 .nb_max = HNS3_MAX_RING_DESC,
2547                 .nb_min = HNS3_MIN_RING_DESC,
2548                 .nb_align = HNS3_ALIGN_RING_DESC,
2549                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2550                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2551         };
2552
2553         info->default_rxconf = (struct rte_eth_rxconf) {
2554                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2555                 /*
2556                  * If there are no available Rx buffer descriptors, incoming
2557                  * packets are always dropped by hardware based on hns3 network
2558                  * engine.
2559                  */
2560                 .rx_drop_en = 1,
2561                 .offloads = 0,
2562         };
2563         info->default_txconf = (struct rte_eth_txconf) {
2564                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2565                 .offloads = 0,
2566         };
2567
2568         info->vmdq_queue_num = 0;
2569
2570         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2571         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2572         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2573
2574         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2575         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2576         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2577         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2578         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2579         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2580
2581         return 0;
2582 }
2583
2584 static int
2585 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2586                     size_t fw_size)
2587 {
2588         struct hns3_adapter *hns = eth_dev->data->dev_private;
2589         struct hns3_hw *hw = &hns->hw;
2590         uint32_t version = hw->fw_version;
2591         int ret;
2592
2593         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2594                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2595                                       HNS3_FW_VERSION_BYTE3_S),
2596                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2597                                       HNS3_FW_VERSION_BYTE2_S),
2598                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2599                                       HNS3_FW_VERSION_BYTE1_S),
2600                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2601                                       HNS3_FW_VERSION_BYTE0_S));
2602         ret += 1; /* add the size of '\0' */
2603         if (fw_size < (uint32_t)ret)
2604                 return ret;
2605         else
2606                 return 0;
2607 }
2608
2609 static int
2610 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2611                      __rte_unused int wait_to_complete)
2612 {
2613         struct hns3_adapter *hns = eth_dev->data->dev_private;
2614         struct hns3_hw *hw = &hns->hw;
2615         struct hns3_mac *mac = &hw->mac;
2616         struct rte_eth_link new_link;
2617
2618         if (!hns3_is_reset_pending(hns)) {
2619                 hns3_update_speed_duplex(eth_dev);
2620                 hns3_update_link_status(hw);
2621         }
2622
2623         memset(&new_link, 0, sizeof(new_link));
2624         switch (mac->link_speed) {
2625         case ETH_SPEED_NUM_10M:
2626         case ETH_SPEED_NUM_100M:
2627         case ETH_SPEED_NUM_1G:
2628         case ETH_SPEED_NUM_10G:
2629         case ETH_SPEED_NUM_25G:
2630         case ETH_SPEED_NUM_40G:
2631         case ETH_SPEED_NUM_50G:
2632         case ETH_SPEED_NUM_100G:
2633         case ETH_SPEED_NUM_200G:
2634                 new_link.link_speed = mac->link_speed;
2635                 break;
2636         default:
2637                 new_link.link_speed = ETH_SPEED_NUM_100M;
2638                 break;
2639         }
2640
2641         new_link.link_duplex = mac->link_duplex;
2642         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2643         new_link.link_autoneg =
2644             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2645
2646         return rte_eth_linkstatus_set(eth_dev, &new_link);
2647 }
2648
2649 static int
2650 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2651 {
2652         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2653         struct hns3_pf *pf = &hns->pf;
2654
2655         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2656                 return -EINVAL;
2657
2658         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2659
2660         return 0;
2661 }
2662
2663 static int
2664 hns3_query_function_status(struct hns3_hw *hw)
2665 {
2666 #define HNS3_QUERY_MAX_CNT              10
2667 #define HNS3_QUERY_SLEEP_MSCOEND        1
2668         struct hns3_func_status_cmd *req;
2669         struct hns3_cmd_desc desc;
2670         int timeout = 0;
2671         int ret;
2672
2673         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2674         req = (struct hns3_func_status_cmd *)desc.data;
2675
2676         do {
2677                 ret = hns3_cmd_send(hw, &desc, 1);
2678                 if (ret) {
2679                         PMD_INIT_LOG(ERR, "query function status failed %d",
2680                                      ret);
2681                         return ret;
2682                 }
2683
2684                 /* Check pf reset is done */
2685                 if (req->pf_state)
2686                         break;
2687
2688                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2689         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2690
2691         return hns3_parse_func_status(hw, req);
2692 }
2693
2694 static int
2695 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2696 {
2697         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2698         struct hns3_pf *pf = &hns->pf;
2699
2700         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2701                 /*
2702                  * The total_tqps_num obtained from firmware is maximum tqp
2703                  * numbers of this port, which should be used for PF and VFs.
2704                  * There is no need for pf to have so many tqp numbers in
2705                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2706                  * coming from config file, is assigned to maximum queue number
2707                  * for the PF of this port by user. So users can modify the
2708                  * maximum queue number of PF according to their own application
2709                  * scenarios, which is more flexible to use. In addition, many
2710                  * memories can be saved due to allocating queue statistics
2711                  * room according to the actual number of queues required. The
2712                  * maximum queue number of PF for network engine with
2713                  * revision_id greater than 0x30 is assigned by config file.
2714                  */
2715                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2716                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2717                                  "must be greater than 0.",
2718                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2719                         return -EINVAL;
2720                 }
2721
2722                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2723                                        hw->total_tqps_num);
2724         } else {
2725                 /*
2726                  * Due to the limitation on the number of PF interrupts
2727                  * available, the maximum queue number assigned to PF on
2728                  * the network engine with revision_id 0x21 is 64.
2729                  */
2730                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2731                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2732         }
2733
2734         return 0;
2735 }
2736
2737 static int
2738 hns3_query_pf_resource(struct hns3_hw *hw)
2739 {
2740         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2741         struct hns3_pf *pf = &hns->pf;
2742         struct hns3_pf_res_cmd *req;
2743         struct hns3_cmd_desc desc;
2744         int ret;
2745
2746         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2747         ret = hns3_cmd_send(hw, &desc, 1);
2748         if (ret) {
2749                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2750                 return ret;
2751         }
2752
2753         req = (struct hns3_pf_res_cmd *)desc.data;
2754         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2755                              rte_le_to_cpu_16(req->ext_tqp_num);
2756         ret = hns3_get_pf_max_tqp_num(hw);
2757         if (ret)
2758                 return ret;
2759
2760         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2761         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2762
2763         if (req->tx_buf_size)
2764                 pf->tx_buf_size =
2765                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2766         else
2767                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2768
2769         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2770
2771         if (req->dv_buf_size)
2772                 pf->dv_buf_size =
2773                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2774         else
2775                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2776
2777         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2778
2779         hw->num_msi =
2780                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2781                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2782
2783         return 0;
2784 }
2785
2786 static void
2787 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2788 {
2789         struct hns3_cfg_param_cmd *req;
2790         uint64_t mac_addr_tmp_high;
2791         uint8_t ext_rss_size_max;
2792         uint64_t mac_addr_tmp;
2793         uint32_t i;
2794
2795         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2796
2797         /* get the configuration */
2798         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2799                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2800         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2801                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2802         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2803                                            HNS3_CFG_TQP_DESC_N_M,
2804                                            HNS3_CFG_TQP_DESC_N_S);
2805
2806         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2807                                        HNS3_CFG_PHY_ADDR_M,
2808                                        HNS3_CFG_PHY_ADDR_S);
2809         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2810                                          HNS3_CFG_MEDIA_TP_M,
2811                                          HNS3_CFG_MEDIA_TP_S);
2812         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2813                                          HNS3_CFG_RX_BUF_LEN_M,
2814                                          HNS3_CFG_RX_BUF_LEN_S);
2815         /* get mac address */
2816         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2817         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2818                                            HNS3_CFG_MAC_ADDR_H_M,
2819                                            HNS3_CFG_MAC_ADDR_H_S);
2820
2821         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2822
2823         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2824                                             HNS3_CFG_DEFAULT_SPEED_M,
2825                                             HNS3_CFG_DEFAULT_SPEED_S);
2826         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2827                                            HNS3_CFG_RSS_SIZE_M,
2828                                            HNS3_CFG_RSS_SIZE_S);
2829
2830         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2831                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2832
2833         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2834         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2835
2836         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2837                                             HNS3_CFG_SPEED_ABILITY_M,
2838                                             HNS3_CFG_SPEED_ABILITY_S);
2839         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2840                                         HNS3_CFG_UMV_TBL_SPACE_M,
2841                                         HNS3_CFG_UMV_TBL_SPACE_S);
2842         if (!cfg->umv_space)
2843                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2844
2845         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2846                                                HNS3_CFG_EXT_RSS_SIZE_M,
2847                                                HNS3_CFG_EXT_RSS_SIZE_S);
2848
2849         /*
2850          * Field ext_rss_size_max obtained from firmware will be more flexible
2851          * for future changes and expansions, which is an exponent of 2, instead
2852          * of reading out directly. If this field is not zero, hns3 PF PMD
2853          * driver uses it as rss_size_max under one TC. Device, whose revision
2854          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2855          * maximum number of queues supported under a TC through this field.
2856          */
2857         if (ext_rss_size_max)
2858                 cfg->rss_size_max = 1U << ext_rss_size_max;
2859 }
2860
2861 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2862  * @hw: pointer to struct hns3_hw
2863  * @hcfg: the config structure to be getted
2864  */
2865 static int
2866 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2867 {
2868         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2869         struct hns3_cfg_param_cmd *req;
2870         uint32_t offset;
2871         uint32_t i;
2872         int ret;
2873
2874         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2875                 offset = 0;
2876                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2877                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2878                                           true);
2879                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2880                                i * HNS3_CFG_RD_LEN_BYTES);
2881                 /* Len should be divided by 4 when send to hardware */
2882                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2883                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2884                 req->offset = rte_cpu_to_le_32(offset);
2885         }
2886
2887         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2888         if (ret) {
2889                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2890                 return ret;
2891         }
2892
2893         hns3_parse_cfg(hcfg, desc);
2894
2895         return 0;
2896 }
2897
2898 static int
2899 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2900 {
2901         switch (speed_cmd) {
2902         case HNS3_CFG_SPEED_10M:
2903                 *speed = ETH_SPEED_NUM_10M;
2904                 break;
2905         case HNS3_CFG_SPEED_100M:
2906                 *speed = ETH_SPEED_NUM_100M;
2907                 break;
2908         case HNS3_CFG_SPEED_1G:
2909                 *speed = ETH_SPEED_NUM_1G;
2910                 break;
2911         case HNS3_CFG_SPEED_10G:
2912                 *speed = ETH_SPEED_NUM_10G;
2913                 break;
2914         case HNS3_CFG_SPEED_25G:
2915                 *speed = ETH_SPEED_NUM_25G;
2916                 break;
2917         case HNS3_CFG_SPEED_40G:
2918                 *speed = ETH_SPEED_NUM_40G;
2919                 break;
2920         case HNS3_CFG_SPEED_50G:
2921                 *speed = ETH_SPEED_NUM_50G;
2922                 break;
2923         case HNS3_CFG_SPEED_100G:
2924                 *speed = ETH_SPEED_NUM_100G;
2925                 break;
2926         case HNS3_CFG_SPEED_200G:
2927                 *speed = ETH_SPEED_NUM_200G;
2928                 break;
2929         default:
2930                 return -EINVAL;
2931         }
2932
2933         return 0;
2934 }
2935
2936 static void
2937 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2938 {
2939         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2940         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2941         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2942         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2943         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2944 }
2945
2946 static void
2947 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2948 {
2949         struct hns3_dev_specs_0_cmd *req0;
2950
2951         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2952
2953         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2954         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2955         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2956         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2957         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2958 }
2959
2960 static int
2961 hns3_query_dev_specifications(struct hns3_hw *hw)
2962 {
2963         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2964         int ret;
2965         int i;
2966
2967         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2968                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2969                                           true);
2970                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2971         }
2972         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2973
2974         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2975         if (ret)
2976                 return ret;
2977
2978         hns3_parse_dev_specifications(hw, desc);
2979
2980         return 0;
2981 }
2982
2983 static int
2984 hns3_get_capability(struct hns3_hw *hw)
2985 {
2986         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2987         struct rte_pci_device *pci_dev;
2988         struct hns3_pf *pf = &hns->pf;
2989         struct rte_eth_dev *eth_dev;
2990         uint16_t device_id;
2991         uint8_t revision;
2992         int ret;
2993
2994         eth_dev = &rte_eth_devices[hw->data->port_id];
2995         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2996         device_id = pci_dev->id.device_id;
2997
2998         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2999             device_id == HNS3_DEV_ID_50GE_RDMA ||
3000             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3001             device_id == HNS3_DEV_ID_200G_RDMA)
3002                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3003
3004         ret = hns3_query_dev_fec_info(eth_dev);
3005         if (ret) {
3006                 PMD_INIT_LOG(ERR,
3007                              "failed to query FEC information, ret = %d", ret);
3008                 return ret;
3009         }
3010
3011         /* Get PCI revision id */
3012         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3013                                   HNS3_PCI_REVISION_ID);
3014         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3015                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3016                              ret);
3017                 return -EIO;
3018         }
3019         hw->revision = revision;
3020
3021         if (revision < PCI_REVISION_ID_HIP09_A) {
3022                 hns3_set_default_dev_specifications(hw);
3023                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3024                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3025                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3026                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3027                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3028                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3029                 hw->rss_info.ipv6_sctp_offload_supported = false;
3030                 return 0;
3031         }
3032
3033         ret = hns3_query_dev_specifications(hw);
3034         if (ret) {
3035                 PMD_INIT_LOG(ERR,
3036                              "failed to query dev specifications, ret = %d",
3037                              ret);
3038                 return ret;
3039         }
3040
3041         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3042         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3043         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3044         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3045         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3046         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3047         hw->rss_info.ipv6_sctp_offload_supported = true;
3048
3049         return 0;
3050 }
3051
3052 static int
3053 hns3_get_board_configuration(struct hns3_hw *hw)
3054 {
3055         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3056         struct hns3_pf *pf = &hns->pf;
3057         struct hns3_cfg cfg;
3058         int ret;
3059
3060         ret = hns3_get_board_cfg(hw, &cfg);
3061         if (ret) {
3062                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3063                 return ret;
3064         }
3065
3066         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3067             !hns3_dev_copper_supported(hw)) {
3068                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3069                 return -EOPNOTSUPP;
3070         }
3071
3072         hw->mac.media_type = cfg.media_type;
3073         hw->rss_size_max = cfg.rss_size_max;
3074         hw->rss_dis_flag = false;
3075         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3076         hw->mac.phy_addr = cfg.phy_addr;
3077         hw->mac.default_addr_setted = false;
3078         hw->num_tx_desc = cfg.tqp_desc_num;
3079         hw->num_rx_desc = cfg.tqp_desc_num;
3080         hw->dcb_info.num_pg = 1;
3081         hw->dcb_info.hw_pfc_map = 0;
3082
3083         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3084         if (ret) {
3085                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3086                              cfg.default_speed, ret);
3087                 return ret;
3088         }
3089
3090         pf->tc_max = cfg.tc_num;
3091         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3092                 PMD_INIT_LOG(WARNING,
3093                              "Get TC num(%u) from flash, set TC num to 1",
3094                              pf->tc_max);
3095                 pf->tc_max = 1;
3096         }
3097
3098         /* Dev does not support DCB */
3099         if (!hns3_dev_dcb_supported(hw)) {
3100                 pf->tc_max = 1;
3101                 pf->pfc_max = 0;
3102         } else
3103                 pf->pfc_max = pf->tc_max;
3104
3105         hw->dcb_info.num_tc = 1;
3106         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3107                                      hw->tqps_num / hw->dcb_info.num_tc);
3108         hns3_set_bit(hw->hw_tc_map, 0, 1);
3109         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3110
3111         pf->wanted_umv_size = cfg.umv_space;
3112
3113         return ret;
3114 }
3115
3116 static int
3117 hns3_get_configuration(struct hns3_hw *hw)
3118 {
3119         int ret;
3120
3121         ret = hns3_query_function_status(hw);
3122         if (ret) {
3123                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3124                 return ret;
3125         }
3126
3127         /* Get device capability */
3128         ret = hns3_get_capability(hw);
3129         if (ret) {
3130                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3131                 return ret;
3132         }
3133
3134         /* Get pf resource */
3135         ret = hns3_query_pf_resource(hw);
3136         if (ret) {
3137                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3138                 return ret;
3139         }
3140
3141         ret = hns3_get_board_configuration(hw);
3142         if (ret)
3143                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3144
3145         return ret;
3146 }
3147
3148 static int
3149 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3150                       uint16_t tqp_vid, bool is_pf)
3151 {
3152         struct hns3_tqp_map_cmd *req;
3153         struct hns3_cmd_desc desc;
3154         int ret;
3155
3156         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3157
3158         req = (struct hns3_tqp_map_cmd *)desc.data;
3159         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3160         req->tqp_vf = func_id;
3161         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3162         if (!is_pf)
3163                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3164         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3165
3166         ret = hns3_cmd_send(hw, &desc, 1);
3167         if (ret)
3168                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3169
3170         return ret;
3171 }
3172
3173 static int
3174 hns3_map_tqp(struct hns3_hw *hw)
3175 {
3176         int ret;
3177         int i;
3178
3179         /*
3180          * In current version, VF is not supported when PF is driven by DPDK
3181          * driver, so we assign total tqps_num tqps allocated to this port
3182          * to PF.
3183          */
3184         for (i = 0; i < hw->total_tqps_num; i++) {
3185                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3186                 if (ret)
3187                         return ret;
3188         }
3189
3190         return 0;
3191 }
3192
3193 static int
3194 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3195 {
3196         struct hns3_config_mac_speed_dup_cmd *req;
3197         struct hns3_cmd_desc desc;
3198         int ret;
3199
3200         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3201
3202         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3203
3204         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3205
3206         switch (speed) {
3207         case ETH_SPEED_NUM_10M:
3208                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3209                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3210                 break;
3211         case ETH_SPEED_NUM_100M:
3212                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3213                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3214                 break;
3215         case ETH_SPEED_NUM_1G:
3216                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3217                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3218                 break;
3219         case ETH_SPEED_NUM_10G:
3220                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3221                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3222                 break;
3223         case ETH_SPEED_NUM_25G:
3224                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3225                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3226                 break;
3227         case ETH_SPEED_NUM_40G:
3228                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3229                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3230                 break;
3231         case ETH_SPEED_NUM_50G:
3232                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3233                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3234                 break;
3235         case ETH_SPEED_NUM_100G:
3236                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3237                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3238                 break;
3239         case ETH_SPEED_NUM_200G:
3240                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3241                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3242                 break;
3243         default:
3244                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3245                 return -EINVAL;
3246         }
3247
3248         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3249
3250         ret = hns3_cmd_send(hw, &desc, 1);
3251         if (ret)
3252                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3253
3254         return ret;
3255 }
3256
3257 static int
3258 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3259 {
3260         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3261         struct hns3_pf *pf = &hns->pf;
3262         struct hns3_priv_buf *priv;
3263         uint32_t i, total_size;
3264
3265         total_size = pf->pkt_buf_size;
3266
3267         /* alloc tx buffer for all enabled tc */
3268         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3269                 priv = &buf_alloc->priv_buf[i];
3270
3271                 if (hw->hw_tc_map & BIT(i)) {
3272                         if (total_size < pf->tx_buf_size)
3273                                 return -ENOMEM;
3274
3275                         priv->tx_buf_size = pf->tx_buf_size;
3276                 } else
3277                         priv->tx_buf_size = 0;
3278
3279                 total_size -= priv->tx_buf_size;
3280         }
3281
3282         return 0;
3283 }
3284
3285 static int
3286 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3287 {
3288 /* TX buffer size is unit by 128 byte */
3289 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3290 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3291         struct hns3_tx_buff_alloc_cmd *req;
3292         struct hns3_cmd_desc desc;
3293         uint32_t buf_size;
3294         uint32_t i;
3295         int ret;
3296
3297         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3298
3299         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3300         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3301                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3302
3303                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3304                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3305                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3306         }
3307
3308         ret = hns3_cmd_send(hw, &desc, 1);
3309         if (ret)
3310                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3311
3312         return ret;
3313 }
3314
3315 static int
3316 hns3_get_tc_num(struct hns3_hw *hw)
3317 {
3318         int cnt = 0;
3319         uint8_t i;
3320
3321         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3322                 if (hw->hw_tc_map & BIT(i))
3323                         cnt++;
3324         return cnt;
3325 }
3326
3327 static uint32_t
3328 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3329 {
3330         struct hns3_priv_buf *priv;
3331         uint32_t rx_priv = 0;
3332         int i;
3333
3334         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3335                 priv = &buf_alloc->priv_buf[i];
3336                 if (priv->enable)
3337                         rx_priv += priv->buf_size;
3338         }
3339         return rx_priv;
3340 }
3341
3342 static uint32_t
3343 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3344 {
3345         uint32_t total_tx_size = 0;
3346         uint32_t i;
3347
3348         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3349                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3350
3351         return total_tx_size;
3352 }
3353
3354 /* Get the number of pfc enabled TCs, which have private buffer */
3355 static int
3356 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3357 {
3358         struct hns3_priv_buf *priv;
3359         int cnt = 0;
3360         uint8_t i;
3361
3362         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3363                 priv = &buf_alloc->priv_buf[i];
3364                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3365                         cnt++;
3366         }
3367
3368         return cnt;
3369 }
3370
3371 /* Get the number of pfc disabled TCs, which have private buffer */
3372 static int
3373 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3374                          struct hns3_pkt_buf_alloc *buf_alloc)
3375 {
3376         struct hns3_priv_buf *priv;
3377         int cnt = 0;
3378         uint8_t i;
3379
3380         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3381                 priv = &buf_alloc->priv_buf[i];
3382                 if (hw->hw_tc_map & BIT(i) &&
3383                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3384                         cnt++;
3385         }
3386
3387         return cnt;
3388 }
3389
3390 static bool
3391 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3392                   uint32_t rx_all)
3393 {
3394         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3395         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3396         struct hns3_pf *pf = &hns->pf;
3397         uint32_t shared_buf, aligned_mps;
3398         uint32_t rx_priv;
3399         uint8_t tc_num;
3400         uint8_t i;
3401
3402         tc_num = hns3_get_tc_num(hw);
3403         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3404
3405         if (hns3_dev_dcb_supported(hw))
3406                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3407                                         pf->dv_buf_size;
3408         else
3409                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3410                                         + pf->dv_buf_size;
3411
3412         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3413         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3414                              HNS3_BUF_SIZE_UNIT);
3415
3416         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3417         if (rx_all < rx_priv + shared_std)
3418                 return false;
3419
3420         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3421         buf_alloc->s_buf.buf_size = shared_buf;
3422         if (hns3_dev_dcb_supported(hw)) {
3423                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3424                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3425                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3426                                   HNS3_BUF_SIZE_UNIT);
3427         } else {
3428                 buf_alloc->s_buf.self.high =
3429                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3430                 buf_alloc->s_buf.self.low = aligned_mps;
3431         }
3432
3433         if (hns3_dev_dcb_supported(hw)) {
3434                 hi_thrd = shared_buf - pf->dv_buf_size;
3435
3436                 if (tc_num <= NEED_RESERVE_TC_NUM)
3437                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3438                                   BUF_MAX_PERCENT;
3439
3440                 if (tc_num)
3441                         hi_thrd = hi_thrd / tc_num;
3442
3443                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3444                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3445                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3446         } else {
3447                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3448                 lo_thrd = aligned_mps;
3449         }
3450
3451         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3452                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3453                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3454         }
3455
3456         return true;
3457 }
3458
3459 static bool
3460 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3461                      struct hns3_pkt_buf_alloc *buf_alloc)
3462 {
3463         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3464         struct hns3_pf *pf = &hns->pf;
3465         struct hns3_priv_buf *priv;
3466         uint32_t aligned_mps;
3467         uint32_t rx_all;
3468         uint8_t i;
3469
3470         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3471         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3472
3473         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3474                 priv = &buf_alloc->priv_buf[i];
3475
3476                 priv->enable = 0;
3477                 priv->wl.low = 0;
3478                 priv->wl.high = 0;
3479                 priv->buf_size = 0;
3480
3481                 if (!(hw->hw_tc_map & BIT(i)))
3482                         continue;
3483
3484                 priv->enable = 1;
3485                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3486                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3487                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3488                                                 HNS3_BUF_SIZE_UNIT);
3489                 } else {
3490                         priv->wl.low = 0;
3491                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3492                                         aligned_mps;
3493                 }
3494
3495                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3496         }
3497
3498         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3499 }
3500
3501 static bool
3502 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3503                              struct hns3_pkt_buf_alloc *buf_alloc)
3504 {
3505         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3506         struct hns3_pf *pf = &hns->pf;
3507         struct hns3_priv_buf *priv;
3508         int no_pfc_priv_num;
3509         uint32_t rx_all;
3510         uint8_t mask;
3511         int i;
3512
3513         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3514         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3515
3516         /* let the last to be cleared first */
3517         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3518                 priv = &buf_alloc->priv_buf[i];
3519                 mask = BIT((uint8_t)i);
3520
3521                 if (hw->hw_tc_map & mask &&
3522                     !(hw->dcb_info.hw_pfc_map & mask)) {
3523                         /* Clear the no pfc TC private buffer */
3524                         priv->wl.low = 0;
3525                         priv->wl.high = 0;
3526                         priv->buf_size = 0;
3527                         priv->enable = 0;
3528                         no_pfc_priv_num--;
3529                 }
3530
3531                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3532                     no_pfc_priv_num == 0)
3533                         break;
3534         }
3535
3536         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3537 }
3538
3539 static bool
3540 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3541                            struct hns3_pkt_buf_alloc *buf_alloc)
3542 {
3543         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3544         struct hns3_pf *pf = &hns->pf;
3545         struct hns3_priv_buf *priv;
3546         uint32_t rx_all;
3547         int pfc_priv_num;
3548         uint8_t mask;
3549         int i;
3550
3551         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3552         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3553
3554         /* let the last to be cleared first */
3555         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3556                 priv = &buf_alloc->priv_buf[i];
3557                 mask = BIT((uint8_t)i);
3558                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3559                         /* Reduce the number of pfc TC with private buffer */
3560                         priv->wl.low = 0;
3561                         priv->enable = 0;
3562                         priv->wl.high = 0;
3563                         priv->buf_size = 0;
3564                         pfc_priv_num--;
3565                 }
3566                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3567                     pfc_priv_num == 0)
3568                         break;
3569         }
3570
3571         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3572 }
3573
3574 static bool
3575 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3576                           struct hns3_pkt_buf_alloc *buf_alloc)
3577 {
3578 #define COMPENSATE_BUFFER       0x3C00
3579 #define COMPENSATE_HALF_MPS_NUM 5
3580 #define PRIV_WL_GAP             0x1800
3581         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3582         struct hns3_pf *pf = &hns->pf;
3583         uint32_t tc_num = hns3_get_tc_num(hw);
3584         uint32_t half_mps = pf->mps >> 1;
3585         struct hns3_priv_buf *priv;
3586         uint32_t min_rx_priv;
3587         uint32_t rx_priv;
3588         uint8_t i;
3589
3590         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3591         if (tc_num)
3592                 rx_priv = rx_priv / tc_num;
3593
3594         if (tc_num <= NEED_RESERVE_TC_NUM)
3595                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3596
3597         /*
3598          * Minimum value of private buffer in rx direction (min_rx_priv) is
3599          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3600          * buffer if rx_priv is greater than min_rx_priv.
3601          */
3602         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3603                         COMPENSATE_HALF_MPS_NUM * half_mps;
3604         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3605         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3606
3607         if (rx_priv < min_rx_priv)
3608                 return false;
3609
3610         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3611                 priv = &buf_alloc->priv_buf[i];
3612                 priv->enable = 0;
3613                 priv->wl.low = 0;
3614                 priv->wl.high = 0;
3615                 priv->buf_size = 0;
3616
3617                 if (!(hw->hw_tc_map & BIT(i)))
3618                         continue;
3619
3620                 priv->enable = 1;
3621                 priv->buf_size = rx_priv;
3622                 priv->wl.high = rx_priv - pf->dv_buf_size;
3623                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3624         }
3625
3626         buf_alloc->s_buf.buf_size = 0;
3627
3628         return true;
3629 }
3630
3631 /*
3632  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3633  * @hw: pointer to struct hns3_hw
3634  * @buf_alloc: pointer to buffer calculation data
3635  * @return: 0: calculate sucessful, negative: fail
3636  */
3637 static int
3638 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3639 {
3640         /* When DCB is not supported, rx private buffer is not allocated. */
3641         if (!hns3_dev_dcb_supported(hw)) {
3642                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3643                 struct hns3_pf *pf = &hns->pf;
3644                 uint32_t rx_all = pf->pkt_buf_size;
3645
3646                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3647                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3648                         return -ENOMEM;
3649
3650                 return 0;
3651         }
3652
3653         /*
3654          * Try to allocate privated packet buffer for all TCs without share
3655          * buffer.
3656          */
3657         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3658                 return 0;
3659
3660         /*
3661          * Try to allocate privated packet buffer for all TCs with share
3662          * buffer.
3663          */
3664         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3665                 return 0;
3666
3667         /*
3668          * For different application scenes, the enabled port number, TC number
3669          * and no_drop TC number are different. In order to obtain the better
3670          * performance, software could allocate the buffer size and configure
3671          * the waterline by tring to decrease the private buffer size according
3672          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3673          * enabled tc.
3674          */
3675         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3676                 return 0;
3677
3678         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3679                 return 0;
3680
3681         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3682                 return 0;
3683
3684         return -ENOMEM;
3685 }
3686
3687 static int
3688 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3689 {
3690         struct hns3_rx_priv_buff_cmd *req;
3691         struct hns3_cmd_desc desc;
3692         uint32_t buf_size;
3693         int ret;
3694         int i;
3695
3696         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3697         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3698
3699         /* Alloc private buffer TCs */
3700         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3701                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3702
3703                 req->buf_num[i] =
3704                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3705                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3706         }
3707
3708         buf_size = buf_alloc->s_buf.buf_size;
3709         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3710                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3711
3712         ret = hns3_cmd_send(hw, &desc, 1);
3713         if (ret)
3714                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3715
3716         return ret;
3717 }
3718
3719 static int
3720 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3721 {
3722 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3723         struct hns3_rx_priv_wl_buf *req;
3724         struct hns3_priv_buf *priv;
3725         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3726         int i, j;
3727         int ret;
3728
3729         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3730                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3731                                           false);
3732                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3733
3734                 /* The first descriptor set the NEXT bit to 1 */
3735                 if (i == 0)
3736                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3737                 else
3738                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3739
3740                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3741                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3742
3743                         priv = &buf_alloc->priv_buf[idx];
3744                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3745                                                         HNS3_BUF_UNIT_S);
3746                         req->tc_wl[j].high |=
3747                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3748                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3749                                                         HNS3_BUF_UNIT_S);
3750                         req->tc_wl[j].low |=
3751                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3752                 }
3753         }
3754
3755         /* Send 2 descriptor at one time */
3756         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3757         if (ret)
3758                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3759                              ret);
3760         return ret;
3761 }
3762
3763 static int
3764 hns3_common_thrd_config(struct hns3_hw *hw,
3765                         struct hns3_pkt_buf_alloc *buf_alloc)
3766 {
3767 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3768         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3769         struct hns3_rx_com_thrd *req;
3770         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3771         struct hns3_tc_thrd *tc;
3772         int tc_idx;
3773         int i, j;
3774         int ret;
3775
3776         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3777                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3778                                           false);
3779                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3780
3781                 /* The first descriptor set the NEXT bit to 1 */
3782                 if (i == 0)
3783                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3784                 else
3785                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3786
3787                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3788                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3789                         tc = &s_buf->tc_thrd[tc_idx];
3790
3791                         req->com_thrd[j].high =
3792                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3793                         req->com_thrd[j].high |=
3794                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3795                         req->com_thrd[j].low =
3796                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3797                         req->com_thrd[j].low |=
3798                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3799                 }
3800         }
3801
3802         /* Send 2 descriptors at one time */
3803         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3804         if (ret)
3805                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3806
3807         return ret;
3808 }
3809
3810 static int
3811 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3812 {
3813         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3814         struct hns3_rx_com_wl *req;
3815         struct hns3_cmd_desc desc;
3816         int ret;
3817
3818         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3819
3820         req = (struct hns3_rx_com_wl *)desc.data;
3821         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3822         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3823
3824         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3825         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3826
3827         ret = hns3_cmd_send(hw, &desc, 1);
3828         if (ret)
3829                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3830
3831         return ret;
3832 }
3833
3834 int
3835 hns3_buffer_alloc(struct hns3_hw *hw)
3836 {
3837         struct hns3_pkt_buf_alloc pkt_buf;
3838         int ret;
3839
3840         memset(&pkt_buf, 0, sizeof(pkt_buf));
3841         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3842         if (ret) {
3843                 PMD_INIT_LOG(ERR,
3844                              "could not calc tx buffer size for all TCs %d",
3845                              ret);
3846                 return ret;
3847         }
3848
3849         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3850         if (ret) {
3851                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3852                 return ret;
3853         }
3854
3855         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3856         if (ret) {
3857                 PMD_INIT_LOG(ERR,
3858                              "could not calc rx priv buffer size for all TCs %d",
3859                              ret);
3860                 return ret;
3861         }
3862
3863         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3864         if (ret) {
3865                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3866                 return ret;
3867         }
3868
3869         if (hns3_dev_dcb_supported(hw)) {
3870                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3871                 if (ret) {
3872                         PMD_INIT_LOG(ERR,
3873                                      "could not configure rx private waterline %d",
3874                                      ret);
3875                         return ret;
3876                 }
3877
3878                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3879                 if (ret) {
3880                         PMD_INIT_LOG(ERR,
3881                                      "could not configure common threshold %d",
3882                                      ret);
3883                         return ret;
3884                 }
3885         }
3886
3887         ret = hns3_common_wl_config(hw, &pkt_buf);
3888         if (ret)
3889                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3890                              ret);
3891
3892         return ret;
3893 }
3894
3895 static int
3896 hns3_mac_init(struct hns3_hw *hw)
3897 {
3898         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3899         struct hns3_mac *mac = &hw->mac;
3900         struct hns3_pf *pf = &hns->pf;
3901         int ret;
3902
3903         pf->support_sfp_query = true;
3904         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3905         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3906         if (ret) {
3907                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3908                 return ret;
3909         }
3910
3911         mac->link_status = ETH_LINK_DOWN;
3912
3913         return hns3_config_mtu(hw, pf->mps);
3914 }
3915
3916 static int
3917 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3918 {
3919 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3920 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3921 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3922 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3923         int return_status;
3924
3925         if (cmdq_resp) {
3926                 PMD_INIT_LOG(ERR,
3927                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3928                              cmdq_resp);
3929                 return -EIO;
3930         }
3931
3932         switch (resp_code) {
3933         case HNS3_ETHERTYPE_SUCCESS_ADD:
3934         case HNS3_ETHERTYPE_ALREADY_ADD:
3935                 return_status = 0;
3936                 break;
3937         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3938                 PMD_INIT_LOG(ERR,
3939                              "add mac ethertype failed for manager table overflow.");
3940                 return_status = -EIO;
3941                 break;
3942         case HNS3_ETHERTYPE_KEY_CONFLICT:
3943                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3944                 return_status = -EIO;
3945                 break;
3946         default:
3947                 PMD_INIT_LOG(ERR,
3948                              "add mac ethertype failed for undefined, code=%u.",
3949                              resp_code);
3950                 return_status = -EIO;
3951                 break;
3952         }
3953
3954         return return_status;
3955 }
3956
3957 static int
3958 hns3_add_mgr_tbl(struct hns3_hw *hw,
3959                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3960 {
3961         struct hns3_cmd_desc desc;
3962         uint8_t resp_code;
3963         uint16_t retval;
3964         int ret;
3965
3966         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3967         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3968
3969         ret = hns3_cmd_send(hw, &desc, 1);
3970         if (ret) {
3971                 PMD_INIT_LOG(ERR,
3972                              "add mac ethertype failed for cmd_send, ret =%d.",
3973                              ret);
3974                 return ret;
3975         }
3976
3977         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3978         retval = rte_le_to_cpu_16(desc.retval);
3979
3980         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3981 }
3982
3983 static void
3984 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3985                      int *table_item_num)
3986 {
3987         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3988
3989         /*
3990          * In current version, we add one item in management table as below:
3991          * 0x0180C200000E -- LLDP MC address
3992          */
3993         tbl = mgr_table;
3994         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3995         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3996         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3997         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3998         tbl->i_port_bitmap = 0x1;
3999         *table_item_num = 1;
4000 }
4001
4002 static int
4003 hns3_init_mgr_tbl(struct hns3_hw *hw)
4004 {
4005 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4006         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4007         int table_item_num;
4008         int ret;
4009         int i;
4010
4011         memset(mgr_table, 0, sizeof(mgr_table));
4012         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4013         for (i = 0; i < table_item_num; i++) {
4014                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4015                 if (ret) {
4016                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4017                                      ret);
4018                         return ret;
4019                 }
4020         }
4021
4022         return 0;
4023 }
4024
4025 static void
4026 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4027                         bool en_mc, bool en_bc, int vport_id)
4028 {
4029         if (!param)
4030                 return;
4031
4032         memset(param, 0, sizeof(struct hns3_promisc_param));
4033         if (en_uc)
4034                 param->enable = HNS3_PROMISC_EN_UC;
4035         if (en_mc)
4036                 param->enable |= HNS3_PROMISC_EN_MC;
4037         if (en_bc)
4038                 param->enable |= HNS3_PROMISC_EN_BC;
4039         param->vf_id = vport_id;
4040 }
4041
4042 static int
4043 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4044 {
4045         struct hns3_promisc_cfg_cmd *req;
4046         struct hns3_cmd_desc desc;
4047         int ret;
4048
4049         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4050
4051         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4052         req->vf_id = param->vf_id;
4053         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4054             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4055
4056         ret = hns3_cmd_send(hw, &desc, 1);
4057         if (ret)
4058                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4059
4060         return ret;
4061 }
4062
4063 static int
4064 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4065 {
4066         struct hns3_promisc_param param;
4067         bool en_bc_pmc = true;
4068         uint8_t vf_id;
4069
4070         /*
4071          * In current version VF is not supported when PF is driven by DPDK
4072          * driver, just need to configure parameters for PF vport.
4073          */
4074         vf_id = HNS3_PF_FUNC_ID;
4075
4076         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4077         return hns3_cmd_set_promisc_mode(hw, &param);
4078 }
4079
4080 static int
4081 hns3_promisc_init(struct hns3_hw *hw)
4082 {
4083         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4084         struct hns3_pf *pf = &hns->pf;
4085         struct hns3_promisc_param param;
4086         uint16_t func_id;
4087         int ret;
4088
4089         ret = hns3_set_promisc_mode(hw, false, false);
4090         if (ret) {
4091                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4092                 return ret;
4093         }
4094
4095         /*
4096          * In current version VFs are not supported when PF is driven by DPDK
4097          * driver. After PF has been taken over by DPDK, the original VF will
4098          * be invalid. So, there is a possibility of entry residues. It should
4099          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4100          * during init.
4101          */
4102         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4103                 hns3_promisc_param_init(&param, false, false, false, func_id);
4104                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4105                 if (ret) {
4106                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4107                                         " ret = %d", func_id, ret);
4108                         return ret;
4109                 }
4110         }
4111
4112         return 0;
4113 }
4114
4115 static void
4116 hns3_promisc_uninit(struct hns3_hw *hw)
4117 {
4118         struct hns3_promisc_param param;
4119         uint16_t func_id;
4120         int ret;
4121
4122         func_id = HNS3_PF_FUNC_ID;
4123
4124         /*
4125          * In current version VFs are not supported when PF is driven by
4126          * DPDK driver, and VFs' promisc mode status has been cleared during
4127          * init and their status will not change. So just clear PF's promisc
4128          * mode status during uninit.
4129          */
4130         hns3_promisc_param_init(&param, false, false, false, func_id);
4131         ret = hns3_cmd_set_promisc_mode(hw, &param);
4132         if (ret)
4133                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4134                                 " uninit, ret = %d", ret);
4135 }
4136
4137 static int
4138 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4139 {
4140         bool allmulti = dev->data->all_multicast ? true : false;
4141         struct hns3_adapter *hns = dev->data->dev_private;
4142         struct hns3_hw *hw = &hns->hw;
4143         uint64_t offloads;
4144         int err;
4145         int ret;
4146
4147         rte_spinlock_lock(&hw->lock);
4148         ret = hns3_set_promisc_mode(hw, true, true);
4149         if (ret) {
4150                 rte_spinlock_unlock(&hw->lock);
4151                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4152                          ret);
4153                 return ret;
4154         }
4155
4156         /*
4157          * When promiscuous mode was enabled, disable the vlan filter to let
4158          * all packets coming in in the receiving direction.
4159          */
4160         offloads = dev->data->dev_conf.rxmode.offloads;
4161         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4162                 ret = hns3_enable_vlan_filter(hns, false);
4163                 if (ret) {
4164                         hns3_err(hw, "failed to enable promiscuous mode due to "
4165                                      "failure to disable vlan filter, ret = %d",
4166                                  ret);
4167                         err = hns3_set_promisc_mode(hw, false, allmulti);
4168                         if (err)
4169                                 hns3_err(hw, "failed to restore promiscuous "
4170                                          "status after disable vlan filter "
4171                                          "failed during enabling promiscuous "
4172                                          "mode, ret = %d", ret);
4173                 }
4174         }
4175
4176         rte_spinlock_unlock(&hw->lock);
4177
4178         return ret;
4179 }
4180
4181 static int
4182 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4183 {
4184         bool allmulti = dev->data->all_multicast ? true : false;
4185         struct hns3_adapter *hns = dev->data->dev_private;
4186         struct hns3_hw *hw = &hns->hw;
4187         uint64_t offloads;
4188         int err;
4189         int ret;
4190
4191         /* If now in all_multicast mode, must remain in all_multicast mode. */
4192         rte_spinlock_lock(&hw->lock);
4193         ret = hns3_set_promisc_mode(hw, false, allmulti);
4194         if (ret) {
4195                 rte_spinlock_unlock(&hw->lock);
4196                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4197                          ret);
4198                 return ret;
4199         }
4200         /* when promiscuous mode was disabled, restore the vlan filter status */
4201         offloads = dev->data->dev_conf.rxmode.offloads;
4202         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4203                 ret = hns3_enable_vlan_filter(hns, true);
4204                 if (ret) {
4205                         hns3_err(hw, "failed to disable promiscuous mode due to"
4206                                  " failure to restore vlan filter, ret = %d",
4207                                  ret);
4208                         err = hns3_set_promisc_mode(hw, true, true);
4209                         if (err)
4210                                 hns3_err(hw, "failed to restore promiscuous "
4211                                          "status after enabling vlan filter "
4212                                          "failed during disabling promiscuous "
4213                                          "mode, ret = %d", ret);
4214                 }
4215         }
4216         rte_spinlock_unlock(&hw->lock);
4217
4218         return ret;
4219 }
4220
4221 static int
4222 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4223 {
4224         struct hns3_adapter *hns = dev->data->dev_private;
4225         struct hns3_hw *hw = &hns->hw;
4226         int ret;
4227
4228         if (dev->data->promiscuous)
4229                 return 0;
4230
4231         rte_spinlock_lock(&hw->lock);
4232         ret = hns3_set_promisc_mode(hw, false, true);
4233         rte_spinlock_unlock(&hw->lock);
4234         if (ret)
4235                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4236                          ret);
4237
4238         return ret;
4239 }
4240
4241 static int
4242 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4243 {
4244         struct hns3_adapter *hns = dev->data->dev_private;
4245         struct hns3_hw *hw = &hns->hw;
4246         int ret;
4247
4248         /* If now in promiscuous mode, must remain in all_multicast mode. */
4249         if (dev->data->promiscuous)
4250                 return 0;
4251
4252         rte_spinlock_lock(&hw->lock);
4253         ret = hns3_set_promisc_mode(hw, false, false);
4254         rte_spinlock_unlock(&hw->lock);
4255         if (ret)
4256                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4257                          ret);
4258
4259         return ret;
4260 }
4261
4262 static int
4263 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4264 {
4265         struct hns3_hw *hw = &hns->hw;
4266         bool allmulti = hw->data->all_multicast ? true : false;
4267         int ret;
4268
4269         if (hw->data->promiscuous) {
4270                 ret = hns3_set_promisc_mode(hw, true, true);
4271                 if (ret)
4272                         hns3_err(hw, "failed to restore promiscuous mode, "
4273                                  "ret = %d", ret);
4274                 return ret;
4275         }
4276
4277         ret = hns3_set_promisc_mode(hw, false, allmulti);
4278         if (ret)
4279                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4280                          ret);
4281         return ret;
4282 }
4283
4284 static int
4285 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4286 {
4287         struct hns3_sfp_speed_cmd *resp;
4288         struct hns3_cmd_desc desc;
4289         int ret;
4290
4291         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4292         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4293         ret = hns3_cmd_send(hw, &desc, 1);
4294         if (ret == -EOPNOTSUPP) {
4295                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4296                 return ret;
4297         } else if (ret) {
4298                 hns3_err(hw, "get sfp speed failed %d", ret);
4299                 return ret;
4300         }
4301
4302         *speed = resp->sfp_speed;
4303
4304         return 0;
4305 }
4306
4307 static uint8_t
4308 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4309 {
4310         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4311                 duplex = ETH_LINK_FULL_DUPLEX;
4312
4313         return duplex;
4314 }
4315
4316 static int
4317 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4318 {
4319         struct hns3_mac *mac = &hw->mac;
4320         uint32_t cur_speed = mac->link_speed;
4321         int ret;
4322
4323         duplex = hns3_check_speed_dup(duplex, speed);
4324         if (mac->link_speed == speed && mac->link_duplex == duplex)
4325                 return 0;
4326
4327         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4328         if (ret)
4329                 return ret;
4330
4331         mac->link_speed = speed;
4332         ret = hns3_dcb_port_shaper_cfg(hw);
4333         if (ret) {
4334                 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4335                 mac->link_speed = cur_speed;
4336                 return ret;
4337         }
4338
4339         mac->link_duplex = duplex;
4340
4341         return 0;
4342 }
4343
4344 static int
4345 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4346 {
4347         struct hns3_adapter *hns = eth_dev->data->dev_private;
4348         struct hns3_hw *hw = &hns->hw;
4349         struct hns3_pf *pf = &hns->pf;
4350         uint32_t speed;
4351         int ret;
4352
4353         /* If IMP do not support get SFP/qSFP speed, return directly */
4354         if (!pf->support_sfp_query)
4355                 return 0;
4356
4357         ret = hns3_get_sfp_speed(hw, &speed);
4358         if (ret == -EOPNOTSUPP) {
4359                 pf->support_sfp_query = false;
4360                 return ret;
4361         } else if (ret)
4362                 return ret;
4363
4364         if (speed == ETH_SPEED_NUM_NONE)
4365                 return 0; /* do nothing if no SFP */
4366
4367         /* Config full duplex for SFP */
4368         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4369 }
4370
4371 static int
4372 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4373 {
4374         struct hns3_config_mac_mode_cmd *req;
4375         struct hns3_cmd_desc desc;
4376         uint32_t loop_en = 0;
4377         uint8_t val = 0;
4378         int ret;
4379
4380         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4381
4382         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4383         if (enable)
4384                 val = 1;
4385         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4386         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4387         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4388         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4389         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4390         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4391         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4392         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4393         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4394         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4395
4396         /*
4397          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4398          * when receiving frames. Otherwise, CRC will be stripped.
4399          */
4400         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4401                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4402         else
4403                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4404         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4405         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4406         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4407         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4408
4409         ret = hns3_cmd_send(hw, &desc, 1);
4410         if (ret)
4411                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4412
4413         return ret;
4414 }
4415
4416 static int
4417 hns3_get_mac_link_status(struct hns3_hw *hw)
4418 {
4419         struct hns3_link_status_cmd *req;
4420         struct hns3_cmd_desc desc;
4421         int link_status;
4422         int ret;
4423
4424         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4425         ret = hns3_cmd_send(hw, &desc, 1);
4426         if (ret) {
4427                 hns3_err(hw, "get link status cmd failed %d", ret);
4428                 return ETH_LINK_DOWN;
4429         }
4430
4431         req = (struct hns3_link_status_cmd *)desc.data;
4432         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4433
4434         return !!link_status;
4435 }
4436
4437 void
4438 hns3_update_link_status(struct hns3_hw *hw)
4439 {
4440         int state;
4441
4442         state = hns3_get_mac_link_status(hw);
4443         if (state != hw->mac.link_status) {
4444                 hw->mac.link_status = state;
4445                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4446         }
4447 }
4448
4449 static void
4450 hns3_service_handler(void *param)
4451 {
4452         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4453         struct hns3_adapter *hns = eth_dev->data->dev_private;
4454         struct hns3_hw *hw = &hns->hw;
4455
4456         if (!hns3_is_reset_pending(hns)) {
4457                 hns3_update_speed_duplex(eth_dev);
4458                 hns3_update_link_status(hw);
4459         } else
4460                 hns3_warn(hw, "Cancel the query when reset is pending");
4461
4462         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4463 }
4464
4465 static int
4466 hns3_init_hardware(struct hns3_adapter *hns)
4467 {
4468         struct hns3_hw *hw = &hns->hw;
4469         int ret;
4470
4471         ret = hns3_map_tqp(hw);
4472         if (ret) {
4473                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4474                 return ret;
4475         }
4476
4477         ret = hns3_init_umv_space(hw);
4478         if (ret) {
4479                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4480                 return ret;
4481         }
4482
4483         ret = hns3_mac_init(hw);
4484         if (ret) {
4485                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4486                 goto err_mac_init;
4487         }
4488
4489         ret = hns3_init_mgr_tbl(hw);
4490         if (ret) {
4491                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4492                 goto err_mac_init;
4493         }
4494
4495         ret = hns3_promisc_init(hw);
4496         if (ret) {
4497                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4498                              ret);
4499                 goto err_mac_init;
4500         }
4501
4502         ret = hns3_init_vlan_config(hns);
4503         if (ret) {
4504                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4505                 goto err_mac_init;
4506         }
4507
4508         ret = hns3_dcb_init(hw);
4509         if (ret) {
4510                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4511                 goto err_mac_init;
4512         }
4513
4514         ret = hns3_init_fd_config(hns);
4515         if (ret) {
4516                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4517                 goto err_mac_init;
4518         }
4519
4520         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4521         if (ret) {
4522                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4523                 goto err_mac_init;
4524         }
4525
4526         ret = hns3_config_gro(hw, false);
4527         if (ret) {
4528                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4529                 goto err_mac_init;
4530         }
4531
4532         /*
4533          * In the initialization clearing the all hardware mapping relationship
4534          * configurations between queues and interrupt vectors is needed, so
4535          * some error caused by the residual configurations, such as the
4536          * unexpected interrupt, can be avoid.
4537          */
4538         ret = hns3_init_ring_with_vector(hw);
4539         if (ret) {
4540                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4541                 goto err_mac_init;
4542         }
4543
4544         return 0;
4545
4546 err_mac_init:
4547         hns3_uninit_umv_space(hw);
4548         return ret;
4549 }
4550
4551 static int
4552 hns3_clear_hw(struct hns3_hw *hw)
4553 {
4554         struct hns3_cmd_desc desc;
4555         int ret;
4556
4557         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4558
4559         ret = hns3_cmd_send(hw, &desc, 1);
4560         if (ret && ret != -EOPNOTSUPP)
4561                 return ret;
4562
4563         return 0;
4564 }
4565
4566 static void
4567 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4568 {
4569         uint32_t val;
4570
4571         /*
4572          * The new firmware support report more hardware error types by
4573          * msix mode. These errors are defined as RAS errors in hardware
4574          * and belong to a different type from the MSI-x errors processed
4575          * by the network driver.
4576          *
4577          * Network driver should open the new error report on initialition
4578          */
4579         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4580         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4581         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4582 }
4583
4584 static int
4585 hns3_init_pf(struct rte_eth_dev *eth_dev)
4586 {
4587         struct rte_device *dev = eth_dev->device;
4588         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4589         struct hns3_adapter *hns = eth_dev->data->dev_private;
4590         struct hns3_hw *hw = &hns->hw;
4591         int ret;
4592
4593         PMD_INIT_FUNC_TRACE();
4594
4595         /* Get hardware io base address from pcie BAR2 IO space */
4596         hw->io_base = pci_dev->mem_resource[2].addr;
4597
4598         /* Firmware command queue initialize */
4599         ret = hns3_cmd_init_queue(hw);
4600         if (ret) {
4601                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4602                 goto err_cmd_init_queue;
4603         }
4604
4605         hns3_clear_all_event_cause(hw);
4606
4607         /* Firmware command initialize */
4608         ret = hns3_cmd_init(hw);
4609         if (ret) {
4610                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4611                 goto err_cmd_init;
4612         }
4613
4614         /*
4615          * To ensure that the hardware environment is clean during
4616          * initialization, the driver actively clear the hardware environment
4617          * during initialization, including PF and corresponding VFs' vlan, mac,
4618          * flow table configurations, etc.
4619          */
4620         ret = hns3_clear_hw(hw);
4621         if (ret) {
4622                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4623                 goto err_cmd_init;
4624         }
4625
4626         hns3_config_all_msix_error(hw, true);
4627
4628         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4629                                          hns3_interrupt_handler,
4630                                          eth_dev);
4631         if (ret) {
4632                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4633                 goto err_intr_callback_register;
4634         }
4635
4636         /* Enable interrupt */
4637         rte_intr_enable(&pci_dev->intr_handle);
4638         hns3_pf_enable_irq0(hw);
4639
4640         /* Get configuration */
4641         ret = hns3_get_configuration(hw);
4642         if (ret) {
4643                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4644                 goto err_get_config;
4645         }
4646
4647         ret = hns3_tqp_stats_init(hw);
4648         if (ret)
4649                 goto err_get_config;
4650
4651         ret = hns3_init_hardware(hns);
4652         if (ret) {
4653                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4654                 goto err_init_hw;
4655         }
4656
4657         /* Initialize flow director filter list & hash */
4658         ret = hns3_fdir_filter_init(hns);
4659         if (ret) {
4660                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4661                 goto err_fdir;
4662         }
4663
4664         hns3_set_default_rss_args(hw);
4665
4666         ret = hns3_enable_hw_error_intr(hns, true);
4667         if (ret) {
4668                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4669                              ret);
4670                 goto err_enable_intr;
4671         }
4672
4673         return 0;
4674
4675 err_enable_intr:
4676         hns3_fdir_filter_uninit(hns);
4677 err_fdir:
4678         hns3_uninit_umv_space(hw);
4679 err_init_hw:
4680         hns3_tqp_stats_uninit(hw);
4681 err_get_config:
4682         hns3_pf_disable_irq0(hw);
4683         rte_intr_disable(&pci_dev->intr_handle);
4684         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4685                              eth_dev);
4686 err_intr_callback_register:
4687 err_cmd_init:
4688         hns3_cmd_uninit(hw);
4689         hns3_cmd_destroy_queue(hw);
4690 err_cmd_init_queue:
4691         hw->io_base = NULL;
4692
4693         return ret;
4694 }
4695
4696 static void
4697 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4698 {
4699         struct hns3_adapter *hns = eth_dev->data->dev_private;
4700         struct rte_device *dev = eth_dev->device;
4701         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4702         struct hns3_hw *hw = &hns->hw;
4703
4704         PMD_INIT_FUNC_TRACE();
4705
4706         hns3_enable_hw_error_intr(hns, false);
4707         hns3_rss_uninit(hns);
4708         (void)hns3_config_gro(hw, false);
4709         hns3_promisc_uninit(hw);
4710         hns3_fdir_filter_uninit(hns);
4711         hns3_uninit_umv_space(hw);
4712         hns3_tqp_stats_uninit(hw);
4713         hns3_pf_disable_irq0(hw);
4714         rte_intr_disable(&pci_dev->intr_handle);
4715         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4716                              eth_dev);
4717         hns3_config_all_msix_error(hw, false);
4718         hns3_cmd_uninit(hw);
4719         hns3_cmd_destroy_queue(hw);
4720         hw->io_base = NULL;
4721 }
4722
4723 static int
4724 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4725 {
4726         struct hns3_hw *hw = &hns->hw;
4727         int ret;
4728
4729         ret = hns3_dcb_cfg_update(hns);
4730         if (ret)
4731                 return ret;
4732
4733         ret = hns3_init_queues(hns, reset_queue);
4734         if (ret) {
4735                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4736                 return ret;
4737         }
4738
4739         ret = hns3_cfg_mac_mode(hw, true);
4740         if (ret) {
4741                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4742                 goto err_config_mac_mode;
4743         }
4744         return 0;
4745
4746 err_config_mac_mode:
4747         hns3_dev_release_mbufs(hns);
4748         /*
4749          * Here is exception handling, hns3_reset_all_tqps will have the
4750          * corresponding error message if it is handled incorrectly, so it is
4751          * not necessary to check hns3_reset_all_tqps return value, here keep
4752          * ret as the error code causing the exception.
4753          */
4754         (void)hns3_reset_all_tqps(hns);
4755         return ret;
4756 }
4757
4758 static int
4759 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4760 {
4761         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4762         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4763         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4764         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4765         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4766         uint32_t intr_vector;
4767         uint16_t q_id;
4768         int ret;
4769
4770         if (dev->data->dev_conf.intr_conf.rxq == 0)
4771                 return 0;
4772
4773         /* disable uio/vfio intr/eventfd mapping */
4774         rte_intr_disable(intr_handle);
4775
4776         /* check and configure queue intr-vector mapping */
4777         if (rte_intr_cap_multiple(intr_handle) ||
4778             !RTE_ETH_DEV_SRIOV(dev).active) {
4779                 intr_vector = hw->used_rx_queues;
4780                 /* creates event fd for each intr vector when MSIX is used */
4781                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4782                         return -EINVAL;
4783         }
4784         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4785                 intr_handle->intr_vec =
4786                         rte_zmalloc("intr_vec",
4787                                     hw->used_rx_queues * sizeof(int), 0);
4788                 if (intr_handle->intr_vec == NULL) {
4789                         hns3_err(hw, "Failed to allocate %u rx_queues"
4790                                      " intr_vec", hw->used_rx_queues);
4791                         ret = -ENOMEM;
4792                         goto alloc_intr_vec_error;
4793                 }
4794         }
4795
4796         if (rte_intr_allow_others(intr_handle)) {
4797                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4798                 base = RTE_INTR_VEC_RXTX_OFFSET;
4799         }
4800         if (rte_intr_dp_is_en(intr_handle)) {
4801                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4802                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4803                                                          HNS3_RING_TYPE_RX,
4804                                                          q_id);
4805                         if (ret)
4806                                 goto bind_vector_error;
4807                         intr_handle->intr_vec[q_id] = vec;
4808                         if (vec < base + intr_handle->nb_efd - 1)
4809                                 vec++;
4810                 }
4811         }
4812         rte_intr_enable(intr_handle);
4813         return 0;
4814
4815 bind_vector_error:
4816         rte_intr_efd_disable(intr_handle);
4817         if (intr_handle->intr_vec) {
4818                 free(intr_handle->intr_vec);
4819                 intr_handle->intr_vec = NULL;
4820         }
4821         return ret;
4822 alloc_intr_vec_error:
4823         rte_intr_efd_disable(intr_handle);
4824         return ret;
4825 }
4826
4827 static int
4828 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4829 {
4830         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4831         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4832         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4833         uint16_t q_id;
4834         int ret;
4835
4836         if (dev->data->dev_conf.intr_conf.rxq == 0)
4837                 return 0;
4838
4839         if (rte_intr_dp_is_en(intr_handle)) {
4840                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4841                         ret = hns3_bind_ring_with_vector(hw,
4842                                         intr_handle->intr_vec[q_id], true,
4843                                         HNS3_RING_TYPE_RX, q_id);
4844                         if (ret)
4845                                 return ret;
4846                 }
4847         }
4848
4849         return 0;
4850 }
4851
4852 static void
4853 hns3_restore_filter(struct rte_eth_dev *dev)
4854 {
4855         hns3_restore_rss_filter(dev);
4856 }
4857
4858 static int
4859 hns3_dev_start(struct rte_eth_dev *dev)
4860 {
4861         struct hns3_adapter *hns = dev->data->dev_private;
4862         struct hns3_hw *hw = &hns->hw;
4863         int ret;
4864
4865         PMD_INIT_FUNC_TRACE();
4866         if (rte_atomic16_read(&hw->reset.resetting))
4867                 return -EBUSY;
4868
4869         rte_spinlock_lock(&hw->lock);
4870         hw->adapter_state = HNS3_NIC_STARTING;
4871
4872         ret = hns3_do_start(hns, true);
4873         if (ret) {
4874                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4875                 rte_spinlock_unlock(&hw->lock);
4876                 return ret;
4877         }
4878         ret = hns3_map_rx_interrupt(dev);
4879         if (ret) {
4880                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4881                 rte_spinlock_unlock(&hw->lock);
4882                 return ret;
4883         }
4884
4885         /*
4886          * There are three register used to control the status of a TQP
4887          * (contains a pair of Tx queue and Rx queue) in the new version network
4888          * engine. One is used to control the enabling of Tx queue, the other is
4889          * used to control the enabling of Rx queue, and the last is the master
4890          * switch used to control the enabling of the tqp. The Tx register and
4891          * TQP register must be enabled at the same time to enable a Tx queue.
4892          * The same applies to the Rx queue. For the older network engine, this
4893          * function only refresh the enabled flag, and it is used to update the
4894          * status of queue in the dpdk framework.
4895          */
4896         ret = hns3_start_all_txqs(dev);
4897         if (ret) {
4898                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4899                 rte_spinlock_unlock(&hw->lock);
4900                 return ret;
4901         }
4902
4903         ret = hns3_start_all_rxqs(dev);
4904         if (ret) {
4905                 hns3_stop_all_txqs(dev);
4906                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4907                 rte_spinlock_unlock(&hw->lock);
4908                 return ret;
4909         }
4910
4911         hw->adapter_state = HNS3_NIC_STARTED;
4912         rte_spinlock_unlock(&hw->lock);
4913
4914         hns3_rx_scattered_calc(dev);
4915         hns3_set_rxtx_function(dev);
4916         hns3_mp_req_start_rxtx(dev);
4917         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4918
4919         hns3_restore_filter(dev);
4920
4921         /* Enable interrupt of all rx queues before enabling queues */
4922         hns3_dev_all_rx_queue_intr_enable(hw, true);
4923
4924         /*
4925          * After finished the initialization, enable tqps to receive/transmit
4926          * packets and refresh all queue status.
4927          */
4928         hns3_start_tqps(hw);
4929
4930         hns3_info(hw, "hns3 dev start successful!");
4931         return 0;
4932 }
4933
4934 static int
4935 hns3_do_stop(struct hns3_adapter *hns)
4936 {
4937         struct hns3_hw *hw = &hns->hw;
4938         int ret;
4939
4940         ret = hns3_cfg_mac_mode(hw, false);
4941         if (ret)
4942                 return ret;
4943         hw->mac.link_status = ETH_LINK_DOWN;
4944
4945         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4946                 hns3_configure_all_mac_addr(hns, true);
4947                 ret = hns3_reset_all_tqps(hns);
4948                 if (ret) {
4949                         hns3_err(hw, "failed to reset all queues ret = %d.",
4950                                  ret);
4951                         return ret;
4952                 }
4953         }
4954         hw->mac.default_addr_setted = false;
4955         return 0;
4956 }
4957
4958 static void
4959 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4960 {
4961         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4962         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4963         struct hns3_adapter *hns = dev->data->dev_private;
4964         struct hns3_hw *hw = &hns->hw;
4965         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4966         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4967         uint16_t q_id;
4968
4969         if (dev->data->dev_conf.intr_conf.rxq == 0)
4970                 return;
4971
4972         /* unmap the ring with vector */
4973         if (rte_intr_allow_others(intr_handle)) {
4974                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4975                 base = RTE_INTR_VEC_RXTX_OFFSET;
4976         }
4977         if (rte_intr_dp_is_en(intr_handle)) {
4978                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4979                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4980                                                          HNS3_RING_TYPE_RX,
4981                                                          q_id);
4982                         if (vec < base + intr_handle->nb_efd - 1)
4983                                 vec++;
4984                 }
4985         }
4986         /* Clean datapath event and queue/vec mapping */
4987         rte_intr_efd_disable(intr_handle);
4988         if (intr_handle->intr_vec) {
4989                 rte_free(intr_handle->intr_vec);
4990                 intr_handle->intr_vec = NULL;
4991         }
4992 }
4993
4994 static int
4995 hns3_dev_stop(struct rte_eth_dev *dev)
4996 {
4997         struct hns3_adapter *hns = dev->data->dev_private;
4998         struct hns3_hw *hw = &hns->hw;
4999
5000         PMD_INIT_FUNC_TRACE();
5001         dev->data->dev_started = 0;
5002
5003         hw->adapter_state = HNS3_NIC_STOPPING;
5004         hns3_set_rxtx_function(dev);
5005         rte_wmb();
5006         /* Disable datapath on secondary process. */
5007         hns3_mp_req_stop_rxtx(dev);
5008         /* Prevent crashes when queues are still in use. */
5009         rte_delay_ms(hw->tqps_num);
5010
5011         rte_spinlock_lock(&hw->lock);
5012         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
5013                 hns3_stop_tqps(hw);
5014                 hns3_do_stop(hns);
5015                 hns3_unmap_rx_interrupt(dev);
5016                 hns3_dev_release_mbufs(hns);
5017                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5018         }
5019         hns3_rx_scattered_reset(dev);
5020         rte_eal_alarm_cancel(hns3_service_handler, dev);
5021         rte_spinlock_unlock(&hw->lock);
5022
5023         return 0;
5024 }
5025
5026 static int
5027 hns3_dev_close(struct rte_eth_dev *eth_dev)
5028 {
5029         struct hns3_adapter *hns = eth_dev->data->dev_private;
5030         struct hns3_hw *hw = &hns->hw;
5031         int ret = 0;
5032
5033         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5034                 rte_free(eth_dev->process_private);
5035                 eth_dev->process_private = NULL;
5036                 return 0;
5037         }
5038
5039         if (hw->adapter_state == HNS3_NIC_STARTED)
5040                 ret = hns3_dev_stop(eth_dev);
5041
5042         hw->adapter_state = HNS3_NIC_CLOSING;
5043         hns3_reset_abort(hns);
5044         hw->adapter_state = HNS3_NIC_CLOSED;
5045
5046         hns3_configure_all_mc_mac_addr(hns, true);
5047         hns3_remove_all_vlan_table(hns);
5048         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5049         hns3_uninit_pf(eth_dev);
5050         hns3_free_all_queues(eth_dev);
5051         rte_free(hw->reset.wait_data);
5052         rte_free(eth_dev->process_private);
5053         eth_dev->process_private = NULL;
5054         hns3_mp_uninit_primary();
5055         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5056
5057         return ret;
5058 }
5059
5060 static int
5061 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5062 {
5063         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5064         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5065
5066         fc_conf->pause_time = pf->pause_time;
5067
5068         /* return fc current mode */
5069         switch (hw->current_mode) {
5070         case HNS3_FC_FULL:
5071                 fc_conf->mode = RTE_FC_FULL;
5072                 break;
5073         case HNS3_FC_TX_PAUSE:
5074                 fc_conf->mode = RTE_FC_TX_PAUSE;
5075                 break;
5076         case HNS3_FC_RX_PAUSE:
5077                 fc_conf->mode = RTE_FC_RX_PAUSE;
5078                 break;
5079         case HNS3_FC_NONE:
5080         default:
5081                 fc_conf->mode = RTE_FC_NONE;
5082                 break;
5083         }
5084
5085         return 0;
5086 }
5087
5088 static void
5089 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5090 {
5091         switch (mode) {
5092         case RTE_FC_NONE:
5093                 hw->requested_mode = HNS3_FC_NONE;
5094                 break;
5095         case RTE_FC_RX_PAUSE:
5096                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5097                 break;
5098         case RTE_FC_TX_PAUSE:
5099                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5100                 break;
5101         case RTE_FC_FULL:
5102                 hw->requested_mode = HNS3_FC_FULL;
5103                 break;
5104         default:
5105                 hw->requested_mode = HNS3_FC_NONE;
5106                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5107                           "configured to RTE_FC_NONE", mode);
5108                 break;
5109         }
5110 }
5111
5112 static int
5113 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5114 {
5115         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5117         int ret;
5118
5119         if (fc_conf->high_water || fc_conf->low_water ||
5120             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5121                 hns3_err(hw, "Unsupported flow control settings specified, "
5122                          "high_water(%u), low_water(%u), send_xon(%u) and "
5123                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5124                          fc_conf->high_water, fc_conf->low_water,
5125                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5126                 return -EINVAL;
5127         }
5128         if (fc_conf->autoneg) {
5129                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5130                 return -EINVAL;
5131         }
5132         if (!fc_conf->pause_time) {
5133                 hns3_err(hw, "Invalid pause time %u setting.",
5134                          fc_conf->pause_time);
5135                 return -EINVAL;
5136         }
5137
5138         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5139             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5140                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5141                          "current_fc_status = %d", hw->current_fc_status);
5142                 return -EOPNOTSUPP;
5143         }
5144
5145         hns3_get_fc_mode(hw, fc_conf->mode);
5146         if (hw->requested_mode == hw->current_mode &&
5147             pf->pause_time == fc_conf->pause_time)
5148                 return 0;
5149
5150         rte_spinlock_lock(&hw->lock);
5151         ret = hns3_fc_enable(dev, fc_conf);
5152         rte_spinlock_unlock(&hw->lock);
5153
5154         return ret;
5155 }
5156
5157 static int
5158 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5159                             struct rte_eth_pfc_conf *pfc_conf)
5160 {
5161         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5163         uint8_t priority;
5164         int ret;
5165
5166         if (!hns3_dev_dcb_supported(hw)) {
5167                 hns3_err(hw, "This port does not support dcb configurations.");
5168                 return -EOPNOTSUPP;
5169         }
5170
5171         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5172             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5173                 hns3_err(hw, "Unsupported flow control settings specified, "
5174                          "high_water(%u), low_water(%u), send_xon(%u) and "
5175                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5176                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5177                          pfc_conf->fc.send_xon,
5178                          pfc_conf->fc.mac_ctrl_frame_fwd);
5179                 return -EINVAL;
5180         }
5181         if (pfc_conf->fc.autoneg) {
5182                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5183                 return -EINVAL;
5184         }
5185         if (pfc_conf->fc.pause_time == 0) {
5186                 hns3_err(hw, "Invalid pause time %u setting.",
5187                          pfc_conf->fc.pause_time);
5188                 return -EINVAL;
5189         }
5190
5191         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5192             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5193                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5194                              "current_fc_status = %d", hw->current_fc_status);
5195                 return -EOPNOTSUPP;
5196         }
5197
5198         priority = pfc_conf->priority;
5199         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5200         if (hw->dcb_info.pfc_en & BIT(priority) &&
5201             hw->requested_mode == hw->current_mode &&
5202             pfc_conf->fc.pause_time == pf->pause_time)
5203                 return 0;
5204
5205         rte_spinlock_lock(&hw->lock);
5206         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5207         rte_spinlock_unlock(&hw->lock);
5208
5209         return ret;
5210 }
5211
5212 static int
5213 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5214 {
5215         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5216         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5217         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5218         int i;
5219
5220         rte_spinlock_lock(&hw->lock);
5221         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5222                 dcb_info->nb_tcs = pf->local_max_tc;
5223         else
5224                 dcb_info->nb_tcs = 1;
5225
5226         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5227                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5228         for (i = 0; i < dcb_info->nb_tcs; i++)
5229                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5230
5231         for (i = 0; i < hw->num_tc; i++) {
5232                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5233                 dcb_info->tc_queue.tc_txq[0][i].base =
5234                                                 hw->tc_queue[i].tqp_offset;
5235                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5236                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5237                                                 hw->tc_queue[i].tqp_count;
5238         }
5239         rte_spinlock_unlock(&hw->lock);
5240
5241         return 0;
5242 }
5243
5244 static int
5245 hns3_reinit_dev(struct hns3_adapter *hns)
5246 {
5247         struct hns3_hw *hw = &hns->hw;
5248         int ret;
5249
5250         ret = hns3_cmd_init(hw);
5251         if (ret) {
5252                 hns3_err(hw, "Failed to init cmd: %d", ret);
5253                 return ret;
5254         }
5255
5256         ret = hns3_reset_all_tqps(hns);
5257         if (ret) {
5258                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5259                 return ret;
5260         }
5261
5262         ret = hns3_init_hardware(hns);
5263         if (ret) {
5264                 hns3_err(hw, "Failed to init hardware: %d", ret);
5265                 return ret;
5266         }
5267
5268         ret = hns3_enable_hw_error_intr(hns, true);
5269         if (ret) {
5270                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5271                              ret);
5272                 return ret;
5273         }
5274         hns3_info(hw, "Reset done, driver initialization finished.");
5275
5276         return 0;
5277 }
5278
5279 static bool
5280 is_pf_reset_done(struct hns3_hw *hw)
5281 {
5282         uint32_t val, reg, reg_bit;
5283
5284         switch (hw->reset.level) {
5285         case HNS3_IMP_RESET:
5286                 reg = HNS3_GLOBAL_RESET_REG;
5287                 reg_bit = HNS3_IMP_RESET_BIT;
5288                 break;
5289         case HNS3_GLOBAL_RESET:
5290                 reg = HNS3_GLOBAL_RESET_REG;
5291                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5292                 break;
5293         case HNS3_FUNC_RESET:
5294                 reg = HNS3_FUN_RST_ING;
5295                 reg_bit = HNS3_FUN_RST_ING_B;
5296                 break;
5297         case HNS3_FLR_RESET:
5298         default:
5299                 hns3_err(hw, "Wait for unsupported reset level: %d",
5300                          hw->reset.level);
5301                 return true;
5302         }
5303         val = hns3_read_dev(hw, reg);
5304         if (hns3_get_bit(val, reg_bit))
5305                 return false;
5306         else
5307                 return true;
5308 }
5309
5310 bool
5311 hns3_is_reset_pending(struct hns3_adapter *hns)
5312 {
5313         struct hns3_hw *hw = &hns->hw;
5314         enum hns3_reset_level reset;
5315
5316         hns3_check_event_cause(hns, NULL);
5317         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5318         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5319                 hns3_warn(hw, "High level reset %d is pending", reset);
5320                 return true;
5321         }
5322         reset = hns3_get_reset_level(hns, &hw->reset.request);
5323         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5324                 hns3_warn(hw, "High level reset %d is request", reset);
5325                 return true;
5326         }
5327         return false;
5328 }
5329
5330 static int
5331 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5332 {
5333         struct hns3_hw *hw = &hns->hw;
5334         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5335         struct timeval tv;
5336
5337         if (wait_data->result == HNS3_WAIT_SUCCESS)
5338                 return 0;
5339         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5340                 gettimeofday(&tv, NULL);
5341                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5342                           tv.tv_sec, tv.tv_usec);
5343                 return -ETIME;
5344         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5345                 return -EAGAIN;
5346
5347         wait_data->hns = hns;
5348         wait_data->check_completion = is_pf_reset_done;
5349         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5350                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5351         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5352         wait_data->count = HNS3_RESET_WAIT_CNT;
5353         wait_data->result = HNS3_WAIT_REQUEST;
5354         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5355         return -EAGAIN;
5356 }
5357
5358 static int
5359 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5360 {
5361         struct hns3_cmd_desc desc;
5362         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5363
5364         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5365         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5366         req->fun_reset_vfid = func_id;
5367
5368         return hns3_cmd_send(hw, &desc, 1);
5369 }
5370
5371 static int
5372 hns3_imp_reset_cmd(struct hns3_hw *hw)
5373 {
5374         struct hns3_cmd_desc desc;
5375
5376         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5377         desc.data[0] = 0xeedd;
5378
5379         return hns3_cmd_send(hw, &desc, 1);
5380 }
5381
5382 static void
5383 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5384 {
5385         struct hns3_hw *hw = &hns->hw;
5386         struct timeval tv;
5387         uint32_t val;
5388
5389         gettimeofday(&tv, NULL);
5390         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5391             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5392                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5393                           tv.tv_sec, tv.tv_usec);
5394                 return;
5395         }
5396
5397         switch (reset_level) {
5398         case HNS3_IMP_RESET:
5399                 hns3_imp_reset_cmd(hw);
5400                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5401                           tv.tv_sec, tv.tv_usec);
5402                 break;
5403         case HNS3_GLOBAL_RESET:
5404                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5405                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5406                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5407                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5408                           tv.tv_sec, tv.tv_usec);
5409                 break;
5410         case HNS3_FUNC_RESET:
5411                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5412                           tv.tv_sec, tv.tv_usec);
5413                 /* schedule again to check later */
5414                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5415                 hns3_schedule_reset(hns);
5416                 break;
5417         default:
5418                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5419                 return;
5420         }
5421         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5422 }
5423
5424 static enum hns3_reset_level
5425 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5426 {
5427         struct hns3_hw *hw = &hns->hw;
5428         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5429
5430         /* Return the highest priority reset level amongst all */
5431         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5432                 reset_level = HNS3_IMP_RESET;
5433         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5434                 reset_level = HNS3_GLOBAL_RESET;
5435         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5436                 reset_level = HNS3_FUNC_RESET;
5437         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5438                 reset_level = HNS3_FLR_RESET;
5439
5440         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5441                 return HNS3_NONE_RESET;
5442
5443         return reset_level;
5444 }
5445
5446 static void
5447 hns3_record_imp_error(struct hns3_adapter *hns)
5448 {
5449         struct hns3_hw *hw = &hns->hw;
5450         uint32_t reg_val;
5451
5452         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5453         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5454                 hns3_warn(hw, "Detected IMP RD poison!");
5455                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5456                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5457                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5458         }
5459
5460         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5461                 hns3_warn(hw, "Detected IMP CMDQ error!");
5462                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5463                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5464                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5465         }
5466 }
5467
5468 static int
5469 hns3_prepare_reset(struct hns3_adapter *hns)
5470 {
5471         struct hns3_hw *hw = &hns->hw;
5472         uint32_t reg_val;
5473         int ret;
5474
5475         switch (hw->reset.level) {
5476         case HNS3_FUNC_RESET:
5477                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5478                 if (ret)
5479                         return ret;
5480
5481                 /*
5482                  * After performaning pf reset, it is not necessary to do the
5483                  * mailbox handling or send any command to firmware, because
5484                  * any mailbox handling or command to firmware is only valid
5485                  * after hns3_cmd_init is called.
5486                  */
5487                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5488                 hw->reset.stats.request_cnt++;
5489                 break;
5490         case HNS3_IMP_RESET:
5491                 hns3_record_imp_error(hns);
5492                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5493                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5494                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5495                 break;
5496         default:
5497                 break;
5498         }
5499         return 0;
5500 }
5501
5502 static int
5503 hns3_set_rst_done(struct hns3_hw *hw)
5504 {
5505         struct hns3_pf_rst_done_cmd *req;
5506         struct hns3_cmd_desc desc;
5507
5508         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5509         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5510         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5511         return hns3_cmd_send(hw, &desc, 1);
5512 }
5513
5514 static int
5515 hns3_stop_service(struct hns3_adapter *hns)
5516 {
5517         struct hns3_hw *hw = &hns->hw;
5518         struct rte_eth_dev *eth_dev;
5519
5520         eth_dev = &rte_eth_devices[hw->data->port_id];
5521         if (hw->adapter_state == HNS3_NIC_STARTED)
5522                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5523         hw->mac.link_status = ETH_LINK_DOWN;
5524
5525         hns3_set_rxtx_function(eth_dev);
5526         rte_wmb();
5527         /* Disable datapath on secondary process. */
5528         hns3_mp_req_stop_rxtx(eth_dev);
5529         rte_delay_ms(hw->tqps_num);
5530
5531         rte_spinlock_lock(&hw->lock);
5532         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5533             hw->adapter_state == HNS3_NIC_STOPPING) {
5534                 hns3_enable_all_queues(hw, false);
5535                 hns3_do_stop(hns);
5536                 hw->reset.mbuf_deferred_free = true;
5537         } else
5538                 hw->reset.mbuf_deferred_free = false;
5539
5540         /*
5541          * It is cumbersome for hardware to pick-and-choose entries for deletion
5542          * from table space. Hence, for function reset software intervention is
5543          * required to delete the entries
5544          */
5545         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5546                 hns3_configure_all_mc_mac_addr(hns, true);
5547         rte_spinlock_unlock(&hw->lock);
5548
5549         return 0;
5550 }
5551
5552 static int
5553 hns3_start_service(struct hns3_adapter *hns)
5554 {
5555         struct hns3_hw *hw = &hns->hw;
5556         struct rte_eth_dev *eth_dev;
5557
5558         if (hw->reset.level == HNS3_IMP_RESET ||
5559             hw->reset.level == HNS3_GLOBAL_RESET)
5560                 hns3_set_rst_done(hw);
5561         eth_dev = &rte_eth_devices[hw->data->port_id];
5562         hns3_set_rxtx_function(eth_dev);
5563         hns3_mp_req_start_rxtx(eth_dev);
5564         if (hw->adapter_state == HNS3_NIC_STARTED) {
5565                 hns3_service_handler(eth_dev);
5566
5567                 /* Enable interrupt of all rx queues before enabling queues */
5568                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5569                 /*
5570                  * Enable state of each rxq and txq will be recovered after
5571                  * reset, so we need to restore them before enable all tqps;
5572                  */
5573                 hns3_restore_tqp_enable_state(hw);
5574                 /*
5575                  * When finished the initialization, enable queues to receive
5576                  * and transmit packets.
5577                  */
5578                 hns3_enable_all_queues(hw, true);
5579         }
5580
5581         return 0;
5582 }
5583
5584 static int
5585 hns3_restore_conf(struct hns3_adapter *hns)
5586 {
5587         struct hns3_hw *hw = &hns->hw;
5588         int ret;
5589
5590         ret = hns3_configure_all_mac_addr(hns, false);
5591         if (ret)
5592                 return ret;
5593
5594         ret = hns3_configure_all_mc_mac_addr(hns, false);
5595         if (ret)
5596                 goto err_mc_mac;
5597
5598         ret = hns3_dev_promisc_restore(hns);
5599         if (ret)
5600                 goto err_promisc;
5601
5602         ret = hns3_restore_vlan_table(hns);
5603         if (ret)
5604                 goto err_promisc;
5605
5606         ret = hns3_restore_vlan_conf(hns);
5607         if (ret)
5608                 goto err_promisc;
5609
5610         ret = hns3_restore_all_fdir_filter(hns);
5611         if (ret)
5612                 goto err_promisc;
5613
5614         ret = hns3_restore_rx_interrupt(hw);
5615         if (ret)
5616                 goto err_promisc;
5617
5618         ret = hns3_restore_gro_conf(hw);
5619         if (ret)
5620                 goto err_promisc;
5621
5622         ret = hns3_restore_fec(hw);
5623         if (ret)
5624                 goto err_promisc;
5625
5626         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5627                 ret = hns3_do_start(hns, false);
5628                 if (ret)
5629                         goto err_promisc;
5630                 hns3_info(hw, "hns3 dev restart successful!");
5631         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5632                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5633         return 0;
5634
5635 err_promisc:
5636         hns3_configure_all_mc_mac_addr(hns, true);
5637 err_mc_mac:
5638         hns3_configure_all_mac_addr(hns, true);
5639         return ret;
5640 }
5641
5642 static void
5643 hns3_reset_service(void *param)
5644 {
5645         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5646         struct hns3_hw *hw = &hns->hw;
5647         enum hns3_reset_level reset_level;
5648         struct timeval tv_delta;
5649         struct timeval tv_start;
5650         struct timeval tv;
5651         uint64_t msec;
5652         int ret;
5653
5654         /*
5655          * The interrupt is not triggered within the delay time.
5656          * The interrupt may have been lost. It is necessary to handle
5657          * the interrupt to recover from the error.
5658          */
5659         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5660                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5661                 hns3_err(hw, "Handling interrupts in delayed tasks");
5662                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5663                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5664                 if (reset_level == HNS3_NONE_RESET) {
5665                         hns3_err(hw, "No reset level is set, try IMP reset");
5666                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5667                 }
5668         }
5669         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5670
5671         /*
5672          * Check if there is any ongoing reset in the hardware. This status can
5673          * be checked from reset_pending. If there is then, we need to wait for
5674          * hardware to complete reset.
5675          *    a. If we are able to figure out in reasonable time that hardware
5676          *       has fully resetted then, we can proceed with driver, client
5677          *       reset.
5678          *    b. else, we can come back later to check this status so re-sched
5679          *       now.
5680          */
5681         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5682         if (reset_level != HNS3_NONE_RESET) {
5683                 gettimeofday(&tv_start, NULL);
5684                 ret = hns3_reset_process(hns, reset_level);
5685                 gettimeofday(&tv, NULL);
5686                 timersub(&tv, &tv_start, &tv_delta);
5687                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5688                        tv_delta.tv_usec / USEC_PER_MSEC;
5689                 if (msec > HNS3_RESET_PROCESS_MS)
5690                         hns3_err(hw, "%d handle long time delta %" PRIx64
5691                                      " ms time=%ld.%.6ld",
5692                                  hw->reset.level, msec,
5693                                  tv.tv_sec, tv.tv_usec);
5694                 if (ret == -EAGAIN)
5695                         return;
5696         }
5697
5698         /* Check if we got any *new* reset requests to be honored */
5699         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5700         if (reset_level != HNS3_NONE_RESET)
5701                 hns3_msix_process(hns, reset_level);
5702 }
5703
5704 static unsigned int
5705 hns3_get_speed_capa_num(uint16_t device_id)
5706 {
5707         unsigned int num;
5708
5709         switch (device_id) {
5710         case HNS3_DEV_ID_25GE:
5711         case HNS3_DEV_ID_25GE_RDMA:
5712                 num = 2;
5713                 break;
5714         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5715         case HNS3_DEV_ID_200G_RDMA:
5716                 num = 1;
5717                 break;
5718         default:
5719                 num = 0;
5720                 break;
5721         }
5722
5723         return num;
5724 }
5725
5726 static int
5727 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5728                         uint16_t device_id)
5729 {
5730         switch (device_id) {
5731         case HNS3_DEV_ID_25GE:
5732         /* fallthrough */
5733         case HNS3_DEV_ID_25GE_RDMA:
5734                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5735                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5736
5737                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5738                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5739                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5740                 break;
5741         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5742                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5743                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5744                 break;
5745         case HNS3_DEV_ID_200G_RDMA:
5746                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5747                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5748                 break;
5749         default:
5750                 return -ENOTSUP;
5751         }
5752
5753         return 0;
5754 }
5755
5756 static int
5757 hns3_fec_get_capability(struct rte_eth_dev *dev,
5758                         struct rte_eth_fec_capa *speed_fec_capa,
5759                         unsigned int num)
5760 {
5761         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5762         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5763         uint16_t device_id = pci_dev->id.device_id;
5764         unsigned int capa_num;
5765         int ret;
5766
5767         capa_num = hns3_get_speed_capa_num(device_id);
5768         if (capa_num == 0) {
5769                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5770                          device_id);
5771                 return -ENOTSUP;
5772         }
5773
5774         if (speed_fec_capa == NULL || num < capa_num)
5775                 return capa_num;
5776
5777         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5778         if (ret)
5779                 return -ENOTSUP;
5780
5781         return capa_num;
5782 }
5783
5784 static int
5785 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5786 {
5787         struct hns3_config_fec_cmd *req;
5788         struct hns3_cmd_desc desc;
5789         int ret;
5790
5791         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5792         req = (struct hns3_config_fec_cmd *)desc.data;
5793         ret = hns3_cmd_send(hw, &desc, 1);
5794         if (ret) {
5795                 hns3_err(hw, "get current fec auto state failed, ret = %d",
5796                          ret);
5797                 return ret;
5798         }
5799
5800         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5801         return 0;
5802 }
5803
5804 static int
5805 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5806 {
5807 #define QUERY_ACTIVE_SPEED      1
5808         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5809         struct hns3_sfp_speed_cmd *resp;
5810         uint32_t tmp_fec_capa;
5811         uint8_t auto_state;
5812         struct hns3_cmd_desc desc;
5813         int ret;
5814
5815         /*
5816          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5817          * configured FEC mode is returned.
5818          * If link is up, current FEC mode is returned.
5819          */
5820         if (hw->mac.link_status == ETH_LINK_DOWN) {
5821                 ret = get_current_fec_auto_state(hw, &auto_state);
5822                 if (ret)
5823                         return ret;
5824
5825                 if (auto_state == 0x1) {
5826                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5827                         return 0;
5828                 }
5829         }
5830
5831         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5832         resp = (struct hns3_sfp_speed_cmd *)desc.data;
5833         resp->query_type = QUERY_ACTIVE_SPEED;
5834
5835         ret = hns3_cmd_send(hw, &desc, 1);
5836         if (ret == -EOPNOTSUPP) {
5837                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5838                 return ret;
5839         } else if (ret) {
5840                 hns3_err(hw, "get FEC failed, ret = %d", ret);
5841                 return ret;
5842         }
5843
5844         /*
5845          * FEC mode order defined in hns3 hardware is inconsistend with
5846          * that defined in the ethdev library. So the sequence needs
5847          * to be converted.
5848          */
5849         switch (resp->active_fec) {
5850         case HNS3_HW_FEC_MODE_NOFEC:
5851                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5852                 break;
5853         case HNS3_HW_FEC_MODE_BASER:
5854                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5855                 break;
5856         case HNS3_HW_FEC_MODE_RS:
5857                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5858                 break;
5859         default:
5860                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5861                 break;
5862         }
5863
5864         *fec_capa = tmp_fec_capa;
5865         return 0;
5866 }
5867
5868 static int
5869 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5870 {
5871         struct hns3_config_fec_cmd *req;
5872         struct hns3_cmd_desc desc;
5873         int ret;
5874
5875         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5876
5877         req = (struct hns3_config_fec_cmd *)desc.data;
5878         switch (mode) {
5879         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5880                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5881                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5882                 break;
5883         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5884                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5885                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5886                 break;
5887         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5888                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5889                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5890                 break;
5891         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5892                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5893                 break;
5894         default:
5895                 return 0;
5896         }
5897         ret = hns3_cmd_send(hw, &desc, 1);
5898         if (ret)
5899                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5900
5901         return ret;
5902 }
5903
5904 static uint32_t
5905 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5906 {
5907         struct hns3_mac *mac = &hw->mac;
5908         uint32_t cur_capa;
5909
5910         switch (mac->link_speed) {
5911         case ETH_SPEED_NUM_10G:
5912                 cur_capa = fec_capa[1].capa;
5913                 break;
5914         case ETH_SPEED_NUM_25G:
5915         case ETH_SPEED_NUM_100G:
5916         case ETH_SPEED_NUM_200G:
5917                 cur_capa = fec_capa[0].capa;
5918                 break;
5919         default:
5920                 cur_capa = 0;
5921                 break;
5922         }
5923
5924         return cur_capa;
5925 }
5926
5927 static bool
5928 is_fec_mode_one_bit_set(uint32_t mode)
5929 {
5930         int cnt = 0;
5931         uint8_t i;
5932
5933         for (i = 0; i < sizeof(mode); i++)
5934                 if (mode >> i & 0x1)
5935                         cnt++;
5936
5937         return cnt == 1 ? true : false;
5938 }
5939
5940 static int
5941 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5942 {
5943 #define FEC_CAPA_NUM 2
5944         struct hns3_adapter *hns = dev->data->dev_private;
5945         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
5946         struct hns3_pf *pf = &hns->pf;
5947
5948         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
5949         uint32_t cur_capa;
5950         uint32_t num = FEC_CAPA_NUM;
5951         int ret;
5952
5953         ret = hns3_fec_get_capability(dev, fec_capa, num);
5954         if (ret < 0)
5955                 return ret;
5956
5957         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
5958         if (!is_fec_mode_one_bit_set(mode))
5959                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
5960                              "FEC mode should be only one bit set", mode);
5961
5962         /*
5963          * Check whether the configured mode is within the FEC capability.
5964          * If not, the configured mode will not be supported.
5965          */
5966         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
5967         if (!(cur_capa & mode)) {
5968                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
5969                 return -EINVAL;
5970         }
5971
5972         ret = hns3_set_fec_hw(hw, mode);
5973         if (ret)
5974                 return ret;
5975
5976         pf->fec_mode = mode;
5977         return 0;
5978 }
5979
5980 static int
5981 hns3_restore_fec(struct hns3_hw *hw)
5982 {
5983         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
5984         struct hns3_pf *pf = &hns->pf;
5985         uint32_t mode = pf->fec_mode;
5986         int ret;
5987
5988         ret = hns3_set_fec_hw(hw, mode);
5989         if (ret)
5990                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
5991                          mode, ret);
5992
5993         return ret;
5994 }
5995
5996 static int
5997 hns3_query_dev_fec_info(struct rte_eth_dev *dev)
5998 {
5999         struct hns3_adapter *hns = dev->data->dev_private;
6000         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6001         struct hns3_pf *pf = &hns->pf;
6002         int ret;
6003
6004         ret = hns3_fec_get(dev, &pf->fec_mode);
6005         if (ret)
6006                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6007
6008         return ret;
6009 }
6010
6011 static const struct eth_dev_ops hns3_eth_dev_ops = {
6012         .dev_configure      = hns3_dev_configure,
6013         .dev_start          = hns3_dev_start,
6014         .dev_stop           = hns3_dev_stop,
6015         .dev_close          = hns3_dev_close,
6016         .promiscuous_enable = hns3_dev_promiscuous_enable,
6017         .promiscuous_disable = hns3_dev_promiscuous_disable,
6018         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6019         .allmulticast_disable = hns3_dev_allmulticast_disable,
6020         .mtu_set            = hns3_dev_mtu_set,
6021         .stats_get          = hns3_stats_get,
6022         .stats_reset        = hns3_stats_reset,
6023         .xstats_get         = hns3_dev_xstats_get,
6024         .xstats_get_names   = hns3_dev_xstats_get_names,
6025         .xstats_reset       = hns3_dev_xstats_reset,
6026         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6027         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6028         .dev_infos_get          = hns3_dev_infos_get,
6029         .fw_version_get         = hns3_fw_version_get,
6030         .rx_queue_setup         = hns3_rx_queue_setup,
6031         .tx_queue_setup         = hns3_tx_queue_setup,
6032         .rx_queue_release       = hns3_dev_rx_queue_release,
6033         .tx_queue_release       = hns3_dev_tx_queue_release,
6034         .rx_queue_start         = hns3_dev_rx_queue_start,
6035         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6036         .tx_queue_start         = hns3_dev_tx_queue_start,
6037         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6038         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6039         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6040         .rxq_info_get           = hns3_rxq_info_get,
6041         .txq_info_get           = hns3_txq_info_get,
6042         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6043         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6044         .flow_ctrl_get          = hns3_flow_ctrl_get,
6045         .flow_ctrl_set          = hns3_flow_ctrl_set,
6046         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6047         .mac_addr_add           = hns3_add_mac_addr,
6048         .mac_addr_remove        = hns3_remove_mac_addr,
6049         .mac_addr_set           = hns3_set_default_mac_addr,
6050         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6051         .link_update            = hns3_dev_link_update,
6052         .rss_hash_update        = hns3_dev_rss_hash_update,
6053         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6054         .reta_update            = hns3_dev_rss_reta_update,
6055         .reta_query             = hns3_dev_rss_reta_query,
6056         .filter_ctrl            = hns3_dev_filter_ctrl,
6057         .vlan_filter_set        = hns3_vlan_filter_set,
6058         .vlan_tpid_set          = hns3_vlan_tpid_set,
6059         .vlan_offload_set       = hns3_vlan_offload_set,
6060         .vlan_pvid_set          = hns3_vlan_pvid_set,
6061         .get_reg                = hns3_get_regs,
6062         .get_dcb_info           = hns3_get_dcb_info,
6063         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6064         .fec_get_capability     = hns3_fec_get_capability,
6065         .fec_get                = hns3_fec_get,
6066         .fec_set                = hns3_fec_set,
6067 };
6068
6069 static const struct hns3_reset_ops hns3_reset_ops = {
6070         .reset_service       = hns3_reset_service,
6071         .stop_service        = hns3_stop_service,
6072         .prepare_reset       = hns3_prepare_reset,
6073         .wait_hardware_ready = hns3_wait_hardware_ready,
6074         .reinit_dev          = hns3_reinit_dev,
6075         .restore_conf        = hns3_restore_conf,
6076         .start_service       = hns3_start_service,
6077 };
6078
6079 static int
6080 hns3_dev_init(struct rte_eth_dev *eth_dev)
6081 {
6082         struct hns3_adapter *hns = eth_dev->data->dev_private;
6083         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6084         struct rte_ether_addr *eth_addr;
6085         struct hns3_hw *hw = &hns->hw;
6086         int ret;
6087
6088         PMD_INIT_FUNC_TRACE();
6089
6090         eth_dev->process_private = (struct hns3_process_private *)
6091             rte_zmalloc_socket("hns3_filter_list",
6092                                sizeof(struct hns3_process_private),
6093                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6094         if (eth_dev->process_private == NULL) {
6095                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6096                 return -ENOMEM;
6097         }
6098         /* initialize flow filter lists */
6099         hns3_filterlist_init(eth_dev);
6100
6101         hns3_set_rxtx_function(eth_dev);
6102         eth_dev->dev_ops = &hns3_eth_dev_ops;
6103         eth_dev->rx_queue_count = hns3_rx_queue_count;
6104         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6105                 ret = hns3_mp_init_secondary();
6106                 if (ret) {
6107                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6108                                      "process, ret = %d", ret);
6109                         goto err_mp_init_secondary;
6110                 }
6111
6112                 hw->secondary_cnt++;
6113                 return 0;
6114         }
6115
6116         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6117
6118         ret = hns3_mp_init_primary();
6119         if (ret) {
6120                 PMD_INIT_LOG(ERR,
6121                              "Failed to init for primary process, ret = %d",
6122                              ret);
6123                 goto err_mp_init_primary;
6124         }
6125
6126         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6127         hns->is_vf = false;
6128         hw->data = eth_dev->data;
6129
6130         /*
6131          * Set default max packet size according to the mtu
6132          * default vale in DPDK frame.
6133          */
6134         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6135
6136         ret = hns3_reset_init(hw);
6137         if (ret)
6138                 goto err_init_reset;
6139         hw->reset.ops = &hns3_reset_ops;
6140
6141         ret = hns3_init_pf(eth_dev);
6142         if (ret) {
6143                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6144                 goto err_init_pf;
6145         }
6146
6147         /* Allocate memory for storing MAC addresses */
6148         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6149                                                sizeof(struct rte_ether_addr) *
6150                                                HNS3_UC_MACADDR_NUM, 0);
6151         if (eth_dev->data->mac_addrs == NULL) {
6152                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6153                              "to store MAC addresses",
6154                              sizeof(struct rte_ether_addr) *
6155                              HNS3_UC_MACADDR_NUM);
6156                 ret = -ENOMEM;
6157                 goto err_rte_zmalloc;
6158         }
6159
6160         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6161         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6162                 rte_eth_random_addr(hw->mac.mac_addr);
6163                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6164                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6165                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6166                           "unicast address, using random MAC address %s",
6167                           mac_str);
6168         }
6169         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6170                             &eth_dev->data->mac_addrs[0]);
6171
6172         hw->adapter_state = HNS3_NIC_INITIALIZED;
6173
6174         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6175                 hns3_err(hw, "Reschedule reset service after dev_init");
6176                 hns3_schedule_reset(hns);
6177         } else {
6178                 /* IMP will wait ready flag before reset */
6179                 hns3_notify_reset_ready(hw, false);
6180         }
6181
6182         hns3_info(hw, "hns3 dev initialization successful!");
6183         return 0;
6184
6185 err_rte_zmalloc:
6186         hns3_uninit_pf(eth_dev);
6187
6188 err_init_pf:
6189         rte_free(hw->reset.wait_data);
6190
6191 err_init_reset:
6192         hns3_mp_uninit_primary();
6193
6194 err_mp_init_primary:
6195 err_mp_init_secondary:
6196         eth_dev->dev_ops = NULL;
6197         eth_dev->rx_pkt_burst = NULL;
6198         eth_dev->tx_pkt_burst = NULL;
6199         eth_dev->tx_pkt_prepare = NULL;
6200         rte_free(eth_dev->process_private);
6201         eth_dev->process_private = NULL;
6202         return ret;
6203 }
6204
6205 static int
6206 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6207 {
6208         struct hns3_adapter *hns = eth_dev->data->dev_private;
6209         struct hns3_hw *hw = &hns->hw;
6210
6211         PMD_INIT_FUNC_TRACE();
6212
6213         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6214                 return -EPERM;
6215
6216         if (hw->adapter_state < HNS3_NIC_CLOSING)
6217                 hns3_dev_close(eth_dev);
6218
6219         hw->adapter_state = HNS3_NIC_REMOVED;
6220         return 0;
6221 }
6222
6223 static int
6224 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6225                    struct rte_pci_device *pci_dev)
6226 {
6227         return rte_eth_dev_pci_generic_probe(pci_dev,
6228                                              sizeof(struct hns3_adapter),
6229                                              hns3_dev_init);
6230 }
6231
6232 static int
6233 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6234 {
6235         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6236 }
6237
6238 static const struct rte_pci_id pci_id_hns3_map[] = {
6239         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6240         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6241         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6242         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6243         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6244         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6245         { .vendor_id = 0, }, /* sentinel */
6246 };
6247
6248 static struct rte_pci_driver rte_hns3_pmd = {
6249         .id_table = pci_id_hns3_map,
6250         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6251         .probe = eth_hns3_pci_probe,
6252         .remove = eth_hns3_pci_remove,
6253 };
6254
6255 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6256 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6257 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6258 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6259 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);