1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_PORT_BASE_VLAN_DISABLE 0
39 #define HNS3_PORT_BASE_VLAN_ENABLE 1
40 #define HNS3_INVLID_PVID 0xFFFF
42 #define HNS3_FILTER_TYPE_VF 0
43 #define HNS3_FILTER_TYPE_PORT 1
44 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
45 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
46 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
47 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
48 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
49 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
50 | HNS3_FILTER_FE_ROCE_EGRESS_B)
51 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
52 | HNS3_FILTER_FE_ROCE_INGRESS_B)
54 /* Reset related Registers */
55 #define HNS3_GLOBAL_RESET_BIT 0
56 #define HNS3_CORE_RESET_BIT 1
57 #define HNS3_IMP_RESET_BIT 2
58 #define HNS3_FUN_RST_ING_B 0
60 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
62 #define HNS3_RESET_WAIT_MS 100
63 #define HNS3_RESET_WAIT_CNT 200
65 int hns3_logtype_init;
66 int hns3_logtype_driver;
69 HNS3_VECTOR0_EVENT_RST,
70 HNS3_VECTOR0_EVENT_MBX,
71 HNS3_VECTOR0_EVENT_ERR,
72 HNS3_VECTOR0_EVENT_OTHER,
75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
83 hns3_pf_disable_irq0(struct hns3_hw *hw)
85 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
89 hns3_pf_enable_irq0(struct hns3_hw *hw)
91 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
94 static enum hns3_evt_cause
95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
97 struct hns3_hw *hw = &hns->hw;
98 uint32_t vector0_int_stats;
99 uint32_t cmdq_src_val;
101 enum hns3_evt_cause ret;
103 /* fetch the events from their corresponding regs */
104 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
105 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
108 * Assumption: If by any chance reset and mailbox events are reported
109 * together then we will only process reset event and defer the
110 * processing of the mailbox events. Since, we would have not cleared
111 * RX CMDQ event this time we would receive again another interrupt
112 * from H/W just for the mailbox.
114 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
115 rte_atomic16_set(&hw->reset.disable_cmd, 1);
116 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
117 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
119 hw->reset.stats.imp_cnt++;
120 hns3_warn(hw, "IMP reset detected, clear reset status");
122 hns3_schedule_delayed_reset(hns);
123 hns3_warn(hw, "IMP reset detected, don't clear reset status");
126 ret = HNS3_VECTOR0_EVENT_RST;
131 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
132 rte_atomic16_set(&hw->reset.disable_cmd, 1);
133 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
134 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
136 hw->reset.stats.global_cnt++;
137 hns3_warn(hw, "Global reset detected, clear reset status");
139 hns3_schedule_delayed_reset(hns);
140 hns3_warn(hw, "Global reset detected, don't clear reset status");
143 ret = HNS3_VECTOR0_EVENT_RST;
147 /* check for vector0 msix event source */
148 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
149 val = vector0_int_stats;
150 ret = HNS3_VECTOR0_EVENT_ERR;
154 /* check for vector0 mailbox(=CMDQ RX) event source */
155 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
156 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
158 ret = HNS3_VECTOR0_EVENT_MBX;
162 if (clearval && (vector0_int_stats || cmdq_src_val))
163 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
164 vector0_int_stats, cmdq_src_val);
165 val = vector0_int_stats;
166 ret = HNS3_VECTOR0_EVENT_OTHER;
175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
177 if (event_type == HNS3_VECTOR0_EVENT_RST)
178 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
179 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
180 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
184 hns3_clear_all_event_cause(struct hns3_hw *hw)
186 uint32_t vector0_int_stats;
187 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
189 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
190 hns3_warn(hw, "Probe during IMP reset interrupt");
192 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
193 hns3_warn(hw, "Probe during Global reset interrupt");
195 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
196 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
197 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
198 BIT(HNS3_VECTOR0_CORERESET_INT_B));
199 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
203 hns3_interrupt_handler(void *param)
205 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
206 struct hns3_adapter *hns = dev->data->dev_private;
207 struct hns3_hw *hw = &hns->hw;
208 enum hns3_evt_cause event_cause;
209 uint32_t clearval = 0;
211 /* Disable interrupt */
212 hns3_pf_disable_irq0(hw);
214 event_cause = hns3_check_event_cause(hns, &clearval);
216 /* vector 0 interrupt is shared with reset and mailbox source events. */
217 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
218 hns3_handle_msix_error(hns, &hw->reset.request);
219 hns3_schedule_reset(hns);
220 } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
221 hns3_schedule_reset(hns);
222 else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
223 hns3_dev_handle_mbx_msg(hw);
225 hns3_err(hw, "Received unknown event");
227 hns3_clear_event_cause(hw, event_cause, clearval);
228 /* Enable interrupt if it is not cause by reset */
229 hns3_pf_enable_irq0(hw);
233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
235 #define HNS3_VLAN_OFFSET_160 160
236 struct hns3_vlan_filter_pf_cfg_cmd *req;
237 struct hns3_hw *hw = &hns->hw;
238 uint8_t vlan_offset_byte_val;
239 struct hns3_cmd_desc desc;
240 uint8_t vlan_offset_byte;
241 uint8_t vlan_offset_160;
244 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
246 vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
247 vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
248 vlan_offset_byte_val = 1 << (vlan_id % 8);
250 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
251 req->vlan_offset = vlan_offset_160;
252 req->vlan_cfg = on ? 0 : 1;
253 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
255 ret = hns3_cmd_send(hw, &desc, 1);
257 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
264 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
266 struct hns3_user_vlan_table *vlan_entry;
267 struct hns3_pf *pf = &hns->pf;
269 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
270 if (vlan_entry->vlan_id == vlan_id) {
271 if (vlan_entry->hd_tbl_status)
272 hns3_set_port_vlan_filter(hns, vlan_id, 0);
273 LIST_REMOVE(vlan_entry, next);
274 rte_free(vlan_entry);
281 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
284 struct hns3_user_vlan_table *vlan_entry;
285 struct hns3_hw *hw = &hns->hw;
286 struct hns3_pf *pf = &hns->pf;
288 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
289 if (vlan_entry->vlan_id == vlan_id)
293 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
294 if (vlan_entry == NULL) {
295 hns3_err(hw, "Failed to malloc hns3 vlan table");
299 vlan_entry->hd_tbl_status = writen_to_tbl;
300 vlan_entry->vlan_id = vlan_id;
302 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
306 hns3_restore_vlan_table(struct hns3_adapter *hns)
308 struct hns3_user_vlan_table *vlan_entry;
309 struct hns3_pf *pf = &hns->pf;
313 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
314 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
319 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
320 if (vlan_entry->hd_tbl_status) {
321 vlan_id = vlan_entry->vlan_id;
322 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
332 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
334 struct hns3_pf *pf = &hns->pf;
335 bool writen_to_tbl = false;
339 * When vlan filter is enabled, hardware regards vlan id 0 as the entry
340 * for normal packet, deleting vlan id 0 is not allowed.
342 if (on == 0 && vlan_id == 0)
346 * When port base vlan enabled, we use port base vlan as the vlan
347 * filter condition. In this case, we don't update vlan filter table
348 * when user add new vlan or remove exist vlan, just update the
349 * vlan list. The vlan id in vlan list will be writen in vlan filter
350 * table until port base vlan disabled
352 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
353 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
354 writen_to_tbl = true;
357 if (ret == 0 && vlan_id) {
359 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
361 hns3_rm_dev_vlan_table(hns, vlan_id);
367 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
369 struct hns3_adapter *hns = dev->data->dev_private;
370 struct hns3_hw *hw = &hns->hw;
373 rte_spinlock_lock(&hw->lock);
374 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
375 rte_spinlock_unlock(&hw->lock);
380 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
383 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
384 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
385 struct hns3_hw *hw = &hns->hw;
386 struct hns3_cmd_desc desc;
389 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
390 vlan_type != ETH_VLAN_TYPE_OUTER)) {
391 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
395 if (tpid != RTE_ETHER_TYPE_VLAN) {
396 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
400 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
401 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
403 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
404 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
405 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
406 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
407 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
408 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
409 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
410 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
413 ret = hns3_cmd_send(hw, &desc, 1);
415 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
420 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
422 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
423 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
424 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
426 ret = hns3_cmd_send(hw, &desc, 1);
428 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
434 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
437 struct hns3_adapter *hns = dev->data->dev_private;
438 struct hns3_hw *hw = &hns->hw;
441 rte_spinlock_lock(&hw->lock);
442 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
443 rte_spinlock_unlock(&hw->lock);
448 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
449 struct hns3_rx_vtag_cfg *vcfg)
451 struct hns3_vport_vtag_rx_cfg_cmd *req;
452 struct hns3_hw *hw = &hns->hw;
453 struct hns3_cmd_desc desc;
458 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
460 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
461 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
462 vcfg->strip_tag1_en ? 1 : 0);
463 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
464 vcfg->strip_tag2_en ? 1 : 0);
465 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
466 vcfg->vlan1_vlan_prionly ? 1 : 0);
467 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
468 vcfg->vlan2_vlan_prionly ? 1 : 0);
471 * In current version VF is not supported when PF is driven by DPDK
472 * driver, the PF-related vf_id is 0, just need to configure parameters
476 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
477 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
478 req->vf_bitmap[req->vf_offset] = bitmap;
480 ret = hns3_cmd_send(hw, &desc, 1);
482 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
488 struct hns3_rx_vtag_cfg *vcfg)
490 struct hns3_pf *pf = &hns->pf;
491 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
496 struct hns3_tx_vtag_cfg *vcfg)
498 struct hns3_pf *pf = &hns->pf;
499 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
505 struct hns3_rx_vtag_cfg rxvlan_cfg;
506 struct hns3_pf *pf = &hns->pf;
507 struct hns3_hw *hw = &hns->hw;
510 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
511 rxvlan_cfg.strip_tag1_en = false;
512 rxvlan_cfg.strip_tag2_en = enable;
514 rxvlan_cfg.strip_tag1_en = enable;
515 rxvlan_cfg.strip_tag2_en = true;
518 rxvlan_cfg.vlan1_vlan_prionly = false;
519 rxvlan_cfg.vlan2_vlan_prionly = false;
520 rxvlan_cfg.rx_vlan_offload_en = enable;
522 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
524 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
528 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
534 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
535 uint8_t fe_type, bool filter_en, uint8_t vf_id)
537 struct hns3_vlan_filter_ctrl_cmd *req;
538 struct hns3_cmd_desc desc;
541 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
543 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
544 req->vlan_type = vlan_type;
545 req->vlan_fe = filter_en ? fe_type : 0;
548 ret = hns3_cmd_send(hw, &desc, 1);
550 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
556 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
558 struct hns3_hw *hw = &hns->hw;
561 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
562 HNS3_FILTER_FE_EGRESS, false, 0);
564 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
568 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
569 HNS3_FILTER_FE_INGRESS, enable, 0);
571 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
577 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
579 struct hns3_adapter *hns = dev->data->dev_private;
580 struct hns3_hw *hw = &hns->hw;
581 struct rte_eth_rxmode *rxmode;
582 unsigned int tmp_mask;
586 rte_spinlock_lock(&hw->lock);
587 rxmode = &dev->data->dev_conf.rxmode;
588 tmp_mask = (unsigned int)mask;
589 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
590 /* Enable or disable VLAN stripping */
591 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
594 ret = hns3_en_hw_strip_rxvtag(hns, enable);
596 rte_spinlock_unlock(&hw->lock);
597 hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
602 rte_spinlock_unlock(&hw->lock);
608 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
609 struct hns3_tx_vtag_cfg *vcfg)
611 struct hns3_vport_vtag_tx_cfg_cmd *req;
612 struct hns3_cmd_desc desc;
613 struct hns3_hw *hw = &hns->hw;
618 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
620 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
621 req->def_vlan_tag1 = vcfg->default_tag1;
622 req->def_vlan_tag2 = vcfg->default_tag2;
623 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
624 vcfg->accept_tag1 ? 1 : 0);
625 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
626 vcfg->accept_untag1 ? 1 : 0);
627 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
628 vcfg->accept_tag2 ? 1 : 0);
629 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
630 vcfg->accept_untag2 ? 1 : 0);
631 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
632 vcfg->insert_tag1_en ? 1 : 0);
633 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
634 vcfg->insert_tag2_en ? 1 : 0);
635 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
638 * In current version VF is not supported when PF is driven by DPDK
639 * driver, the PF-related vf_id is 0, just need to configure parameters
643 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
644 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
645 req->vf_bitmap[req->vf_offset] = bitmap;
647 ret = hns3_cmd_send(hw, &desc, 1);
649 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
655 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
658 struct hns3_hw *hw = &hns->hw;
659 struct hns3_tx_vtag_cfg txvlan_cfg;
662 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
663 txvlan_cfg.accept_tag1 = true;
664 txvlan_cfg.insert_tag1_en = false;
665 txvlan_cfg.default_tag1 = 0;
667 txvlan_cfg.accept_tag1 = false;
668 txvlan_cfg.insert_tag1_en = true;
669 txvlan_cfg.default_tag1 = pvid;
672 txvlan_cfg.accept_untag1 = true;
673 txvlan_cfg.accept_tag2 = true;
674 txvlan_cfg.accept_untag2 = true;
675 txvlan_cfg.insert_tag2_en = false;
676 txvlan_cfg.default_tag2 = 0;
678 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
680 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
685 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
690 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
692 struct hns3_pf *pf = &hns->pf;
694 pf->port_base_vlan_cfg.state = on ?
695 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
697 pf->port_base_vlan_cfg.pvid = pvid;
701 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
703 struct hns3_user_vlan_table *vlan_entry;
704 struct hns3_pf *pf = &hns->pf;
706 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
707 if (vlan_entry->hd_tbl_status)
708 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
710 vlan_entry->hd_tbl_status = false;
714 vlan_entry = LIST_FIRST(&pf->vlan_list);
716 LIST_REMOVE(vlan_entry, next);
717 rte_free(vlan_entry);
718 vlan_entry = LIST_FIRST(&pf->vlan_list);
724 hns3_add_all_vlan_table(struct hns3_adapter *hns)
726 struct hns3_user_vlan_table *vlan_entry;
727 struct hns3_pf *pf = &hns->pf;
729 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
730 if (!vlan_entry->hd_tbl_status)
731 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
733 vlan_entry->hd_tbl_status = true;
738 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
740 struct hns3_hw *hw = &hns->hw;
741 struct hns3_pf *pf = &hns->pf;
744 hns3_rm_all_vlan_table(hns, true);
745 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
746 ret = hns3_set_port_vlan_filter(hns,
747 pf->port_base_vlan_cfg.pvid, 0);
749 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
757 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
758 uint16_t port_base_vlan_state,
759 uint16_t new_pvid, uint16_t old_pvid)
761 struct hns3_pf *pf = &hns->pf;
762 struct hns3_hw *hw = &hns->hw;
765 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
766 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
767 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
770 "Failed to clear clear old pvid filter, ret =%d",
776 hns3_rm_all_vlan_table(hns, false);
777 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
781 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
783 hns3_err(hw, "Failed to set port vlan filter, ret =%d",
789 if (new_pvid == pf->port_base_vlan_cfg.pvid)
790 hns3_add_all_vlan_table(hns);
796 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
798 struct hns3_rx_vtag_cfg rx_vlan_cfg;
799 struct hns3_hw *hw = &hns->hw;
803 rx_strip_en = on ? true : false;
804 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
805 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
806 rx_vlan_cfg.vlan1_vlan_prionly = false;
807 rx_vlan_cfg.vlan2_vlan_prionly = false;
808 rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
810 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
812 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
816 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
821 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
823 struct hns3_pf *pf = &hns->pf;
824 struct hns3_hw *hw = &hns->hw;
825 uint16_t port_base_vlan_state;
829 if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
830 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
831 hns3_warn(hw, "Invalid operation! As current pvid set "
832 "is %u, disable pvid %u is invalid",
833 pf->port_base_vlan_cfg.pvid, pvid);
837 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
838 HNS3_PORT_BASE_VLAN_DISABLE;
839 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
841 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
845 ret = hns3_en_rx_strip_all(hns, on);
847 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
851 if (pvid == HNS3_INVLID_PVID)
853 old_pvid = pf->port_base_vlan_cfg.pvid;
854 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
857 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
863 hns3_store_port_base_vlan_info(hns, pvid, on);
868 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
870 struct hns3_adapter *hns = dev->data->dev_private;
871 struct hns3_hw *hw = &hns->hw;
874 rte_spinlock_lock(&hw->lock);
875 ret = hns3_vlan_pvid_configure(hns, pvid, on);
876 rte_spinlock_unlock(&hw->lock);
881 init_port_base_vlan_info(struct hns3_hw *hw)
883 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
884 struct hns3_pf *pf = &hns->pf;
886 pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
887 pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
891 hns3_default_vlan_config(struct hns3_adapter *hns)
893 struct hns3_hw *hw = &hns->hw;
896 ret = hns3_set_port_vlan_filter(hns, 0, 1);
898 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
903 hns3_init_vlan_config(struct hns3_adapter *hns)
905 struct hns3_hw *hw = &hns->hw;
909 * This function can be called in the initialization and reset process,
910 * when in reset process, it means that hardware had been reseted
911 * successfully and we need to restore the hardware configuration to
912 * ensure that the hardware configuration remains unchanged before and
915 if (rte_atomic16_read(&hw->reset.resetting) == 0)
916 init_port_base_vlan_info(hw);
918 ret = hns3_enable_vlan_filter(hns, true);
920 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
924 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
925 RTE_ETHER_TYPE_VLAN);
927 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
932 * When in the reinit dev stage of the reset process, the following
933 * vlan-related configurations may differ from those at initialization,
934 * we will restore configurations to hardware in hns3_restore_vlan_table
935 * and hns3_restore_vlan_conf later.
937 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
938 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
940 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
944 ret = hns3_en_hw_strip_rxvtag(hns, false);
946 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
952 return hns3_default_vlan_config(hns);
956 hns3_restore_vlan_conf(struct hns3_adapter *hns)
958 struct hns3_pf *pf = &hns->pf;
959 struct hns3_hw *hw = &hns->hw;
962 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
964 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
968 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
970 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
976 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
978 struct hns3_adapter *hns = dev->data->dev_private;
979 struct rte_eth_dev_data *data = dev->data;
980 struct rte_eth_txmode *txmode;
981 struct hns3_hw *hw = &hns->hw;
984 txmode = &data->dev_conf.txmode;
985 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
987 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
988 "configuration is not supported! Ignore these two "
989 "parameters: hw_vlan_reject_tagged(%d), "
990 "hw_vlan_reject_untagged(%d)",
991 txmode->hw_vlan_reject_tagged,
992 txmode->hw_vlan_reject_untagged);
994 /* Apply vlan offload setting */
995 ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
997 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1001 /* Apply pvid setting */
1002 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1003 txmode->hw_vlan_insert_pvid);
1005 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1012 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1013 unsigned int tso_mss_max)
1015 struct hns3_cfg_tso_status_cmd *req;
1016 struct hns3_cmd_desc desc;
1019 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1021 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1024 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1026 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1029 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1031 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1033 return hns3_cmd_send(hw, &desc, 1);
1037 hns3_config_gro(struct hns3_hw *hw, bool en)
1039 struct hns3_cfg_gro_status_cmd *req;
1040 struct hns3_cmd_desc desc;
1043 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1044 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1046 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1048 ret = hns3_cmd_send(hw, &desc, 1);
1050 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1056 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1057 uint16_t *allocated_size, bool is_alloc)
1059 struct hns3_umv_spc_alc_cmd *req;
1060 struct hns3_cmd_desc desc;
1063 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1064 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1065 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1066 req->space_size = rte_cpu_to_le_32(space_size);
1068 ret = hns3_cmd_send(hw, &desc, 1);
1070 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1071 is_alloc ? "allocate" : "free", ret);
1075 if (is_alloc && allocated_size)
1076 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1082 hns3_init_umv_space(struct hns3_hw *hw)
1084 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1085 struct hns3_pf *pf = &hns->pf;
1086 uint16_t allocated_size = 0;
1089 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1094 if (allocated_size < pf->wanted_umv_size)
1095 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1096 pf->wanted_umv_size, allocated_size);
1098 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1099 pf->wanted_umv_size;
1100 pf->used_umv_size = 0;
1105 hns3_uninit_umv_space(struct hns3_hw *hw)
1107 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1108 struct hns3_pf *pf = &hns->pf;
1111 if (pf->max_umv_size == 0)
1114 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1118 pf->max_umv_size = 0;
1124 hns3_is_umv_space_full(struct hns3_hw *hw)
1126 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1127 struct hns3_pf *pf = &hns->pf;
1130 is_full = (pf->used_umv_size >= pf->max_umv_size);
1136 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1138 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1139 struct hns3_pf *pf = &hns->pf;
1142 if (pf->used_umv_size > 0)
1143 pf->used_umv_size--;
1145 pf->used_umv_size++;
1149 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1150 const uint8_t *addr, bool is_mc)
1152 const unsigned char *mac_addr = addr;
1153 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1154 ((uint32_t)mac_addr[2] << 16) |
1155 ((uint32_t)mac_addr[1] << 8) |
1156 (uint32_t)mac_addr[0];
1157 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1159 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1161 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1162 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1163 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1166 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1167 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1171 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1173 enum hns3_mac_vlan_tbl_opcode op)
1176 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1181 if (op == HNS3_MAC_VLAN_ADD) {
1182 if (resp_code == 0 || resp_code == 1) {
1184 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1185 hns3_err(hw, "add mac addr failed for uc_overflow");
1187 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1188 hns3_err(hw, "add mac addr failed for mc_overflow");
1192 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1195 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1196 if (resp_code == 0) {
1198 } else if (resp_code == 1) {
1199 hns3_dbg(hw, "remove mac addr failed for miss");
1203 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1206 } else if (op == HNS3_MAC_VLAN_LKUP) {
1207 if (resp_code == 0) {
1209 } else if (resp_code == 1) {
1210 hns3_dbg(hw, "lookup mac addr failed for miss");
1214 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1219 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1226 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1227 struct hns3_mac_vlan_tbl_entry_cmd *req,
1228 struct hns3_cmd_desc *desc, bool is_mc)
1234 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1236 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1237 memcpy(desc[0].data, req,
1238 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1239 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1241 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1242 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1244 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1246 memcpy(desc[0].data, req,
1247 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1248 ret = hns3_cmd_send(hw, desc, 1);
1251 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1255 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1256 retval = rte_le_to_cpu_16(desc[0].retval);
1258 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1259 HNS3_MAC_VLAN_LKUP);
1263 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1264 struct hns3_mac_vlan_tbl_entry_cmd *req,
1265 struct hns3_cmd_desc *mc_desc)
1272 if (mc_desc == NULL) {
1273 struct hns3_cmd_desc desc;
1275 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1276 memcpy(desc.data, req,
1277 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1278 ret = hns3_cmd_send(hw, &desc, 1);
1279 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1280 retval = rte_le_to_cpu_16(desc.retval);
1282 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1285 hns3_cmd_reuse_desc(&mc_desc[0], false);
1286 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1287 hns3_cmd_reuse_desc(&mc_desc[1], false);
1288 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1289 hns3_cmd_reuse_desc(&mc_desc[2], false);
1290 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1291 memcpy(mc_desc[0].data, req,
1292 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1293 mc_desc[0].retval = 0;
1294 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1295 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1296 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1298 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1303 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1311 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1312 struct hns3_mac_vlan_tbl_entry_cmd *req)
1314 struct hns3_cmd_desc desc;
1319 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1321 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1323 ret = hns3_cmd_send(hw, &desc, 1);
1325 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1328 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1329 retval = rte_le_to_cpu_16(desc.retval);
1331 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1332 HNS3_MAC_VLAN_REMOVE);
1336 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1338 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1339 struct hns3_mac_vlan_tbl_entry_cmd req;
1340 struct hns3_pf *pf = &hns->pf;
1341 struct hns3_cmd_desc desc;
1342 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1343 uint16_t egress_port = 0;
1347 /* check if mac addr is valid */
1348 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1349 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1351 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1356 memset(&req, 0, sizeof(req));
1359 * In current version VF is not supported when PF is driven by DPDK
1360 * driver, the PF-related vf_id is 0, just need to configure parameters
1364 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1365 HNS3_MAC_EPORT_VFID_S, vf_id);
1367 req.egress_port = rte_cpu_to_le_16(egress_port);
1369 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1372 * Lookup the mac address in the mac_vlan table, and add
1373 * it if the entry is inexistent. Repeated unicast entry
1374 * is not allowed in the mac vlan table.
1376 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1377 if (ret == -ENOENT) {
1378 if (!hns3_is_umv_space_full(hw)) {
1379 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1381 hns3_update_umv_space(hw, false);
1385 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1390 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1392 /* check if we just hit the duplicate */
1394 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1398 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1405 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1406 uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1408 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1412 rte_spinlock_lock(&hw->lock);
1413 ret = hns3_add_uc_addr_common(hw, mac_addr);
1415 rte_spinlock_unlock(&hw->lock);
1416 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1418 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1423 hw->mac.default_addr_setted = true;
1424 rte_spinlock_unlock(&hw->lock);
1430 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1432 struct hns3_mac_vlan_tbl_entry_cmd req;
1433 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1436 /* check if mac addr is valid */
1437 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1438 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1440 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1445 memset(&req, 0, sizeof(req));
1446 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1447 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1448 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1449 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1452 hns3_update_umv_space(hw, true);
1458 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1460 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461 /* index will be checked by upper level rte interface */
1462 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1463 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1466 rte_spinlock_lock(&hw->lock);
1467 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1469 rte_spinlock_unlock(&hw->lock);
1470 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1472 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1476 rte_spinlock_unlock(&hw->lock);
1480 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1481 struct rte_ether_addr *mac_addr)
1483 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484 struct rte_ether_addr *oaddr;
1485 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1486 bool default_addr_setted;
1487 bool rm_succes = false;
1490 /* check if mac addr is valid */
1491 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1492 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1494 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1499 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1500 default_addr_setted = hw->mac.default_addr_setted;
1501 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1504 rte_spinlock_lock(&hw->lock);
1505 if (default_addr_setted) {
1506 ret = hns3_remove_uc_addr_common(hw, oaddr);
1508 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1510 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1517 ret = hns3_add_uc_addr_common(hw, mac_addr);
1519 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1521 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1522 goto err_add_uc_addr;
1525 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1527 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1528 goto err_pause_addr_cfg;
1531 rte_ether_addr_copy(mac_addr,
1532 (struct rte_ether_addr *)hw->mac.mac_addr);
1533 hw->mac.default_addr_setted = true;
1534 rte_spinlock_unlock(&hw->lock);
1539 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1541 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1544 "Failed to roll back to del setted mac addr(%s): %d",
1550 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1552 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1555 "Failed to restore old uc mac addr(%s): %d",
1557 hw->mac.default_addr_setted = false;
1560 rte_spinlock_unlock(&hw->lock);
1566 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1568 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1569 struct hns3_hw *hw = &hns->hw;
1570 struct rte_ether_addr *addr;
1575 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1576 addr = &hw->data->mac_addrs[i];
1577 if (!rte_is_valid_assigned_ether_addr(addr))
1580 ret = hns3_remove_uc_addr_common(hw, addr);
1582 ret = hns3_add_uc_addr_common(hw, addr);
1585 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1588 "Failed to %s mac addr(%s). ret:%d i:%d",
1589 del ? "remove" : "restore", mac_str, ret, i);
1596 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1598 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1602 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1603 word_num = vfid / 32;
1604 bit_num = vfid % 32;
1606 desc[1].data[word_num] &=
1607 rte_cpu_to_le_32(~(1UL << bit_num));
1609 desc[1].data[word_num] |=
1610 rte_cpu_to_le_32(1UL << bit_num);
1612 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1613 bit_num = vfid % 32;
1615 desc[2].data[word_num] &=
1616 rte_cpu_to_le_32(~(1UL << bit_num));
1618 desc[2].data[word_num] |=
1619 rte_cpu_to_le_32(1UL << bit_num);
1624 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1626 struct hns3_mac_vlan_tbl_entry_cmd req;
1627 struct hns3_cmd_desc desc[3];
1628 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1632 /* Check if mac addr is valid */
1633 if (!rte_is_multicast_ether_addr(mac_addr)) {
1634 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1636 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1641 memset(&req, 0, sizeof(req));
1642 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1643 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1644 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1646 /* This mac addr do not exist, add new entry for it */
1647 memset(desc[0].data, 0, sizeof(desc[0].data));
1648 memset(desc[1].data, 0, sizeof(desc[0].data));
1649 memset(desc[2].data, 0, sizeof(desc[0].data));
1653 * In current version VF is not supported when PF is driven by DPDK
1654 * driver, the PF-related vf_id is 0, just need to configure parameters
1658 hns3_update_desc_vfid(desc, vf_id, false);
1659 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1662 hns3_err(hw, "mc mac vlan table is full");
1663 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1665 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1672 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1674 struct hns3_mac_vlan_tbl_entry_cmd req;
1675 struct hns3_cmd_desc desc[3];
1676 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1680 /* Check if mac addr is valid */
1681 if (!rte_is_multicast_ether_addr(mac_addr)) {
1682 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1684 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1689 memset(&req, 0, sizeof(req));
1690 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1691 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1692 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1695 * This mac addr exist, remove this handle's VFID for it.
1696 * In current version VF is not supported when PF is driven by
1697 * DPDK driver, the PF-related vf_id is 0, just need to
1698 * configure parameters for vf_id 0.
1701 hns3_update_desc_vfid(desc, vf_id, true);
1703 /* All the vfid is zero, so need to delete this entry */
1704 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1705 } else if (ret == -ENOENT) {
1706 /* This mac addr doesn't exist. */
1711 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1713 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1720 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1721 struct rte_ether_addr *mc_addr_set,
1722 uint32_t nb_mc_addr)
1724 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1725 struct rte_ether_addr *addr;
1729 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1730 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1731 "invalid. valid range: 0~%d",
1732 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1736 /* Check if input mac addresses are valid */
1737 for (i = 0; i < nb_mc_addr; i++) {
1738 addr = &mc_addr_set[i];
1739 if (!rte_is_multicast_ether_addr(addr)) {
1740 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1743 "Failed to set mc mac addr, addr(%s) invalid.",
1748 /* Check if there are duplicate addresses */
1749 for (j = i + 1; j < nb_mc_addr; j++) {
1750 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1751 rte_ether_format_addr(mac_str,
1752 RTE_ETHER_ADDR_FMT_SIZE,
1754 hns3_err(hw, "Failed to set mc mac addr, "
1755 "addrs invalid. two same addrs(%s).",
1766 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1767 struct rte_ether_addr *mc_addr_set,
1769 struct rte_ether_addr *reserved_addr_list,
1770 int *reserved_addr_num,
1771 struct rte_ether_addr *add_addr_list,
1773 struct rte_ether_addr *rm_addr_list,
1776 struct rte_ether_addr *addr;
1777 int current_addr_num;
1778 int reserved_num = 0;
1786 /* Calculate the mc mac address list that should be removed */
1787 current_addr_num = hw->mc_addrs_num;
1788 for (i = 0; i < current_addr_num; i++) {
1789 addr = &hw->mc_addrs[i];
1791 for (j = 0; j < mc_addr_num; j++) {
1792 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1799 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1802 rte_ether_addr_copy(addr,
1803 &reserved_addr_list[reserved_num]);
1808 /* Calculate the mc mac address list that should be added */
1809 for (i = 0; i < mc_addr_num; i++) {
1810 addr = &mc_addr_set[i];
1812 for (j = 0; j < current_addr_num; j++) {
1813 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1820 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1825 /* Reorder the mc mac address list maintained by driver */
1826 for (i = 0; i < reserved_num; i++)
1827 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1829 for (i = 0; i < rm_num; i++) {
1830 num = reserved_num + i;
1831 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1834 *reserved_addr_num = reserved_num;
1835 *add_addr_num = add_num;
1836 *rm_addr_num = rm_num;
1840 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1841 struct rte_ether_addr *mc_addr_set,
1842 uint32_t nb_mc_addr)
1844 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1846 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1847 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1848 struct rte_ether_addr *addr;
1849 int reserved_addr_num;
1857 /* Check if input parameters are valid */
1858 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1862 rte_spinlock_lock(&hw->lock);
1865 * Calculate the mc mac address lists those should be removed and be
1866 * added, Reorder the mc mac address list maintained by driver.
1868 mc_addr_num = (int)nb_mc_addr;
1869 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1870 reserved_addr_list, &reserved_addr_num,
1871 add_addr_list, &add_addr_num,
1872 rm_addr_list, &rm_addr_num);
1874 /* Remove mc mac addresses */
1875 for (i = 0; i < rm_addr_num; i++) {
1876 num = rm_addr_num - i - 1;
1877 addr = &rm_addr_list[num];
1878 ret = hns3_remove_mc_addr(hw, addr);
1880 rte_spinlock_unlock(&hw->lock);
1886 /* Add mc mac addresses */
1887 for (i = 0; i < add_addr_num; i++) {
1888 addr = &add_addr_list[i];
1889 ret = hns3_add_mc_addr(hw, addr);
1891 rte_spinlock_unlock(&hw->lock);
1895 num = reserved_addr_num + i;
1896 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1899 rte_spinlock_unlock(&hw->lock);
1905 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1907 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1908 struct hns3_hw *hw = &hns->hw;
1909 struct rte_ether_addr *addr;
1914 for (i = 0; i < hw->mc_addrs_num; i++) {
1915 addr = &hw->mc_addrs[i];
1916 if (!rte_is_multicast_ether_addr(addr))
1919 ret = hns3_remove_mc_addr(hw, addr);
1921 ret = hns3_add_mc_addr(hw, addr);
1924 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1926 hns3_dbg(hw, "%s mc mac addr: %s failed",
1927 del ? "Remove" : "Restore", mac_str);
1934 hns3_check_mq_mode(struct rte_eth_dev *dev)
1936 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1937 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1938 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1941 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1946 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1947 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1949 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1950 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1951 "rx_mq_mode = %d", rx_mq_mode);
1955 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1956 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1957 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1958 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1959 rx_mq_mode, tx_mq_mode);
1963 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1964 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1965 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1966 dcb_rx_conf->nb_tcs, pf->tc_max);
1970 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1971 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1972 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1973 "nb_tcs(%d) != %d or %d in rx direction.",
1974 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1978 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1979 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1980 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1984 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1985 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1986 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1987 "is not equal to one in tx direction.",
1988 i, dcb_rx_conf->dcb_tc[i]);
1991 if (dcb_rx_conf->dcb_tc[i] > max_tc)
1992 max_tc = dcb_rx_conf->dcb_tc[i];
1995 num_tc = max_tc + 1;
1996 if (num_tc > dcb_rx_conf->nb_tcs) {
1997 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1998 num_tc, dcb_rx_conf->nb_tcs);
2007 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2009 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011 if (!hns3_dev_dcb_supported(hw)) {
2012 hns3_err(hw, "this port does not support dcb configurations.");
2016 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2017 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2021 /* Check multiple queue mode */
2022 return hns3_check_mq_mode(dev);
2026 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2027 enum hns3_ring_type queue_type, uint16_t queue_id)
2029 struct hns3_cmd_desc desc;
2030 struct hns3_ctrl_vector_chain_cmd *req =
2031 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2032 enum hns3_cmd_status status;
2033 enum hns3_opcode_type op;
2034 uint16_t tqp_type_and_id = 0;
2039 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2040 hns3_cmd_setup_basic_desc(&desc, op, false);
2041 req->int_vector_id = vector_id;
2043 if (queue_type == HNS3_RING_TYPE_RX)
2044 gl = HNS3_RING_GL_RX;
2046 gl = HNS3_RING_GL_TX;
2050 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2052 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2053 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2055 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2056 req->int_cause_num = 1;
2057 op_str = mmap ? "Map" : "Unmap";
2058 status = hns3_cmd_send(hw, &desc, 1);
2060 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2061 op_str, queue_id, req->int_vector_id, status);
2069 hns3_init_ring_with_vector(struct hns3_hw *hw)
2076 * In hns3 network engine, vector 0 is always the misc interrupt of this
2077 * function, vector 1~N can be used respectively for the queues of the
2078 * function. Tx and Rx queues with the same number share the interrupt
2079 * vector. In the initialization clearing the all hardware mapping
2080 * relationship configurations between queues and interrupt vectors is
2081 * needed, so some error caused by the residual configurations, such as
2082 * the unexpected Tx interrupt, can be avoid. Because of the hardware
2083 * constraints in hns3 hardware engine, we have to implement clearing
2084 * the mapping relationship configurations by binding all queues to the
2085 * last interrupt vector and reserving the last interrupt vector. This
2086 * method results in a decrease of the maximum queues when upper
2087 * applications call the rte_eth_dev_configure API function to enable
2090 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2091 hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2092 for (i = 0; i < hw->intr_tqps_num; i++) {
2094 * Set gap limiter and rate limiter configuration of queue's
2097 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2098 HNS3_TQP_INTR_GL_DEFAULT);
2099 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2100 HNS3_TQP_INTR_GL_DEFAULT);
2101 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2103 ret = hns3_bind_ring_with_vector(hw, vec, false,
2104 HNS3_RING_TYPE_TX, i);
2106 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2107 "vector: %d, ret=%d", i, vec, ret);
2111 ret = hns3_bind_ring_with_vector(hw, vec, false,
2112 HNS3_RING_TYPE_RX, i);
2114 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2115 "vector: %d, ret=%d", i, vec, ret);
2124 hns3_dev_configure(struct rte_eth_dev *dev)
2126 struct hns3_adapter *hns = dev->data->dev_private;
2127 struct rte_eth_conf *conf = &dev->data->dev_conf;
2128 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2129 struct hns3_hw *hw = &hns->hw;
2130 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2131 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2132 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2133 struct rte_eth_rss_conf rss_conf;
2138 * Hardware does not support individually enable/disable/reset the Tx or
2139 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2140 * and Rx queues at the same time. When the numbers of Tx queues
2141 * allocated by upper applications are not equal to the numbers of Rx
2142 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2143 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2144 * these fake queues are imperceptible, and can not be used by upper
2147 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2149 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2153 hw->adapter_state = HNS3_NIC_CONFIGURING;
2154 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2155 hns3_err(hw, "setting link speed/duplex not supported");
2160 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2161 ret = hns3_check_dcb_cfg(dev);
2166 /* When RSS is not configured, redirect the packet queue 0 */
2167 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2168 rss_conf = conf->rx_adv_conf.rss_conf;
2169 if (rss_conf.rss_key == NULL) {
2170 rss_conf.rss_key = rss_cfg->key;
2171 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2174 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2180 * If jumbo frames are enabled, MTU needs to be refreshed
2181 * according to the maximum RX packet length.
2183 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2185 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2186 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2187 * can safely assign to "uint16_t" type variable.
2189 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2190 ret = hns3_dev_mtu_set(dev, mtu);
2193 dev->data->mtu = mtu;
2196 ret = hns3_dev_configure_vlan(dev);
2200 hw->adapter_state = HNS3_NIC_CONFIGURED;
2205 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2206 hw->adapter_state = HNS3_NIC_INITIALIZED;
2212 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2214 struct hns3_config_max_frm_size_cmd *req;
2215 struct hns3_cmd_desc desc;
2217 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2219 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2220 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2221 req->min_frm_size = RTE_ETHER_MIN_LEN;
2223 return hns3_cmd_send(hw, &desc, 1);
2227 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2231 ret = hns3_set_mac_mtu(hw, mps);
2233 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2237 ret = hns3_buffer_alloc(hw);
2239 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2247 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2249 struct hns3_adapter *hns = dev->data->dev_private;
2250 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2251 struct hns3_hw *hw = &hns->hw;
2252 bool is_jumbo_frame;
2255 if (dev->data->dev_started) {
2256 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2257 "before configuration", dev->data->port_id);
2261 rte_spinlock_lock(&hw->lock);
2262 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2263 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2266 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2267 * assign to "uint16_t" type variable.
2269 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2271 rte_spinlock_unlock(&hw->lock);
2272 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2273 dev->data->port_id, mtu, ret);
2276 hns->pf.mps = (uint16_t)frame_size;
2278 dev->data->dev_conf.rxmode.offloads |=
2279 DEV_RX_OFFLOAD_JUMBO_FRAME;
2281 dev->data->dev_conf.rxmode.offloads &=
2282 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2283 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2284 rte_spinlock_unlock(&hw->lock);
2290 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2292 struct hns3_adapter *hns = eth_dev->data->dev_private;
2293 struct hns3_hw *hw = &hns->hw;
2294 uint16_t queue_num = hw->tqps_num;
2297 * In interrupt mode, 'max_rx_queues' is set based on the number of
2298 * MSI-X interrupt resources of the hardware.
2300 if (hw->data->dev_conf.intr_conf.rxq == 1)
2301 queue_num = hw->intr_tqps_num;
2303 info->max_rx_queues = queue_num;
2304 info->max_tx_queues = hw->tqps_num;
2305 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2306 info->min_rx_bufsize = hw->rx_buf_len;
2307 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2308 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2309 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2310 DEV_RX_OFFLOAD_TCP_CKSUM |
2311 DEV_RX_OFFLOAD_UDP_CKSUM |
2312 DEV_RX_OFFLOAD_SCTP_CKSUM |
2313 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2314 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2315 DEV_RX_OFFLOAD_KEEP_CRC |
2316 DEV_RX_OFFLOAD_SCATTER |
2317 DEV_RX_OFFLOAD_VLAN_STRIP |
2318 DEV_RX_OFFLOAD_QINQ_STRIP |
2319 DEV_RX_OFFLOAD_VLAN_FILTER |
2320 DEV_RX_OFFLOAD_VLAN_EXTEND |
2321 DEV_RX_OFFLOAD_JUMBO_FRAME);
2322 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2323 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2324 DEV_TX_OFFLOAD_IPV4_CKSUM |
2325 DEV_TX_OFFLOAD_TCP_CKSUM |
2326 DEV_TX_OFFLOAD_UDP_CKSUM |
2327 DEV_TX_OFFLOAD_SCTP_CKSUM |
2328 DEV_TX_OFFLOAD_VLAN_INSERT |
2329 DEV_TX_OFFLOAD_QINQ_INSERT |
2330 DEV_TX_OFFLOAD_MULTI_SEGS |
2331 DEV_TX_OFFLOAD_TCP_TSO |
2332 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2333 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2334 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2335 info->tx_queue_offload_capa);
2337 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2338 .nb_max = HNS3_MAX_RING_DESC,
2339 .nb_min = HNS3_MIN_RING_DESC,
2340 .nb_align = HNS3_ALIGN_RING_DESC,
2343 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2344 .nb_max = HNS3_MAX_RING_DESC,
2345 .nb_min = HNS3_MIN_RING_DESC,
2346 .nb_align = HNS3_ALIGN_RING_DESC,
2349 info->vmdq_queue_num = 0;
2351 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2352 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2353 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2355 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2356 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2357 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2358 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2359 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2360 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2366 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2369 struct hns3_adapter *hns = eth_dev->data->dev_private;
2370 struct hns3_hw *hw = &hns->hw;
2373 ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2374 ret += 1; /* add the size of '\0' */
2375 if (fw_size < (uint32_t)ret)
2382 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2383 __rte_unused int wait_to_complete)
2385 struct hns3_adapter *hns = eth_dev->data->dev_private;
2386 struct hns3_hw *hw = &hns->hw;
2387 struct hns3_mac *mac = &hw->mac;
2388 struct rte_eth_link new_link;
2390 if (!hns3_is_reset_pending(hns)) {
2391 hns3_update_speed_duplex(eth_dev);
2392 hns3_update_link_status(hw);
2395 memset(&new_link, 0, sizeof(new_link));
2396 switch (mac->link_speed) {
2397 case ETH_SPEED_NUM_10M:
2398 case ETH_SPEED_NUM_100M:
2399 case ETH_SPEED_NUM_1G:
2400 case ETH_SPEED_NUM_10G:
2401 case ETH_SPEED_NUM_25G:
2402 case ETH_SPEED_NUM_40G:
2403 case ETH_SPEED_NUM_50G:
2404 case ETH_SPEED_NUM_100G:
2405 new_link.link_speed = mac->link_speed;
2408 new_link.link_speed = ETH_SPEED_NUM_100M;
2412 new_link.link_duplex = mac->link_duplex;
2413 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2414 new_link.link_autoneg =
2415 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2417 return rte_eth_linkstatus_set(eth_dev, &new_link);
2421 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2423 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2424 struct hns3_pf *pf = &hns->pf;
2426 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2429 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2435 hns3_query_function_status(struct hns3_hw *hw)
2437 #define HNS3_QUERY_MAX_CNT 10
2438 #define HNS3_QUERY_SLEEP_MSCOEND 1
2439 struct hns3_func_status_cmd *req;
2440 struct hns3_cmd_desc desc;
2444 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2445 req = (struct hns3_func_status_cmd *)desc.data;
2448 ret = hns3_cmd_send(hw, &desc, 1);
2450 PMD_INIT_LOG(ERR, "query function status failed %d",
2455 /* Check pf reset is done */
2459 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2460 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2462 return hns3_parse_func_status(hw, req);
2466 hns3_query_pf_resource(struct hns3_hw *hw)
2468 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2469 struct hns3_pf *pf = &hns->pf;
2470 struct hns3_pf_res_cmd *req;
2471 struct hns3_cmd_desc desc;
2475 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2476 ret = hns3_cmd_send(hw, &desc, 1);
2478 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2482 req = (struct hns3_pf_res_cmd *)desc.data;
2483 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2484 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2485 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2486 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2488 if (req->tx_buf_size)
2490 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2492 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2494 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2496 if (req->dv_buf_size)
2498 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2500 pf->dv_buf_size = HNS3_DEFAULT_DV;
2502 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2504 num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2505 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2506 hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2512 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2514 struct hns3_cfg_param_cmd *req;
2515 uint64_t mac_addr_tmp_high;
2516 uint64_t mac_addr_tmp;
2519 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2521 /* get the configuration */
2522 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2523 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2524 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2525 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2526 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2527 HNS3_CFG_TQP_DESC_N_M,
2528 HNS3_CFG_TQP_DESC_N_S);
2530 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2531 HNS3_CFG_PHY_ADDR_M,
2532 HNS3_CFG_PHY_ADDR_S);
2533 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2534 HNS3_CFG_MEDIA_TP_M,
2535 HNS3_CFG_MEDIA_TP_S);
2536 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2537 HNS3_CFG_RX_BUF_LEN_M,
2538 HNS3_CFG_RX_BUF_LEN_S);
2539 /* get mac address */
2540 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2541 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2542 HNS3_CFG_MAC_ADDR_H_M,
2543 HNS3_CFG_MAC_ADDR_H_S);
2545 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2547 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2548 HNS3_CFG_DEFAULT_SPEED_M,
2549 HNS3_CFG_DEFAULT_SPEED_S);
2550 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2551 HNS3_CFG_RSS_SIZE_M,
2552 HNS3_CFG_RSS_SIZE_S);
2554 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2555 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2557 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2558 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2560 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2561 HNS3_CFG_SPEED_ABILITY_M,
2562 HNS3_CFG_SPEED_ABILITY_S);
2563 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2564 HNS3_CFG_UMV_TBL_SPACE_M,
2565 HNS3_CFG_UMV_TBL_SPACE_S);
2566 if (!cfg->umv_space)
2567 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2570 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2571 * @hw: pointer to struct hns3_hw
2572 * @hcfg: the config structure to be getted
2575 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2577 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2578 struct hns3_cfg_param_cmd *req;
2583 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2585 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2586 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2588 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2589 i * HNS3_CFG_RD_LEN_BYTES);
2590 /* Len should be divided by 4 when send to hardware */
2591 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2592 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2593 req->offset = rte_cpu_to_le_32(offset);
2596 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2598 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2602 hns3_parse_cfg(hcfg, desc);
2608 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2610 switch (speed_cmd) {
2611 case HNS3_CFG_SPEED_10M:
2612 *speed = ETH_SPEED_NUM_10M;
2614 case HNS3_CFG_SPEED_100M:
2615 *speed = ETH_SPEED_NUM_100M;
2617 case HNS3_CFG_SPEED_1G:
2618 *speed = ETH_SPEED_NUM_1G;
2620 case HNS3_CFG_SPEED_10G:
2621 *speed = ETH_SPEED_NUM_10G;
2623 case HNS3_CFG_SPEED_25G:
2624 *speed = ETH_SPEED_NUM_25G;
2626 case HNS3_CFG_SPEED_40G:
2627 *speed = ETH_SPEED_NUM_40G;
2629 case HNS3_CFG_SPEED_50G:
2630 *speed = ETH_SPEED_NUM_50G;
2632 case HNS3_CFG_SPEED_100G:
2633 *speed = ETH_SPEED_NUM_100G;
2643 hns3_get_board_configuration(struct hns3_hw *hw)
2645 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2646 struct hns3_pf *pf = &hns->pf;
2647 struct hns3_cfg cfg;
2650 ret = hns3_get_board_cfg(hw, &cfg);
2652 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2656 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2657 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2661 hw->mac.media_type = cfg.media_type;
2662 hw->rss_size_max = cfg.rss_size_max;
2663 hw->rx_buf_len = cfg.rx_buf_len;
2664 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2665 hw->mac.phy_addr = cfg.phy_addr;
2666 hw->mac.default_addr_setted = false;
2667 hw->num_tx_desc = cfg.tqp_desc_num;
2668 hw->num_rx_desc = cfg.tqp_desc_num;
2669 hw->dcb_info.num_pg = 1;
2670 hw->dcb_info.hw_pfc_map = 0;
2672 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2674 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2675 cfg.default_speed, ret);
2679 pf->tc_max = cfg.tc_num;
2680 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2681 PMD_INIT_LOG(WARNING,
2682 "Get TC num(%u) from flash, set TC num to 1",
2687 /* Dev does not support DCB */
2688 if (!hns3_dev_dcb_supported(hw)) {
2692 pf->pfc_max = pf->tc_max;
2694 hw->dcb_info.num_tc = 1;
2695 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2696 hw->tqps_num / hw->dcb_info.num_tc);
2697 hns3_set_bit(hw->hw_tc_map, 0, 1);
2698 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2700 pf->wanted_umv_size = cfg.umv_space;
2706 hns3_get_configuration(struct hns3_hw *hw)
2710 ret = hns3_query_function_status(hw);
2712 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2716 /* Get pf resource */
2717 ret = hns3_query_pf_resource(hw);
2719 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2723 ret = hns3_get_board_configuration(hw);
2725 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2733 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2734 uint16_t tqp_vid, bool is_pf)
2736 struct hns3_tqp_map_cmd *req;
2737 struct hns3_cmd_desc desc;
2740 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2742 req = (struct hns3_tqp_map_cmd *)desc.data;
2743 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2744 req->tqp_vf = func_id;
2745 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2747 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2748 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2750 ret = hns3_cmd_send(hw, &desc, 1);
2752 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2758 hns3_map_tqp(struct hns3_hw *hw)
2760 uint16_t tqps_num = hw->total_tqps_num;
2769 * In current version VF is not supported when PF is driven by DPDK
2770 * driver, so we allocate tqps to PF as much as possible.
2773 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2774 for (func_id = 0; func_id < num; func_id++) {
2775 is_pf = func_id == 0 ? true : false;
2777 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2778 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2789 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2791 struct hns3_config_mac_speed_dup_cmd *req;
2792 struct hns3_cmd_desc desc;
2795 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2797 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2799 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2802 case ETH_SPEED_NUM_10M:
2803 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2804 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2806 case ETH_SPEED_NUM_100M:
2807 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2808 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2810 case ETH_SPEED_NUM_1G:
2811 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2812 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2814 case ETH_SPEED_NUM_10G:
2815 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2816 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2818 case ETH_SPEED_NUM_25G:
2819 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2820 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2822 case ETH_SPEED_NUM_40G:
2823 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2824 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2826 case ETH_SPEED_NUM_50G:
2827 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2828 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2830 case ETH_SPEED_NUM_100G:
2831 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2832 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2835 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2839 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2841 ret = hns3_cmd_send(hw, &desc, 1);
2843 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2849 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2851 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2852 struct hns3_pf *pf = &hns->pf;
2853 struct hns3_priv_buf *priv;
2854 uint32_t i, total_size;
2856 total_size = pf->pkt_buf_size;
2858 /* alloc tx buffer for all enabled tc */
2859 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2860 priv = &buf_alloc->priv_buf[i];
2862 if (hw->hw_tc_map & BIT(i)) {
2863 if (total_size < pf->tx_buf_size)
2866 priv->tx_buf_size = pf->tx_buf_size;
2868 priv->tx_buf_size = 0;
2870 total_size -= priv->tx_buf_size;
2877 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2879 /* TX buffer size is unit by 128 byte */
2880 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
2881 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
2882 struct hns3_tx_buff_alloc_cmd *req;
2883 struct hns3_cmd_desc desc;
2888 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2890 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2891 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2892 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2894 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2895 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2896 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2899 ret = hns3_cmd_send(hw, &desc, 1);
2901 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2907 hns3_get_tc_num(struct hns3_hw *hw)
2912 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2913 if (hw->hw_tc_map & BIT(i))
2919 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2921 struct hns3_priv_buf *priv;
2922 uint32_t rx_priv = 0;
2925 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2926 priv = &buf_alloc->priv_buf[i];
2928 rx_priv += priv->buf_size;
2934 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2936 uint32_t total_tx_size = 0;
2939 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2940 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2942 return total_tx_size;
2945 /* Get the number of pfc enabled TCs, which have private buffer */
2947 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2949 struct hns3_priv_buf *priv;
2953 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2954 priv = &buf_alloc->priv_buf[i];
2955 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2962 /* Get the number of pfc disabled TCs, which have private buffer */
2964 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2965 struct hns3_pkt_buf_alloc *buf_alloc)
2967 struct hns3_priv_buf *priv;
2971 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2972 priv = &buf_alloc->priv_buf[i];
2973 if (hw->hw_tc_map & BIT(i) &&
2974 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2982 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2985 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2986 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2987 struct hns3_pf *pf = &hns->pf;
2988 uint32_t shared_buf, aligned_mps;
2993 tc_num = hns3_get_tc_num(hw);
2994 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2996 if (hns3_dev_dcb_supported(hw))
2997 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3000 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3003 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3004 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3005 HNS3_BUF_SIZE_UNIT);
3007 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3008 if (rx_all < rx_priv + shared_std)
3011 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3012 buf_alloc->s_buf.buf_size = shared_buf;
3013 if (hns3_dev_dcb_supported(hw)) {
3014 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3015 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3016 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3017 HNS3_BUF_SIZE_UNIT);
3019 buf_alloc->s_buf.self.high =
3020 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3021 buf_alloc->s_buf.self.low = aligned_mps;
3024 if (hns3_dev_dcb_supported(hw)) {
3025 hi_thrd = shared_buf - pf->dv_buf_size;
3027 if (tc_num <= NEED_RESERVE_TC_NUM)
3028 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3032 hi_thrd = hi_thrd / tc_num;
3034 hi_thrd = max_t(uint32_t, hi_thrd,
3035 HNS3_BUF_MUL_BY * aligned_mps);
3036 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3037 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3039 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3040 lo_thrd = aligned_mps;
3043 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3044 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3045 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3052 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3053 struct hns3_pkt_buf_alloc *buf_alloc)
3055 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3056 struct hns3_pf *pf = &hns->pf;
3057 struct hns3_priv_buf *priv;
3058 uint32_t aligned_mps;
3062 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3063 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3065 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3066 priv = &buf_alloc->priv_buf[i];
3073 if (!(hw->hw_tc_map & BIT(i)))
3077 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3078 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3079 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3080 HNS3_BUF_SIZE_UNIT);
3083 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3087 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3090 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3094 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3095 struct hns3_pkt_buf_alloc *buf_alloc)
3097 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3098 struct hns3_pf *pf = &hns->pf;
3099 struct hns3_priv_buf *priv;
3100 int no_pfc_priv_num;
3105 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3106 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3108 /* let the last to be cleared first */
3109 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3110 priv = &buf_alloc->priv_buf[i];
3111 mask = BIT((uint8_t)i);
3113 if (hw->hw_tc_map & mask &&
3114 !(hw->dcb_info.hw_pfc_map & mask)) {
3115 /* Clear the no pfc TC private buffer */
3123 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3124 no_pfc_priv_num == 0)
3128 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3132 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3133 struct hns3_pkt_buf_alloc *buf_alloc)
3135 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3136 struct hns3_pf *pf = &hns->pf;
3137 struct hns3_priv_buf *priv;
3143 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3144 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3146 /* let the last to be cleared first */
3147 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3148 priv = &buf_alloc->priv_buf[i];
3149 mask = BIT((uint8_t)i);
3151 if (hw->hw_tc_map & mask &&
3152 hw->dcb_info.hw_pfc_map & mask) {
3153 /* Reduce the number of pfc TC with private buffer */
3160 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3165 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3169 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3170 struct hns3_pkt_buf_alloc *buf_alloc)
3172 #define COMPENSATE_BUFFER 0x3C00
3173 #define COMPENSATE_HALF_MPS_NUM 5
3174 #define PRIV_WL_GAP 0x1800
3175 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3176 struct hns3_pf *pf = &hns->pf;
3177 uint32_t tc_num = hns3_get_tc_num(hw);
3178 uint32_t half_mps = pf->mps >> 1;
3179 struct hns3_priv_buf *priv;
3180 uint32_t min_rx_priv;
3184 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3186 rx_priv = rx_priv / tc_num;
3188 if (tc_num <= NEED_RESERVE_TC_NUM)
3189 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3192 * Minimum value of private buffer in rx direction (min_rx_priv) is
3193 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3194 * buffer if rx_priv is greater than min_rx_priv.
3196 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3197 COMPENSATE_HALF_MPS_NUM * half_mps;
3198 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3199 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3201 if (rx_priv < min_rx_priv)
3204 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3205 priv = &buf_alloc->priv_buf[i];
3212 if (!(hw->hw_tc_map & BIT(i)))
3216 priv->buf_size = rx_priv;
3217 priv->wl.high = rx_priv - pf->dv_buf_size;
3218 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3221 buf_alloc->s_buf.buf_size = 0;
3227 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3228 * @hw: pointer to struct hns3_hw
3229 * @buf_alloc: pointer to buffer calculation data
3230 * @return: 0: calculate sucessful, negative: fail
3233 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3235 /* When DCB is not supported, rx private buffer is not allocated. */
3236 if (!hns3_dev_dcb_supported(hw)) {
3237 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3238 struct hns3_pf *pf = &hns->pf;
3239 uint32_t rx_all = pf->pkt_buf_size;
3241 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3242 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3249 * Try to allocate privated packet buffer for all TCs without share
3252 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3256 * Try to allocate privated packet buffer for all TCs with share
3259 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3263 * For different application scenes, the enabled port number, TC number
3264 * and no_drop TC number are different. In order to obtain the better
3265 * performance, software could allocate the buffer size and configure
3266 * the waterline by tring to decrease the private buffer size according
3267 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3270 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3273 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3276 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3283 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3285 struct hns3_rx_priv_buff_cmd *req;
3286 struct hns3_cmd_desc desc;
3291 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3292 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3294 /* Alloc private buffer TCs */
3295 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3296 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3299 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3300 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3303 buf_size = buf_alloc->s_buf.buf_size;
3304 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3305 (1 << HNS3_TC0_PRI_BUF_EN_B));
3307 ret = hns3_cmd_send(hw, &desc, 1);
3309 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3315 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3317 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3318 struct hns3_rx_priv_wl_buf *req;
3319 struct hns3_priv_buf *priv;
3320 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3324 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3325 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3327 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3329 /* The first descriptor set the NEXT bit to 1 */
3331 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3333 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3335 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3336 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3338 priv = &buf_alloc->priv_buf[idx];
3339 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3341 req->tc_wl[j].high |=
3342 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3343 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3345 req->tc_wl[j].low |=
3346 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3350 /* Send 2 descriptor at one time */
3351 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3353 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3359 hns3_common_thrd_config(struct hns3_hw *hw,
3360 struct hns3_pkt_buf_alloc *buf_alloc)
3362 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3363 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3364 struct hns3_rx_com_thrd *req;
3365 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3366 struct hns3_tc_thrd *tc;
3371 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3372 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3374 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3376 /* The first descriptor set the NEXT bit to 1 */
3378 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3380 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3382 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3383 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3384 tc = &s_buf->tc_thrd[tc_idx];
3386 req->com_thrd[j].high =
3387 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3388 req->com_thrd[j].high |=
3389 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3390 req->com_thrd[j].low =
3391 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3392 req->com_thrd[j].low |=
3393 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3397 /* Send 2 descriptors at one time */
3398 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3400 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3406 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3408 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3409 struct hns3_rx_com_wl *req;
3410 struct hns3_cmd_desc desc;
3413 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3415 req = (struct hns3_rx_com_wl *)desc.data;
3416 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3417 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3419 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3420 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3422 ret = hns3_cmd_send(hw, &desc, 1);
3424 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3430 hns3_buffer_alloc(struct hns3_hw *hw)
3432 struct hns3_pkt_buf_alloc pkt_buf;
3435 memset(&pkt_buf, 0, sizeof(pkt_buf));
3436 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3439 "could not calc tx buffer size for all TCs %d",
3444 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3446 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3450 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3453 "could not calc rx priv buffer size for all TCs %d",
3458 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3460 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3464 if (hns3_dev_dcb_supported(hw)) {
3465 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3468 "could not configure rx private waterline %d",
3473 ret = hns3_common_thrd_config(hw, &pkt_buf);
3476 "could not configure common threshold %d",
3482 ret = hns3_common_wl_config(hw, &pkt_buf);
3484 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3491 hns3_mac_init(struct hns3_hw *hw)
3493 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3494 struct hns3_mac *mac = &hw->mac;
3495 struct hns3_pf *pf = &hns->pf;
3498 pf->support_sfp_query = true;
3499 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3500 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3502 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3506 mac->link_status = ETH_LINK_DOWN;
3508 return hns3_config_mtu(hw, pf->mps);
3512 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3514 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3515 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3516 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3517 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3522 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3527 switch (resp_code) {
3528 case HNS3_ETHERTYPE_SUCCESS_ADD:
3529 case HNS3_ETHERTYPE_ALREADY_ADD:
3532 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3534 "add mac ethertype failed for manager table overflow.");
3535 return_status = -EIO;
3537 case HNS3_ETHERTYPE_KEY_CONFLICT:
3538 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3539 return_status = -EIO;
3543 "add mac ethertype failed for undefined, code=%d.",
3545 return_status = -EIO;
3548 return return_status;
3552 hns3_add_mgr_tbl(struct hns3_hw *hw,
3553 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3555 struct hns3_cmd_desc desc;
3560 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3561 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3563 ret = hns3_cmd_send(hw, &desc, 1);
3566 "add mac ethertype failed for cmd_send, ret =%d.",
3571 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3572 retval = rte_le_to_cpu_16(desc.retval);
3574 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3578 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3579 int *table_item_num)
3581 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3584 * In current version, we add one item in management table as below:
3585 * 0x0180C200000E -- LLDP MC address
3588 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3589 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3590 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3591 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3592 tbl->i_port_bitmap = 0x1;
3593 *table_item_num = 1;
3597 hns3_init_mgr_tbl(struct hns3_hw *hw)
3599 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3600 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3605 memset(mgr_table, 0, sizeof(mgr_table));
3606 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3607 for (i = 0; i < table_item_num; i++) {
3608 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3610 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3620 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3621 bool en_mc, bool en_bc, int vport_id)
3626 memset(param, 0, sizeof(struct hns3_promisc_param));
3628 param->enable = HNS3_PROMISC_EN_UC;
3630 param->enable |= HNS3_PROMISC_EN_MC;
3632 param->enable |= HNS3_PROMISC_EN_BC;
3633 param->vf_id = vport_id;
3637 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3639 struct hns3_promisc_cfg_cmd *req;
3640 struct hns3_cmd_desc desc;
3643 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3645 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3646 req->vf_id = param->vf_id;
3647 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3648 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3650 ret = hns3_cmd_send(hw, &desc, 1);
3652 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3658 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3660 struct hns3_promisc_param param;
3661 bool en_bc_pmc = true;
3666 * In current version VF is not supported when PF is driven by DPDK
3667 * driver, the PF-related vf_id is 0, just need to configure parameters
3672 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3673 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3681 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3683 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3684 struct hns3_pf *pf = &hns->pf;
3685 struct hns3_promisc_param param;
3689 /* func_id 0 is denoted PF, the VFs start from 1 */
3690 for (func_id = 1; func_id < pf->func_num; func_id++) {
3691 hns3_promisc_param_init(¶m, false, false, false, func_id);
3692 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3701 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3703 struct hns3_adapter *hns = dev->data->dev_private;
3704 struct hns3_hw *hw = &hns->hw;
3707 rte_spinlock_lock(&hw->lock);
3708 ret = hns3_set_promisc_mode(hw, true, true);
3709 rte_spinlock_unlock(&hw->lock);
3711 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3718 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3720 bool allmulti = dev->data->all_multicast ? true : false;
3721 struct hns3_adapter *hns = dev->data->dev_private;
3722 struct hns3_hw *hw = &hns->hw;
3725 /* If now in all_multicast mode, must remain in all_multicast mode. */
3726 rte_spinlock_lock(&hw->lock);
3727 ret = hns3_set_promisc_mode(hw, false, allmulti);
3728 rte_spinlock_unlock(&hw->lock);
3730 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3737 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3739 struct hns3_adapter *hns = dev->data->dev_private;
3740 struct hns3_hw *hw = &hns->hw;
3743 if (dev->data->promiscuous)
3746 rte_spinlock_lock(&hw->lock);
3747 ret = hns3_set_promisc_mode(hw, false, true);
3748 rte_spinlock_unlock(&hw->lock);
3750 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3757 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3759 struct hns3_adapter *hns = dev->data->dev_private;
3760 struct hns3_hw *hw = &hns->hw;
3763 /* If now in promiscuous mode, must remain in all_multicast mode. */
3764 if (dev->data->promiscuous)
3767 rte_spinlock_lock(&hw->lock);
3768 ret = hns3_set_promisc_mode(hw, false, false);
3769 rte_spinlock_unlock(&hw->lock);
3771 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
3778 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3780 struct hns3_hw *hw = &hns->hw;
3781 bool allmulti = hw->data->all_multicast ? true : false;
3783 if (hw->data->promiscuous)
3784 return hns3_set_promisc_mode(hw, true, true);
3786 return hns3_set_promisc_mode(hw, false, allmulti);
3790 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3792 struct hns3_sfp_speed_cmd *resp;
3793 struct hns3_cmd_desc desc;
3796 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3797 resp = (struct hns3_sfp_speed_cmd *)desc.data;
3798 ret = hns3_cmd_send(hw, &desc, 1);
3799 if (ret == -EOPNOTSUPP) {
3800 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3803 hns3_err(hw, "get sfp speed failed %d", ret);
3807 *speed = resp->sfp_speed;
3813 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3815 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3816 duplex = ETH_LINK_FULL_DUPLEX;
3822 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3824 struct hns3_mac *mac = &hw->mac;
3827 duplex = hns3_check_speed_dup(duplex, speed);
3828 if (mac->link_speed == speed && mac->link_duplex == duplex)
3831 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3835 mac->link_speed = speed;
3836 mac->link_duplex = duplex;
3842 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3844 struct hns3_adapter *hns = eth_dev->data->dev_private;
3845 struct hns3_hw *hw = &hns->hw;
3846 struct hns3_pf *pf = &hns->pf;
3850 /* If IMP do not support get SFP/qSFP speed, return directly */
3851 if (!pf->support_sfp_query)
3854 ret = hns3_get_sfp_speed(hw, &speed);
3855 if (ret == -EOPNOTSUPP) {
3856 pf->support_sfp_query = false;
3861 if (speed == ETH_SPEED_NUM_NONE)
3862 return 0; /* do nothing if no SFP */
3864 /* Config full duplex for SFP */
3865 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3869 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3871 struct hns3_config_mac_mode_cmd *req;
3872 struct hns3_cmd_desc desc;
3873 uint32_t loop_en = 0;
3877 req = (struct hns3_config_mac_mode_cmd *)desc.data;
3879 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3882 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3883 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3884 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3885 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3886 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3887 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3888 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3889 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3890 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3891 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3892 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3893 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3894 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3895 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3896 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3898 ret = hns3_cmd_send(hw, &desc, 1);
3900 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3906 hns3_get_mac_link_status(struct hns3_hw *hw)
3908 struct hns3_link_status_cmd *req;
3909 struct hns3_cmd_desc desc;
3913 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3914 ret = hns3_cmd_send(hw, &desc, 1);
3916 hns3_err(hw, "get link status cmd failed %d", ret);
3917 return ETH_LINK_DOWN;
3920 req = (struct hns3_link_status_cmd *)desc.data;
3921 link_status = req->status & HNS3_LINK_STATUS_UP_M;
3923 return !!link_status;
3927 hns3_update_link_status(struct hns3_hw *hw)
3931 state = hns3_get_mac_link_status(hw);
3932 if (state != hw->mac.link_status) {
3933 hw->mac.link_status = state;
3934 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3939 hns3_service_handler(void *param)
3941 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3942 struct hns3_adapter *hns = eth_dev->data->dev_private;
3943 struct hns3_hw *hw = &hns->hw;
3945 if (!hns3_is_reset_pending(hns)) {
3946 hns3_update_speed_duplex(eth_dev);
3947 hns3_update_link_status(hw);
3949 hns3_warn(hw, "Cancel the query when reset is pending");
3951 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3955 hns3_init_hardware(struct hns3_adapter *hns)
3957 struct hns3_hw *hw = &hns->hw;
3960 ret = hns3_map_tqp(hw);
3962 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3966 ret = hns3_init_umv_space(hw);
3968 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3972 ret = hns3_mac_init(hw);
3974 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3978 ret = hns3_init_mgr_tbl(hw);
3980 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3984 ret = hns3_set_promisc_mode(hw, false, false);
3986 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3990 ret = hns3_clear_all_vfs_promisc_mode(hw);
3992 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3997 ret = hns3_init_vlan_config(hns);
3999 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4003 ret = hns3_dcb_init(hw);
4005 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4009 ret = hns3_init_fd_config(hns);
4011 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4015 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4017 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4021 ret = hns3_config_gro(hw, false);
4023 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4029 hns3_uninit_umv_space(hw);
4034 hns3_init_pf(struct rte_eth_dev *eth_dev)
4036 struct rte_device *dev = eth_dev->device;
4037 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4038 struct hns3_adapter *hns = eth_dev->data->dev_private;
4039 struct hns3_hw *hw = &hns->hw;
4042 PMD_INIT_FUNC_TRACE();
4044 /* Get hardware io base address from pcie BAR2 IO space */
4045 hw->io_base = pci_dev->mem_resource[2].addr;
4047 /* Firmware command queue initialize */
4048 ret = hns3_cmd_init_queue(hw);
4050 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4051 goto err_cmd_init_queue;
4054 hns3_clear_all_event_cause(hw);
4056 /* Firmware command initialize */
4057 ret = hns3_cmd_init(hw);
4059 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4063 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4064 hns3_interrupt_handler,
4067 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4068 goto err_intr_callback_register;
4071 /* Enable interrupt */
4072 rte_intr_enable(&pci_dev->intr_handle);
4073 hns3_pf_enable_irq0(hw);
4075 /* Get configuration */
4076 ret = hns3_get_configuration(hw);
4078 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4079 goto err_get_config;
4082 ret = hns3_init_hardware(hns);
4084 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4085 goto err_get_config;
4088 /* Initialize flow director filter list & hash */
4089 ret = hns3_fdir_filter_init(hns);
4091 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4095 hns3_set_default_rss_args(hw);
4097 ret = hns3_enable_hw_error_intr(hns, true);
4099 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4105 * In the initialization clearing the all hardware mapping relationship
4106 * configurations between queues and interrupt vectors is needed, so
4107 * some error caused by the residual configurations, such as the
4108 * unexpected interrupt, can be avoid.
4110 ret = hns3_init_ring_with_vector(hw);
4117 hns3_fdir_filter_uninit(hns);
4119 hns3_uninit_umv_space(hw);
4122 hns3_pf_disable_irq0(hw);
4123 rte_intr_disable(&pci_dev->intr_handle);
4124 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4127 err_intr_callback_register:
4128 hns3_cmd_uninit(hw);
4131 hns3_cmd_destroy_queue(hw);
4140 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4142 struct hns3_adapter *hns = eth_dev->data->dev_private;
4143 struct rte_device *dev = eth_dev->device;
4144 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4145 struct hns3_hw *hw = &hns->hw;
4147 PMD_INIT_FUNC_TRACE();
4149 hns3_enable_hw_error_intr(hns, false);
4150 hns3_rss_uninit(hns);
4151 hns3_fdir_filter_uninit(hns);
4152 hns3_uninit_umv_space(hw);
4153 hns3_pf_disable_irq0(hw);
4154 rte_intr_disable(&pci_dev->intr_handle);
4155 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4157 hns3_cmd_uninit(hw);
4158 hns3_cmd_destroy_queue(hw);
4163 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4165 struct hns3_hw *hw = &hns->hw;
4168 ret = hns3_dcb_cfg_update(hns);
4173 ret = hns3_start_queues(hns, reset_queue);
4175 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4180 ret = hns3_cfg_mac_mode(hw, true);
4182 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4183 goto err_config_mac_mode;
4187 err_config_mac_mode:
4188 hns3_stop_queues(hns, true);
4193 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4195 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4196 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4197 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4198 uint32_t intr_vector;
4204 if (dev->data->dev_conf.intr_conf.rxq == 0)
4207 /* disable uio/vfio intr/eventfd mapping */
4208 rte_intr_disable(intr_handle);
4210 /* check and configure queue intr-vector mapping */
4211 if (rte_intr_cap_multiple(intr_handle) ||
4212 !RTE_ETH_DEV_SRIOV(dev).active) {
4213 intr_vector = hw->used_rx_queues;
4214 /* creates event fd for each intr vector when MSIX is used */
4215 if (rte_intr_efd_enable(intr_handle, intr_vector))
4218 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4219 intr_handle->intr_vec =
4220 rte_zmalloc("intr_vec",
4221 hw->used_rx_queues * sizeof(int), 0);
4222 if (intr_handle->intr_vec == NULL) {
4223 hns3_err(hw, "Failed to allocate %d rx_queues"
4224 " intr_vec", hw->used_rx_queues);
4226 goto alloc_intr_vec_error;
4230 if (rte_intr_allow_others(intr_handle)) {
4231 vec = RTE_INTR_VEC_RXTX_OFFSET;
4232 base = RTE_INTR_VEC_RXTX_OFFSET;
4234 if (rte_intr_dp_is_en(intr_handle)) {
4235 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4236 ret = hns3_bind_ring_with_vector(hw, vec, true,
4240 goto bind_vector_error;
4241 intr_handle->intr_vec[q_id] = vec;
4242 if (vec < base + intr_handle->nb_efd - 1)
4246 rte_intr_enable(intr_handle);
4250 rte_intr_efd_disable(intr_handle);
4251 if (intr_handle->intr_vec) {
4252 free(intr_handle->intr_vec);
4253 intr_handle->intr_vec = NULL;
4256 alloc_intr_vec_error:
4257 rte_intr_efd_disable(intr_handle);
4262 hns3_dev_start(struct rte_eth_dev *dev)
4264 struct hns3_adapter *hns = dev->data->dev_private;
4265 struct hns3_hw *hw = &hns->hw;
4268 PMD_INIT_FUNC_TRACE();
4269 if (rte_atomic16_read(&hw->reset.resetting))
4272 rte_spinlock_lock(&hw->lock);
4273 hw->adapter_state = HNS3_NIC_STARTING;
4275 ret = hns3_do_start(hns, true);
4277 hw->adapter_state = HNS3_NIC_CONFIGURED;
4278 rte_spinlock_unlock(&hw->lock);
4282 hw->adapter_state = HNS3_NIC_STARTED;
4283 rte_spinlock_unlock(&hw->lock);
4285 ret = hns3_map_rx_interrupt(dev);
4288 hns3_set_rxtx_function(dev);
4289 hns3_mp_req_start_rxtx(dev);
4290 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4292 hns3_info(hw, "hns3 dev start successful!");
4297 hns3_do_stop(struct hns3_adapter *hns)
4299 struct hns3_hw *hw = &hns->hw;
4303 ret = hns3_cfg_mac_mode(hw, false);
4306 hw->mac.link_status = ETH_LINK_DOWN;
4308 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4309 hns3_configure_all_mac_addr(hns, true);
4312 reset_queue = false;
4313 hw->mac.default_addr_setted = false;
4314 return hns3_stop_queues(hns, reset_queue);
4318 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4320 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4321 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4322 struct hns3_adapter *hns = dev->data->dev_private;
4323 struct hns3_hw *hw = &hns->hw;
4328 if (dev->data->dev_conf.intr_conf.rxq == 0)
4331 /* unmap the ring with vector */
4332 if (rte_intr_allow_others(intr_handle)) {
4333 vec = RTE_INTR_VEC_RXTX_OFFSET;
4334 base = RTE_INTR_VEC_RXTX_OFFSET;
4336 if (rte_intr_dp_is_en(intr_handle)) {
4337 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4338 (void)hns3_bind_ring_with_vector(hw, vec, false,
4341 if (vec < base + intr_handle->nb_efd - 1)
4345 /* Clean datapath event and queue/vec mapping */
4346 rte_intr_efd_disable(intr_handle);
4347 if (intr_handle->intr_vec) {
4348 rte_free(intr_handle->intr_vec);
4349 intr_handle->intr_vec = NULL;
4354 hns3_dev_stop(struct rte_eth_dev *dev)
4356 struct hns3_adapter *hns = dev->data->dev_private;
4357 struct hns3_hw *hw = &hns->hw;
4359 PMD_INIT_FUNC_TRACE();
4361 hw->adapter_state = HNS3_NIC_STOPPING;
4362 hns3_set_rxtx_function(dev);
4364 /* Disable datapath on secondary process. */
4365 hns3_mp_req_stop_rxtx(dev);
4366 /* Prevent crashes when queues are still in use. */
4367 rte_delay_ms(hw->tqps_num);
4369 rte_spinlock_lock(&hw->lock);
4370 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4372 hns3_dev_release_mbufs(hns);
4373 hw->adapter_state = HNS3_NIC_CONFIGURED;
4375 rte_eal_alarm_cancel(hns3_service_handler, dev);
4376 rte_spinlock_unlock(&hw->lock);
4377 hns3_unmap_rx_interrupt(dev);
4381 hns3_dev_close(struct rte_eth_dev *eth_dev)
4383 struct hns3_adapter *hns = eth_dev->data->dev_private;
4384 struct hns3_hw *hw = &hns->hw;
4386 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4387 rte_free(eth_dev->process_private);
4388 eth_dev->process_private = NULL;
4392 if (hw->adapter_state == HNS3_NIC_STARTED)
4393 hns3_dev_stop(eth_dev);
4395 hw->adapter_state = HNS3_NIC_CLOSING;
4396 hns3_reset_abort(hns);
4397 hw->adapter_state = HNS3_NIC_CLOSED;
4399 hns3_configure_all_mc_mac_addr(hns, true);
4400 hns3_remove_all_vlan_table(hns);
4401 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4402 hns3_uninit_pf(eth_dev);
4403 hns3_free_all_queues(eth_dev);
4404 rte_free(hw->reset.wait_data);
4405 rte_free(eth_dev->process_private);
4406 eth_dev->process_private = NULL;
4407 hns3_mp_uninit_primary();
4408 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4412 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4414 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4417 fc_conf->pause_time = pf->pause_time;
4419 /* return fc current mode */
4420 switch (hw->current_mode) {
4422 fc_conf->mode = RTE_FC_FULL;
4424 case HNS3_FC_TX_PAUSE:
4425 fc_conf->mode = RTE_FC_TX_PAUSE;
4427 case HNS3_FC_RX_PAUSE:
4428 fc_conf->mode = RTE_FC_RX_PAUSE;
4432 fc_conf->mode = RTE_FC_NONE;
4440 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4444 hw->requested_mode = HNS3_FC_NONE;
4446 case RTE_FC_RX_PAUSE:
4447 hw->requested_mode = HNS3_FC_RX_PAUSE;
4449 case RTE_FC_TX_PAUSE:
4450 hw->requested_mode = HNS3_FC_TX_PAUSE;
4453 hw->requested_mode = HNS3_FC_FULL;
4456 hw->requested_mode = HNS3_FC_NONE;
4457 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4458 "configured to RTE_FC_NONE", mode);
4464 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4466 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4467 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4470 if (fc_conf->high_water || fc_conf->low_water ||
4471 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4472 hns3_err(hw, "Unsupported flow control settings specified, "
4473 "high_water(%u), low_water(%u), send_xon(%u) and "
4474 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4475 fc_conf->high_water, fc_conf->low_water,
4476 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4479 if (fc_conf->autoneg) {
4480 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4483 if (!fc_conf->pause_time) {
4484 hns3_err(hw, "Invalid pause time %d setting.",
4485 fc_conf->pause_time);
4489 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4490 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4491 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4492 "current_fc_status = %d", hw->current_fc_status);
4496 hns3_get_fc_mode(hw, fc_conf->mode);
4497 if (hw->requested_mode == hw->current_mode &&
4498 pf->pause_time == fc_conf->pause_time)
4501 rte_spinlock_lock(&hw->lock);
4502 ret = hns3_fc_enable(dev, fc_conf);
4503 rte_spinlock_unlock(&hw->lock);
4509 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4510 struct rte_eth_pfc_conf *pfc_conf)
4512 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4513 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4517 if (!hns3_dev_dcb_supported(hw)) {
4518 hns3_err(hw, "This port does not support dcb configurations.");
4522 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4523 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4524 hns3_err(hw, "Unsupported flow control settings specified, "
4525 "high_water(%u), low_water(%u), send_xon(%u) and "
4526 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4527 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4528 pfc_conf->fc.send_xon,
4529 pfc_conf->fc.mac_ctrl_frame_fwd);
4532 if (pfc_conf->fc.autoneg) {
4533 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4536 if (pfc_conf->fc.pause_time == 0) {
4537 hns3_err(hw, "Invalid pause time %d setting.",
4538 pfc_conf->fc.pause_time);
4542 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4543 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4544 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4545 "current_fc_status = %d", hw->current_fc_status);
4549 priority = pfc_conf->priority;
4550 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4551 if (hw->dcb_info.pfc_en & BIT(priority) &&
4552 hw->requested_mode == hw->current_mode &&
4553 pfc_conf->fc.pause_time == pf->pause_time)
4556 rte_spinlock_lock(&hw->lock);
4557 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4558 rte_spinlock_unlock(&hw->lock);
4564 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4566 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4568 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4571 rte_spinlock_lock(&hw->lock);
4572 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4573 dcb_info->nb_tcs = pf->local_max_tc;
4575 dcb_info->nb_tcs = 1;
4577 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4578 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4579 for (i = 0; i < dcb_info->nb_tcs; i++)
4580 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4582 for (i = 0; i < hw->num_tc; i++) {
4583 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4584 dcb_info->tc_queue.tc_txq[0][i].base =
4585 hw->tc_queue[i].tqp_offset;
4586 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4587 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4588 hw->tc_queue[i].tqp_count;
4590 rte_spinlock_unlock(&hw->lock);
4596 hns3_reinit_dev(struct hns3_adapter *hns)
4598 struct hns3_hw *hw = &hns->hw;
4601 ret = hns3_cmd_init(hw);
4603 hns3_err(hw, "Failed to init cmd: %d", ret);
4607 ret = hns3_reset_all_queues(hns);
4609 hns3_err(hw, "Failed to reset all queues: %d", ret);
4613 ret = hns3_init_hardware(hns);
4615 hns3_err(hw, "Failed to init hardware: %d", ret);
4619 ret = hns3_enable_hw_error_intr(hns, true);
4621 hns3_err(hw, "fail to enable hw error interrupts: %d",
4625 hns3_info(hw, "Reset done, driver initialization finished.");
4630 hns3_uninit_umv_space(hw);
4632 hns3_cmd_uninit(hw);
4638 is_pf_reset_done(struct hns3_hw *hw)
4640 uint32_t val, reg, reg_bit;
4642 switch (hw->reset.level) {
4643 case HNS3_IMP_RESET:
4644 reg = HNS3_GLOBAL_RESET_REG;
4645 reg_bit = HNS3_IMP_RESET_BIT;
4647 case HNS3_GLOBAL_RESET:
4648 reg = HNS3_GLOBAL_RESET_REG;
4649 reg_bit = HNS3_GLOBAL_RESET_BIT;
4651 case HNS3_FUNC_RESET:
4652 reg = HNS3_FUN_RST_ING;
4653 reg_bit = HNS3_FUN_RST_ING_B;
4655 case HNS3_FLR_RESET:
4657 hns3_err(hw, "Wait for unsupported reset level: %d",
4661 val = hns3_read_dev(hw, reg);
4662 if (hns3_get_bit(val, reg_bit))
4669 hns3_is_reset_pending(struct hns3_adapter *hns)
4671 struct hns3_hw *hw = &hns->hw;
4672 enum hns3_reset_level reset;
4674 hns3_check_event_cause(hns, NULL);
4675 reset = hns3_get_reset_level(hns, &hw->reset.pending);
4676 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4677 hns3_warn(hw, "High level reset %d is pending", reset);
4680 reset = hns3_get_reset_level(hns, &hw->reset.request);
4681 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4682 hns3_warn(hw, "High level reset %d is request", reset);
4689 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4691 struct hns3_hw *hw = &hns->hw;
4692 struct hns3_wait_data *wait_data = hw->reset.wait_data;
4695 if (wait_data->result == HNS3_WAIT_SUCCESS)
4697 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4698 gettimeofday(&tv, NULL);
4699 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4700 tv.tv_sec, tv.tv_usec);
4702 } else if (wait_data->result == HNS3_WAIT_REQUEST)
4705 wait_data->hns = hns;
4706 wait_data->check_completion = is_pf_reset_done;
4707 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4708 HNS3_RESET_WAIT_MS + get_timeofday_ms();
4709 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4710 wait_data->count = HNS3_RESET_WAIT_CNT;
4711 wait_data->result = HNS3_WAIT_REQUEST;
4712 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4717 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4719 struct hns3_cmd_desc desc;
4720 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4722 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4723 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4724 req->fun_reset_vfid = func_id;
4726 return hns3_cmd_send(hw, &desc, 1);
4730 hns3_imp_reset_cmd(struct hns3_hw *hw)
4732 struct hns3_cmd_desc desc;
4734 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4735 desc.data[0] = 0xeedd;
4737 return hns3_cmd_send(hw, &desc, 1);
4741 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4743 struct hns3_hw *hw = &hns->hw;
4747 gettimeofday(&tv, NULL);
4748 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4749 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4750 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4751 tv.tv_sec, tv.tv_usec);
4755 switch (reset_level) {
4756 case HNS3_IMP_RESET:
4757 hns3_imp_reset_cmd(hw);
4758 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4759 tv.tv_sec, tv.tv_usec);
4761 case HNS3_GLOBAL_RESET:
4762 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4763 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4764 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4765 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4766 tv.tv_sec, tv.tv_usec);
4768 case HNS3_FUNC_RESET:
4769 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4770 tv.tv_sec, tv.tv_usec);
4771 /* schedule again to check later */
4772 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4773 hns3_schedule_reset(hns);
4776 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4779 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4782 static enum hns3_reset_level
4783 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4785 struct hns3_hw *hw = &hns->hw;
4786 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4788 /* Return the highest priority reset level amongst all */
4789 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4790 reset_level = HNS3_IMP_RESET;
4791 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4792 reset_level = HNS3_GLOBAL_RESET;
4793 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4794 reset_level = HNS3_FUNC_RESET;
4795 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4796 reset_level = HNS3_FLR_RESET;
4798 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4799 return HNS3_NONE_RESET;
4805 hns3_prepare_reset(struct hns3_adapter *hns)
4807 struct hns3_hw *hw = &hns->hw;
4811 switch (hw->reset.level) {
4812 case HNS3_FUNC_RESET:
4813 ret = hns3_func_reset_cmd(hw, 0);
4818 * After performaning pf reset, it is not necessary to do the
4819 * mailbox handling or send any command to firmware, because
4820 * any mailbox handling or command to firmware is only valid
4821 * after hns3_cmd_init is called.
4823 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4824 hw->reset.stats.request_cnt++;
4826 case HNS3_IMP_RESET:
4827 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4828 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4829 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4838 hns3_set_rst_done(struct hns3_hw *hw)
4840 struct hns3_pf_rst_done_cmd *req;
4841 struct hns3_cmd_desc desc;
4843 req = (struct hns3_pf_rst_done_cmd *)desc.data;
4844 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4845 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4846 return hns3_cmd_send(hw, &desc, 1);
4850 hns3_stop_service(struct hns3_adapter *hns)
4852 struct hns3_hw *hw = &hns->hw;
4853 struct rte_eth_dev *eth_dev;
4855 eth_dev = &rte_eth_devices[hw->data->port_id];
4856 if (hw->adapter_state == HNS3_NIC_STARTED)
4857 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4858 hw->mac.link_status = ETH_LINK_DOWN;
4860 hns3_set_rxtx_function(eth_dev);
4862 /* Disable datapath on secondary process. */
4863 hns3_mp_req_stop_rxtx(eth_dev);
4864 rte_delay_ms(hw->tqps_num);
4866 rte_spinlock_lock(&hw->lock);
4867 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4868 hw->adapter_state == HNS3_NIC_STOPPING) {
4870 hw->reset.mbuf_deferred_free = true;
4872 hw->reset.mbuf_deferred_free = false;
4875 * It is cumbersome for hardware to pick-and-choose entries for deletion
4876 * from table space. Hence, for function reset software intervention is
4877 * required to delete the entries
4879 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4880 hns3_configure_all_mc_mac_addr(hns, true);
4881 rte_spinlock_unlock(&hw->lock);
4887 hns3_start_service(struct hns3_adapter *hns)
4889 struct hns3_hw *hw = &hns->hw;
4890 struct rte_eth_dev *eth_dev;
4892 if (hw->reset.level == HNS3_IMP_RESET ||
4893 hw->reset.level == HNS3_GLOBAL_RESET)
4894 hns3_set_rst_done(hw);
4895 eth_dev = &rte_eth_devices[hw->data->port_id];
4896 hns3_set_rxtx_function(eth_dev);
4897 hns3_mp_req_start_rxtx(eth_dev);
4898 if (hw->adapter_state == HNS3_NIC_STARTED)
4899 hns3_service_handler(eth_dev);
4905 hns3_restore_conf(struct hns3_adapter *hns)
4907 struct hns3_hw *hw = &hns->hw;
4910 ret = hns3_configure_all_mac_addr(hns, false);
4914 ret = hns3_configure_all_mc_mac_addr(hns, false);
4918 ret = hns3_dev_promisc_restore(hns);
4922 ret = hns3_restore_vlan_table(hns);
4926 ret = hns3_restore_vlan_conf(hns);
4930 ret = hns3_restore_all_fdir_filter(hns);
4934 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4935 ret = hns3_do_start(hns, false);
4938 hns3_info(hw, "hns3 dev restart successful!");
4939 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4940 hw->adapter_state = HNS3_NIC_CONFIGURED;
4944 hns3_configure_all_mc_mac_addr(hns, true);
4946 hns3_configure_all_mac_addr(hns, true);
4951 hns3_reset_service(void *param)
4953 struct hns3_adapter *hns = (struct hns3_adapter *)param;
4954 struct hns3_hw *hw = &hns->hw;
4955 enum hns3_reset_level reset_level;
4956 struct timeval tv_delta;
4957 struct timeval tv_start;
4963 * The interrupt is not triggered within the delay time.
4964 * The interrupt may have been lost. It is necessary to handle
4965 * the interrupt to recover from the error.
4967 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4968 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4969 hns3_err(hw, "Handling interrupts in delayed tasks");
4970 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4971 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4972 if (reset_level == HNS3_NONE_RESET) {
4973 hns3_err(hw, "No reset level is set, try IMP reset");
4974 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4977 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4980 * Check if there is any ongoing reset in the hardware. This status can
4981 * be checked from reset_pending. If there is then, we need to wait for
4982 * hardware to complete reset.
4983 * a. If we are able to figure out in reasonable time that hardware
4984 * has fully resetted then, we can proceed with driver, client
4986 * b. else, we can come back later to check this status so re-sched
4989 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4990 if (reset_level != HNS3_NONE_RESET) {
4991 gettimeofday(&tv_start, NULL);
4992 ret = hns3_reset_process(hns, reset_level);
4993 gettimeofday(&tv, NULL);
4994 timersub(&tv, &tv_start, &tv_delta);
4995 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4996 tv_delta.tv_usec / USEC_PER_MSEC;
4997 if (msec > HNS3_RESET_PROCESS_MS)
4998 hns3_err(hw, "%d handle long time delta %" PRIx64
4999 " ms time=%ld.%.6ld",
5000 hw->reset.level, msec,
5001 tv.tv_sec, tv.tv_usec);
5006 /* Check if we got any *new* reset requests to be honored */
5007 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5008 if (reset_level != HNS3_NONE_RESET)
5009 hns3_msix_process(hns, reset_level);
5012 static const struct eth_dev_ops hns3_eth_dev_ops = {
5013 .dev_start = hns3_dev_start,
5014 .dev_stop = hns3_dev_stop,
5015 .dev_close = hns3_dev_close,
5016 .promiscuous_enable = hns3_dev_promiscuous_enable,
5017 .promiscuous_disable = hns3_dev_promiscuous_disable,
5018 .allmulticast_enable = hns3_dev_allmulticast_enable,
5019 .allmulticast_disable = hns3_dev_allmulticast_disable,
5020 .mtu_set = hns3_dev_mtu_set,
5021 .stats_get = hns3_stats_get,
5022 .stats_reset = hns3_stats_reset,
5023 .xstats_get = hns3_dev_xstats_get,
5024 .xstats_get_names = hns3_dev_xstats_get_names,
5025 .xstats_reset = hns3_dev_xstats_reset,
5026 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5027 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5028 .dev_infos_get = hns3_dev_infos_get,
5029 .fw_version_get = hns3_fw_version_get,
5030 .rx_queue_setup = hns3_rx_queue_setup,
5031 .tx_queue_setup = hns3_tx_queue_setup,
5032 .rx_queue_release = hns3_dev_rx_queue_release,
5033 .tx_queue_release = hns3_dev_tx_queue_release,
5034 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5035 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5036 .dev_configure = hns3_dev_configure,
5037 .flow_ctrl_get = hns3_flow_ctrl_get,
5038 .flow_ctrl_set = hns3_flow_ctrl_set,
5039 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5040 .mac_addr_add = hns3_add_mac_addr,
5041 .mac_addr_remove = hns3_remove_mac_addr,
5042 .mac_addr_set = hns3_set_default_mac_addr,
5043 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5044 .link_update = hns3_dev_link_update,
5045 .rss_hash_update = hns3_dev_rss_hash_update,
5046 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5047 .reta_update = hns3_dev_rss_reta_update,
5048 .reta_query = hns3_dev_rss_reta_query,
5049 .filter_ctrl = hns3_dev_filter_ctrl,
5050 .vlan_filter_set = hns3_vlan_filter_set,
5051 .vlan_tpid_set = hns3_vlan_tpid_set,
5052 .vlan_offload_set = hns3_vlan_offload_set,
5053 .vlan_pvid_set = hns3_vlan_pvid_set,
5054 .get_reg = hns3_get_regs,
5055 .get_dcb_info = hns3_get_dcb_info,
5056 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5059 static const struct hns3_reset_ops hns3_reset_ops = {
5060 .reset_service = hns3_reset_service,
5061 .stop_service = hns3_stop_service,
5062 .prepare_reset = hns3_prepare_reset,
5063 .wait_hardware_ready = hns3_wait_hardware_ready,
5064 .reinit_dev = hns3_reinit_dev,
5065 .restore_conf = hns3_restore_conf,
5066 .start_service = hns3_start_service,
5070 hns3_dev_init(struct rte_eth_dev *eth_dev)
5072 struct rte_device *dev = eth_dev->device;
5073 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5074 struct hns3_adapter *hns = eth_dev->data->dev_private;
5075 struct hns3_hw *hw = &hns->hw;
5076 uint16_t device_id = pci_dev->id.device_id;
5079 PMD_INIT_FUNC_TRACE();
5080 eth_dev->process_private = (struct hns3_process_private *)
5081 rte_zmalloc_socket("hns3_filter_list",
5082 sizeof(struct hns3_process_private),
5083 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5084 if (eth_dev->process_private == NULL) {
5085 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5088 /* initialize flow filter lists */
5089 hns3_filterlist_init(eth_dev);
5091 hns3_set_rxtx_function(eth_dev);
5092 eth_dev->dev_ops = &hns3_eth_dev_ops;
5093 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5094 hns3_mp_init_secondary();
5095 hw->secondary_cnt++;
5099 hns3_mp_init_primary();
5100 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5102 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5103 device_id == HNS3_DEV_ID_50GE_RDMA ||
5104 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5105 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5108 hw->data = eth_dev->data;
5111 * Set default max packet size according to the mtu
5112 * default vale in DPDK frame.
5114 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5116 ret = hns3_reset_init(hw);
5118 goto err_init_reset;
5119 hw->reset.ops = &hns3_reset_ops;
5121 ret = hns3_init_pf(eth_dev);
5123 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5127 /* Allocate memory for storing MAC addresses */
5128 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5129 sizeof(struct rte_ether_addr) *
5130 HNS3_UC_MACADDR_NUM, 0);
5131 if (eth_dev->data->mac_addrs == NULL) {
5132 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5133 "to store MAC addresses",
5134 sizeof(struct rte_ether_addr) *
5135 HNS3_UC_MACADDR_NUM);
5137 goto err_rte_zmalloc;
5140 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5141 ð_dev->data->mac_addrs[0]);
5143 hw->adapter_state = HNS3_NIC_INITIALIZED;
5145 * Pass the information to the rte_eth_dev_close() that it should also
5146 * release the private port resources.
5148 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5150 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5151 hns3_err(hw, "Reschedule reset service after dev_init");
5152 hns3_schedule_reset(hns);
5154 /* IMP will wait ready flag before reset */
5155 hns3_notify_reset_ready(hw, false);
5158 hns3_info(hw, "hns3 dev initialization successful!");
5162 hns3_uninit_pf(eth_dev);
5165 rte_free(hw->reset.wait_data);
5167 eth_dev->dev_ops = NULL;
5168 eth_dev->rx_pkt_burst = NULL;
5169 eth_dev->tx_pkt_burst = NULL;
5170 eth_dev->tx_pkt_prepare = NULL;
5171 rte_free(eth_dev->process_private);
5172 eth_dev->process_private = NULL;
5177 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5179 struct hns3_adapter *hns = eth_dev->data->dev_private;
5180 struct hns3_hw *hw = &hns->hw;
5182 PMD_INIT_FUNC_TRACE();
5184 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5187 eth_dev->dev_ops = NULL;
5188 eth_dev->rx_pkt_burst = NULL;
5189 eth_dev->tx_pkt_burst = NULL;
5190 eth_dev->tx_pkt_prepare = NULL;
5191 if (hw->adapter_state < HNS3_NIC_CLOSING)
5192 hns3_dev_close(eth_dev);
5194 hw->adapter_state = HNS3_NIC_REMOVED;
5199 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5200 struct rte_pci_device *pci_dev)
5202 return rte_eth_dev_pci_generic_probe(pci_dev,
5203 sizeof(struct hns3_adapter),
5208 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5210 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5213 static const struct rte_pci_id pci_id_hns3_map[] = {
5214 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5215 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5216 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5217 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5218 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5219 { .vendor_id = 0, /* sentinel */ },
5222 static struct rte_pci_driver rte_hns3_pmd = {
5223 .id_table = pci_id_hns3_map,
5224 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5225 .probe = eth_hns3_pci_probe,
5226 .remove = eth_hns3_pci_remove,
5229 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5230 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5231 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5233 RTE_INIT(hns3_init_log)
5235 hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5236 if (hns3_logtype_init >= 0)
5237 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5238 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5239 if (hns3_logtype_driver >= 0)
5240 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);