drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_bus_pci.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_dev.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_regs.h"
  27 #include "hns3_dcb.h"
  28
  29 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  30 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  31
  32 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  33
  34 int hns3_logtype_init;
  35 int hns3_logtype_driver;
  36
  37 static int
  38 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
  39                 unsigned int tso_mss_max)
  40 {
  41         struct hns3_cfg_tso_status_cmd *req;
  42         struct hns3_cmd_desc desc;
  43         uint16_t tso_mss;
  44
  45         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
  46
  47         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
  48
  49         tso_mss = 0;
  50         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  51                        tso_mss_min);
  52         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
  53
  54         tso_mss = 0;
  55         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  56                        tso_mss_max);
  57         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
  58
  59         return hns3_cmd_send(hw, &desc, 1);
  60 }
  61
  62 int
  63 hns3_config_gro(struct hns3_hw *hw, bool en)
  64 {
  65         struct hns3_cfg_gro_status_cmd *req;
  66         struct hns3_cmd_desc desc;
  67         int ret;
  68
  69         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
  70         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
  71
  72         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
  73
  74         ret = hns3_cmd_send(hw, &desc, 1);
  75         if (ret)
  76                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
  77
  78         return ret;
  79 }
  80
  81 static int
  82 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
  83                    uint16_t *allocated_size, bool is_alloc)
  84 {
  85         struct hns3_umv_spc_alc_cmd *req;
  86         struct hns3_cmd_desc desc;
  87         int ret;
  88
  89         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
  90         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
  91         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
  92         req->space_size = rte_cpu_to_le_32(space_size);
  93
  94         ret = hns3_cmd_send(hw, &desc, 1);
  95         if (ret) {
  96                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
  97                              is_alloc ? "allocate" : "free", ret);
  98                 return ret;
  99         }
 100
 101         if (is_alloc && allocated_size)
 102                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
 103
 104         return 0;
 105 }
 106
 107 static int
 108 hns3_init_umv_space(struct hns3_hw *hw)
 109 {
 110         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 111         struct hns3_pf *pf = &hns->pf;
 112         uint16_t allocated_size = 0;
 113         int ret;
 114
 115         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
 116                                  true);
 117         if (ret)
 118                 return ret;
 119
 120         if (allocated_size < pf->wanted_umv_size)
 121                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
 122                              pf->wanted_umv_size, allocated_size);
 123
 124         pf->max_umv_size = (!!allocated_size) ? allocated_size :
 125                                                 pf->wanted_umv_size;
 126         pf->used_umv_size = 0;
 127         return 0;
 128 }
 129
 130 static int
 131 hns3_uninit_umv_space(struct hns3_hw *hw)
 132 {
 133         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 134         struct hns3_pf *pf = &hns->pf;
 135         int ret;
 136
 137         if (pf->max_umv_size == 0)
 138                 return 0;
 139
 140         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
 141         if (ret)
 142                 return ret;
 143
 144         pf->max_umv_size = 0;
 145
 146         return 0;
 147 }
 148
 149 static bool
 150 hns3_is_umv_space_full(struct hns3_hw *hw)
 151 {
 152         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 153         struct hns3_pf *pf = &hns->pf;
 154         bool is_full;
 155
 156         is_full = (pf->used_umv_size >= pf->max_umv_size);
 157
 158         return is_full;
 159 }
 160
 161 static void
 162 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
 163 {
 164         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 165         struct hns3_pf *pf = &hns->pf;
 166
 167         if (is_free) {
 168                 if (pf->used_umv_size > 0)
 169                         pf->used_umv_size--;
 170         } else
 171                 pf->used_umv_size++;
 172 }
 173
 174 static void
 175 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
 176                       const uint8_t *addr, bool is_mc)
 177 {
 178         const unsigned char *mac_addr = addr;
 179         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
 180                             ((uint32_t)mac_addr[2] << 16) |
 181                             ((uint32_t)mac_addr[1] << 8) |
 182                             (uint32_t)mac_addr[0];
 183         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
 184
 185         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 186         if (is_mc) {
 187                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 188                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
 189                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 190         }
 191
 192         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
 193         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
 194 }
 195
 196 static int
 197 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
 198                              uint8_t resp_code,
 199                              enum hns3_mac_vlan_tbl_opcode op)
 200 {
 201         if (cmdq_resp) {
 202                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
 203                          cmdq_resp);
 204                 return -EIO;
 205         }
 206
 207         if (op == HNS3_MAC_VLAN_ADD) {
 208                 if (resp_code == 0 || resp_code == 1) {
 209                         return 0;
 210                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
 211                         hns3_err(hw, "add mac addr failed for uc_overflow");
 212                         return -ENOSPC;
 213                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
 214                         hns3_err(hw, "add mac addr failed for mc_overflow");
 215                         return -ENOSPC;
 216                 }
 217
 218                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
 219                          resp_code);
 220                 return -EIO;
 221         } else if (op == HNS3_MAC_VLAN_REMOVE) {
 222                 if (resp_code == 0) {
 223                         return 0;
 224                 } else if (resp_code == 1) {
 225                         hns3_dbg(hw, "remove mac addr failed for miss");
 226                         return -ENOENT;
 227                 }
 228
 229                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
 230                          resp_code);
 231                 return -EIO;
 232         } else if (op == HNS3_MAC_VLAN_LKUP) {
 233                 if (resp_code == 0) {
 234                         return 0;
 235                 } else if (resp_code == 1) {
 236                         hns3_dbg(hw, "lookup mac addr failed for miss");
 237                         return -ENOENT;
 238                 }
 239
 240                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
 241                          resp_code);
 242                 return -EIO;
 243         }
 244
 245         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
 246                  op);
 247
 248         return -EINVAL;
 249 }
 250
 251 static int
 252 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
 253                          struct hns3_mac_vlan_tbl_entry_cmd *req,
 254                          struct hns3_cmd_desc *desc, bool is_mc)
 255 {
 256         uint8_t resp_code;
 257         uint16_t retval;
 258         int ret;
 259
 260         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
 261         if (is_mc) {
 262                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 263                 memcpy(desc[0].data, req,
 264                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 265                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
 266                                           true);
 267                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 268                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
 269                                           true);
 270                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 271         } else {
 272                 memcpy(desc[0].data, req,
 273                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 274                 ret = hns3_cmd_send(hw, desc, 1);
 275         }
 276         if (ret) {
 277                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
 278                          ret);
 279                 return ret;
 280         }
 281         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
 282         retval = rte_le_to_cpu_16(desc[0].retval);
 283
 284         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 285                                             HNS3_MAC_VLAN_LKUP);
 286 }
 287
 288 static int
 289 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
 290                       struct hns3_mac_vlan_tbl_entry_cmd *req,
 291                       struct hns3_cmd_desc *mc_desc)
 292 {
 293         uint8_t resp_code;
 294         uint16_t retval;
 295         int cfg_status;
 296         int ret;
 297
 298         if (mc_desc == NULL) {
 299                 struct hns3_cmd_desc desc;
 300
 301                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
 302                 memcpy(desc.data, req,
 303                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 304                 ret = hns3_cmd_send(hw, &desc, 1);
 305                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 306                 retval = rte_le_to_cpu_16(desc.retval);
 307
 308                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 309                                                           HNS3_MAC_VLAN_ADD);
 310         } else {
 311                 hns3_cmd_reuse_desc(&mc_desc[0], false);
 312                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 313                 hns3_cmd_reuse_desc(&mc_desc[1], false);
 314                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 315                 hns3_cmd_reuse_desc(&mc_desc[2], false);
 316                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
 317                 memcpy(mc_desc[0].data, req,
 318                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 319                 mc_desc[0].retval = 0;
 320                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 321                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
 322                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
 323
 324                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 325                                                           HNS3_MAC_VLAN_ADD);
 326         }
 327
 328         if (ret) {
 329                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
 330                 return ret;
 331         }
 332
 333         return cfg_status;
 334 }
 335
 336 static int
 337 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
 338                          struct hns3_mac_vlan_tbl_entry_cmd *req)
 339 {
 340         struct hns3_cmd_desc desc;
 341         uint8_t resp_code;
 342         uint16_t retval;
 343         int ret;
 344
 345         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
 346
 347         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 348
 349         ret = hns3_cmd_send(hw, &desc, 1);
 350         if (ret) {
 351                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
 352                 return ret;
 353         }
 354         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 355         retval = rte_le_to_cpu_16(desc.retval);
 356
 357         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 358                                             HNS3_MAC_VLAN_REMOVE);
 359 }
 360
 361 static int
 362 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 363 {
 364         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 365         struct hns3_mac_vlan_tbl_entry_cmd req;
 366         struct hns3_pf *pf = &hns->pf;
 367         struct hns3_cmd_desc desc;
 368         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 369         uint16_t egress_port = 0;
 370         uint8_t vf_id;
 371         int ret;
 372
 373         /* check if mac addr is valid */
 374         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 375                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 376                                       mac_addr);
 377                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
 378                          mac_str);
 379                 return -EINVAL;
 380         }
 381
 382         memset(&req, 0, sizeof(req));
 383
 384         /*
 385          * In current version VF is not supported when PF is driven by DPDK
 386          * driver, the PF-related vf_id is 0, just need to configure parameters
 387          * for vf_id 0.
 388          */
 389         vf_id = 0;
 390         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
 391                        HNS3_MAC_EPORT_VFID_S, vf_id);
 392
 393         req.egress_port = rte_cpu_to_le_16(egress_port);
 394
 395         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 396
 397         /*
 398          * Lookup the mac address in the mac_vlan table, and add
 399          * it if the entry is inexistent. Repeated unicast entry
 400          * is not allowed in the mac vlan table.
 401          */
 402         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
 403         if (ret == -ENOENT) {
 404                 if (!hns3_is_umv_space_full(hw)) {
 405                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
 406                         if (!ret)
 407                                 hns3_update_umv_space(hw, false);
 408                         return ret;
 409                 }
 410
 411                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
 412
 413                 return -ENOSPC;
 414         }
 415
 416         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
 417
 418         /* check if we just hit the duplicate */
 419         if (ret == 0) {
 420                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
 421                 return 0;
 422         }
 423
 424         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
 425                  mac_str);
 426
 427         return ret;
 428 }
 429
 430 static int
 431 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 432                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
 433 {
 434         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 435         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 436         int ret;
 437
 438         rte_spinlock_lock(&hw->lock);
 439         ret = hns3_add_uc_addr_common(hw, mac_addr);
 440         if (ret) {
 441                 rte_spinlock_unlock(&hw->lock);
 442                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 443                                       mac_addr);
 444                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
 445                 return ret;
 446         }
 447
 448         if (idx == 0)
 449                 hw->mac.default_addr_setted = true;
 450         rte_spinlock_unlock(&hw->lock);
 451
 452         return ret;
 453 }
 454
 455 static int
 456 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 457 {
 458         struct hns3_mac_vlan_tbl_entry_cmd req;
 459         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 460         int ret;
 461
 462         /* check if mac addr is valid */
 463         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 464                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 465                                       mac_addr);
 466                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
 467                          mac_str);
 468                 return -EINVAL;
 469         }
 470
 471         memset(&req, 0, sizeof(req));
 472         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 473         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 474         ret = hns3_remove_mac_vlan_tbl(hw, &req);
 475         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
 476                 return 0;
 477         else if (ret == 0)
 478                 hns3_update_umv_space(hw, true);
 479
 480         return ret;
 481 }
 482
 483 static void
 484 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 485 {
 486         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 487         /* index will be checked by upper level rte interface */
 488         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 489         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 490         int ret;
 491
 492         rte_spinlock_lock(&hw->lock);
 493         ret = hns3_remove_uc_addr_common(hw, mac_addr);
 494         if (ret) {
 495                 rte_spinlock_unlock(&hw->lock);
 496                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 497                                       mac_addr);
 498                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
 499                 return;
 500         }
 501
 502         if (idx == 0)
 503                 hw->mac.default_addr_setted = false;
 504         rte_spinlock_unlock(&hw->lock);
 505 }
 506
 507 static int
 508 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
 509                           struct rte_ether_addr *mac_addr)
 510 {
 511         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 512         struct rte_ether_addr *oaddr;
 513         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 514         bool default_addr_setted;
 515         bool rm_succes = false;
 516         int ret, ret_val;
 517
 518         /* check if mac addr is valid */
 519         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 520                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 521                                       mac_addr);
 522                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
 523                          mac_str);
 524                 return -EINVAL;
 525         }
 526
 527         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
 528         default_addr_setted = hw->mac.default_addr_setted;
 529         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
 530                 return 0;
 531
 532         rte_spinlock_lock(&hw->lock);
 533         if (default_addr_setted) {
 534                 ret = hns3_remove_uc_addr_common(hw, oaddr);
 535                 if (ret) {
 536                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 537                                               oaddr);
 538                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
 539                                   mac_str, ret);
 540                         rm_succes = false;
 541                 } else
 542                         rm_succes = true;
 543         }
 544
 545         ret = hns3_add_uc_addr_common(hw, mac_addr);
 546         if (ret) {
 547                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 548                                       mac_addr);
 549                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
 550                 goto err_add_uc_addr;
 551         }
 552
 553         rte_ether_addr_copy(mac_addr,
 554                             (struct rte_ether_addr *)hw->mac.mac_addr);
 555         hw->mac.default_addr_setted = true;
 556         rte_spinlock_unlock(&hw->lock);
 557
 558         return 0;
 559
 560 err_add_uc_addr:
 561         if (rm_succes) {
 562                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
 563                 if (ret_val) {
 564                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 565                                               oaddr);
 566                         hns3_warn(hw,
 567                                   "Failed to restore old uc mac addr(%s): %d",
 568                                   mac_str, ret_val);
 569                         hw->mac.default_addr_setted = false;
 570                 }
 571         }
 572         rte_spinlock_unlock(&hw->lock);
 573
 574         return ret;
 575 }
 576
 577 static void
 578 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
 579 {
 580 #define HNS3_VF_NUM_IN_FIRST_DESC 192
 581         uint8_t word_num;
 582         uint8_t bit_num;
 583
 584         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
 585                 word_num = vfid / 32;
 586                 bit_num = vfid % 32;
 587                 if (clr)
 588                         desc[1].data[word_num] &=
 589                             rte_cpu_to_le_32(~(1UL << bit_num));
 590                 else
 591                         desc[1].data[word_num] |=
 592                             rte_cpu_to_le_32(1UL << bit_num);
 593         } else {
 594                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
 595                 bit_num = vfid % 32;
 596                 if (clr)
 597                         desc[2].data[word_num] &=
 598                             rte_cpu_to_le_32(~(1UL << bit_num));
 599                 else
 600                         desc[2].data[word_num] |=
 601                             rte_cpu_to_le_32(1UL << bit_num);
 602         }
 603 }
 604
 605 static int
 606 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 607 {
 608         struct hns3_mac_vlan_tbl_entry_cmd req;
 609         struct hns3_cmd_desc desc[3];
 610         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 611         uint8_t vf_id;
 612         int ret;
 613
 614         /* Check if mac addr is valid */
 615         if (!rte_is_multicast_ether_addr(mac_addr)) {
 616                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 617                                       mac_addr);
 618                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
 619                          mac_str);
 620                 return -EINVAL;
 621         }
 622
 623         memset(&req, 0, sizeof(req));
 624         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 625         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 626         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 627         if (ret) {
 628                 /* This mac addr do not exist, add new entry for it */
 629                 memset(desc[0].data, 0, sizeof(desc[0].data));
 630                 memset(desc[1].data, 0, sizeof(desc[0].data));
 631                 memset(desc[2].data, 0, sizeof(desc[0].data));
 632         }
 633
 634         /*
 635          * In current version VF is not supported when PF is driven by DPDK
 636          * driver, the PF-related vf_id is 0, just need to configure parameters
 637          * for vf_id 0.
 638          */
 639         vf_id = 0;
 640         hns3_update_desc_vfid(desc, vf_id, false);
 641         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
 642         if (ret) {
 643                 if (ret == -ENOSPC)
 644                         hns3_err(hw, "mc mac vlan table is full");
 645                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 646                                       mac_addr);
 647                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
 648         }
 649
 650         return ret;
 651 }
 652
 653 static int
 654 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 655 {
 656         struct hns3_mac_vlan_tbl_entry_cmd req;
 657         struct hns3_cmd_desc desc[3];
 658         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 659         uint8_t vf_id;
 660         int ret;
 661
 662         /* Check if mac addr is valid */
 663         if (!rte_is_multicast_ether_addr(mac_addr)) {
 664                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 665                                       mac_addr);
 666                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
 667                          mac_str);
 668                 return -EINVAL;
 669         }
 670
 671         memset(&req, 0, sizeof(req));
 672         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 673         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 674         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 675         if (ret == 0) {
 676                 /*
 677                  * This mac addr exist, remove this handle's VFID for it.
 678                  * In current version VF is not supported when PF is driven by
 679                  * DPDK driver, the PF-related vf_id is 0, just need to
 680                  * configure parameters for vf_id 0.
 681                  */
 682                 vf_id = 0;
 683                 hns3_update_desc_vfid(desc, vf_id, true);
 684
 685                 /* All the vfid is zero, so need to delete this entry */
 686                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
 687         } else if (ret == -ENOENT) {
 688                 /* This mac addr doesn't exist. */
 689                 return 0;
 690         }
 691
 692         if (ret) {
 693                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 694                                       mac_addr);
 695                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
 696         }
 697
 698         return ret;
 699 }
 700
 701 static int
 702 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
 703                            struct rte_ether_addr *mc_addr_set,
 704                            uint32_t nb_mc_addr)
 705 {
 706         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 707         struct rte_ether_addr *addr;
 708         uint32_t i;
 709         uint32_t j;
 710
 711         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 712                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 713                          "invalid. valid range: 0~%d",
 714                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 715                 return -EINVAL;
 716         }
 717
 718         /* Check if input mac addresses are valid */
 719         for (i = 0; i < nb_mc_addr; i++) {
 720                 addr = &mc_addr_set[i];
 721                 if (!rte_is_multicast_ether_addr(addr)) {
 722                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 723                                               addr);
 724                         hns3_err(hw,
 725                                  "Failed to set mc mac addr, addr(%s) invalid.",
 726                                  mac_str);
 727                         return -EINVAL;
 728                 }
 729
 730                 /* Check if there are duplicate addresses */
 731                 for (j = i + 1; j < nb_mc_addr; j++) {
 732                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 733                                 rte_ether_format_addr(mac_str,
 734                                                       RTE_ETHER_ADDR_FMT_SIZE,
 735                                                       addr);
 736                                 hns3_err(hw, "Failed to set mc mac addr, "
 737                                          "addrs invalid. two same addrs(%s).",
 738                                          mac_str);
 739                                 return -EINVAL;
 740                         }
 741                 }
 742         }
 743
 744         return 0;
 745 }
 746
 747 static void
 748 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
 749                            struct rte_ether_addr *mc_addr_set,
 750                            int mc_addr_num,
 751                            struct rte_ether_addr *reserved_addr_list,
 752                            int *reserved_addr_num,
 753                            struct rte_ether_addr *add_addr_list,
 754                            int *add_addr_num,
 755                            struct rte_ether_addr *rm_addr_list,
 756                            int *rm_addr_num)
 757 {
 758         struct rte_ether_addr *addr;
 759         int current_addr_num;
 760         int reserved_num = 0;
 761         int add_num = 0;
 762         int rm_num = 0;
 763         int num;
 764         int i;
 765         int j;
 766         bool same_addr;
 767
 768         /* Calculate the mc mac address list that should be removed */
 769         current_addr_num = hw->mc_addrs_num;
 770         for (i = 0; i < current_addr_num; i++) {
 771                 addr = &hw->mc_addrs[i];
 772                 same_addr = false;
 773                 for (j = 0; j < mc_addr_num; j++) {
 774                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 775                                 same_addr = true;
 776                                 break;
 777                         }
 778                 }
 779
 780                 if (!same_addr) {
 781                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
 782                         rm_num++;
 783                 } else {
 784                         rte_ether_addr_copy(addr,
 785                                             &reserved_addr_list[reserved_num]);
 786                         reserved_num++;
 787                 }
 788         }
 789
 790         /* Calculate the mc mac address list that should be added */
 791         for (i = 0; i < mc_addr_num; i++) {
 792                 addr = &mc_addr_set[i];
 793                 same_addr = false;
 794                 for (j = 0; j < current_addr_num; j++) {
 795                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
 796                                 same_addr = true;
 797                                 break;
 798                         }
 799                 }
 800
 801                 if (!same_addr) {
 802                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
 803                         add_num++;
 804                 }
 805         }
 806
 807         /* Reorder the mc mac address list maintained by driver */
 808         for (i = 0; i < reserved_num; i++)
 809                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
 810
 811         for (i = 0; i < rm_num; i++) {
 812                 num = reserved_num + i;
 813                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
 814         }
 815
 816         *reserved_addr_num = reserved_num;
 817         *add_addr_num = add_num;
 818         *rm_addr_num = rm_num;
 819 }
 820
 821 static int
 822 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 823                           struct rte_ether_addr *mc_addr_set,
 824                           uint32_t nb_mc_addr)
 825 {
 826         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 827         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
 828         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
 829         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
 830         struct rte_ether_addr *addr;
 831         int reserved_addr_num;
 832         int add_addr_num;
 833         int rm_addr_num;
 834         int mc_addr_num;
 835         int num;
 836         int ret;
 837         int i;
 838
 839         /* Check if input parameters are valid */
 840         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 841         if (ret)
 842                 return ret;
 843
 844         rte_spinlock_lock(&hw->lock);
 845
 846         /*
 847          * Calculate the mc mac address lists those should be removed and be
 848          * added, Reorder the mc mac address list maintained by driver.
 849          */
 850         mc_addr_num = (int)nb_mc_addr;
 851         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
 852                                    reserved_addr_list, &reserved_addr_num,
 853                                    add_addr_list, &add_addr_num,
 854                                    rm_addr_list, &rm_addr_num);
 855
 856         /* Remove mc mac addresses */
 857         for (i = 0; i < rm_addr_num; i++) {
 858                 num = rm_addr_num - i - 1;
 859                 addr = &rm_addr_list[num];
 860                 ret = hns3_remove_mc_addr(hw, addr);
 861                 if (ret) {
 862                         rte_spinlock_unlock(&hw->lock);
 863                         return ret;
 864                 }
 865                 hw->mc_addrs_num--;
 866         }
 867
 868         /* Add mc mac addresses */
 869         for (i = 0; i < add_addr_num; i++) {
 870                 addr = &add_addr_list[i];
 871                 ret = hns3_add_mc_addr(hw, addr);
 872                 if (ret) {
 873                         rte_spinlock_unlock(&hw->lock);
 874                         return ret;
 875                 }
 876
 877                 num = reserved_addr_num + i;
 878                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
 879                 hw->mc_addrs_num++;
 880         }
 881         rte_spinlock_unlock(&hw->lock);
 882
 883         return 0;
 884 }
 885
 886 static int
 887 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 888 {
 889         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 890         struct hns3_hw *hw = &hns->hw;
 891         struct rte_ether_addr *addr;
 892         int err = 0;
 893         int ret;
 894         int i;
 895
 896         for (i = 0; i < hw->mc_addrs_num; i++) {
 897                 addr = &hw->mc_addrs[i];
 898                 if (!rte_is_multicast_ether_addr(addr))
 899                         continue;
 900                 if (del)
 901                         ret = hns3_remove_mc_addr(hw, addr);
 902                 else
 903                         ret = hns3_add_mc_addr(hw, addr);
 904                 if (ret) {
 905                         err = ret;
 906                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 907                                               addr);
 908                         hns3_dbg(hw, "%s mc mac addr: %s failed",
 909                                  del ? "Remove" : "Restore", mac_str);
 910                 }
 911         }
 912         return err;
 913 }
 914
 915 static int
 916 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
 917 {
 918         struct hns3_config_max_frm_size_cmd *req;
 919         struct hns3_cmd_desc desc;
 920
 921         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
 922
 923         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
 924         req->max_frm_size = rte_cpu_to_le_16(new_mps);
 925         req->min_frm_size = HNS3_MIN_FRAME_LEN;
 926
 927         return hns3_cmd_send(hw, &desc, 1);
 928 }
 929
 930 static int
 931 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
 932 {
 933         int ret;
 934
 935         ret = hns3_set_mac_mtu(hw, mps);
 936         if (ret) {
 937                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
 938                 return ret;
 939         }
 940
 941         ret = hns3_buffer_alloc(hw);
 942         if (ret) {
 943                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
 944                 return ret;
 945         }
 946
 947         return 0;
 948 }
 949
 950 static int
 951 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 952 {
 953         struct hns3_adapter *hns = dev->data->dev_private;
 954         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 955         struct hns3_hw *hw = &hns->hw;
 956         bool is_jumbo_frame;
 957         int ret;
 958
 959         if (dev->data->dev_started) {
 960                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
 961                          "before configuration", dev->data->port_id);
 962                 return -EBUSY;
 963         }
 964
 965         rte_spinlock_lock(&hw->lock);
 966         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
 967         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
 968
 969         /*
 970          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
 971          * assign to "uint16_t" type variable.
 972          */
 973         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
 974         if (ret) {
 975                 rte_spinlock_unlock(&hw->lock);
 976                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
 977                          dev->data->port_id, mtu, ret);
 978                 return ret;
 979         }
 980         hns->pf.mps = (uint16_t)frame_size;
 981         if (is_jumbo_frame)
 982                 dev->data->dev_conf.rxmode.offloads |=
 983                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 984         else
 985                 dev->data->dev_conf.rxmode.offloads &=
 986                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 987         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 988         rte_spinlock_unlock(&hw->lock);
 989
 990         return 0;
 991 }
 992
 993 static int
 994 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 995 {
 996         struct hns3_adapter *hns = eth_dev->data->dev_private;
 997         struct hns3_hw *hw = &hns->hw;
 998
 999         info->max_rx_queues = hw->tqps_num;
1000         info->max_tx_queues = hw->tqps_num;
1001         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
1002         info->min_rx_bufsize = hw->rx_buf_len;
1003         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
1004         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
1005         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1006                                  DEV_RX_OFFLOAD_TCP_CKSUM |
1007                                  DEV_RX_OFFLOAD_UDP_CKSUM |
1008                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
1009                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1010                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1011                                  DEV_RX_OFFLOAD_KEEP_CRC |
1012                                  DEV_RX_OFFLOAD_SCATTER |
1013                                  DEV_RX_OFFLOAD_VLAN_STRIP |
1014                                  DEV_RX_OFFLOAD_QINQ_STRIP |
1015                                  DEV_RX_OFFLOAD_VLAN_FILTER |
1016                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
1017                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
1018         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1019         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1020                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
1021                                  DEV_TX_OFFLOAD_TCP_CKSUM |
1022                                  DEV_TX_OFFLOAD_UDP_CKSUM |
1023                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
1024                                  DEV_TX_OFFLOAD_VLAN_INSERT |
1025                                  DEV_TX_OFFLOAD_QINQ_INSERT |
1026                                  DEV_TX_OFFLOAD_MULTI_SEGS |
1027                                  info->tx_queue_offload_capa);
1028
1029         info->vmdq_queue_num = 0;
1030
1031         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1032         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1033         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1034
1035         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1036         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1037         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1038         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1039
1040         return 0;
1041 }
1042
1043 static int
1044 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1045                     size_t fw_size)
1046 {
1047         struct hns3_adapter *hns = eth_dev->data->dev_private;
1048         struct hns3_hw *hw = &hns->hw;
1049         int ret;
1050
1051         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
1052         ret += 1; /* add the size of '\0' */
1053         if (fw_size < (uint32_t)ret)
1054                 return ret;
1055         else
1056                 return 0;
1057 }
1058
1059 static int
1060 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
1061                      __rte_unused int wait_to_complete)
1062 {
1063         struct hns3_adapter *hns = eth_dev->data->dev_private;
1064         struct hns3_hw *hw = &hns->hw;
1065         struct hns3_mac *mac = &hw->mac;
1066         struct rte_eth_link new_link;
1067
1068         memset(&new_link, 0, sizeof(new_link));
1069         switch (mac->link_speed) {
1070         case ETH_SPEED_NUM_10M:
1071         case ETH_SPEED_NUM_100M:
1072         case ETH_SPEED_NUM_1G:
1073         case ETH_SPEED_NUM_10G:
1074         case ETH_SPEED_NUM_25G:
1075         case ETH_SPEED_NUM_40G:
1076         case ETH_SPEED_NUM_50G:
1077         case ETH_SPEED_NUM_100G:
1078                 new_link.link_speed = mac->link_speed;
1079                 break;
1080         default:
1081                 new_link.link_speed = ETH_SPEED_NUM_100M;
1082                 break;
1083         }
1084
1085         new_link.link_duplex = mac->link_duplex;
1086         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1087         new_link.link_autoneg =
1088             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1089
1090         return rte_eth_linkstatus_set(eth_dev, &new_link);
1091 }
1092
1093 static int
1094 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
1095 {
1096         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1097         struct hns3_pf *pf = &hns->pf;
1098
1099         if (!(status->pf_state & HNS3_PF_STATE_DONE))
1100                 return -EINVAL;
1101
1102         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
1103
1104         return 0;
1105 }
1106
1107 static int
1108 hns3_query_function_status(struct hns3_hw *hw)
1109 {
1110 #define HNS3_QUERY_MAX_CNT              10
1111 #define HNS3_QUERY_SLEEP_MSCOEND        1
1112         struct hns3_func_status_cmd *req;
1113         struct hns3_cmd_desc desc;
1114         int timeout = 0;
1115         int ret;
1116
1117         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
1118         req = (struct hns3_func_status_cmd *)desc.data;
1119
1120         do {
1121                 ret = hns3_cmd_send(hw, &desc, 1);
1122                 if (ret) {
1123                         PMD_INIT_LOG(ERR, "query function status failed %d",
1124                                      ret);
1125                         return ret;
1126                 }
1127
1128                 /* Check pf reset is done */
1129                 if (req->pf_state)
1130                         break;
1131
1132                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
1133         } while (timeout++ < HNS3_QUERY_MAX_CNT);
1134
1135         return hns3_parse_func_status(hw, req);
1136 }
1137
1138 static int
1139 hns3_query_pf_resource(struct hns3_hw *hw)
1140 {
1141         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1142         struct hns3_pf *pf = &hns->pf;
1143         struct hns3_pf_res_cmd *req;
1144         struct hns3_cmd_desc desc;
1145         int ret;
1146
1147         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
1148         ret = hns3_cmd_send(hw, &desc, 1);
1149         if (ret) {
1150                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
1151                 return ret;
1152         }
1153
1154         req = (struct hns3_pf_res_cmd *)desc.data;
1155         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
1156         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
1157         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1158
1159         if (req->tx_buf_size)
1160                 pf->tx_buf_size =
1161                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
1162         else
1163                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
1164
1165         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
1166
1167         if (req->dv_buf_size)
1168                 pf->dv_buf_size =
1169                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
1170         else
1171                 pf->dv_buf_size = HNS3_DEFAULT_DV;
1172
1173         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
1174
1175         hw->num_msi =
1176             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
1177                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
1178
1179         return 0;
1180 }
1181
1182 static void
1183 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
1184 {
1185         struct hns3_cfg_param_cmd *req;
1186         uint64_t mac_addr_tmp_high;
1187         uint64_t mac_addr_tmp;
1188         uint32_t i;
1189
1190         req = (struct hns3_cfg_param_cmd *)desc[0].data;
1191
1192         /* get the configuration */
1193         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1194                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
1195         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1196                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
1197         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1198                                            HNS3_CFG_TQP_DESC_N_M,
1199                                            HNS3_CFG_TQP_DESC_N_S);
1200
1201         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1202                                        HNS3_CFG_PHY_ADDR_M,
1203                                        HNS3_CFG_PHY_ADDR_S);
1204         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1205                                          HNS3_CFG_MEDIA_TP_M,
1206                                          HNS3_CFG_MEDIA_TP_S);
1207         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1208                                          HNS3_CFG_RX_BUF_LEN_M,
1209                                          HNS3_CFG_RX_BUF_LEN_S);
1210         /* get mac address */
1211         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
1212         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1213                                            HNS3_CFG_MAC_ADDR_H_M,
1214                                            HNS3_CFG_MAC_ADDR_H_S);
1215
1216         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1217
1218         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1219                                             HNS3_CFG_DEFAULT_SPEED_M,
1220                                             HNS3_CFG_DEFAULT_SPEED_S);
1221         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1222                                            HNS3_CFG_RSS_SIZE_M,
1223                                            HNS3_CFG_RSS_SIZE_S);
1224
1225         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
1226                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1227
1228         req = (struct hns3_cfg_param_cmd *)desc[1].data;
1229         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
1230
1231         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1232                                             HNS3_CFG_SPEED_ABILITY_M,
1233                                             HNS3_CFG_SPEED_ABILITY_S);
1234         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1235                                         HNS3_CFG_UMV_TBL_SPACE_M,
1236                                         HNS3_CFG_UMV_TBL_SPACE_S);
1237         if (!cfg->umv_space)
1238                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
1239 }
1240
1241 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
1242  * @hw: pointer to struct hns3_hw
1243  * @hcfg: the config structure to be getted
1244  */
1245 static int
1246 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
1247 {
1248         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
1249         struct hns3_cfg_param_cmd *req;
1250         uint32_t offset;
1251         uint32_t i;
1252         int ret;
1253
1254         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
1255                 offset = 0;
1256                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
1257                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
1258                                           true);
1259                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
1260                                i * HNS3_CFG_RD_LEN_BYTES);
1261                 /* Len should be divided by 4 when send to hardware */
1262                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
1263                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
1264                 req->offset = rte_cpu_to_le_32(offset);
1265         }
1266
1267         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
1268         if (ret) {
1269                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
1270                 return ret;
1271         }
1272
1273         hns3_parse_cfg(hcfg, desc);
1274
1275         return 0;
1276 }
1277
1278 static int
1279 hns3_parse_speed(int speed_cmd, uint32_t *speed)
1280 {
1281         switch (speed_cmd) {
1282         case HNS3_CFG_SPEED_10M:
1283                 *speed = ETH_SPEED_NUM_10M;
1284                 break;
1285         case HNS3_CFG_SPEED_100M:
1286                 *speed = ETH_SPEED_NUM_100M;
1287                 break;
1288         case HNS3_CFG_SPEED_1G:
1289                 *speed = ETH_SPEED_NUM_1G;
1290                 break;
1291         case HNS3_CFG_SPEED_10G:
1292                 *speed = ETH_SPEED_NUM_10G;
1293                 break;
1294         case HNS3_CFG_SPEED_25G:
1295                 *speed = ETH_SPEED_NUM_25G;
1296                 break;
1297         case HNS3_CFG_SPEED_40G:
1298                 *speed = ETH_SPEED_NUM_40G;
1299                 break;
1300         case HNS3_CFG_SPEED_50G:
1301                 *speed = ETH_SPEED_NUM_50G;
1302                 break;
1303         case HNS3_CFG_SPEED_100G:
1304                 *speed = ETH_SPEED_NUM_100G;
1305                 break;
1306         default:
1307                 return -EINVAL;
1308         }
1309
1310         return 0;
1311 }
1312
1313 static int
1314 hns3_get_board_configuration(struct hns3_hw *hw)
1315 {
1316         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1317         struct hns3_pf *pf = &hns->pf;
1318         struct hns3_cfg cfg;
1319         int ret;
1320
1321         ret = hns3_get_board_cfg(hw, &cfg);
1322         if (ret) {
1323                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
1324                 return ret;
1325         }
1326
1327         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
1328                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
1329                 return -EOPNOTSUPP;
1330         }
1331
1332         hw->mac.media_type = cfg.media_type;
1333         hw->rss_size_max = cfg.rss_size_max;
1334         hw->rx_buf_len = cfg.rx_buf_len;
1335         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
1336         hw->mac.phy_addr = cfg.phy_addr;
1337         hw->mac.default_addr_setted = false;
1338         hw->num_tx_desc = cfg.tqp_desc_num;
1339         hw->num_rx_desc = cfg.tqp_desc_num;
1340         hw->dcb_info.num_pg = 1;
1341         hw->dcb_info.hw_pfc_map = 0;
1342
1343         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
1344         if (ret) {
1345                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
1346                              cfg.default_speed, ret);
1347                 return ret;
1348         }
1349
1350         pf->tc_max = cfg.tc_num;
1351         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
1352                 PMD_INIT_LOG(WARNING,
1353                              "Get TC num(%u) from flash, set TC num to 1",
1354                              pf->tc_max);
1355                 pf->tc_max = 1;
1356         }
1357
1358         /* Dev does not support DCB */
1359         if (!hns3_dev_dcb_supported(hw)) {
1360                 pf->tc_max = 1;
1361                 pf->pfc_max = 0;
1362         } else
1363                 pf->pfc_max = pf->tc_max;
1364
1365         hw->dcb_info.num_tc = 1;
1366         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
1367                                      hw->tqps_num / hw->dcb_info.num_tc);
1368         hns3_set_bit(hw->hw_tc_map, 0, 1);
1369         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
1370
1371         pf->wanted_umv_size = cfg.umv_space;
1372
1373         return ret;
1374 }
1375
1376 static int
1377 hns3_get_configuration(struct hns3_hw *hw)
1378 {
1379         int ret;
1380
1381         ret = hns3_query_function_status(hw);
1382         if (ret) {
1383                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
1384                 return ret;
1385         }
1386
1387         /* Get pf resource */
1388         ret = hns3_query_pf_resource(hw);
1389         if (ret) {
1390                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
1391                 return ret;
1392         }
1393
1394         ret = hns3_get_board_configuration(hw);
1395         if (ret) {
1396                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
1397                 return ret;
1398         }
1399
1400         return 0;
1401 }
1402
1403 static int
1404 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
1405                       uint16_t tqp_vid, bool is_pf)
1406 {
1407         struct hns3_tqp_map_cmd *req;
1408         struct hns3_cmd_desc desc;
1409         int ret;
1410
1411         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
1412
1413         req = (struct hns3_tqp_map_cmd *)desc.data;
1414         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
1415         req->tqp_vf = func_id;
1416         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
1417         if (!is_pf)
1418                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
1419         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
1420
1421         ret = hns3_cmd_send(hw, &desc, 1);
1422         if (ret)
1423                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
1424
1425         return ret;
1426 }
1427
1428 static int
1429 hns3_map_tqp(struct hns3_hw *hw)
1430 {
1431         uint16_t tqps_num = hw->total_tqps_num;
1432         uint16_t func_id;
1433         uint16_t tqp_id;
1434         int num;
1435         int ret;
1436         int i;
1437
1438         /*
1439          * In current version VF is not supported when PF is driven by DPDK
1440          * driver, so we allocate tqps to PF as much as possible.
1441          */
1442         tqp_id = 0;
1443         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1444         for (func_id = 0; func_id < num; func_id++) {
1445                 for (i = 0;
1446                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
1447                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
1448                                                     true);
1449                         if (ret)
1450                                 return ret;
1451                 }
1452         }
1453
1454         return 0;
1455 }
1456
1457 static int
1458 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
1459 {
1460         struct hns3_config_mac_speed_dup_cmd *req;
1461         struct hns3_cmd_desc desc;
1462         int ret;
1463
1464         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
1465
1466         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
1467
1468         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
1469
1470         switch (speed) {
1471         case ETH_SPEED_NUM_10M:
1472                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1473                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
1474                 break;
1475         case ETH_SPEED_NUM_100M:
1476                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1477                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
1478                 break;
1479         case ETH_SPEED_NUM_1G:
1480                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1481                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
1482                 break;
1483         case ETH_SPEED_NUM_10G:
1484                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1485                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
1486                 break;
1487         case ETH_SPEED_NUM_25G:
1488                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1489                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
1490                 break;
1491         case ETH_SPEED_NUM_40G:
1492                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1493                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
1494                 break;
1495         case ETH_SPEED_NUM_50G:
1496                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1497                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
1498                 break;
1499         case ETH_SPEED_NUM_100G:
1500                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1501                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
1502                 break;
1503         default:
1504                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
1505                 return -EINVAL;
1506         }
1507
1508         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
1509
1510         ret = hns3_cmd_send(hw, &desc, 1);
1511         if (ret)
1512                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
1513
1514         return ret;
1515 }
1516
1517 static int
1518 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1519 {
1520         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1521         struct hns3_pf *pf = &hns->pf;
1522         struct hns3_priv_buf *priv;
1523         uint32_t i, total_size;
1524
1525         total_size = pf->pkt_buf_size;
1526
1527         /* alloc tx buffer for all enabled tc */
1528         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1529                 priv = &buf_alloc->priv_buf[i];
1530
1531                 if (hw->hw_tc_map & BIT(i)) {
1532                         if (total_size < pf->tx_buf_size)
1533                                 return -ENOMEM;
1534
1535                         priv->tx_buf_size = pf->tx_buf_size;
1536                 } else
1537                         priv->tx_buf_size = 0;
1538
1539                 total_size -= priv->tx_buf_size;
1540         }
1541
1542         return 0;
1543 }
1544
1545 static int
1546 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1547 {
1548 /* TX buffer size is unit by 128 byte */
1549 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
1550 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
1551         struct hns3_tx_buff_alloc_cmd *req;
1552         struct hns3_cmd_desc desc;
1553         uint32_t buf_size;
1554         uint32_t i;
1555         int ret;
1556
1557         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
1558
1559         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
1560         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1561                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1562
1563                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
1564                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
1565                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
1566         }
1567
1568         ret = hns3_cmd_send(hw, &desc, 1);
1569         if (ret)
1570                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
1571
1572         return ret;
1573 }
1574
1575 static int
1576 hns3_get_tc_num(struct hns3_hw *hw)
1577 {
1578         int cnt = 0;
1579         uint8_t i;
1580
1581         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1582                 if (hw->hw_tc_map & BIT(i))
1583                         cnt++;
1584         return cnt;
1585 }
1586
1587 static uint32_t
1588 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1589 {
1590         struct hns3_priv_buf *priv;
1591         uint32_t rx_priv = 0;
1592         int i;
1593
1594         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1595                 priv = &buf_alloc->priv_buf[i];
1596                 if (priv->enable)
1597                         rx_priv += priv->buf_size;
1598         }
1599         return rx_priv;
1600 }
1601
1602 static uint32_t
1603 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1604 {
1605         uint32_t total_tx_size = 0;
1606         uint32_t i;
1607
1608         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1609                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1610
1611         return total_tx_size;
1612 }
1613
1614 /* Get the number of pfc enabled TCs, which have private buffer */
1615 static int
1616 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1617 {
1618         struct hns3_priv_buf *priv;
1619         int cnt = 0;
1620         uint8_t i;
1621
1622         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1623                 priv = &buf_alloc->priv_buf[i];
1624                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1625                         cnt++;
1626         }
1627
1628         return cnt;
1629 }
1630
1631 /* Get the number of pfc disabled TCs, which have private buffer */
1632 static int
1633 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
1634                          struct hns3_pkt_buf_alloc *buf_alloc)
1635 {
1636         struct hns3_priv_buf *priv;
1637         int cnt = 0;
1638         uint8_t i;
1639
1640         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1641                 priv = &buf_alloc->priv_buf[i];
1642                 if (hw->hw_tc_map & BIT(i) &&
1643                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1644                         cnt++;
1645         }
1646
1647         return cnt;
1648 }
1649
1650 static bool
1651 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
1652                   uint32_t rx_all)
1653 {
1654         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
1655         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1656         struct hns3_pf *pf = &hns->pf;
1657         uint32_t shared_buf, aligned_mps;
1658         uint32_t rx_priv;
1659         uint8_t tc_num;
1660         uint8_t i;
1661
1662         tc_num = hns3_get_tc_num(hw);
1663         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1664
1665         if (hns3_dev_dcb_supported(hw))
1666                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
1667                                         pf->dv_buf_size;
1668         else
1669                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
1670                                         + pf->dv_buf_size;
1671
1672         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
1673         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
1674                              HNS3_BUF_SIZE_UNIT);
1675
1676         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
1677         if (rx_all < rx_priv + shared_std)
1678                 return false;
1679
1680         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
1681         buf_alloc->s_buf.buf_size = shared_buf;
1682         if (hns3_dev_dcb_supported(hw)) {
1683                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
1684                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1685                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
1686                                   HNS3_BUF_SIZE_UNIT);
1687         } else {
1688                 buf_alloc->s_buf.self.high =
1689                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1690                 buf_alloc->s_buf.self.low = aligned_mps;
1691         }
1692
1693         if (hns3_dev_dcb_supported(hw)) {
1694                 hi_thrd = shared_buf - pf->dv_buf_size;
1695
1696                 if (tc_num <= NEED_RESERVE_TC_NUM)
1697                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
1698                                         / BUF_MAX_PERCENT;
1699
1700                 if (tc_num)
1701                         hi_thrd = hi_thrd / tc_num;
1702
1703                 hi_thrd = max_t(uint32_t, hi_thrd,
1704                                 HNS3_BUF_MUL_BY * aligned_mps);
1705                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
1706                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
1707         } else {
1708                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1709                 lo_thrd = aligned_mps;
1710         }
1711
1712         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1713                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
1714                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
1715         }
1716
1717         return true;
1718 }
1719
1720 static bool
1721 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
1722                      struct hns3_pkt_buf_alloc *buf_alloc)
1723 {
1724         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1725         struct hns3_pf *pf = &hns->pf;
1726         struct hns3_priv_buf *priv;
1727         uint32_t aligned_mps;
1728         uint32_t rx_all;
1729         uint8_t i;
1730
1731         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1732         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1733
1734         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1735                 priv = &buf_alloc->priv_buf[i];
1736
1737                 priv->enable = 0;
1738                 priv->wl.low = 0;
1739                 priv->wl.high = 0;
1740                 priv->buf_size = 0;
1741
1742                 if (!(hw->hw_tc_map & BIT(i)))
1743                         continue;
1744
1745                 priv->enable = 1;
1746                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
1747                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
1748                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
1749                                                 HNS3_BUF_SIZE_UNIT);
1750                 } else {
1751                         priv->wl.low = 0;
1752                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
1753                                         aligned_mps;
1754                 }
1755
1756                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
1757         }
1758
1759         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1760 }
1761
1762 static bool
1763 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
1764                              struct hns3_pkt_buf_alloc *buf_alloc)
1765 {
1766         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1767         struct hns3_pf *pf = &hns->pf;
1768         struct hns3_priv_buf *priv;
1769         int no_pfc_priv_num;
1770         uint32_t rx_all;
1771         uint8_t mask;
1772         int i;
1773
1774         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1775         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
1776
1777         /* let the last to be cleared first */
1778         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1779                 priv = &buf_alloc->priv_buf[i];
1780                 mask = BIT((uint8_t)i);
1781
1782                 if (hw->hw_tc_map & mask &&
1783                     !(hw->dcb_info.hw_pfc_map & mask)) {
1784                         /* Clear the no pfc TC private buffer */
1785                         priv->wl.low = 0;
1786                         priv->wl.high = 0;
1787                         priv->buf_size = 0;
1788                         priv->enable = 0;
1789                         no_pfc_priv_num--;
1790                 }
1791
1792                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1793                     no_pfc_priv_num == 0)
1794                         break;
1795         }
1796
1797         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1798 }
1799
1800 static bool
1801 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
1802                            struct hns3_pkt_buf_alloc *buf_alloc)
1803 {
1804         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1805         struct hns3_pf *pf = &hns->pf;
1806         struct hns3_priv_buf *priv;
1807         uint32_t rx_all;
1808         int pfc_priv_num;
1809         uint8_t mask;
1810         int i;
1811
1812         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1813         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
1814
1815         /* let the last to be cleared first */
1816         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1817                 priv = &buf_alloc->priv_buf[i];
1818                 mask = BIT((uint8_t)i);
1819
1820                 if (hw->hw_tc_map & mask &&
1821                     hw->dcb_info.hw_pfc_map & mask) {
1822                         /* Reduce the number of pfc TC with private buffer */
1823                         priv->wl.low = 0;
1824                         priv->enable = 0;
1825                         priv->wl.high = 0;
1826                         priv->buf_size = 0;
1827                         pfc_priv_num--;
1828                 }
1829                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1830                     pfc_priv_num == 0)
1831                         break;
1832         }
1833
1834         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1835 }
1836
1837 static bool
1838 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
1839                           struct hns3_pkt_buf_alloc *buf_alloc)
1840 {
1841 #define COMPENSATE_BUFFER       0x3C00
1842 #define COMPENSATE_HALF_MPS_NUM 5
1843 #define PRIV_WL_GAP             0x1800
1844         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1845         struct hns3_pf *pf = &hns->pf;
1846         uint32_t tc_num = hns3_get_tc_num(hw);
1847         uint32_t half_mps = pf->mps >> 1;
1848         struct hns3_priv_buf *priv;
1849         uint32_t min_rx_priv;
1850         uint32_t rx_priv;
1851         uint8_t i;
1852
1853         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1854         if (tc_num)
1855                 rx_priv = rx_priv / tc_num;
1856
1857         if (tc_num <= NEED_RESERVE_TC_NUM)
1858                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
1859
1860         /*
1861          * Minimum value of private buffer in rx direction (min_rx_priv) is
1862          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
1863          * buffer if rx_priv is greater than min_rx_priv.
1864          */
1865         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
1866                         COMPENSATE_HALF_MPS_NUM * half_mps;
1867         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
1868         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
1869
1870         if (rx_priv < min_rx_priv)
1871                 return false;
1872
1873         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1874                 priv = &buf_alloc->priv_buf[i];
1875
1876                 priv->enable = 0;
1877                 priv->wl.low = 0;
1878                 priv->wl.high = 0;
1879                 priv->buf_size = 0;
1880
1881                 if (!(hw->hw_tc_map & BIT(i)))
1882                         continue;
1883
1884                 priv->enable = 1;
1885                 priv->buf_size = rx_priv;
1886                 priv->wl.high = rx_priv - pf->dv_buf_size;
1887                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
1888         }
1889
1890         buf_alloc->s_buf.buf_size = 0;
1891
1892         return true;
1893 }
1894
1895 /*
1896  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
1897  * @hw: pointer to struct hns3_hw
1898  * @buf_alloc: pointer to buffer calculation data
1899  * @return: 0: calculate sucessful, negative: fail
1900  */
1901 static int
1902 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1903 {
1904         /* When DCB is not supported, rx private buffer is not allocated. */
1905         if (!hns3_dev_dcb_supported(hw)) {
1906                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1907                 struct hns3_pf *pf = &hns->pf;
1908                 uint32_t rx_all = pf->pkt_buf_size;
1909
1910                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
1911                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
1912                         return -ENOMEM;
1913
1914                 return 0;
1915         }
1916
1917         /*
1918          * Try to allocate privated packet buffer for all TCs without share
1919          * buffer.
1920          */
1921         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
1922                 return 0;
1923
1924         /*
1925          * Try to allocate privated packet buffer for all TCs with share
1926          * buffer.
1927          */
1928         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
1929                 return 0;
1930
1931         /*
1932          * For different application scenes, the enabled port number, TC number
1933          * and no_drop TC number are different. In order to obtain the better
1934          * performance, software could allocate the buffer size and configure
1935          * the waterline by tring to decrease the private buffer size according
1936          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
1937          * enabled tc.
1938          */
1939         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
1940                 return 0;
1941
1942         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
1943                 return 0;
1944
1945         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
1946                 return 0;
1947
1948         return -ENOMEM;
1949 }
1950
1951 static int
1952 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1953 {
1954         struct hns3_rx_priv_buff_cmd *req;
1955         struct hns3_cmd_desc desc;
1956         uint32_t buf_size;
1957         int ret;
1958         int i;
1959
1960         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
1961         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
1962
1963         /* Alloc private buffer TCs */
1964         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1965                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
1966
1967                 req->buf_num[i] =
1968                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
1969                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
1970         }
1971
1972         buf_size = buf_alloc->s_buf.buf_size;
1973         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
1974                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
1975
1976         ret = hns3_cmd_send(hw, &desc, 1);
1977         if (ret)
1978                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
1979
1980         return ret;
1981 }
1982
1983 static int
1984 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1985 {
1986 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
1987         struct hns3_rx_priv_wl_buf *req;
1988         struct hns3_priv_buf *priv;
1989         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
1990         int i, j;
1991         int ret;
1992
1993         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
1994                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
1995                                           false);
1996                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
1997
1998                 /* The first descriptor set the NEXT bit to 1 */
1999                 if (i == 0)
2000                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2001                 else
2002                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2003
2004                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2005                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
2006
2007                         priv = &buf_alloc->priv_buf[idx];
2008                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
2009                                                         HNS3_BUF_UNIT_S);
2010                         req->tc_wl[j].high |=
2011                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2012                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
2013                                                         HNS3_BUF_UNIT_S);
2014                         req->tc_wl[j].low |=
2015                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2016                 }
2017         }
2018
2019         /* Send 2 descriptor at one time */
2020         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
2021         if (ret)
2022                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
2023                              ret);
2024         return ret;
2025 }
2026
2027 static int
2028 hns3_common_thrd_config(struct hns3_hw *hw,
2029                         struct hns3_pkt_buf_alloc *buf_alloc)
2030 {
2031 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
2032         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
2033         struct hns3_rx_com_thrd *req;
2034         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
2035         struct hns3_tc_thrd *tc;
2036         int tc_idx;
2037         int i, j;
2038         int ret;
2039
2040         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
2041                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
2042                                           false);
2043                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
2044
2045                 /* The first descriptor set the NEXT bit to 1 */
2046                 if (i == 0)
2047                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2048                 else
2049                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2050
2051                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2052                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
2053                         tc = &s_buf->tc_thrd[tc_idx];
2054
2055                         req->com_thrd[j].high =
2056                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
2057                         req->com_thrd[j].high |=
2058                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2059                         req->com_thrd[j].low =
2060                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
2061                         req->com_thrd[j].low |=
2062                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2063                 }
2064         }
2065
2066         /* Send 2 descriptors at one time */
2067         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
2068         if (ret)
2069                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
2070
2071         return ret;
2072 }
2073
2074 static int
2075 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2076 {
2077         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
2078         struct hns3_rx_com_wl *req;
2079         struct hns3_cmd_desc desc;
2080         int ret;
2081
2082         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
2083
2084         req = (struct hns3_rx_com_wl *)desc.data;
2085         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
2086         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2087
2088         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
2089         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2090
2091         ret = hns3_cmd_send(hw, &desc, 1);
2092         if (ret)
2093                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
2094
2095         return ret;
2096 }
2097
2098 int
2099 hns3_buffer_alloc(struct hns3_hw *hw)
2100 {
2101         struct hns3_pkt_buf_alloc pkt_buf;
2102         int ret;
2103
2104         memset(&pkt_buf, 0, sizeof(pkt_buf));
2105         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
2106         if (ret) {
2107                 PMD_INIT_LOG(ERR,
2108                              "could not calc tx buffer size for all TCs %d",
2109                              ret);
2110                 return ret;
2111         }
2112
2113         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
2114         if (ret) {
2115                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
2116                 return ret;
2117         }
2118
2119         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
2120         if (ret) {
2121                 PMD_INIT_LOG(ERR,
2122                              "could not calc rx priv buffer size for all TCs %d",
2123                              ret);
2124                 return ret;
2125         }
2126
2127         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
2128         if (ret) {
2129                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
2130                 return ret;
2131         }
2132
2133         if (hns3_dev_dcb_supported(hw)) {
2134                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
2135                 if (ret) {
2136                         PMD_INIT_LOG(ERR,
2137                                      "could not configure rx private waterline %d",
2138                                      ret);
2139                         return ret;
2140                 }
2141
2142                 ret = hns3_common_thrd_config(hw, &pkt_buf);
2143                 if (ret) {
2144                         PMD_INIT_LOG(ERR,
2145                                      "could not configure common threshold %d",
2146                                      ret);
2147                         return ret;
2148                 }
2149         }
2150
2151         ret = hns3_common_wl_config(hw, &pkt_buf);
2152         if (ret)
2153                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
2154                              ret);
2155
2156         return ret;
2157 }
2158
2159 static int
2160 hns3_mac_init(struct hns3_hw *hw)
2161 {
2162         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2163         struct hns3_mac *mac = &hw->mac;
2164         struct hns3_pf *pf = &hns->pf;
2165         int ret;
2166
2167         pf->support_sfp_query = true;
2168         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
2169         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
2170         if (ret) {
2171                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
2172                 return ret;
2173         }
2174
2175         mac->link_status = ETH_LINK_DOWN;
2176
2177         return hns3_config_mtu(hw, pf->mps);
2178 }
2179
2180 static int
2181 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
2182 {
2183 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
2184 #define HNS3_ETHERTYPE_ALREADY_ADD              1
2185 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
2186 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
2187         int return_status;
2188
2189         if (cmdq_resp) {
2190                 PMD_INIT_LOG(ERR,
2191                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
2192                              cmdq_resp);
2193                 return -EIO;
2194         }
2195
2196         switch (resp_code) {
2197         case HNS3_ETHERTYPE_SUCCESS_ADD:
2198         case HNS3_ETHERTYPE_ALREADY_ADD:
2199                 return_status = 0;
2200                 break;
2201         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
2202                 PMD_INIT_LOG(ERR,
2203                              "add mac ethertype failed for manager table overflow.");
2204                 return_status = -EIO;
2205                 break;
2206         case HNS3_ETHERTYPE_KEY_CONFLICT:
2207                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
2208                 return_status = -EIO;
2209                 break;
2210         default:
2211                 PMD_INIT_LOG(ERR,
2212                              "add mac ethertype failed for undefined, code=%d.",
2213                              resp_code);
2214                 return_status = -EIO;
2215         }
2216
2217         return return_status;
2218 }
2219
2220 static int
2221 hns3_add_mgr_tbl(struct hns3_hw *hw,
2222                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
2223 {
2224         struct hns3_cmd_desc desc;
2225         uint8_t resp_code;
2226         uint16_t retval;
2227         int ret;
2228
2229         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
2230         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
2231
2232         ret = hns3_cmd_send(hw, &desc, 1);
2233         if (ret) {
2234                 PMD_INIT_LOG(ERR,
2235                              "add mac ethertype failed for cmd_send, ret =%d.",
2236                              ret);
2237                 return ret;
2238         }
2239
2240         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
2241         retval = rte_le_to_cpu_16(desc.retval);
2242
2243         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
2244 }
2245
2246 static void
2247 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
2248                      int *table_item_num)
2249 {
2250         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
2251
2252         /*
2253          * In current version, we add one item in management table as below:
2254          * 0x0180C200000E -- LLDP MC address
2255          */
2256         tbl = mgr_table;
2257         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
2258         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
2259         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
2260         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
2261         tbl->i_port_bitmap = 0x1;
2262         *table_item_num = 1;
2263 }
2264
2265 static int
2266 hns3_init_mgr_tbl(struct hns3_hw *hw)
2267 {
2268 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
2269         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
2270         int table_item_num;
2271         int ret;
2272         int i;
2273
2274         memset(mgr_table, 0, sizeof(mgr_table));
2275         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
2276         for (i = 0; i < table_item_num; i++) {
2277                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
2278                 if (ret) {
2279                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
2280                                      ret);
2281                         return ret;
2282                 }
2283         }
2284
2285         return 0;
2286 }
2287
2288 static void
2289 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
2290                         bool en_mc, bool en_bc, int vport_id)
2291 {
2292         if (!param)
2293                 return;
2294
2295         memset(param, 0, sizeof(struct hns3_promisc_param));
2296         if (en_uc)
2297                 param->enable = HNS3_PROMISC_EN_UC;
2298         if (en_mc)
2299                 param->enable |= HNS3_PROMISC_EN_MC;
2300         if (en_bc)
2301                 param->enable |= HNS3_PROMISC_EN_BC;
2302         param->vf_id = vport_id;
2303 }
2304
2305 static int
2306 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
2307 {
2308         struct hns3_promisc_cfg_cmd *req;
2309         struct hns3_cmd_desc desc;
2310         int ret;
2311
2312         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
2313
2314         req = (struct hns3_promisc_cfg_cmd *)desc.data;
2315         req->vf_id = param->vf_id;
2316         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
2317             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
2318
2319         ret = hns3_cmd_send(hw, &desc, 1);
2320         if (ret)
2321                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
2322
2323         return ret;
2324 }
2325
2326 static int
2327 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
2328 {
2329         struct hns3_promisc_param param;
2330         bool en_bc_pmc = true;
2331         uint8_t vf_id;
2332         int ret;
2333
2334         /*
2335          * In current version VF is not supported when PF is driven by DPDK
2336          * driver, the PF-related vf_id is 0, just need to configure parameters
2337          * for vf_id 0.
2338          */
2339         vf_id = 0;
2340
2341         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
2342         ret = hns3_cmd_set_promisc_mode(hw, &param);
2343         if (ret)
2344                 return ret;
2345
2346         return 0;
2347 }
2348
2349 static int
2350 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
2351 {
2352         struct hns3_sfp_speed_cmd *resp;
2353         struct hns3_cmd_desc desc;
2354         int ret;
2355
2356         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
2357         resp = (struct hns3_sfp_speed_cmd *)desc.data;
2358         ret = hns3_cmd_send(hw, &desc, 1);
2359         if (ret == -EOPNOTSUPP) {
2360                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
2361                 return ret;
2362         } else if (ret) {
2363                 hns3_err(hw, "get sfp speed failed %d", ret);
2364                 return ret;
2365         }
2366
2367         *speed = resp->sfp_speed;
2368
2369         return 0;
2370 }
2371
2372 static uint8_t
2373 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
2374 {
2375         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
2376                 duplex = ETH_LINK_FULL_DUPLEX;
2377
2378         return duplex;
2379 }
2380
2381 static int
2382 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2383 {
2384         struct hns3_mac *mac = &hw->mac;
2385         int ret;
2386
2387         duplex = hns3_check_speed_dup(duplex, speed);
2388         if (mac->link_speed == speed && mac->link_duplex == duplex)
2389                 return 0;
2390
2391         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
2392         if (ret)
2393                 return ret;
2394
2395         mac->link_speed = speed;
2396         mac->link_duplex = duplex;
2397
2398         return 0;
2399 }
2400
2401 static int
2402 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
2403 {
2404         struct hns3_adapter *hns = eth_dev->data->dev_private;
2405         struct hns3_hw *hw = &hns->hw;
2406         struct hns3_pf *pf = &hns->pf;
2407         uint32_t speed;
2408         int ret;
2409
2410         /* If IMP do not support get SFP/qSFP speed, return directly */
2411         if (!pf->support_sfp_query)
2412                 return 0;
2413
2414         ret = hns3_get_sfp_speed(hw, &speed);
2415         if (ret == -EOPNOTSUPP) {
2416                 pf->support_sfp_query = false;
2417                 return ret;
2418         } else if (ret)
2419                 return ret;
2420
2421         if (speed == ETH_SPEED_NUM_NONE)
2422                 return 0; /* do nothing if no SFP */
2423
2424         /* Config full duplex for SFP */
2425         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
2426 }
2427
2428 static int
2429 hns3_get_mac_link_status(struct hns3_hw *hw)
2430 {
2431         struct hns3_link_status_cmd *req;
2432         struct hns3_cmd_desc desc;
2433         int link_status;
2434         int ret;
2435
2436         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
2437         ret = hns3_cmd_send(hw, &desc, 1);
2438         if (ret) {
2439                 hns3_err(hw, "get link status cmd failed %d", ret);
2440                 return ret;
2441         }
2442
2443         req = (struct hns3_link_status_cmd *)desc.data;
2444         link_status = req->status & HNS3_LINK_STATUS_UP_M;
2445
2446         return !!link_status;
2447 }
2448
2449 static void
2450 hns3_update_link_status(struct hns3_hw *hw)
2451 {
2452         int state;
2453
2454         state = hns3_get_mac_link_status(hw);
2455         if (state != hw->mac.link_status)
2456                 hw->mac.link_status = state;
2457 }
2458
2459 static void
2460 hns3_service_handler(void *param)
2461 {
2462         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
2463         struct hns3_adapter *hns = eth_dev->data->dev_private;
2464         struct hns3_hw *hw = &hns->hw;
2465
2466         hns3_update_speed_duplex(eth_dev);
2467         hns3_update_link_status(hw);
2468
2469         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
2470 }
2471
2472 static int
2473 hns3_init_hardware(struct hns3_adapter *hns)
2474 {
2475         struct hns3_hw *hw = &hns->hw;
2476         int ret;
2477
2478         ret = hns3_map_tqp(hw);
2479         if (ret) {
2480                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
2481                 return ret;
2482         }
2483
2484         ret = hns3_init_umv_space(hw);
2485         if (ret) {
2486                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
2487                 return ret;
2488         }
2489
2490         ret = hns3_mac_init(hw);
2491         if (ret) {
2492                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
2493                 goto err_mac_init;
2494         }
2495
2496         ret = hns3_init_mgr_tbl(hw);
2497         if (ret) {
2498                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
2499                 goto err_mac_init;
2500         }
2501
2502         ret = hns3_set_promisc_mode(hw, false, false);
2503         if (ret) {
2504                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
2505                 goto err_mac_init;
2506         }
2507
2508         ret = hns3_dcb_init(hw);
2509         if (ret) {
2510                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
2511                 goto err_mac_init;
2512         }
2513
2514         ret = hns3_init_fd_config(hns);
2515         if (ret) {
2516                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
2517                 goto err_mac_init;
2518         }
2519
2520         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
2521         if (ret) {
2522                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
2523                 goto err_mac_init;
2524         }
2525
2526         ret = hns3_config_gro(hw, false);
2527         if (ret) {
2528                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
2529                 goto err_mac_init;
2530         }
2531         return 0;
2532
2533 err_mac_init:
2534         hns3_uninit_umv_space(hw);
2535         return ret;
2536 }
2537
2538 static int
2539 hns3_init_pf(struct rte_eth_dev *eth_dev)
2540 {
2541         struct rte_device *dev = eth_dev->device;
2542         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2543         struct hns3_adapter *hns = eth_dev->data->dev_private;
2544         struct hns3_hw *hw = &hns->hw;
2545         int ret;
2546
2547         PMD_INIT_FUNC_TRACE();
2548
2549         /* Get hardware io base address from pcie BAR2 IO space */
2550         hw->io_base = pci_dev->mem_resource[2].addr;
2551
2552         /* Firmware command queue initialize */
2553         ret = hns3_cmd_init_queue(hw);
2554         if (ret) {
2555                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
2556                 goto err_cmd_init_queue;
2557         }
2558
2559         /* Firmware command initialize */
2560         ret = hns3_cmd_init(hw);
2561         if (ret) {
2562                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
2563                 goto err_cmd_init;
2564         }
2565
2566         /* Get configuration */
2567         ret = hns3_get_configuration(hw);
2568         if (ret) {
2569                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
2570                 goto err_get_config;
2571         }
2572
2573         ret = hns3_init_hardware(hns);
2574         if (ret) {
2575                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
2576                 goto err_get_config;
2577         }
2578
2579         /* Initialize flow director filter list & hash */
2580         ret = hns3_fdir_filter_init(hns);
2581         if (ret) {
2582                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
2583                 goto err_hw_init;
2584         }
2585
2586         hns3_set_default_rss_args(hw);
2587
2588         return 0;
2589
2590 err_hw_init:
2591         hns3_uninit_umv_space(hw);
2592
2593 err_get_config:
2594         hns3_cmd_uninit(hw);
2595
2596 err_cmd_init:
2597         hns3_cmd_destroy_queue(hw);
2598
2599 err_cmd_init_queue:
2600         hw->io_base = NULL;
2601
2602         return ret;
2603 }
2604
2605 static void
2606 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
2607 {
2608         struct hns3_adapter *hns = eth_dev->data->dev_private;
2609         struct hns3_hw *hw = &hns->hw;
2610
2611         PMD_INIT_FUNC_TRACE();
2612
2613         hns3_rss_uninit(hns);
2614         hns3_fdir_filter_uninit(hns);
2615         hns3_uninit_umv_space(hw);
2616         hns3_cmd_uninit(hw);
2617         hns3_cmd_destroy_queue(hw);
2618         hw->io_base = NULL;
2619 }
2620
2621 static void
2622 hns3_dev_close(struct rte_eth_dev *eth_dev)
2623 {
2624         struct hns3_adapter *hns = eth_dev->data->dev_private;
2625         struct hns3_hw *hw = &hns->hw;
2626
2627         hw->adapter_state = HNS3_NIC_CLOSING;
2628         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
2629
2630         hns3_configure_all_mc_mac_addr(hns, true);
2631         hns3_uninit_pf(eth_dev);
2632         rte_free(eth_dev->process_private);
2633         eth_dev->process_private = NULL;
2634         hw->adapter_state = HNS3_NIC_CLOSED;
2635 }
2636
2637 static int
2638 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2639 {
2640         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2642
2643         fc_conf->pause_time = pf->pause_time;
2644
2645         /* return fc current mode */
2646         switch (hw->current_mode) {
2647         case HNS3_FC_FULL:
2648                 fc_conf->mode = RTE_FC_FULL;
2649                 break;
2650         case HNS3_FC_TX_PAUSE:
2651                 fc_conf->mode = RTE_FC_TX_PAUSE;
2652                 break;
2653         case HNS3_FC_RX_PAUSE:
2654                 fc_conf->mode = RTE_FC_RX_PAUSE;
2655                 break;
2656         case HNS3_FC_NONE:
2657         default:
2658                 fc_conf->mode = RTE_FC_NONE;
2659                 break;
2660         }
2661
2662         return 0;
2663 }
2664
2665 static void
2666 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
2667 {
2668         switch (mode) {
2669         case RTE_FC_NONE:
2670                 hw->requested_mode = HNS3_FC_NONE;
2671                 break;
2672         case RTE_FC_RX_PAUSE:
2673                 hw->requested_mode = HNS3_FC_RX_PAUSE;
2674                 break;
2675         case RTE_FC_TX_PAUSE:
2676                 hw->requested_mode = HNS3_FC_TX_PAUSE;
2677                 break;
2678         case RTE_FC_FULL:
2679                 hw->requested_mode = HNS3_FC_FULL;
2680                 break;
2681         default:
2682                 hw->requested_mode = HNS3_FC_NONE;
2683                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
2684                           "configured to RTE_FC_NONE", mode);
2685                 break;
2686         }
2687 }
2688
2689 static int
2690 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2691 {
2692         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2693         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2694         int ret;
2695
2696         if (fc_conf->high_water || fc_conf->low_water ||
2697             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
2698                 hns3_err(hw, "Unsupported flow control settings specified, "
2699                          "high_water(%u), low_water(%u), send_xon(%u) and "
2700                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
2701                          fc_conf->high_water, fc_conf->low_water,
2702                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
2703                 return -EINVAL;
2704         }
2705         if (fc_conf->autoneg) {
2706                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
2707                 return -EINVAL;
2708         }
2709         if (!fc_conf->pause_time) {
2710                 hns3_err(hw, "Invalid pause time %d setting.",
2711                          fc_conf->pause_time);
2712                 return -EINVAL;
2713         }
2714
2715         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
2716             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
2717                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
2718                          "current_fc_status = %d", hw->current_fc_status);
2719                 return -EOPNOTSUPP;
2720         }
2721
2722         hns3_get_fc_mode(hw, fc_conf->mode);
2723         if (hw->requested_mode == hw->current_mode &&
2724             pf->pause_time == fc_conf->pause_time)
2725                 return 0;
2726
2727         rte_spinlock_lock(&hw->lock);
2728         ret = hns3_fc_enable(dev, fc_conf);
2729         rte_spinlock_unlock(&hw->lock);
2730
2731         return ret;
2732 }
2733
2734 static int
2735 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
2736                             struct rte_eth_pfc_conf *pfc_conf)
2737 {
2738         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2739         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2740         uint8_t priority;
2741         int ret;
2742
2743         if (!hns3_dev_dcb_supported(hw)) {
2744                 hns3_err(hw, "This port does not support dcb configurations.");
2745                 return -EOPNOTSUPP;
2746         }
2747
2748         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
2749             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
2750                 hns3_err(hw, "Unsupported flow control settings specified, "
2751                          "high_water(%u), low_water(%u), send_xon(%u) and "
2752                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
2753                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
2754                          pfc_conf->fc.send_xon,
2755                          pfc_conf->fc.mac_ctrl_frame_fwd);
2756                 return -EINVAL;
2757         }
2758         if (pfc_conf->fc.autoneg) {
2759                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
2760                 return -EINVAL;
2761         }
2762         if (pfc_conf->fc.pause_time == 0) {
2763                 hns3_err(hw, "Invalid pause time %d setting.",
2764                          pfc_conf->fc.pause_time);
2765                 return -EINVAL;
2766         }
2767
2768         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
2769             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
2770                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
2771                              "current_fc_status = %d", hw->current_fc_status);
2772                 return -EOPNOTSUPP;
2773         }
2774
2775         priority = pfc_conf->priority;
2776         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
2777         if (hw->dcb_info.pfc_en & BIT(priority) &&
2778             hw->requested_mode == hw->current_mode &&
2779             pfc_conf->fc.pause_time == pf->pause_time)
2780                 return 0;
2781
2782         rte_spinlock_lock(&hw->lock);
2783         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
2784         rte_spinlock_unlock(&hw->lock);
2785
2786         return ret;
2787 }
2788
2789 static int
2790 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
2791 {
2792         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2794         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2795         int i;
2796
2797         rte_spinlock_lock(&hw->lock);
2798         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
2799                 dcb_info->nb_tcs = pf->local_max_tc;
2800         else
2801                 dcb_info->nb_tcs = 1;
2802
2803         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
2804                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
2805         for (i = 0; i < dcb_info->nb_tcs; i++)
2806                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
2807
2808         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2809                 dcb_info->tc_queue.tc_rxq[0][i].base =
2810                                         hw->tc_queue[i].tqp_offset;
2811                 dcb_info->tc_queue.tc_txq[0][i].base =
2812                                         hw->tc_queue[i].tqp_offset;
2813                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue =
2814                                         hw->tc_queue[i].tqp_count;
2815                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
2816                                         hw->tc_queue[i].tqp_count;
2817         }
2818         rte_spinlock_unlock(&hw->lock);
2819
2820         return 0;
2821 }
2822
2823 static const struct eth_dev_ops hns3_eth_dev_ops = {
2824         .dev_close          = hns3_dev_close,
2825         .mtu_set            = hns3_dev_mtu_set,
2826         .dev_infos_get          = hns3_dev_infos_get,
2827         .fw_version_get         = hns3_fw_version_get,
2828         .flow_ctrl_get          = hns3_flow_ctrl_get,
2829         .flow_ctrl_set          = hns3_flow_ctrl_set,
2830         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
2831         .mac_addr_add           = hns3_add_mac_addr,
2832         .mac_addr_remove        = hns3_remove_mac_addr,
2833         .mac_addr_set           = hns3_set_default_mac_addr,
2834         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
2835         .link_update            = hns3_dev_link_update,
2836         .rss_hash_update        = hns3_dev_rss_hash_update,
2837         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
2838         .reta_update            = hns3_dev_rss_reta_update,
2839         .reta_query             = hns3_dev_rss_reta_query,
2840         .filter_ctrl            = hns3_dev_filter_ctrl,
2841         .get_dcb_info           = hns3_get_dcb_info,
2842 };
2843
2844 static int
2845 hns3_dev_init(struct rte_eth_dev *eth_dev)
2846 {
2847         struct rte_device *dev = eth_dev->device;
2848         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2849         struct hns3_adapter *hns = eth_dev->data->dev_private;
2850         struct hns3_hw *hw = &hns->hw;
2851         uint16_t device_id = pci_dev->id.device_id;
2852         int ret;
2853
2854         PMD_INIT_FUNC_TRACE();
2855         eth_dev->process_private = (struct hns3_process_private *)
2856             rte_zmalloc_socket("hns3_filter_list",
2857                                sizeof(struct hns3_process_private),
2858                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2859         if (eth_dev->process_private == NULL) {
2860                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2861                 return -ENOMEM;
2862         }
2863         /* initialize flow filter lists */
2864         hns3_filterlist_init(eth_dev);
2865
2866         eth_dev->dev_ops = &hns3_eth_dev_ops;
2867         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2868                 return 0;
2869
2870         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2871
2872         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2873             device_id == HNS3_DEV_ID_50GE_RDMA ||
2874             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
2875                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
2876
2877         hns->is_vf = false;
2878         hw->data = eth_dev->data;
2879
2880         /*
2881          * Set default max packet size according to the mtu
2882          * default vale in DPDK frame.
2883          */
2884         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
2885
2886         ret = hns3_init_pf(eth_dev);
2887         if (ret) {
2888                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
2889                 goto err_init_pf;
2890         }
2891
2892         /* Allocate memory for storing MAC addresses */
2893         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
2894                                                sizeof(struct rte_ether_addr) *
2895                                                HNS3_UC_MACADDR_NUM, 0);
2896         if (eth_dev->data->mac_addrs == NULL) {
2897                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2898                              "to store MAC addresses",
2899                              sizeof(struct rte_ether_addr) *
2900                              HNS3_UC_MACADDR_NUM);
2901                 ret = -ENOMEM;
2902                 goto err_rte_zmalloc;
2903         }
2904
2905         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2906                             &eth_dev->data->mac_addrs[0]);
2907
2908         hw->adapter_state = HNS3_NIC_INITIALIZED;
2909         /*
2910          * Pass the information to the rte_eth_dev_close() that it should also
2911          * release the private port resources.
2912          */
2913         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2914
2915         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
2916         hns3_info(hw, "hns3 dev initialization successful!");
2917         return 0;
2918
2919 err_rte_zmalloc:
2920         hns3_uninit_pf(eth_dev);
2921
2922 err_init_pf:
2923         eth_dev->dev_ops = NULL;
2924         eth_dev->rx_pkt_burst = NULL;
2925         eth_dev->tx_pkt_burst = NULL;
2926         eth_dev->tx_pkt_prepare = NULL;
2927         rte_free(eth_dev->process_private);
2928         eth_dev->process_private = NULL;
2929         return ret;
2930 }
2931
2932 static int
2933 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
2934 {
2935         struct hns3_adapter *hns = eth_dev->data->dev_private;
2936         struct hns3_hw *hw = &hns->hw;
2937
2938         PMD_INIT_FUNC_TRACE();
2939
2940         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2941                 return -EPERM;
2942
2943         eth_dev->dev_ops = NULL;
2944         eth_dev->rx_pkt_burst = NULL;
2945         eth_dev->tx_pkt_burst = NULL;
2946         eth_dev->tx_pkt_prepare = NULL;
2947         if (hw->adapter_state < HNS3_NIC_CLOSING)
2948                 hns3_dev_close(eth_dev);
2949
2950         hw->adapter_state = HNS3_NIC_REMOVED;
2951         return 0;
2952 }
2953
2954 static int
2955 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2956                    struct rte_pci_device *pci_dev)
2957 {
2958         return rte_eth_dev_pci_generic_probe(pci_dev,
2959                                              sizeof(struct hns3_adapter),
2960                                              hns3_dev_init);
2961 }
2962
2963 static int
2964 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
2965 {
2966         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
2967 }
2968
2969 static const struct rte_pci_id pci_id_hns3_map[] = {
2970         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
2971         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
2972         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
2973         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
2974         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
2975         { .vendor_id = 0, /* sentinel */ },
2976 };
2977
2978 static struct rte_pci_driver rte_hns3_pmd = {
2979         .id_table = pci_id_hns3_map,
2980         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2981         .probe = eth_hns3_pci_probe,
2982         .remove = eth_hns3_pci_remove,
2983 };
2984
2985 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
2986 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
2987 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
2988
2989 RTE_INIT(hns3_init_log)
2990 {
2991         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
2992         if (hns3_logtype_init >= 0)
2993                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
2994         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
2995         if (hns3_logtype_driver >= 0)
2996                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
2997 }