1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_PORT_BASE_VLAN_DISABLE 0
39 #define HNS3_PORT_BASE_VLAN_ENABLE 1
40 #define HNS3_INVLID_PVID 0xFFFF
42 #define HNS3_FILTER_TYPE_VF 0
43 #define HNS3_FILTER_TYPE_PORT 1
44 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
45 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
46 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
47 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
48 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
49 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
50 | HNS3_FILTER_FE_ROCE_EGRESS_B)
51 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
52 | HNS3_FILTER_FE_ROCE_INGRESS_B)
54 /* Reset related Registers */
55 #define HNS3_GLOBAL_RESET_BIT 0
56 #define HNS3_CORE_RESET_BIT 1
57 #define HNS3_IMP_RESET_BIT 2
58 #define HNS3_FUN_RST_ING_B 0
60 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
62 #define HNS3_RESET_WAIT_MS 100
63 #define HNS3_RESET_WAIT_CNT 200
65 int hns3_logtype_init;
66 int hns3_logtype_driver;
69 HNS3_VECTOR0_EVENT_RST,
70 HNS3_VECTOR0_EVENT_MBX,
71 HNS3_VECTOR0_EVENT_ERR,
72 HNS3_VECTOR0_EVENT_OTHER,
75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
83 hns3_pf_disable_irq0(struct hns3_hw *hw)
85 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
89 hns3_pf_enable_irq0(struct hns3_hw *hw)
91 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
94 static enum hns3_evt_cause
95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
97 struct hns3_hw *hw = &hns->hw;
98 uint32_t vector0_int_stats;
99 uint32_t cmdq_src_val;
101 enum hns3_evt_cause ret;
103 /* fetch the events from their corresponding regs */
104 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
105 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
108 * Assumption: If by any chance reset and mailbox events are reported
109 * together then we will only process reset event and defer the
110 * processing of the mailbox events. Since, we would have not cleared
111 * RX CMDQ event this time we would receive again another interrupt
112 * from H/W just for the mailbox.
114 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
115 rte_atomic16_set(&hw->reset.disable_cmd, 1);
116 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
117 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
119 hw->reset.stats.imp_cnt++;
120 hns3_warn(hw, "IMP reset detected, clear reset status");
122 hns3_schedule_delayed_reset(hns);
123 hns3_warn(hw, "IMP reset detected, don't clear reset status");
126 ret = HNS3_VECTOR0_EVENT_RST;
131 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
132 rte_atomic16_set(&hw->reset.disable_cmd, 1);
133 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
134 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
136 hw->reset.stats.global_cnt++;
137 hns3_warn(hw, "Global reset detected, clear reset status");
139 hns3_schedule_delayed_reset(hns);
140 hns3_warn(hw, "Global reset detected, don't clear reset status");
143 ret = HNS3_VECTOR0_EVENT_RST;
147 /* check for vector0 msix event source */
148 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
149 val = vector0_int_stats;
150 ret = HNS3_VECTOR0_EVENT_ERR;
154 /* check for vector0 mailbox(=CMDQ RX) event source */
155 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
156 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
158 ret = HNS3_VECTOR0_EVENT_MBX;
162 if (clearval && (vector0_int_stats || cmdq_src_val))
163 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
164 vector0_int_stats, cmdq_src_val);
165 val = vector0_int_stats;
166 ret = HNS3_VECTOR0_EVENT_OTHER;
175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
177 if (event_type == HNS3_VECTOR0_EVENT_RST)
178 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
179 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
180 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
184 hns3_clear_all_event_cause(struct hns3_hw *hw)
186 uint32_t vector0_int_stats;
187 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
189 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
190 hns3_warn(hw, "Probe during IMP reset interrupt");
192 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
193 hns3_warn(hw, "Probe during Global reset interrupt");
195 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
196 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
197 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
198 BIT(HNS3_VECTOR0_CORERESET_INT_B));
199 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
203 hns3_interrupt_handler(void *param)
205 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
206 struct hns3_adapter *hns = dev->data->dev_private;
207 struct hns3_hw *hw = &hns->hw;
208 enum hns3_evt_cause event_cause;
209 uint32_t clearval = 0;
211 /* Disable interrupt */
212 hns3_pf_disable_irq0(hw);
214 event_cause = hns3_check_event_cause(hns, &clearval);
216 /* vector 0 interrupt is shared with reset and mailbox source events. */
217 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
218 hns3_handle_msix_error(hns, &hw->reset.request);
219 hns3_schedule_reset(hns);
220 } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
221 hns3_schedule_reset(hns);
222 else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
223 hns3_dev_handle_mbx_msg(hw);
225 hns3_err(hw, "Received unknown event");
227 hns3_clear_event_cause(hw, event_cause, clearval);
228 /* Enable interrupt if it is not cause by reset */
229 hns3_pf_enable_irq0(hw);
233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
235 #define HNS3_VLAN_OFFSET_160 160
236 struct hns3_vlan_filter_pf_cfg_cmd *req;
237 struct hns3_hw *hw = &hns->hw;
238 uint8_t vlan_offset_byte_val;
239 struct hns3_cmd_desc desc;
240 uint8_t vlan_offset_byte;
241 uint8_t vlan_offset_160;
244 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
246 vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
247 vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
248 vlan_offset_byte_val = 1 << (vlan_id % 8);
250 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
251 req->vlan_offset = vlan_offset_160;
252 req->vlan_cfg = on ? 0 : 1;
253 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
255 ret = hns3_cmd_send(hw, &desc, 1);
257 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
264 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
266 struct hns3_user_vlan_table *vlan_entry;
267 struct hns3_pf *pf = &hns->pf;
269 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
270 if (vlan_entry->vlan_id == vlan_id) {
271 if (vlan_entry->hd_tbl_status)
272 hns3_set_port_vlan_filter(hns, vlan_id, 0);
273 LIST_REMOVE(vlan_entry, next);
274 rte_free(vlan_entry);
281 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
284 struct hns3_user_vlan_table *vlan_entry;
285 struct hns3_hw *hw = &hns->hw;
286 struct hns3_pf *pf = &hns->pf;
288 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
289 if (vlan_entry->vlan_id == vlan_id)
293 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
294 if (vlan_entry == NULL) {
295 hns3_err(hw, "Failed to malloc hns3 vlan table");
299 vlan_entry->hd_tbl_status = writen_to_tbl;
300 vlan_entry->vlan_id = vlan_id;
302 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
306 hns3_restore_vlan_table(struct hns3_adapter *hns)
308 struct hns3_user_vlan_table *vlan_entry;
309 struct hns3_pf *pf = &hns->pf;
313 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
314 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
319 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
320 if (vlan_entry->hd_tbl_status) {
321 vlan_id = vlan_entry->vlan_id;
322 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
332 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
334 struct hns3_pf *pf = &hns->pf;
335 bool writen_to_tbl = false;
339 * When vlan filter is enabled, hardware regards vlan id 0 as the entry
340 * for normal packet, deleting vlan id 0 is not allowed.
342 if (on == 0 && vlan_id == 0)
346 * When port base vlan enabled, we use port base vlan as the vlan
347 * filter condition. In this case, we don't update vlan filter table
348 * when user add new vlan or remove exist vlan, just update the
349 * vlan list. The vlan id in vlan list will be writen in vlan filter
350 * table until port base vlan disabled
352 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
353 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
354 writen_to_tbl = true;
357 if (ret == 0 && vlan_id) {
359 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
361 hns3_rm_dev_vlan_table(hns, vlan_id);
367 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
369 struct hns3_adapter *hns = dev->data->dev_private;
370 struct hns3_hw *hw = &hns->hw;
373 rte_spinlock_lock(&hw->lock);
374 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
375 rte_spinlock_unlock(&hw->lock);
380 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
383 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
384 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
385 struct hns3_hw *hw = &hns->hw;
386 struct hns3_cmd_desc desc;
389 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
390 vlan_type != ETH_VLAN_TYPE_OUTER)) {
391 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
395 if (tpid != RTE_ETHER_TYPE_VLAN) {
396 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
400 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
401 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
403 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
404 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
405 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
406 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
407 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
408 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
409 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
410 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
413 ret = hns3_cmd_send(hw, &desc, 1);
415 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
420 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
422 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
423 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
424 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
426 ret = hns3_cmd_send(hw, &desc, 1);
428 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
434 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
437 struct hns3_adapter *hns = dev->data->dev_private;
438 struct hns3_hw *hw = &hns->hw;
441 rte_spinlock_lock(&hw->lock);
442 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
443 rte_spinlock_unlock(&hw->lock);
448 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
449 struct hns3_rx_vtag_cfg *vcfg)
451 struct hns3_vport_vtag_rx_cfg_cmd *req;
452 struct hns3_hw *hw = &hns->hw;
453 struct hns3_cmd_desc desc;
458 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
460 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
461 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
462 vcfg->strip_tag1_en ? 1 : 0);
463 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
464 vcfg->strip_tag2_en ? 1 : 0);
465 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
466 vcfg->vlan1_vlan_prionly ? 1 : 0);
467 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
468 vcfg->vlan2_vlan_prionly ? 1 : 0);
471 * In current version VF is not supported when PF is driven by DPDK
472 * driver, the PF-related vf_id is 0, just need to configure parameters
476 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
477 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
478 req->vf_bitmap[req->vf_offset] = bitmap;
480 ret = hns3_cmd_send(hw, &desc, 1);
482 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
488 struct hns3_rx_vtag_cfg *vcfg)
490 struct hns3_pf *pf = &hns->pf;
491 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
496 struct hns3_tx_vtag_cfg *vcfg)
498 struct hns3_pf *pf = &hns->pf;
499 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
505 struct hns3_rx_vtag_cfg rxvlan_cfg;
506 struct hns3_pf *pf = &hns->pf;
507 struct hns3_hw *hw = &hns->hw;
510 if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
511 rxvlan_cfg.strip_tag1_en = false;
512 rxvlan_cfg.strip_tag2_en = enable;
514 rxvlan_cfg.strip_tag1_en = enable;
515 rxvlan_cfg.strip_tag2_en = true;
518 rxvlan_cfg.vlan1_vlan_prionly = false;
519 rxvlan_cfg.vlan2_vlan_prionly = false;
520 rxvlan_cfg.rx_vlan_offload_en = enable;
522 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
524 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
528 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
534 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
535 uint8_t fe_type, bool filter_en, uint8_t vf_id)
537 struct hns3_vlan_filter_ctrl_cmd *req;
538 struct hns3_cmd_desc desc;
541 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
543 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
544 req->vlan_type = vlan_type;
545 req->vlan_fe = filter_en ? fe_type : 0;
548 ret = hns3_cmd_send(hw, &desc, 1);
550 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
556 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
558 struct hns3_hw *hw = &hns->hw;
561 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
562 HNS3_FILTER_FE_EGRESS, false, 0);
564 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
568 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
569 HNS3_FILTER_FE_INGRESS, enable, 0);
571 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
577 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
579 struct hns3_adapter *hns = dev->data->dev_private;
580 struct hns3_hw *hw = &hns->hw;
581 struct rte_eth_rxmode *rxmode;
582 unsigned int tmp_mask;
586 rte_spinlock_lock(&hw->lock);
587 rxmode = &dev->data->dev_conf.rxmode;
588 tmp_mask = (unsigned int)mask;
589 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
590 /* Enable or disable VLAN stripping */
591 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
594 ret = hns3_en_hw_strip_rxvtag(hns, enable);
596 rte_spinlock_unlock(&hw->lock);
597 hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
602 rte_spinlock_unlock(&hw->lock);
608 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
609 struct hns3_tx_vtag_cfg *vcfg)
611 struct hns3_vport_vtag_tx_cfg_cmd *req;
612 struct hns3_cmd_desc desc;
613 struct hns3_hw *hw = &hns->hw;
618 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
620 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
621 req->def_vlan_tag1 = vcfg->default_tag1;
622 req->def_vlan_tag2 = vcfg->default_tag2;
623 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
624 vcfg->accept_tag1 ? 1 : 0);
625 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
626 vcfg->accept_untag1 ? 1 : 0);
627 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
628 vcfg->accept_tag2 ? 1 : 0);
629 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
630 vcfg->accept_untag2 ? 1 : 0);
631 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
632 vcfg->insert_tag1_en ? 1 : 0);
633 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
634 vcfg->insert_tag2_en ? 1 : 0);
635 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
638 * In current version VF is not supported when PF is driven by DPDK
639 * driver, the PF-related vf_id is 0, just need to configure parameters
643 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
644 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
645 req->vf_bitmap[req->vf_offset] = bitmap;
647 ret = hns3_cmd_send(hw, &desc, 1);
649 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
655 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
658 struct hns3_hw *hw = &hns->hw;
659 struct hns3_tx_vtag_cfg txvlan_cfg;
662 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
663 txvlan_cfg.accept_tag1 = true;
664 txvlan_cfg.insert_tag1_en = false;
665 txvlan_cfg.default_tag1 = 0;
667 txvlan_cfg.accept_tag1 = false;
668 txvlan_cfg.insert_tag1_en = true;
669 txvlan_cfg.default_tag1 = pvid;
672 txvlan_cfg.accept_untag1 = true;
673 txvlan_cfg.accept_tag2 = true;
674 txvlan_cfg.accept_untag2 = true;
675 txvlan_cfg.insert_tag2_en = false;
676 txvlan_cfg.default_tag2 = 0;
678 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
680 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
685 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
690 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
692 struct hns3_pf *pf = &hns->pf;
694 pf->port_base_vlan_cfg.state = on ?
695 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
697 pf->port_base_vlan_cfg.pvid = pvid;
701 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
703 struct hns3_user_vlan_table *vlan_entry;
704 struct hns3_pf *pf = &hns->pf;
706 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
707 if (vlan_entry->hd_tbl_status)
708 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
710 vlan_entry->hd_tbl_status = false;
714 vlan_entry = LIST_FIRST(&pf->vlan_list);
716 LIST_REMOVE(vlan_entry, next);
717 rte_free(vlan_entry);
718 vlan_entry = LIST_FIRST(&pf->vlan_list);
724 hns3_add_all_vlan_table(struct hns3_adapter *hns)
726 struct hns3_user_vlan_table *vlan_entry;
727 struct hns3_pf *pf = &hns->pf;
729 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
730 if (!vlan_entry->hd_tbl_status)
731 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
733 vlan_entry->hd_tbl_status = true;
738 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
740 struct hns3_hw *hw = &hns->hw;
741 struct hns3_pf *pf = &hns->pf;
744 hns3_rm_all_vlan_table(hns, true);
745 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
746 ret = hns3_set_port_vlan_filter(hns,
747 pf->port_base_vlan_cfg.pvid, 0);
749 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
757 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
758 uint16_t port_base_vlan_state,
759 uint16_t new_pvid, uint16_t old_pvid)
761 struct hns3_pf *pf = &hns->pf;
762 struct hns3_hw *hw = &hns->hw;
765 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
766 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
767 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
770 "Failed to clear clear old pvid filter, ret =%d",
776 hns3_rm_all_vlan_table(hns, false);
777 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
781 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
783 hns3_err(hw, "Failed to set port vlan filter, ret =%d",
789 if (new_pvid == pf->port_base_vlan_cfg.pvid)
790 hns3_add_all_vlan_table(hns);
796 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
798 struct hns3_rx_vtag_cfg rx_vlan_cfg;
799 struct hns3_hw *hw = &hns->hw;
803 rx_strip_en = on ? true : false;
804 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
805 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
806 rx_vlan_cfg.vlan1_vlan_prionly = false;
807 rx_vlan_cfg.vlan2_vlan_prionly = false;
808 rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
810 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
812 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
816 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
821 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
823 struct hns3_pf *pf = &hns->pf;
824 struct hns3_hw *hw = &hns->hw;
825 uint16_t port_base_vlan_state;
829 if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
830 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
831 hns3_warn(hw, "Invalid operation! As current pvid set "
832 "is %u, disable pvid %u is invalid",
833 pf->port_base_vlan_cfg.pvid, pvid);
837 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
838 HNS3_PORT_BASE_VLAN_DISABLE;
839 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
841 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
845 ret = hns3_en_rx_strip_all(hns, on);
847 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
851 if (pvid == HNS3_INVLID_PVID)
853 old_pvid = pf->port_base_vlan_cfg.pvid;
854 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
857 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
863 hns3_store_port_base_vlan_info(hns, pvid, on);
868 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
870 struct hns3_adapter *hns = dev->data->dev_private;
871 struct hns3_hw *hw = &hns->hw;
874 rte_spinlock_lock(&hw->lock);
875 ret = hns3_vlan_pvid_configure(hns, pvid, on);
876 rte_spinlock_unlock(&hw->lock);
881 init_port_base_vlan_info(struct hns3_hw *hw)
883 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
884 struct hns3_pf *pf = &hns->pf;
886 pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
887 pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
891 hns3_default_vlan_config(struct hns3_adapter *hns)
893 struct hns3_hw *hw = &hns->hw;
896 ret = hns3_set_port_vlan_filter(hns, 0, 1);
898 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
903 hns3_init_vlan_config(struct hns3_adapter *hns)
905 struct hns3_hw *hw = &hns->hw;
909 * This function can be called in the initialization and reset process,
910 * when in reset process, it means that hardware had been reseted
911 * successfully and we need to restore the hardware configuration to
912 * ensure that the hardware configuration remains unchanged before and
915 if (rte_atomic16_read(&hw->reset.resetting) == 0)
916 init_port_base_vlan_info(hw);
918 ret = hns3_enable_vlan_filter(hns, true);
920 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
924 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
925 RTE_ETHER_TYPE_VLAN);
927 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
932 * When in the reinit dev stage of the reset process, the following
933 * vlan-related configurations may differ from those at initialization,
934 * we will restore configurations to hardware in hns3_restore_vlan_table
935 * and hns3_restore_vlan_conf later.
937 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
938 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
940 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
944 ret = hns3_en_hw_strip_rxvtag(hns, false);
946 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
952 return hns3_default_vlan_config(hns);
956 hns3_restore_vlan_conf(struct hns3_adapter *hns)
958 struct hns3_pf *pf = &hns->pf;
959 struct hns3_hw *hw = &hns->hw;
962 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
964 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
968 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
970 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
976 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
978 struct hns3_adapter *hns = dev->data->dev_private;
979 struct rte_eth_dev_data *data = dev->data;
980 struct rte_eth_txmode *txmode;
981 struct hns3_hw *hw = &hns->hw;
984 txmode = &data->dev_conf.txmode;
985 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
987 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
988 "configuration is not supported! Ignore these two "
989 "parameters: hw_vlan_reject_tagged(%d), "
990 "hw_vlan_reject_untagged(%d)",
991 txmode->hw_vlan_reject_tagged,
992 txmode->hw_vlan_reject_untagged);
994 /* Apply vlan offload setting */
995 ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
997 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1001 /* Apply pvid setting */
1002 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1003 txmode->hw_vlan_insert_pvid);
1005 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1012 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1013 unsigned int tso_mss_max)
1015 struct hns3_cfg_tso_status_cmd *req;
1016 struct hns3_cmd_desc desc;
1019 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1021 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1024 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1026 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1029 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1031 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1033 return hns3_cmd_send(hw, &desc, 1);
1037 hns3_config_gro(struct hns3_hw *hw, bool en)
1039 struct hns3_cfg_gro_status_cmd *req;
1040 struct hns3_cmd_desc desc;
1043 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1044 req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1046 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1048 ret = hns3_cmd_send(hw, &desc, 1);
1050 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1056 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1057 uint16_t *allocated_size, bool is_alloc)
1059 struct hns3_umv_spc_alc_cmd *req;
1060 struct hns3_cmd_desc desc;
1063 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1064 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1065 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1066 req->space_size = rte_cpu_to_le_32(space_size);
1068 ret = hns3_cmd_send(hw, &desc, 1);
1070 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1071 is_alloc ? "allocate" : "free", ret);
1075 if (is_alloc && allocated_size)
1076 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1082 hns3_init_umv_space(struct hns3_hw *hw)
1084 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1085 struct hns3_pf *pf = &hns->pf;
1086 uint16_t allocated_size = 0;
1089 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1094 if (allocated_size < pf->wanted_umv_size)
1095 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1096 pf->wanted_umv_size, allocated_size);
1098 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1099 pf->wanted_umv_size;
1100 pf->used_umv_size = 0;
1105 hns3_uninit_umv_space(struct hns3_hw *hw)
1107 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1108 struct hns3_pf *pf = &hns->pf;
1111 if (pf->max_umv_size == 0)
1114 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1118 pf->max_umv_size = 0;
1124 hns3_is_umv_space_full(struct hns3_hw *hw)
1126 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1127 struct hns3_pf *pf = &hns->pf;
1130 is_full = (pf->used_umv_size >= pf->max_umv_size);
1136 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1138 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1139 struct hns3_pf *pf = &hns->pf;
1142 if (pf->used_umv_size > 0)
1143 pf->used_umv_size--;
1145 pf->used_umv_size++;
1149 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1150 const uint8_t *addr, bool is_mc)
1152 const unsigned char *mac_addr = addr;
1153 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1154 ((uint32_t)mac_addr[2] << 16) |
1155 ((uint32_t)mac_addr[1] << 8) |
1156 (uint32_t)mac_addr[0];
1157 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1159 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1161 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1162 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1163 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1166 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1167 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1171 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1173 enum hns3_mac_vlan_tbl_opcode op)
1176 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1181 if (op == HNS3_MAC_VLAN_ADD) {
1182 if (resp_code == 0 || resp_code == 1) {
1184 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1185 hns3_err(hw, "add mac addr failed for uc_overflow");
1187 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1188 hns3_err(hw, "add mac addr failed for mc_overflow");
1192 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1195 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1196 if (resp_code == 0) {
1198 } else if (resp_code == 1) {
1199 hns3_dbg(hw, "remove mac addr failed for miss");
1203 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1206 } else if (op == HNS3_MAC_VLAN_LKUP) {
1207 if (resp_code == 0) {
1209 } else if (resp_code == 1) {
1210 hns3_dbg(hw, "lookup mac addr failed for miss");
1214 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1219 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1226 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1227 struct hns3_mac_vlan_tbl_entry_cmd *req,
1228 struct hns3_cmd_desc *desc, bool is_mc)
1234 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1236 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1237 memcpy(desc[0].data, req,
1238 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1239 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1241 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1242 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1244 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1246 memcpy(desc[0].data, req,
1247 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1248 ret = hns3_cmd_send(hw, desc, 1);
1251 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1255 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1256 retval = rte_le_to_cpu_16(desc[0].retval);
1258 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1259 HNS3_MAC_VLAN_LKUP);
1263 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1264 struct hns3_mac_vlan_tbl_entry_cmd *req,
1265 struct hns3_cmd_desc *mc_desc)
1272 if (mc_desc == NULL) {
1273 struct hns3_cmd_desc desc;
1275 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1276 memcpy(desc.data, req,
1277 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1278 ret = hns3_cmd_send(hw, &desc, 1);
1279 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1280 retval = rte_le_to_cpu_16(desc.retval);
1282 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1285 hns3_cmd_reuse_desc(&mc_desc[0], false);
1286 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1287 hns3_cmd_reuse_desc(&mc_desc[1], false);
1288 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1289 hns3_cmd_reuse_desc(&mc_desc[2], false);
1290 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1291 memcpy(mc_desc[0].data, req,
1292 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1293 mc_desc[0].retval = 0;
1294 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1295 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1296 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1298 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1303 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1311 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1312 struct hns3_mac_vlan_tbl_entry_cmd *req)
1314 struct hns3_cmd_desc desc;
1319 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1321 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1323 ret = hns3_cmd_send(hw, &desc, 1);
1325 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1328 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1329 retval = rte_le_to_cpu_16(desc.retval);
1331 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1332 HNS3_MAC_VLAN_REMOVE);
1336 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1338 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1339 struct hns3_mac_vlan_tbl_entry_cmd req;
1340 struct hns3_pf *pf = &hns->pf;
1341 struct hns3_cmd_desc desc;
1342 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1343 uint16_t egress_port = 0;
1347 /* check if mac addr is valid */
1348 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1349 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1351 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1356 memset(&req, 0, sizeof(req));
1359 * In current version VF is not supported when PF is driven by DPDK
1360 * driver, the PF-related vf_id is 0, just need to configure parameters
1364 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1365 HNS3_MAC_EPORT_VFID_S, vf_id);
1367 req.egress_port = rte_cpu_to_le_16(egress_port);
1369 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1372 * Lookup the mac address in the mac_vlan table, and add
1373 * it if the entry is inexistent. Repeated unicast entry
1374 * is not allowed in the mac vlan table.
1376 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1377 if (ret == -ENOENT) {
1378 if (!hns3_is_umv_space_full(hw)) {
1379 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1381 hns3_update_umv_space(hw, false);
1385 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1390 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1392 /* check if we just hit the duplicate */
1394 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1398 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1405 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1406 uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1408 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1412 rte_spinlock_lock(&hw->lock);
1413 ret = hns3_add_uc_addr_common(hw, mac_addr);
1415 rte_spinlock_unlock(&hw->lock);
1416 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1418 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1423 hw->mac.default_addr_setted = true;
1424 rte_spinlock_unlock(&hw->lock);
1430 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1432 struct hns3_mac_vlan_tbl_entry_cmd req;
1433 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1436 /* check if mac addr is valid */
1437 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1438 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1440 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1445 memset(&req, 0, sizeof(req));
1446 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1447 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1448 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1449 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1452 hns3_update_umv_space(hw, true);
1458 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1460 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461 /* index will be checked by upper level rte interface */
1462 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1463 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1466 rte_spinlock_lock(&hw->lock);
1467 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1469 rte_spinlock_unlock(&hw->lock);
1470 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1472 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1477 hw->mac.default_addr_setted = false;
1478 rte_spinlock_unlock(&hw->lock);
1482 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1483 struct rte_ether_addr *mac_addr)
1485 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486 struct rte_ether_addr *oaddr;
1487 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1488 bool default_addr_setted;
1489 bool rm_succes = false;
1492 /* check if mac addr is valid */
1493 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1494 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1496 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1501 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1502 default_addr_setted = hw->mac.default_addr_setted;
1503 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1506 rte_spinlock_lock(&hw->lock);
1507 if (default_addr_setted) {
1508 ret = hns3_remove_uc_addr_common(hw, oaddr);
1510 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1519 ret = hns3_add_uc_addr_common(hw, mac_addr);
1521 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1523 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1524 goto err_add_uc_addr;
1527 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1529 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1530 goto err_pause_addr_cfg;
1533 rte_ether_addr_copy(mac_addr,
1534 (struct rte_ether_addr *)hw->mac.mac_addr);
1535 hw->mac.default_addr_setted = true;
1536 rte_spinlock_unlock(&hw->lock);
1541 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1543 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1546 "Failed to roll back to del setted mac addr(%s): %d",
1552 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1554 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1557 "Failed to restore old uc mac addr(%s): %d",
1559 hw->mac.default_addr_setted = false;
1562 rte_spinlock_unlock(&hw->lock);
1568 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1570 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1571 struct hns3_hw *hw = &hns->hw;
1572 struct rte_ether_addr *addr;
1577 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1578 addr = &hw->data->mac_addrs[i];
1579 if (!rte_is_valid_assigned_ether_addr(addr))
1582 ret = hns3_remove_uc_addr_common(hw, addr);
1584 ret = hns3_add_uc_addr_common(hw, addr);
1587 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1590 "Failed to %s mac addr(%s). ret:%d i:%d",
1591 del ? "remove" : "restore", mac_str, ret, i);
1598 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1600 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1604 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1605 word_num = vfid / 32;
1606 bit_num = vfid % 32;
1608 desc[1].data[word_num] &=
1609 rte_cpu_to_le_32(~(1UL << bit_num));
1611 desc[1].data[word_num] |=
1612 rte_cpu_to_le_32(1UL << bit_num);
1614 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1615 bit_num = vfid % 32;
1617 desc[2].data[word_num] &=
1618 rte_cpu_to_le_32(~(1UL << bit_num));
1620 desc[2].data[word_num] |=
1621 rte_cpu_to_le_32(1UL << bit_num);
1626 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1628 struct hns3_mac_vlan_tbl_entry_cmd req;
1629 struct hns3_cmd_desc desc[3];
1630 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1634 /* Check if mac addr is valid */
1635 if (!rte_is_multicast_ether_addr(mac_addr)) {
1636 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1638 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1643 memset(&req, 0, sizeof(req));
1644 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1645 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1646 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1648 /* This mac addr do not exist, add new entry for it */
1649 memset(desc[0].data, 0, sizeof(desc[0].data));
1650 memset(desc[1].data, 0, sizeof(desc[0].data));
1651 memset(desc[2].data, 0, sizeof(desc[0].data));
1655 * In current version VF is not supported when PF is driven by DPDK
1656 * driver, the PF-related vf_id is 0, just need to configure parameters
1660 hns3_update_desc_vfid(desc, vf_id, false);
1661 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1664 hns3_err(hw, "mc mac vlan table is full");
1665 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1667 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1674 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1676 struct hns3_mac_vlan_tbl_entry_cmd req;
1677 struct hns3_cmd_desc desc[3];
1678 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1682 /* Check if mac addr is valid */
1683 if (!rte_is_multicast_ether_addr(mac_addr)) {
1684 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1686 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1691 memset(&req, 0, sizeof(req));
1692 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1693 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1694 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1697 * This mac addr exist, remove this handle's VFID for it.
1698 * In current version VF is not supported when PF is driven by
1699 * DPDK driver, the PF-related vf_id is 0, just need to
1700 * configure parameters for vf_id 0.
1703 hns3_update_desc_vfid(desc, vf_id, true);
1705 /* All the vfid is zero, so need to delete this entry */
1706 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1707 } else if (ret == -ENOENT) {
1708 /* This mac addr doesn't exist. */
1713 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1715 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1722 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1723 struct rte_ether_addr *mc_addr_set,
1724 uint32_t nb_mc_addr)
1726 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1727 struct rte_ether_addr *addr;
1731 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1732 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1733 "invalid. valid range: 0~%d",
1734 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1738 /* Check if input mac addresses are valid */
1739 for (i = 0; i < nb_mc_addr; i++) {
1740 addr = &mc_addr_set[i];
1741 if (!rte_is_multicast_ether_addr(addr)) {
1742 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1745 "Failed to set mc mac addr, addr(%s) invalid.",
1750 /* Check if there are duplicate addresses */
1751 for (j = i + 1; j < nb_mc_addr; j++) {
1752 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1753 rte_ether_format_addr(mac_str,
1754 RTE_ETHER_ADDR_FMT_SIZE,
1756 hns3_err(hw, "Failed to set mc mac addr, "
1757 "addrs invalid. two same addrs(%s).",
1768 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1769 struct rte_ether_addr *mc_addr_set,
1771 struct rte_ether_addr *reserved_addr_list,
1772 int *reserved_addr_num,
1773 struct rte_ether_addr *add_addr_list,
1775 struct rte_ether_addr *rm_addr_list,
1778 struct rte_ether_addr *addr;
1779 int current_addr_num;
1780 int reserved_num = 0;
1788 /* Calculate the mc mac address list that should be removed */
1789 current_addr_num = hw->mc_addrs_num;
1790 for (i = 0; i < current_addr_num; i++) {
1791 addr = &hw->mc_addrs[i];
1793 for (j = 0; j < mc_addr_num; j++) {
1794 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1801 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1804 rte_ether_addr_copy(addr,
1805 &reserved_addr_list[reserved_num]);
1810 /* Calculate the mc mac address list that should be added */
1811 for (i = 0; i < mc_addr_num; i++) {
1812 addr = &mc_addr_set[i];
1814 for (j = 0; j < current_addr_num; j++) {
1815 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1822 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1827 /* Reorder the mc mac address list maintained by driver */
1828 for (i = 0; i < reserved_num; i++)
1829 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1831 for (i = 0; i < rm_num; i++) {
1832 num = reserved_num + i;
1833 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1836 *reserved_addr_num = reserved_num;
1837 *add_addr_num = add_num;
1838 *rm_addr_num = rm_num;
1842 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1843 struct rte_ether_addr *mc_addr_set,
1844 uint32_t nb_mc_addr)
1846 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1848 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1849 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1850 struct rte_ether_addr *addr;
1851 int reserved_addr_num;
1859 /* Check if input parameters are valid */
1860 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1864 rte_spinlock_lock(&hw->lock);
1867 * Calculate the mc mac address lists those should be removed and be
1868 * added, Reorder the mc mac address list maintained by driver.
1870 mc_addr_num = (int)nb_mc_addr;
1871 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1872 reserved_addr_list, &reserved_addr_num,
1873 add_addr_list, &add_addr_num,
1874 rm_addr_list, &rm_addr_num);
1876 /* Remove mc mac addresses */
1877 for (i = 0; i < rm_addr_num; i++) {
1878 num = rm_addr_num - i - 1;
1879 addr = &rm_addr_list[num];
1880 ret = hns3_remove_mc_addr(hw, addr);
1882 rte_spinlock_unlock(&hw->lock);
1888 /* Add mc mac addresses */
1889 for (i = 0; i < add_addr_num; i++) {
1890 addr = &add_addr_list[i];
1891 ret = hns3_add_mc_addr(hw, addr);
1893 rte_spinlock_unlock(&hw->lock);
1897 num = reserved_addr_num + i;
1898 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1901 rte_spinlock_unlock(&hw->lock);
1907 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1909 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1910 struct hns3_hw *hw = &hns->hw;
1911 struct rte_ether_addr *addr;
1916 for (i = 0; i < hw->mc_addrs_num; i++) {
1917 addr = &hw->mc_addrs[i];
1918 if (!rte_is_multicast_ether_addr(addr))
1921 ret = hns3_remove_mc_addr(hw, addr);
1923 ret = hns3_add_mc_addr(hw, addr);
1926 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928 hns3_dbg(hw, "%s mc mac addr: %s failed",
1929 del ? "Remove" : "Restore", mac_str);
1936 hns3_check_mq_mode(struct rte_eth_dev *dev)
1938 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1939 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1940 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1942 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1943 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1948 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1949 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1951 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1952 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1953 "rx_mq_mode = %d", rx_mq_mode);
1957 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1958 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1959 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1960 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1961 rx_mq_mode, tx_mq_mode);
1965 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1966 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1967 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1968 dcb_rx_conf->nb_tcs, pf->tc_max);
1972 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1973 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1974 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1975 "nb_tcs(%d) != %d or %d in rx direction.",
1976 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1980 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1981 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1982 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1986 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1987 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1988 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1989 "is not equal to one in tx direction.",
1990 i, dcb_rx_conf->dcb_tc[i]);
1993 if (dcb_rx_conf->dcb_tc[i] > max_tc)
1994 max_tc = dcb_rx_conf->dcb_tc[i];
1997 num_tc = max_tc + 1;
1998 if (num_tc > dcb_rx_conf->nb_tcs) {
1999 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2000 num_tc, dcb_rx_conf->nb_tcs);
2009 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2011 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013 if (!hns3_dev_dcb_supported(hw)) {
2014 hns3_err(hw, "this port does not support dcb configurations.");
2018 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2019 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2023 /* Check multiple queue mode */
2024 return hns3_check_mq_mode(dev);
2028 hns3_bind_ring_with_vector(struct rte_eth_dev *dev, uint8_t vector_id,
2029 bool mmap, uint16_t queue_id)
2031 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032 struct hns3_cmd_desc desc;
2033 struct hns3_ctrl_vector_chain_cmd *req =
2034 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2035 enum hns3_cmd_status status;
2036 enum hns3_opcode_type op;
2037 uint16_t tqp_type_and_id = 0;
2039 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2040 hns3_cmd_setup_basic_desc(&desc, op, false);
2041 req->int_vector_id = vector_id;
2043 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2045 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2046 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2048 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2050 req->int_cause_num = 1;
2051 status = hns3_cmd_send(hw, &desc, 1);
2053 hns3_err(hw, "Map TQP %d fail, vector_id is %d, status is %d.",
2054 queue_id, vector_id, status);
2062 hns3_dev_configure(struct rte_eth_dev *dev)
2064 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2066 struct rte_eth_conf *conf = &dev->data->dev_conf;
2067 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2068 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2069 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2070 struct rte_eth_rss_conf rss_conf;
2075 * Hardware does not support where the number of rx and tx queues is
2076 * not equal in hip08.
2078 if (nb_rx_q != nb_tx_q) {
2080 "nb_rx_queues(%u) not equal with nb_tx_queues(%u)! "
2081 "Hardware does not support this configuration!",
2086 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2087 hns3_err(hw, "setting link speed/duplex not supported");
2091 hw->adapter_state = HNS3_NIC_CONFIGURING;
2092 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2093 ret = hns3_check_dcb_cfg(dev);
2098 /* When RSS is not configured, redirect the packet queue 0 */
2099 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2100 rss_conf = conf->rx_adv_conf.rss_conf;
2101 if (rss_conf.rss_key == NULL) {
2102 rss_conf.rss_key = rss_cfg->key;
2103 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2106 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2112 * If jumbo frames are enabled, MTU needs to be refreshed
2113 * according to the maximum RX packet length.
2115 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2117 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2118 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2119 * can safely assign to "uint16_t" type variable.
2121 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2122 ret = hns3_dev_mtu_set(dev, mtu);
2125 dev->data->mtu = mtu;
2128 ret = hns3_dev_configure_vlan(dev);
2132 hw->adapter_state = HNS3_NIC_CONFIGURED;
2137 hw->adapter_state = HNS3_NIC_INITIALIZED;
2142 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2144 struct hns3_config_max_frm_size_cmd *req;
2145 struct hns3_cmd_desc desc;
2147 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2149 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2150 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2151 req->min_frm_size = RTE_ETHER_MIN_LEN;
2153 return hns3_cmd_send(hw, &desc, 1);
2157 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2161 ret = hns3_set_mac_mtu(hw, mps);
2163 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2167 ret = hns3_buffer_alloc(hw);
2169 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2177 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2179 struct hns3_adapter *hns = dev->data->dev_private;
2180 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2181 struct hns3_hw *hw = &hns->hw;
2182 bool is_jumbo_frame;
2185 if (dev->data->dev_started) {
2186 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2187 "before configuration", dev->data->port_id);
2191 rte_spinlock_lock(&hw->lock);
2192 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2193 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2196 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2197 * assign to "uint16_t" type variable.
2199 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2201 rte_spinlock_unlock(&hw->lock);
2202 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2203 dev->data->port_id, mtu, ret);
2206 hns->pf.mps = (uint16_t)frame_size;
2208 dev->data->dev_conf.rxmode.offloads |=
2209 DEV_RX_OFFLOAD_JUMBO_FRAME;
2211 dev->data->dev_conf.rxmode.offloads &=
2212 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2213 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2214 rte_spinlock_unlock(&hw->lock);
2220 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2222 struct hns3_adapter *hns = eth_dev->data->dev_private;
2223 struct hns3_hw *hw = &hns->hw;
2225 info->max_rx_queues = hw->tqps_num;
2226 info->max_tx_queues = hw->tqps_num;
2227 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2228 info->min_rx_bufsize = hw->rx_buf_len;
2229 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2230 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2231 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2232 DEV_RX_OFFLOAD_TCP_CKSUM |
2233 DEV_RX_OFFLOAD_UDP_CKSUM |
2234 DEV_RX_OFFLOAD_SCTP_CKSUM |
2235 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2236 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2237 DEV_RX_OFFLOAD_KEEP_CRC |
2238 DEV_RX_OFFLOAD_SCATTER |
2239 DEV_RX_OFFLOAD_VLAN_STRIP |
2240 DEV_RX_OFFLOAD_QINQ_STRIP |
2241 DEV_RX_OFFLOAD_VLAN_FILTER |
2242 DEV_RX_OFFLOAD_VLAN_EXTEND |
2243 DEV_RX_OFFLOAD_JUMBO_FRAME);
2244 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2245 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2246 DEV_TX_OFFLOAD_IPV4_CKSUM |
2247 DEV_TX_OFFLOAD_TCP_CKSUM |
2248 DEV_TX_OFFLOAD_UDP_CKSUM |
2249 DEV_TX_OFFLOAD_SCTP_CKSUM |
2250 DEV_TX_OFFLOAD_VLAN_INSERT |
2251 DEV_TX_OFFLOAD_QINQ_INSERT |
2252 DEV_TX_OFFLOAD_MULTI_SEGS |
2253 info->tx_queue_offload_capa);
2255 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2256 .nb_max = HNS3_MAX_RING_DESC,
2257 .nb_min = HNS3_MIN_RING_DESC,
2258 .nb_align = HNS3_ALIGN_RING_DESC,
2261 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2262 .nb_max = HNS3_MAX_RING_DESC,
2263 .nb_min = HNS3_MIN_RING_DESC,
2264 .nb_align = HNS3_ALIGN_RING_DESC,
2267 info->vmdq_queue_num = 0;
2269 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2270 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2271 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2273 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2274 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2275 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2276 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2277 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2278 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2284 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2287 struct hns3_adapter *hns = eth_dev->data->dev_private;
2288 struct hns3_hw *hw = &hns->hw;
2291 ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2292 ret += 1; /* add the size of '\0' */
2293 if (fw_size < (uint32_t)ret)
2300 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2301 __rte_unused int wait_to_complete)
2303 struct hns3_adapter *hns = eth_dev->data->dev_private;
2304 struct hns3_hw *hw = &hns->hw;
2305 struct hns3_mac *mac = &hw->mac;
2306 struct rte_eth_link new_link;
2308 if (!hns3_is_reset_pending(hns)) {
2309 hns3_update_speed_duplex(eth_dev);
2310 hns3_update_link_status(hw);
2313 memset(&new_link, 0, sizeof(new_link));
2314 switch (mac->link_speed) {
2315 case ETH_SPEED_NUM_10M:
2316 case ETH_SPEED_NUM_100M:
2317 case ETH_SPEED_NUM_1G:
2318 case ETH_SPEED_NUM_10G:
2319 case ETH_SPEED_NUM_25G:
2320 case ETH_SPEED_NUM_40G:
2321 case ETH_SPEED_NUM_50G:
2322 case ETH_SPEED_NUM_100G:
2323 new_link.link_speed = mac->link_speed;
2326 new_link.link_speed = ETH_SPEED_NUM_100M;
2330 new_link.link_duplex = mac->link_duplex;
2331 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2332 new_link.link_autoneg =
2333 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2335 return rte_eth_linkstatus_set(eth_dev, &new_link);
2339 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2341 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2342 struct hns3_pf *pf = &hns->pf;
2344 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2347 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2353 hns3_query_function_status(struct hns3_hw *hw)
2355 #define HNS3_QUERY_MAX_CNT 10
2356 #define HNS3_QUERY_SLEEP_MSCOEND 1
2357 struct hns3_func_status_cmd *req;
2358 struct hns3_cmd_desc desc;
2362 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2363 req = (struct hns3_func_status_cmd *)desc.data;
2366 ret = hns3_cmd_send(hw, &desc, 1);
2368 PMD_INIT_LOG(ERR, "query function status failed %d",
2373 /* Check pf reset is done */
2377 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2378 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2380 return hns3_parse_func_status(hw, req);
2384 hns3_query_pf_resource(struct hns3_hw *hw)
2386 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2387 struct hns3_pf *pf = &hns->pf;
2388 struct hns3_pf_res_cmd *req;
2389 struct hns3_cmd_desc desc;
2392 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2393 ret = hns3_cmd_send(hw, &desc, 1);
2395 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2399 req = (struct hns3_pf_res_cmd *)desc.data;
2400 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2401 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2402 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2404 if (req->tx_buf_size)
2406 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2408 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2410 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2412 if (req->dv_buf_size)
2414 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2416 pf->dv_buf_size = HNS3_DEFAULT_DV;
2418 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2421 hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2422 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2428 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2430 struct hns3_cfg_param_cmd *req;
2431 uint64_t mac_addr_tmp_high;
2432 uint64_t mac_addr_tmp;
2435 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2437 /* get the configuration */
2438 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2439 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2440 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2441 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2442 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2443 HNS3_CFG_TQP_DESC_N_M,
2444 HNS3_CFG_TQP_DESC_N_S);
2446 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2447 HNS3_CFG_PHY_ADDR_M,
2448 HNS3_CFG_PHY_ADDR_S);
2449 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2450 HNS3_CFG_MEDIA_TP_M,
2451 HNS3_CFG_MEDIA_TP_S);
2452 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2453 HNS3_CFG_RX_BUF_LEN_M,
2454 HNS3_CFG_RX_BUF_LEN_S);
2455 /* get mac address */
2456 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2457 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2458 HNS3_CFG_MAC_ADDR_H_M,
2459 HNS3_CFG_MAC_ADDR_H_S);
2461 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2463 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2464 HNS3_CFG_DEFAULT_SPEED_M,
2465 HNS3_CFG_DEFAULT_SPEED_S);
2466 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2467 HNS3_CFG_RSS_SIZE_M,
2468 HNS3_CFG_RSS_SIZE_S);
2470 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2471 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2473 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2474 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2476 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2477 HNS3_CFG_SPEED_ABILITY_M,
2478 HNS3_CFG_SPEED_ABILITY_S);
2479 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2480 HNS3_CFG_UMV_TBL_SPACE_M,
2481 HNS3_CFG_UMV_TBL_SPACE_S);
2482 if (!cfg->umv_space)
2483 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2486 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2487 * @hw: pointer to struct hns3_hw
2488 * @hcfg: the config structure to be getted
2491 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2493 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2494 struct hns3_cfg_param_cmd *req;
2499 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2501 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2502 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2504 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2505 i * HNS3_CFG_RD_LEN_BYTES);
2506 /* Len should be divided by 4 when send to hardware */
2507 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2508 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2509 req->offset = rte_cpu_to_le_32(offset);
2512 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2514 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2518 hns3_parse_cfg(hcfg, desc);
2524 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2526 switch (speed_cmd) {
2527 case HNS3_CFG_SPEED_10M:
2528 *speed = ETH_SPEED_NUM_10M;
2530 case HNS3_CFG_SPEED_100M:
2531 *speed = ETH_SPEED_NUM_100M;
2533 case HNS3_CFG_SPEED_1G:
2534 *speed = ETH_SPEED_NUM_1G;
2536 case HNS3_CFG_SPEED_10G:
2537 *speed = ETH_SPEED_NUM_10G;
2539 case HNS3_CFG_SPEED_25G:
2540 *speed = ETH_SPEED_NUM_25G;
2542 case HNS3_CFG_SPEED_40G:
2543 *speed = ETH_SPEED_NUM_40G;
2545 case HNS3_CFG_SPEED_50G:
2546 *speed = ETH_SPEED_NUM_50G;
2548 case HNS3_CFG_SPEED_100G:
2549 *speed = ETH_SPEED_NUM_100G;
2559 hns3_get_board_configuration(struct hns3_hw *hw)
2561 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2562 struct hns3_pf *pf = &hns->pf;
2563 struct hns3_cfg cfg;
2566 ret = hns3_get_board_cfg(hw, &cfg);
2568 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2572 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2573 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2577 hw->mac.media_type = cfg.media_type;
2578 hw->rss_size_max = cfg.rss_size_max;
2579 hw->rx_buf_len = cfg.rx_buf_len;
2580 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2581 hw->mac.phy_addr = cfg.phy_addr;
2582 hw->mac.default_addr_setted = false;
2583 hw->num_tx_desc = cfg.tqp_desc_num;
2584 hw->num_rx_desc = cfg.tqp_desc_num;
2585 hw->dcb_info.num_pg = 1;
2586 hw->dcb_info.hw_pfc_map = 0;
2588 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2590 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2591 cfg.default_speed, ret);
2595 pf->tc_max = cfg.tc_num;
2596 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2597 PMD_INIT_LOG(WARNING,
2598 "Get TC num(%u) from flash, set TC num to 1",
2603 /* Dev does not support DCB */
2604 if (!hns3_dev_dcb_supported(hw)) {
2608 pf->pfc_max = pf->tc_max;
2610 hw->dcb_info.num_tc = 1;
2611 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2612 hw->tqps_num / hw->dcb_info.num_tc);
2613 hns3_set_bit(hw->hw_tc_map, 0, 1);
2614 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2616 pf->wanted_umv_size = cfg.umv_space;
2622 hns3_get_configuration(struct hns3_hw *hw)
2626 ret = hns3_query_function_status(hw);
2628 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2632 /* Get pf resource */
2633 ret = hns3_query_pf_resource(hw);
2635 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2639 ret = hns3_get_board_configuration(hw);
2641 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2649 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2650 uint16_t tqp_vid, bool is_pf)
2652 struct hns3_tqp_map_cmd *req;
2653 struct hns3_cmd_desc desc;
2656 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2658 req = (struct hns3_tqp_map_cmd *)desc.data;
2659 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2660 req->tqp_vf = func_id;
2661 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2663 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2664 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2666 ret = hns3_cmd_send(hw, &desc, 1);
2668 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2674 hns3_map_tqp(struct hns3_hw *hw)
2676 uint16_t tqps_num = hw->total_tqps_num;
2684 * In current version VF is not supported when PF is driven by DPDK
2685 * driver, so we allocate tqps to PF as much as possible.
2688 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2689 for (func_id = 0; func_id < num; func_id++) {
2691 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2692 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2703 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2705 struct hns3_config_mac_speed_dup_cmd *req;
2706 struct hns3_cmd_desc desc;
2709 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2711 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2713 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2716 case ETH_SPEED_NUM_10M:
2717 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2718 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2720 case ETH_SPEED_NUM_100M:
2721 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2722 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2724 case ETH_SPEED_NUM_1G:
2725 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2726 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2728 case ETH_SPEED_NUM_10G:
2729 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2730 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2732 case ETH_SPEED_NUM_25G:
2733 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2734 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2736 case ETH_SPEED_NUM_40G:
2737 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2738 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2740 case ETH_SPEED_NUM_50G:
2741 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2742 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2744 case ETH_SPEED_NUM_100G:
2745 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2746 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2749 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2753 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2755 ret = hns3_cmd_send(hw, &desc, 1);
2757 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2763 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2765 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2766 struct hns3_pf *pf = &hns->pf;
2767 struct hns3_priv_buf *priv;
2768 uint32_t i, total_size;
2770 total_size = pf->pkt_buf_size;
2772 /* alloc tx buffer for all enabled tc */
2773 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2774 priv = &buf_alloc->priv_buf[i];
2776 if (hw->hw_tc_map & BIT(i)) {
2777 if (total_size < pf->tx_buf_size)
2780 priv->tx_buf_size = pf->tx_buf_size;
2782 priv->tx_buf_size = 0;
2784 total_size -= priv->tx_buf_size;
2791 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2793 /* TX buffer size is unit by 128 byte */
2794 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
2795 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
2796 struct hns3_tx_buff_alloc_cmd *req;
2797 struct hns3_cmd_desc desc;
2802 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2804 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2805 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2806 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2808 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2809 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2810 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2813 ret = hns3_cmd_send(hw, &desc, 1);
2815 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2821 hns3_get_tc_num(struct hns3_hw *hw)
2826 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2827 if (hw->hw_tc_map & BIT(i))
2833 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2835 struct hns3_priv_buf *priv;
2836 uint32_t rx_priv = 0;
2839 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2840 priv = &buf_alloc->priv_buf[i];
2842 rx_priv += priv->buf_size;
2848 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2850 uint32_t total_tx_size = 0;
2853 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2854 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2856 return total_tx_size;
2859 /* Get the number of pfc enabled TCs, which have private buffer */
2861 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2863 struct hns3_priv_buf *priv;
2867 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2868 priv = &buf_alloc->priv_buf[i];
2869 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2876 /* Get the number of pfc disabled TCs, which have private buffer */
2878 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2879 struct hns3_pkt_buf_alloc *buf_alloc)
2881 struct hns3_priv_buf *priv;
2885 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2886 priv = &buf_alloc->priv_buf[i];
2887 if (hw->hw_tc_map & BIT(i) &&
2888 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2896 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2899 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2900 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2901 struct hns3_pf *pf = &hns->pf;
2902 uint32_t shared_buf, aligned_mps;
2907 tc_num = hns3_get_tc_num(hw);
2908 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2910 if (hns3_dev_dcb_supported(hw))
2911 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2914 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2917 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2918 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2919 HNS3_BUF_SIZE_UNIT);
2921 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2922 if (rx_all < rx_priv + shared_std)
2925 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2926 buf_alloc->s_buf.buf_size = shared_buf;
2927 if (hns3_dev_dcb_supported(hw)) {
2928 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2929 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2930 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2931 HNS3_BUF_SIZE_UNIT);
2933 buf_alloc->s_buf.self.high =
2934 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2935 buf_alloc->s_buf.self.low = aligned_mps;
2938 if (hns3_dev_dcb_supported(hw)) {
2939 hi_thrd = shared_buf - pf->dv_buf_size;
2941 if (tc_num <= NEED_RESERVE_TC_NUM)
2942 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2946 hi_thrd = hi_thrd / tc_num;
2948 hi_thrd = max_t(uint32_t, hi_thrd,
2949 HNS3_BUF_MUL_BY * aligned_mps);
2950 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2951 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2953 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2954 lo_thrd = aligned_mps;
2957 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2958 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2959 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2966 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2967 struct hns3_pkt_buf_alloc *buf_alloc)
2969 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2970 struct hns3_pf *pf = &hns->pf;
2971 struct hns3_priv_buf *priv;
2972 uint32_t aligned_mps;
2976 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2977 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2979 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2980 priv = &buf_alloc->priv_buf[i];
2987 if (!(hw->hw_tc_map & BIT(i)))
2991 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
2992 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
2993 priv->wl.high = roundup(priv->wl.low + aligned_mps,
2994 HNS3_BUF_SIZE_UNIT);
2997 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3001 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3004 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3008 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3009 struct hns3_pkt_buf_alloc *buf_alloc)
3011 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3012 struct hns3_pf *pf = &hns->pf;
3013 struct hns3_priv_buf *priv;
3014 int no_pfc_priv_num;
3019 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3020 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3022 /* let the last to be cleared first */
3023 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3024 priv = &buf_alloc->priv_buf[i];
3025 mask = BIT((uint8_t)i);
3027 if (hw->hw_tc_map & mask &&
3028 !(hw->dcb_info.hw_pfc_map & mask)) {
3029 /* Clear the no pfc TC private buffer */
3037 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3038 no_pfc_priv_num == 0)
3042 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3046 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3047 struct hns3_pkt_buf_alloc *buf_alloc)
3049 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3050 struct hns3_pf *pf = &hns->pf;
3051 struct hns3_priv_buf *priv;
3057 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3058 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3060 /* let the last to be cleared first */
3061 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3062 priv = &buf_alloc->priv_buf[i];
3063 mask = BIT((uint8_t)i);
3065 if (hw->hw_tc_map & mask &&
3066 hw->dcb_info.hw_pfc_map & mask) {
3067 /* Reduce the number of pfc TC with private buffer */
3074 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3079 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3083 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3084 struct hns3_pkt_buf_alloc *buf_alloc)
3086 #define COMPENSATE_BUFFER 0x3C00
3087 #define COMPENSATE_HALF_MPS_NUM 5
3088 #define PRIV_WL_GAP 0x1800
3089 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3090 struct hns3_pf *pf = &hns->pf;
3091 uint32_t tc_num = hns3_get_tc_num(hw);
3092 uint32_t half_mps = pf->mps >> 1;
3093 struct hns3_priv_buf *priv;
3094 uint32_t min_rx_priv;
3098 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3100 rx_priv = rx_priv / tc_num;
3102 if (tc_num <= NEED_RESERVE_TC_NUM)
3103 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3106 * Minimum value of private buffer in rx direction (min_rx_priv) is
3107 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3108 * buffer if rx_priv is greater than min_rx_priv.
3110 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3111 COMPENSATE_HALF_MPS_NUM * half_mps;
3112 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3113 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3115 if (rx_priv < min_rx_priv)
3118 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3119 priv = &buf_alloc->priv_buf[i];
3126 if (!(hw->hw_tc_map & BIT(i)))
3130 priv->buf_size = rx_priv;
3131 priv->wl.high = rx_priv - pf->dv_buf_size;
3132 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3135 buf_alloc->s_buf.buf_size = 0;
3141 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3142 * @hw: pointer to struct hns3_hw
3143 * @buf_alloc: pointer to buffer calculation data
3144 * @return: 0: calculate sucessful, negative: fail
3147 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3149 /* When DCB is not supported, rx private buffer is not allocated. */
3150 if (!hns3_dev_dcb_supported(hw)) {
3151 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3152 struct hns3_pf *pf = &hns->pf;
3153 uint32_t rx_all = pf->pkt_buf_size;
3155 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3156 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3163 * Try to allocate privated packet buffer for all TCs without share
3166 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3170 * Try to allocate privated packet buffer for all TCs with share
3173 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3177 * For different application scenes, the enabled port number, TC number
3178 * and no_drop TC number are different. In order to obtain the better
3179 * performance, software could allocate the buffer size and configure
3180 * the waterline by tring to decrease the private buffer size according
3181 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3184 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3187 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3190 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3197 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3199 struct hns3_rx_priv_buff_cmd *req;
3200 struct hns3_cmd_desc desc;
3205 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3206 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3208 /* Alloc private buffer TCs */
3209 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3210 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3213 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3214 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3217 buf_size = buf_alloc->s_buf.buf_size;
3218 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3219 (1 << HNS3_TC0_PRI_BUF_EN_B));
3221 ret = hns3_cmd_send(hw, &desc, 1);
3223 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3229 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3231 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3232 struct hns3_rx_priv_wl_buf *req;
3233 struct hns3_priv_buf *priv;
3234 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3238 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3239 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3241 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3243 /* The first descriptor set the NEXT bit to 1 */
3245 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3247 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3249 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3250 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3252 priv = &buf_alloc->priv_buf[idx];
3253 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3255 req->tc_wl[j].high |=
3256 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3257 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3259 req->tc_wl[j].low |=
3260 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3264 /* Send 2 descriptor at one time */
3265 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3267 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3273 hns3_common_thrd_config(struct hns3_hw *hw,
3274 struct hns3_pkt_buf_alloc *buf_alloc)
3276 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3277 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3278 struct hns3_rx_com_thrd *req;
3279 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3280 struct hns3_tc_thrd *tc;
3285 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3286 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3288 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3290 /* The first descriptor set the NEXT bit to 1 */
3292 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3294 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3296 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3297 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3298 tc = &s_buf->tc_thrd[tc_idx];
3300 req->com_thrd[j].high =
3301 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3302 req->com_thrd[j].high |=
3303 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3304 req->com_thrd[j].low =
3305 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3306 req->com_thrd[j].low |=
3307 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3311 /* Send 2 descriptors at one time */
3312 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3314 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3320 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3322 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3323 struct hns3_rx_com_wl *req;
3324 struct hns3_cmd_desc desc;
3327 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3329 req = (struct hns3_rx_com_wl *)desc.data;
3330 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3331 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3333 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3334 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3336 ret = hns3_cmd_send(hw, &desc, 1);
3338 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3344 hns3_buffer_alloc(struct hns3_hw *hw)
3346 struct hns3_pkt_buf_alloc pkt_buf;
3349 memset(&pkt_buf, 0, sizeof(pkt_buf));
3350 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3353 "could not calc tx buffer size for all TCs %d",
3358 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3360 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3364 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3367 "could not calc rx priv buffer size for all TCs %d",
3372 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3374 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3378 if (hns3_dev_dcb_supported(hw)) {
3379 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3382 "could not configure rx private waterline %d",
3387 ret = hns3_common_thrd_config(hw, &pkt_buf);
3390 "could not configure common threshold %d",
3396 ret = hns3_common_wl_config(hw, &pkt_buf);
3398 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3405 hns3_mac_init(struct hns3_hw *hw)
3407 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3408 struct hns3_mac *mac = &hw->mac;
3409 struct hns3_pf *pf = &hns->pf;
3412 pf->support_sfp_query = true;
3413 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3414 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3416 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3420 mac->link_status = ETH_LINK_DOWN;
3422 return hns3_config_mtu(hw, pf->mps);
3426 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3428 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3429 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3430 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3431 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3436 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3441 switch (resp_code) {
3442 case HNS3_ETHERTYPE_SUCCESS_ADD:
3443 case HNS3_ETHERTYPE_ALREADY_ADD:
3446 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3448 "add mac ethertype failed for manager table overflow.");
3449 return_status = -EIO;
3451 case HNS3_ETHERTYPE_KEY_CONFLICT:
3452 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3453 return_status = -EIO;
3457 "add mac ethertype failed for undefined, code=%d.",
3459 return_status = -EIO;
3462 return return_status;
3466 hns3_add_mgr_tbl(struct hns3_hw *hw,
3467 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3469 struct hns3_cmd_desc desc;
3474 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3475 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3477 ret = hns3_cmd_send(hw, &desc, 1);
3480 "add mac ethertype failed for cmd_send, ret =%d.",
3485 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3486 retval = rte_le_to_cpu_16(desc.retval);
3488 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3492 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3493 int *table_item_num)
3495 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3498 * In current version, we add one item in management table as below:
3499 * 0x0180C200000E -- LLDP MC address
3502 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3503 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3504 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3505 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3506 tbl->i_port_bitmap = 0x1;
3507 *table_item_num = 1;
3511 hns3_init_mgr_tbl(struct hns3_hw *hw)
3513 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3514 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3519 memset(mgr_table, 0, sizeof(mgr_table));
3520 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3521 for (i = 0; i < table_item_num; i++) {
3522 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3524 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3534 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3535 bool en_mc, bool en_bc, int vport_id)
3540 memset(param, 0, sizeof(struct hns3_promisc_param));
3542 param->enable = HNS3_PROMISC_EN_UC;
3544 param->enable |= HNS3_PROMISC_EN_MC;
3546 param->enable |= HNS3_PROMISC_EN_BC;
3547 param->vf_id = vport_id;
3551 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3553 struct hns3_promisc_cfg_cmd *req;
3554 struct hns3_cmd_desc desc;
3557 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3559 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3560 req->vf_id = param->vf_id;
3561 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3562 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3564 ret = hns3_cmd_send(hw, &desc, 1);
3566 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3572 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3574 struct hns3_promisc_param param;
3575 bool en_bc_pmc = true;
3580 * In current version VF is not supported when PF is driven by DPDK
3581 * driver, the PF-related vf_id is 0, just need to configure parameters
3586 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3587 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3595 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3597 struct hns3_adapter *hns = dev->data->dev_private;
3598 struct hns3_hw *hw = &hns->hw;
3599 bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3602 rte_spinlock_lock(&hw->lock);
3603 ret = hns3_set_promisc_mode(hw, true, en_mc_pmc);
3604 rte_spinlock_unlock(&hw->lock);
3606 hns3_err(hw, "Failed to enable promiscuous mode: %d", ret);
3612 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3614 struct hns3_adapter *hns = dev->data->dev_private;
3615 struct hns3_hw *hw = &hns->hw;
3616 bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3619 /* If now in all_multicast mode, must remain in all_multicast mode. */
3620 rte_spinlock_lock(&hw->lock);
3621 ret = hns3_set_promisc_mode(hw, false, en_mc_pmc);
3622 rte_spinlock_unlock(&hw->lock);
3624 hns3_err(hw, "Failed to disable promiscuous mode: %d", ret);
3630 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3632 struct hns3_adapter *hns = dev->data->dev_private;
3633 struct hns3_hw *hw = &hns->hw;
3634 bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3637 rte_spinlock_lock(&hw->lock);
3638 ret = hns3_set_promisc_mode(hw, en_uc_pmc, true);
3639 rte_spinlock_unlock(&hw->lock);
3641 hns3_err(hw, "Failed to enable allmulticast mode: %d", ret);
3647 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3649 struct hns3_adapter *hns = dev->data->dev_private;
3650 struct hns3_hw *hw = &hns->hw;
3651 bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3654 /* If now in promiscuous mode, must remain in all_multicast mode. */
3655 if (dev->data->promiscuous == 1)
3658 rte_spinlock_lock(&hw->lock);
3659 ret = hns3_set_promisc_mode(hw, en_uc_pmc, false);
3660 rte_spinlock_unlock(&hw->lock);
3662 hns3_err(hw, "Failed to disable allmulticast mode: %d", ret);
3668 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3670 struct hns3_hw *hw = &hns->hw;
3674 en_uc_pmc = (hw->data->promiscuous == 1) ? true : false;
3675 en_mc_pmc = (hw->data->all_multicast == 1) ? true : false;
3677 return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);
3681 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3683 struct hns3_sfp_speed_cmd *resp;
3684 struct hns3_cmd_desc desc;
3687 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3688 resp = (struct hns3_sfp_speed_cmd *)desc.data;
3689 ret = hns3_cmd_send(hw, &desc, 1);
3690 if (ret == -EOPNOTSUPP) {
3691 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3694 hns3_err(hw, "get sfp speed failed %d", ret);
3698 *speed = resp->sfp_speed;
3704 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3706 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3707 duplex = ETH_LINK_FULL_DUPLEX;
3713 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3715 struct hns3_mac *mac = &hw->mac;
3718 duplex = hns3_check_speed_dup(duplex, speed);
3719 if (mac->link_speed == speed && mac->link_duplex == duplex)
3722 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3726 mac->link_speed = speed;
3727 mac->link_duplex = duplex;
3733 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3735 struct hns3_adapter *hns = eth_dev->data->dev_private;
3736 struct hns3_hw *hw = &hns->hw;
3737 struct hns3_pf *pf = &hns->pf;
3741 /* If IMP do not support get SFP/qSFP speed, return directly */
3742 if (!pf->support_sfp_query)
3745 ret = hns3_get_sfp_speed(hw, &speed);
3746 if (ret == -EOPNOTSUPP) {
3747 pf->support_sfp_query = false;
3752 if (speed == ETH_SPEED_NUM_NONE)
3753 return 0; /* do nothing if no SFP */
3755 /* Config full duplex for SFP */
3756 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3760 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3762 struct hns3_config_mac_mode_cmd *req;
3763 struct hns3_cmd_desc desc;
3764 uint32_t loop_en = 0;
3768 req = (struct hns3_config_mac_mode_cmd *)desc.data;
3770 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3773 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3774 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3775 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3776 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3777 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3778 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3779 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3780 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3781 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3782 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3783 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3784 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3785 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3786 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3787 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3789 ret = hns3_cmd_send(hw, &desc, 1);
3791 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3797 hns3_get_mac_link_status(struct hns3_hw *hw)
3799 struct hns3_link_status_cmd *req;
3800 struct hns3_cmd_desc desc;
3804 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3805 ret = hns3_cmd_send(hw, &desc, 1);
3807 hns3_err(hw, "get link status cmd failed %d", ret);
3811 req = (struct hns3_link_status_cmd *)desc.data;
3812 link_status = req->status & HNS3_LINK_STATUS_UP_M;
3814 return !!link_status;
3818 hns3_update_link_status(struct hns3_hw *hw)
3822 state = hns3_get_mac_link_status(hw);
3823 if (state != hw->mac.link_status) {
3824 hw->mac.link_status = state;
3825 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3830 hns3_service_handler(void *param)
3832 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3833 struct hns3_adapter *hns = eth_dev->data->dev_private;
3834 struct hns3_hw *hw = &hns->hw;
3836 if (!hns3_is_reset_pending(hns)) {
3837 hns3_update_speed_duplex(eth_dev);
3838 hns3_update_link_status(hw);
3840 hns3_warn(hw, "Cancel the query when reset is pending");
3842 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3846 hns3_init_hardware(struct hns3_adapter *hns)
3848 struct hns3_hw *hw = &hns->hw;
3851 ret = hns3_map_tqp(hw);
3853 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3857 ret = hns3_init_umv_space(hw);
3859 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3863 ret = hns3_mac_init(hw);
3865 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3869 ret = hns3_init_mgr_tbl(hw);
3871 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3875 ret = hns3_set_promisc_mode(hw, false, false);
3877 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3881 ret = hns3_init_vlan_config(hns);
3883 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3887 ret = hns3_dcb_init(hw);
3889 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3893 ret = hns3_init_fd_config(hns);
3895 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3899 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3901 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3905 ret = hns3_config_gro(hw, false);
3907 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3913 hns3_uninit_umv_space(hw);
3918 hns3_init_pf(struct rte_eth_dev *eth_dev)
3920 struct rte_device *dev = eth_dev->device;
3921 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3922 struct hns3_adapter *hns = eth_dev->data->dev_private;
3923 struct hns3_hw *hw = &hns->hw;
3926 PMD_INIT_FUNC_TRACE();
3928 /* Get hardware io base address from pcie BAR2 IO space */
3929 hw->io_base = pci_dev->mem_resource[2].addr;
3931 /* Firmware command queue initialize */
3932 ret = hns3_cmd_init_queue(hw);
3934 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3935 goto err_cmd_init_queue;
3938 hns3_clear_all_event_cause(hw);
3940 /* Firmware command initialize */
3941 ret = hns3_cmd_init(hw);
3943 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3947 ret = rte_intr_callback_register(&pci_dev->intr_handle,
3948 hns3_interrupt_handler,
3951 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
3952 goto err_intr_callback_register;
3955 /* Enable interrupt */
3956 rte_intr_enable(&pci_dev->intr_handle);
3957 hns3_pf_enable_irq0(hw);
3959 /* Get configuration */
3960 ret = hns3_get_configuration(hw);
3962 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
3963 goto err_get_config;
3966 ret = hns3_init_hardware(hns);
3968 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
3969 goto err_get_config;
3972 /* Initialize flow director filter list & hash */
3973 ret = hns3_fdir_filter_init(hns);
3975 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
3979 hns3_set_default_rss_args(hw);
3981 ret = hns3_enable_hw_error_intr(hns, true);
3983 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
3991 hns3_fdir_filter_uninit(hns);
3993 hns3_uninit_umv_space(hw);
3996 hns3_pf_disable_irq0(hw);
3997 rte_intr_disable(&pci_dev->intr_handle);
3998 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4001 err_intr_callback_register:
4002 hns3_cmd_uninit(hw);
4005 hns3_cmd_destroy_queue(hw);
4014 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4016 struct hns3_adapter *hns = eth_dev->data->dev_private;
4017 struct rte_device *dev = eth_dev->device;
4018 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4019 struct hns3_hw *hw = &hns->hw;
4021 PMD_INIT_FUNC_TRACE();
4023 hns3_enable_hw_error_intr(hns, false);
4024 hns3_rss_uninit(hns);
4025 hns3_fdir_filter_uninit(hns);
4026 hns3_uninit_umv_space(hw);
4027 hns3_pf_disable_irq0(hw);
4028 rte_intr_disable(&pci_dev->intr_handle);
4029 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4031 hns3_cmd_uninit(hw);
4032 hns3_cmd_destroy_queue(hw);
4037 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4039 struct hns3_hw *hw = &hns->hw;
4042 ret = hns3_dcb_cfg_update(hns);
4047 ret = hns3_start_queues(hns, reset_queue);
4049 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4054 ret = hns3_cfg_mac_mode(hw, true);
4056 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4057 goto err_config_mac_mode;
4061 err_config_mac_mode:
4062 hns3_stop_queues(hns, true);
4067 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4069 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4070 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4071 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4072 uint32_t intr_vector;
4078 if (dev->data->dev_conf.intr_conf.rxq == 0)
4081 /* disable uio/vfio intr/eventfd mapping */
4082 rte_intr_disable(intr_handle);
4084 /* check and configure queue intr-vector mapping */
4085 if (rte_intr_cap_multiple(intr_handle) ||
4086 !RTE_ETH_DEV_SRIOV(dev).active) {
4087 intr_vector = dev->data->nb_rx_queues;
4088 /* creates event fd for each intr vector when MSIX is used */
4089 if (rte_intr_efd_enable(intr_handle, intr_vector))
4092 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4093 intr_handle->intr_vec =
4094 rte_zmalloc("intr_vec",
4095 dev->data->nb_rx_queues * sizeof(int), 0);
4096 if (intr_handle->intr_vec == NULL) {
4097 hns3_err(hw, "Failed to allocate %d rx_queues"
4098 " intr_vec", dev->data->nb_rx_queues);
4100 goto alloc_intr_vec_error;
4104 if (rte_intr_allow_others(intr_handle)) {
4105 vec = RTE_INTR_VEC_RXTX_OFFSET;
4106 base = RTE_INTR_VEC_RXTX_OFFSET;
4108 if (rte_intr_dp_is_en(intr_handle)) {
4109 for (q_id = 0; q_id < dev->data->nb_rx_queues; q_id++) {
4110 ret = hns3_bind_ring_with_vector(dev, vec, true, q_id);
4112 goto bind_vector_error;
4113 intr_handle->intr_vec[q_id] = vec;
4114 if (vec < base + intr_handle->nb_efd - 1)
4118 rte_intr_enable(intr_handle);
4122 rte_intr_efd_disable(intr_handle);
4123 if (intr_handle->intr_vec) {
4124 free(intr_handle->intr_vec);
4125 intr_handle->intr_vec = NULL;
4128 alloc_intr_vec_error:
4129 rte_intr_efd_disable(intr_handle);
4134 hns3_dev_start(struct rte_eth_dev *dev)
4136 struct hns3_adapter *hns = dev->data->dev_private;
4137 struct hns3_hw *hw = &hns->hw;
4140 PMD_INIT_FUNC_TRACE();
4141 if (rte_atomic16_read(&hw->reset.resetting))
4144 rte_spinlock_lock(&hw->lock);
4145 hw->adapter_state = HNS3_NIC_STARTING;
4147 ret = hns3_do_start(hns, true);
4149 hw->adapter_state = HNS3_NIC_CONFIGURED;
4150 rte_spinlock_unlock(&hw->lock);
4154 hw->adapter_state = HNS3_NIC_STARTED;
4155 rte_spinlock_unlock(&hw->lock);
4157 ret = hns3_map_rx_interrupt(dev);
4160 hns3_set_rxtx_function(dev);
4161 hns3_mp_req_start_rxtx(dev);
4163 hns3_info(hw, "hns3 dev start successful!");
4168 hns3_do_stop(struct hns3_adapter *hns)
4170 struct hns3_hw *hw = &hns->hw;
4174 ret = hns3_cfg_mac_mode(hw, false);
4177 hw->mac.link_status = ETH_LINK_DOWN;
4179 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4180 hns3_configure_all_mac_addr(hns, true);
4183 reset_queue = false;
4184 hw->mac.default_addr_setted = false;
4185 return hns3_stop_queues(hns, reset_queue);
4189 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4191 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4192 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4197 if (dev->data->dev_conf.intr_conf.rxq == 0)
4200 /* unmap the ring with vector */
4201 if (rte_intr_allow_others(intr_handle)) {
4202 vec = RTE_INTR_VEC_RXTX_OFFSET;
4203 base = RTE_INTR_VEC_RXTX_OFFSET;
4205 if (rte_intr_dp_is_en(intr_handle)) {
4206 for (q_id = 0; q_id < dev->data->nb_rx_queues; q_id++) {
4207 (void)hns3_bind_ring_with_vector(dev, vec, false, q_id);
4208 if (vec < base + intr_handle->nb_efd - 1)
4212 /* Clean datapath event and queue/vec mapping */
4213 rte_intr_efd_disable(intr_handle);
4214 if (intr_handle->intr_vec) {
4215 rte_free(intr_handle->intr_vec);
4216 intr_handle->intr_vec = NULL;
4221 hns3_dev_stop(struct rte_eth_dev *dev)
4223 struct hns3_adapter *hns = dev->data->dev_private;
4224 struct hns3_hw *hw = &hns->hw;
4226 PMD_INIT_FUNC_TRACE();
4228 hw->adapter_state = HNS3_NIC_STOPPING;
4229 hns3_set_rxtx_function(dev);
4231 /* Disable datapath on secondary process. */
4232 hns3_mp_req_stop_rxtx(dev);
4233 /* Prevent crashes when queues are still in use. */
4234 rte_delay_ms(hw->tqps_num);
4236 rte_spinlock_lock(&hw->lock);
4237 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4239 hns3_dev_release_mbufs(hns);
4240 hw->adapter_state = HNS3_NIC_CONFIGURED;
4242 rte_spinlock_unlock(&hw->lock);
4243 hns3_unmap_rx_interrupt(dev);
4247 hns3_dev_close(struct rte_eth_dev *eth_dev)
4249 struct hns3_adapter *hns = eth_dev->data->dev_private;
4250 struct hns3_hw *hw = &hns->hw;
4252 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4253 rte_free(eth_dev->process_private);
4254 eth_dev->process_private = NULL;
4258 if (hw->adapter_state == HNS3_NIC_STARTED)
4259 hns3_dev_stop(eth_dev);
4261 hw->adapter_state = HNS3_NIC_CLOSING;
4262 hns3_reset_abort(hns);
4263 hw->adapter_state = HNS3_NIC_CLOSED;
4264 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4266 hns3_configure_all_mc_mac_addr(hns, true);
4267 hns3_remove_all_vlan_table(hns);
4268 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4269 hns3_uninit_pf(eth_dev);
4270 hns3_free_all_queues(eth_dev);
4271 rte_free(hw->reset.wait_data);
4272 rte_free(eth_dev->process_private);
4273 eth_dev->process_private = NULL;
4274 hns3_mp_uninit_primary();
4275 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4279 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4281 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4284 fc_conf->pause_time = pf->pause_time;
4286 /* return fc current mode */
4287 switch (hw->current_mode) {
4289 fc_conf->mode = RTE_FC_FULL;
4291 case HNS3_FC_TX_PAUSE:
4292 fc_conf->mode = RTE_FC_TX_PAUSE;
4294 case HNS3_FC_RX_PAUSE:
4295 fc_conf->mode = RTE_FC_RX_PAUSE;
4299 fc_conf->mode = RTE_FC_NONE;
4307 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4311 hw->requested_mode = HNS3_FC_NONE;
4313 case RTE_FC_RX_PAUSE:
4314 hw->requested_mode = HNS3_FC_RX_PAUSE;
4316 case RTE_FC_TX_PAUSE:
4317 hw->requested_mode = HNS3_FC_TX_PAUSE;
4320 hw->requested_mode = HNS3_FC_FULL;
4323 hw->requested_mode = HNS3_FC_NONE;
4324 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4325 "configured to RTE_FC_NONE", mode);
4331 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4333 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4334 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4337 if (fc_conf->high_water || fc_conf->low_water ||
4338 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4339 hns3_err(hw, "Unsupported flow control settings specified, "
4340 "high_water(%u), low_water(%u), send_xon(%u) and "
4341 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4342 fc_conf->high_water, fc_conf->low_water,
4343 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4346 if (fc_conf->autoneg) {
4347 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4350 if (!fc_conf->pause_time) {
4351 hns3_err(hw, "Invalid pause time %d setting.",
4352 fc_conf->pause_time);
4356 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4357 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4358 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4359 "current_fc_status = %d", hw->current_fc_status);
4363 hns3_get_fc_mode(hw, fc_conf->mode);
4364 if (hw->requested_mode == hw->current_mode &&
4365 pf->pause_time == fc_conf->pause_time)
4368 rte_spinlock_lock(&hw->lock);
4369 ret = hns3_fc_enable(dev, fc_conf);
4370 rte_spinlock_unlock(&hw->lock);
4376 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4377 struct rte_eth_pfc_conf *pfc_conf)
4379 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4380 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4384 if (!hns3_dev_dcb_supported(hw)) {
4385 hns3_err(hw, "This port does not support dcb configurations.");
4389 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4390 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4391 hns3_err(hw, "Unsupported flow control settings specified, "
4392 "high_water(%u), low_water(%u), send_xon(%u) and "
4393 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4394 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4395 pfc_conf->fc.send_xon,
4396 pfc_conf->fc.mac_ctrl_frame_fwd);
4399 if (pfc_conf->fc.autoneg) {
4400 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4403 if (pfc_conf->fc.pause_time == 0) {
4404 hns3_err(hw, "Invalid pause time %d setting.",
4405 pfc_conf->fc.pause_time);
4409 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4410 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4411 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4412 "current_fc_status = %d", hw->current_fc_status);
4416 priority = pfc_conf->priority;
4417 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4418 if (hw->dcb_info.pfc_en & BIT(priority) &&
4419 hw->requested_mode == hw->current_mode &&
4420 pfc_conf->fc.pause_time == pf->pause_time)
4423 rte_spinlock_lock(&hw->lock);
4424 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4425 rte_spinlock_unlock(&hw->lock);
4431 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4433 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4434 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4435 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4438 rte_spinlock_lock(&hw->lock);
4439 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4440 dcb_info->nb_tcs = pf->local_max_tc;
4442 dcb_info->nb_tcs = 1;
4444 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4445 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4446 for (i = 0; i < dcb_info->nb_tcs; i++)
4447 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4449 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4450 dcb_info->tc_queue.tc_rxq[0][i].base =
4451 hw->tc_queue[i].tqp_offset;
4452 dcb_info->tc_queue.tc_txq[0][i].base =
4453 hw->tc_queue[i].tqp_offset;
4454 dcb_info->tc_queue.tc_rxq[0][i].nb_queue =
4455 hw->tc_queue[i].tqp_count;
4456 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4457 hw->tc_queue[i].tqp_count;
4459 rte_spinlock_unlock(&hw->lock);
4465 hns3_reinit_dev(struct hns3_adapter *hns)
4467 struct hns3_hw *hw = &hns->hw;
4470 ret = hns3_cmd_init(hw);
4472 hns3_err(hw, "Failed to init cmd: %d", ret);
4476 ret = hns3_reset_all_queues(hns);
4478 hns3_err(hw, "Failed to reset all queues: %d", ret);
4482 ret = hns3_init_hardware(hns);
4484 hns3_err(hw, "Failed to init hardware: %d", ret);
4488 ret = hns3_enable_hw_error_intr(hns, true);
4490 hns3_err(hw, "fail to enable hw error interrupts: %d",
4494 hns3_info(hw, "Reset done, driver initialization finished.");
4499 hns3_uninit_umv_space(hw);
4501 hns3_cmd_uninit(hw);
4507 is_pf_reset_done(struct hns3_hw *hw)
4509 uint32_t val, reg, reg_bit;
4511 switch (hw->reset.level) {
4512 case HNS3_IMP_RESET:
4513 reg = HNS3_GLOBAL_RESET_REG;
4514 reg_bit = HNS3_IMP_RESET_BIT;
4516 case HNS3_GLOBAL_RESET:
4517 reg = HNS3_GLOBAL_RESET_REG;
4518 reg_bit = HNS3_GLOBAL_RESET_BIT;
4520 case HNS3_FUNC_RESET:
4521 reg = HNS3_FUN_RST_ING;
4522 reg_bit = HNS3_FUN_RST_ING_B;
4524 case HNS3_FLR_RESET:
4526 hns3_err(hw, "Wait for unsupported reset level: %d",
4530 val = hns3_read_dev(hw, reg);
4531 if (hns3_get_bit(val, reg_bit))
4538 hns3_is_reset_pending(struct hns3_adapter *hns)
4540 struct hns3_hw *hw = &hns->hw;
4541 enum hns3_reset_level reset;
4543 hns3_check_event_cause(hns, NULL);
4544 reset = hns3_get_reset_level(hns, &hw->reset.pending);
4545 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4546 hns3_warn(hw, "High level reset %d is pending", reset);
4549 reset = hns3_get_reset_level(hns, &hw->reset.request);
4550 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4551 hns3_warn(hw, "High level reset %d is request", reset);
4558 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4560 struct hns3_hw *hw = &hns->hw;
4561 struct hns3_wait_data *wait_data = hw->reset.wait_data;
4564 if (wait_data->result == HNS3_WAIT_SUCCESS)
4566 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4567 gettimeofday(&tv, NULL);
4568 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4569 tv.tv_sec, tv.tv_usec);
4571 } else if (wait_data->result == HNS3_WAIT_REQUEST)
4574 wait_data->hns = hns;
4575 wait_data->check_completion = is_pf_reset_done;
4576 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4577 HNS3_RESET_WAIT_MS + get_timeofday_ms();
4578 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4579 wait_data->count = HNS3_RESET_WAIT_CNT;
4580 wait_data->result = HNS3_WAIT_REQUEST;
4581 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4586 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4588 struct hns3_cmd_desc desc;
4589 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4591 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4592 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4593 req->fun_reset_vfid = func_id;
4595 return hns3_cmd_send(hw, &desc, 1);
4599 hns3_imp_reset_cmd(struct hns3_hw *hw)
4601 struct hns3_cmd_desc desc;
4603 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4604 desc.data[0] = 0xeedd;
4606 return hns3_cmd_send(hw, &desc, 1);
4610 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4612 struct hns3_hw *hw = &hns->hw;
4616 gettimeofday(&tv, NULL);
4617 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4618 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4619 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4620 tv.tv_sec, tv.tv_usec);
4624 switch (reset_level) {
4625 case HNS3_IMP_RESET:
4626 hns3_imp_reset_cmd(hw);
4627 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4628 tv.tv_sec, tv.tv_usec);
4630 case HNS3_GLOBAL_RESET:
4631 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4632 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4633 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4634 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4635 tv.tv_sec, tv.tv_usec);
4637 case HNS3_FUNC_RESET:
4638 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4639 tv.tv_sec, tv.tv_usec);
4640 /* schedule again to check later */
4641 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4642 hns3_schedule_reset(hns);
4645 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4648 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4651 static enum hns3_reset_level
4652 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4654 struct hns3_hw *hw = &hns->hw;
4655 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4657 /* Return the highest priority reset level amongst all */
4658 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4659 reset_level = HNS3_IMP_RESET;
4660 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4661 reset_level = HNS3_GLOBAL_RESET;
4662 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4663 reset_level = HNS3_FUNC_RESET;
4664 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4665 reset_level = HNS3_FLR_RESET;
4667 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4668 return HNS3_NONE_RESET;
4674 hns3_prepare_reset(struct hns3_adapter *hns)
4676 struct hns3_hw *hw = &hns->hw;
4680 switch (hw->reset.level) {
4681 case HNS3_FUNC_RESET:
4682 ret = hns3_func_reset_cmd(hw, 0);
4687 * After performaning pf reset, it is not necessary to do the
4688 * mailbox handling or send any command to firmware, because
4689 * any mailbox handling or command to firmware is only valid
4690 * after hns3_cmd_init is called.
4692 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4693 hw->reset.stats.request_cnt++;
4695 case HNS3_IMP_RESET:
4696 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4697 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4698 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4707 hns3_set_rst_done(struct hns3_hw *hw)
4709 struct hns3_pf_rst_done_cmd *req;
4710 struct hns3_cmd_desc desc;
4712 req = (struct hns3_pf_rst_done_cmd *)desc.data;
4713 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4714 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4715 return hns3_cmd_send(hw, &desc, 1);
4719 hns3_stop_service(struct hns3_adapter *hns)
4721 struct hns3_hw *hw = &hns->hw;
4722 struct rte_eth_dev *eth_dev;
4724 eth_dev = &rte_eth_devices[hw->data->port_id];
4725 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4726 hw->mac.link_status = ETH_LINK_DOWN;
4728 hns3_set_rxtx_function(eth_dev);
4730 /* Disable datapath on secondary process. */
4731 hns3_mp_req_stop_rxtx(eth_dev);
4732 rte_delay_ms(hw->tqps_num);
4734 rte_spinlock_lock(&hw->lock);
4735 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4736 hw->adapter_state == HNS3_NIC_STOPPING) {
4738 hw->reset.mbuf_deferred_free = true;
4740 hw->reset.mbuf_deferred_free = false;
4743 * It is cumbersome for hardware to pick-and-choose entries for deletion
4744 * from table space. Hence, for function reset software intervention is
4745 * required to delete the entries
4747 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4748 hns3_configure_all_mc_mac_addr(hns, true);
4749 rte_spinlock_unlock(&hw->lock);
4755 hns3_start_service(struct hns3_adapter *hns)
4757 struct hns3_hw *hw = &hns->hw;
4758 struct rte_eth_dev *eth_dev;
4760 if (hw->reset.level == HNS3_IMP_RESET ||
4761 hw->reset.level == HNS3_GLOBAL_RESET)
4762 hns3_set_rst_done(hw);
4763 eth_dev = &rte_eth_devices[hw->data->port_id];
4764 hns3_set_rxtx_function(eth_dev);
4765 hns3_mp_req_start_rxtx(eth_dev);
4766 hns3_service_handler(eth_dev);
4771 hns3_restore_conf(struct hns3_adapter *hns)
4773 struct hns3_hw *hw = &hns->hw;
4776 ret = hns3_configure_all_mac_addr(hns, false);
4780 ret = hns3_configure_all_mc_mac_addr(hns, false);
4784 ret = hns3_dev_promisc_restore(hns);
4788 ret = hns3_restore_vlan_table(hns);
4792 ret = hns3_restore_vlan_conf(hns);
4796 ret = hns3_restore_all_fdir_filter(hns);
4800 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4801 ret = hns3_do_start(hns, false);
4804 hns3_info(hw, "hns3 dev restart successful!");
4805 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4806 hw->adapter_state = HNS3_NIC_CONFIGURED;
4810 hns3_configure_all_mc_mac_addr(hns, true);
4812 hns3_configure_all_mac_addr(hns, true);
4817 hns3_reset_service(void *param)
4819 struct hns3_adapter *hns = (struct hns3_adapter *)param;
4820 struct hns3_hw *hw = &hns->hw;
4821 enum hns3_reset_level reset_level;
4822 struct timeval tv_delta;
4823 struct timeval tv_start;
4829 * The interrupt is not triggered within the delay time.
4830 * The interrupt may have been lost. It is necessary to handle
4831 * the interrupt to recover from the error.
4833 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4834 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4835 hns3_err(hw, "Handling interrupts in delayed tasks");
4836 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4837 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4838 if (reset_level == HNS3_NONE_RESET) {
4839 hns3_err(hw, "No reset level is set, try IMP reset");
4840 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4843 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4846 * Check if there is any ongoing reset in the hardware. This status can
4847 * be checked from reset_pending. If there is then, we need to wait for
4848 * hardware to complete reset.
4849 * a. If we are able to figure out in reasonable time that hardware
4850 * has fully resetted then, we can proceed with driver, client
4852 * b. else, we can come back later to check this status so re-sched
4855 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4856 if (reset_level != HNS3_NONE_RESET) {
4857 gettimeofday(&tv_start, NULL);
4858 ret = hns3_reset_process(hns, reset_level);
4859 gettimeofday(&tv, NULL);
4860 timersub(&tv, &tv_start, &tv_delta);
4861 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4862 tv_delta.tv_usec / USEC_PER_MSEC;
4863 if (msec > HNS3_RESET_PROCESS_MS)
4864 hns3_err(hw, "%d handle long time delta %" PRIx64
4865 " ms time=%ld.%.6ld",
4866 hw->reset.level, msec,
4867 tv.tv_sec, tv.tv_usec);
4872 /* Check if we got any *new* reset requests to be honored */
4873 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
4874 if (reset_level != HNS3_NONE_RESET)
4875 hns3_msix_process(hns, reset_level);
4878 static const struct eth_dev_ops hns3_eth_dev_ops = {
4879 .dev_start = hns3_dev_start,
4880 .dev_stop = hns3_dev_stop,
4881 .dev_close = hns3_dev_close,
4882 .promiscuous_enable = hns3_dev_promiscuous_enable,
4883 .promiscuous_disable = hns3_dev_promiscuous_disable,
4884 .allmulticast_enable = hns3_dev_allmulticast_enable,
4885 .allmulticast_disable = hns3_dev_allmulticast_disable,
4886 .mtu_set = hns3_dev_mtu_set,
4887 .stats_get = hns3_stats_get,
4888 .stats_reset = hns3_stats_reset,
4889 .xstats_get = hns3_dev_xstats_get,
4890 .xstats_get_names = hns3_dev_xstats_get_names,
4891 .xstats_reset = hns3_dev_xstats_reset,
4892 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
4893 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
4894 .dev_infos_get = hns3_dev_infos_get,
4895 .fw_version_get = hns3_fw_version_get,
4896 .rx_queue_setup = hns3_rx_queue_setup,
4897 .tx_queue_setup = hns3_tx_queue_setup,
4898 .rx_queue_release = hns3_dev_rx_queue_release,
4899 .tx_queue_release = hns3_dev_tx_queue_release,
4900 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
4901 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
4902 .dev_configure = hns3_dev_configure,
4903 .flow_ctrl_get = hns3_flow_ctrl_get,
4904 .flow_ctrl_set = hns3_flow_ctrl_set,
4905 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
4906 .mac_addr_add = hns3_add_mac_addr,
4907 .mac_addr_remove = hns3_remove_mac_addr,
4908 .mac_addr_set = hns3_set_default_mac_addr,
4909 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
4910 .link_update = hns3_dev_link_update,
4911 .rss_hash_update = hns3_dev_rss_hash_update,
4912 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
4913 .reta_update = hns3_dev_rss_reta_update,
4914 .reta_query = hns3_dev_rss_reta_query,
4915 .filter_ctrl = hns3_dev_filter_ctrl,
4916 .vlan_filter_set = hns3_vlan_filter_set,
4917 .vlan_tpid_set = hns3_vlan_tpid_set,
4918 .vlan_offload_set = hns3_vlan_offload_set,
4919 .vlan_pvid_set = hns3_vlan_pvid_set,
4920 .get_reg = hns3_get_regs,
4921 .get_dcb_info = hns3_get_dcb_info,
4922 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
4925 static const struct hns3_reset_ops hns3_reset_ops = {
4926 .reset_service = hns3_reset_service,
4927 .stop_service = hns3_stop_service,
4928 .prepare_reset = hns3_prepare_reset,
4929 .wait_hardware_ready = hns3_wait_hardware_ready,
4930 .reinit_dev = hns3_reinit_dev,
4931 .restore_conf = hns3_restore_conf,
4932 .start_service = hns3_start_service,
4936 hns3_dev_init(struct rte_eth_dev *eth_dev)
4938 struct rte_device *dev = eth_dev->device;
4939 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4940 struct hns3_adapter *hns = eth_dev->data->dev_private;
4941 struct hns3_hw *hw = &hns->hw;
4942 uint16_t device_id = pci_dev->id.device_id;
4945 PMD_INIT_FUNC_TRACE();
4946 eth_dev->process_private = (struct hns3_process_private *)
4947 rte_zmalloc_socket("hns3_filter_list",
4948 sizeof(struct hns3_process_private),
4949 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
4950 if (eth_dev->process_private == NULL) {
4951 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
4954 /* initialize flow filter lists */
4955 hns3_filterlist_init(eth_dev);
4957 hns3_set_rxtx_function(eth_dev);
4958 eth_dev->dev_ops = &hns3_eth_dev_ops;
4959 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4960 hns3_mp_init_secondary();
4961 hw->secondary_cnt++;
4965 hns3_mp_init_primary();
4966 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
4968 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
4969 device_id == HNS3_DEV_ID_50GE_RDMA ||
4970 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
4971 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
4974 hw->data = eth_dev->data;
4977 * Set default max packet size according to the mtu
4978 * default vale in DPDK frame.
4980 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
4982 ret = hns3_reset_init(hw);
4984 goto err_init_reset;
4985 hw->reset.ops = &hns3_reset_ops;
4987 ret = hns3_init_pf(eth_dev);
4989 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
4993 /* Allocate memory for storing MAC addresses */
4994 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
4995 sizeof(struct rte_ether_addr) *
4996 HNS3_UC_MACADDR_NUM, 0);
4997 if (eth_dev->data->mac_addrs == NULL) {
4998 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
4999 "to store MAC addresses",
5000 sizeof(struct rte_ether_addr) *
5001 HNS3_UC_MACADDR_NUM);
5003 goto err_rte_zmalloc;
5006 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5007 ð_dev->data->mac_addrs[0]);
5009 hw->adapter_state = HNS3_NIC_INITIALIZED;
5011 * Pass the information to the rte_eth_dev_close() that it should also
5012 * release the private port resources.
5014 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5016 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5017 hns3_err(hw, "Reschedule reset service after dev_init");
5018 hns3_schedule_reset(hns);
5020 /* IMP will wait ready flag before reset */
5021 hns3_notify_reset_ready(hw, false);
5024 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
5025 hns3_info(hw, "hns3 dev initialization successful!");
5029 hns3_uninit_pf(eth_dev);
5032 rte_free(hw->reset.wait_data);
5034 eth_dev->dev_ops = NULL;
5035 eth_dev->rx_pkt_burst = NULL;
5036 eth_dev->tx_pkt_burst = NULL;
5037 eth_dev->tx_pkt_prepare = NULL;
5038 rte_free(eth_dev->process_private);
5039 eth_dev->process_private = NULL;
5044 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5046 struct hns3_adapter *hns = eth_dev->data->dev_private;
5047 struct hns3_hw *hw = &hns->hw;
5049 PMD_INIT_FUNC_TRACE();
5051 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5054 eth_dev->dev_ops = NULL;
5055 eth_dev->rx_pkt_burst = NULL;
5056 eth_dev->tx_pkt_burst = NULL;
5057 eth_dev->tx_pkt_prepare = NULL;
5058 if (hw->adapter_state < HNS3_NIC_CLOSING)
5059 hns3_dev_close(eth_dev);
5061 hw->adapter_state = HNS3_NIC_REMOVED;
5066 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5067 struct rte_pci_device *pci_dev)
5069 return rte_eth_dev_pci_generic_probe(pci_dev,
5070 sizeof(struct hns3_adapter),
5075 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5077 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5080 static const struct rte_pci_id pci_id_hns3_map[] = {
5081 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5082 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5083 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5084 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5085 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5086 { .vendor_id = 0, /* sentinel */ },
5089 static struct rte_pci_driver rte_hns3_pmd = {
5090 .id_table = pci_id_hns3_map,
5091 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5092 .probe = eth_hns3_pci_probe,
5093 .remove = eth_hns3_pci_remove,
5096 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5097 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5098 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5100 RTE_INIT(hns3_init_log)
5102 hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5103 if (hns3_logtype_init >= 0)
5104 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5105 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5106 if (hns3_logtype_driver >= 0)
5107 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);