drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8
   9 #include "hns3_ethdev.h"
  10 #include "hns3_common.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17 #include "hns3_flow.h"
  18
  19 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  20 #define HNS3_SERVICE_QUICK_INTERVAL     10
  21 #define HNS3_INVALID_PVID               0xFFFF
  22
  23 #define HNS3_FILTER_TYPE_VF             0
  24 #define HNS3_FILTER_TYPE_PORT           1
  25 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  26 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  27 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  28 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  29 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  30 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  31                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  32 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  34
  35 /* Reset related Registers */
  36 #define HNS3_GLOBAL_RESET_BIT           0
  37 #define HNS3_CORE_RESET_BIT             1
  38 #define HNS3_IMP_RESET_BIT              2
  39 #define HNS3_FUN_RST_ING_B              0
  40
  41 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  43 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  45
  46 #define HNS3_RESET_WAIT_MS      100
  47 #define HNS3_RESET_WAIT_CNT     200
  48
  49 /* FEC mode order defined in HNS3 hardware */
  50 #define HNS3_HW_FEC_MODE_NOFEC  0
  51 #define HNS3_HW_FEC_MODE_BASER  1
  52 #define HNS3_HW_FEC_MODE_RS     2
  53
  54 enum hns3_evt_cause {
  55         HNS3_VECTOR0_EVENT_RST,
  56         HNS3_VECTOR0_EVENT_MBX,
  57         HNS3_VECTOR0_EVENT_ERR,
  58         HNS3_VECTOR0_EVENT_PTP,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  96 static bool hns3_update_link_status(struct hns3_hw *hw);
  97
  98 static int hns3_add_mc_mac_addr(struct hns3_hw *hw,
  99                                 struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 101                                    struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 104 static int hns3_do_stop(struct hns3_adapter *hns);
 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
 107
 108
 109 static void
 110 hns3_pf_disable_irq0(struct hns3_hw *hw)
 111 {
 112         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 113 }
 114
 115 static void
 116 hns3_pf_enable_irq0(struct hns3_hw *hw)
 117 {
 118         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 119 }
 120
 121 static enum hns3_evt_cause
 122 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 123                           uint32_t *vec_val)
 124 {
 125         struct hns3_hw *hw = &hns->hw;
 126
 127         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 128         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 129         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 130         if (!is_delay) {
 131                 hw->reset.stats.imp_cnt++;
 132                 hns3_warn(hw, "IMP reset detected, clear reset status");
 133         } else {
 134                 hns3_schedule_delayed_reset(hns);
 135                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 136         }
 137
 138         return HNS3_VECTOR0_EVENT_RST;
 139 }
 140
 141 static enum hns3_evt_cause
 142 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 143                              uint32_t *vec_val)
 144 {
 145         struct hns3_hw *hw = &hns->hw;
 146
 147         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 148         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 149         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 150         if (!is_delay) {
 151                 hw->reset.stats.global_cnt++;
 152                 hns3_warn(hw, "Global reset detected, clear reset status");
 153         } else {
 154                 hns3_schedule_delayed_reset(hns);
 155                 hns3_warn(hw,
 156                           "Global reset detected, don't clear reset status");
 157         }
 158
 159         return HNS3_VECTOR0_EVENT_RST;
 160 }
 161
 162 static enum hns3_evt_cause
 163 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 164 {
 165         struct hns3_hw *hw = &hns->hw;
 166         uint32_t vector0_int_stats;
 167         uint32_t cmdq_src_val;
 168         uint32_t hw_err_src_reg;
 169         uint32_t val;
 170         enum hns3_evt_cause ret;
 171         bool is_delay;
 172
 173         /* fetch the events from their corresponding regs */
 174         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 175         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 176         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 177
 178         is_delay = clearval == NULL ? true : false;
 179         /*
 180          * Assumption: If by any chance reset and mailbox events are reported
 181          * together then we will only process reset event and defer the
 182          * processing of the mailbox events. Since, we would have not cleared
 183          * RX CMDQ event this time we would receive again another interrupt
 184          * from H/W just for the mailbox.
 185          */
 186         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 187                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 188                 goto out;
 189         }
 190
 191         /* Global reset */
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 193                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 194                 goto out;
 195         }
 196
 197         /* Check for vector0 1588 event source */
 198         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 199                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 200                 ret = HNS3_VECTOR0_EVENT_PTP;
 201                 goto out;
 202         }
 203
 204         /* check for vector0 msix event source */
 205         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 206             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 207                 val = vector0_int_stats | hw_err_src_reg;
 208                 ret = HNS3_VECTOR0_EVENT_ERR;
 209                 goto out;
 210         }
 211
 212         /* check for vector0 mailbox(=CMDQ RX) event source */
 213         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 214                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 215                 val = cmdq_src_val;
 216                 ret = HNS3_VECTOR0_EVENT_MBX;
 217                 goto out;
 218         }
 219
 220         val = vector0_int_stats;
 221         ret = HNS3_VECTOR0_EVENT_OTHER;
 222 out:
 223
 224         if (clearval)
 225                 *clearval = val;
 226         return ret;
 227 }
 228
 229 static void
 230 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 231 {
 232         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 233             event_type == HNS3_VECTOR0_EVENT_PTP)
 234                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 235         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 236                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 237 }
 238
 239 static void
 240 hns3_clear_all_event_cause(struct hns3_hw *hw)
 241 {
 242         uint32_t vector0_int_stats;
 243
 244         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 245         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 246                 hns3_warn(hw, "Probe during IMP reset interrupt");
 247
 248         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 249                 hns3_warn(hw, "Probe during Global reset interrupt");
 250
 251         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 252                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 253                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 254                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 255         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 256         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 257                                 BIT(HNS3_VECTOR0_1588_INT_B));
 258 }
 259
 260 static void
 261 hns3_handle_mac_tnl(struct hns3_hw *hw)
 262 {
 263         struct hns3_cmd_desc desc;
 264         uint32_t status;
 265         int ret;
 266
 267         /* query and clear mac tnl interrupt */
 268         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 269         ret = hns3_cmd_send(hw, &desc, 1);
 270         if (ret) {
 271                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 272                 return;
 273         }
 274
 275         status = rte_le_to_cpu_32(desc.data[0]);
 276         if (status) {
 277                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 278                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 279                                           false);
 280                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 281                 ret = hns3_cmd_send(hw, &desc, 1);
 282                 if (ret)
 283                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 284                                  ret);
 285         }
 286 }
 287
 288 static void
 289 hns3_interrupt_handler(void *param)
 290 {
 291         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 292         struct hns3_adapter *hns = dev->data->dev_private;
 293         struct hns3_hw *hw = &hns->hw;
 294         enum hns3_evt_cause event_cause;
 295         uint32_t clearval = 0;
 296         uint32_t vector0_int;
 297         uint32_t ras_int;
 298         uint32_t cmdq_int;
 299
 300         /* Disable interrupt */
 301         hns3_pf_disable_irq0(hw);
 302
 303         event_cause = hns3_check_event_cause(hns, &clearval);
 304         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 305         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 306         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 307         hns3_clear_event_cause(hw, event_cause, clearval);
 308         /* vector 0 interrupt is shared with reset and mailbox source events. */
 309         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 310                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 311                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 312                           vector0_int, ras_int, cmdq_int);
 313                 hns3_handle_mac_tnl(hw);
 314                 hns3_handle_error(hns);
 315         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 316                 hns3_warn(hw, "received reset interrupt");
 317                 hns3_schedule_reset(hns);
 318         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 319                 hns3_dev_handle_mbx_msg(hw);
 320         } else {
 321                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 322                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 323                           vector0_int, ras_int, cmdq_int);
 324         }
 325
 326         /* Enable interrupt if it is not cause by reset */
 327         hns3_pf_enable_irq0(hw);
 328 }
 329
 330 static int
 331 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 332 {
 333 #define HNS3_VLAN_ID_OFFSET_STEP        160
 334 #define HNS3_VLAN_BYTE_SIZE             8
 335         struct hns3_vlan_filter_pf_cfg_cmd *req;
 336         struct hns3_hw *hw = &hns->hw;
 337         uint8_t vlan_offset_byte_val;
 338         struct hns3_cmd_desc desc;
 339         uint8_t vlan_offset_byte;
 340         uint8_t vlan_offset_base;
 341         int ret;
 342
 343         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 344
 345         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 346         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 347                            HNS3_VLAN_BYTE_SIZE;
 348         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 349
 350         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 351         req->vlan_offset = vlan_offset_base;
 352         req->vlan_cfg = on ? 0 : 1;
 353         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 354
 355         ret = hns3_cmd_send(hw, &desc, 1);
 356         if (ret)
 357                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 358                          vlan_id, ret);
 359
 360         return ret;
 361 }
 362
 363 static void
 364 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 365 {
 366         struct hns3_user_vlan_table *vlan_entry;
 367         struct hns3_pf *pf = &hns->pf;
 368
 369         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 370                 if (vlan_entry->vlan_id == vlan_id) {
 371                         if (vlan_entry->hd_tbl_status)
 372                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 373                         LIST_REMOVE(vlan_entry, next);
 374                         rte_free(vlan_entry);
 375                         break;
 376                 }
 377         }
 378 }
 379
 380 static void
 381 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 382                         bool writen_to_tbl)
 383 {
 384         struct hns3_user_vlan_table *vlan_entry;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_pf *pf = &hns->pf;
 387
 388         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 389                 if (vlan_entry->vlan_id == vlan_id)
 390                         return;
 391         }
 392
 393         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 394         if (vlan_entry == NULL) {
 395                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 396                 return;
 397         }
 398
 399         vlan_entry->hd_tbl_status = writen_to_tbl;
 400         vlan_entry->vlan_id = vlan_id;
 401
 402         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 403 }
 404
 405 static int
 406 hns3_restore_vlan_table(struct hns3_adapter *hns)
 407 {
 408         struct hns3_user_vlan_table *vlan_entry;
 409         struct hns3_hw *hw = &hns->hw;
 410         struct hns3_pf *pf = &hns->pf;
 411         uint16_t vlan_id;
 412         int ret = 0;
 413
 414         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 415                 return hns3_vlan_pvid_configure(hns,
 416                                                 hw->port_base_vlan_cfg.pvid, 1);
 417
 418         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 419                 if (vlan_entry->hd_tbl_status) {
 420                         vlan_id = vlan_entry->vlan_id;
 421                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 422                         if (ret)
 423                                 break;
 424                 }
 425         }
 426
 427         return ret;
 428 }
 429
 430 static int
 431 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 432 {
 433         struct hns3_hw *hw = &hns->hw;
 434         bool writen_to_tbl = false;
 435         int ret = 0;
 436
 437         /*
 438          * When vlan filter is enabled, hardware regards packets without vlan
 439          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 440          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 441          */
 442         if (on == 0 && vlan_id == 0)
 443                 return 0;
 444
 445         /*
 446          * When port base vlan enabled, we use port base vlan as the vlan
 447          * filter condition. In this case, we don't update vlan filter table
 448          * when user add new vlan or remove exist vlan, just update the
 449          * vlan list. The vlan id in vlan list will be written in vlan filter
 450          * table until port base vlan disabled
 451          */
 452         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 453                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 454                 writen_to_tbl = true;
 455         }
 456
 457         if (ret == 0) {
 458                 if (on)
 459                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 460                 else
 461                         hns3_rm_dev_vlan_table(hns, vlan_id);
 462         }
 463         return ret;
 464 }
 465
 466 static int
 467 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 468 {
 469         struct hns3_adapter *hns = dev->data->dev_private;
 470         struct hns3_hw *hw = &hns->hw;
 471         int ret;
 472
 473         rte_spinlock_lock(&hw->lock);
 474         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 475         rte_spinlock_unlock(&hw->lock);
 476         return ret;
 477 }
 478
 479 static int
 480 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 481                          uint16_t tpid)
 482 {
 483         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 484         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 485         struct hns3_hw *hw = &hns->hw;
 486         struct hns3_cmd_desc desc;
 487         int ret;
 488
 489         if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
 490              vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) {
 491                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 492                 return -EINVAL;
 493         }
 494
 495         if (tpid != RTE_ETHER_TYPE_VLAN) {
 496                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 497                 return -EINVAL;
 498         }
 499
 500         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 501         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 502
 503         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
 504                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 505                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 506         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
 507                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 508                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 509                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 510                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 511         }
 512
 513         ret = hns3_cmd_send(hw, &desc, 1);
 514         if (ret) {
 515                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 516                          ret);
 517                 return ret;
 518         }
 519
 520         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 521
 522         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 523         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 524         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 525
 526         ret = hns3_cmd_send(hw, &desc, 1);
 527         if (ret)
 528                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 529                          ret);
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 535                    uint16_t tpid)
 536 {
 537         struct hns3_adapter *hns = dev->data->dev_private;
 538         struct hns3_hw *hw = &hns->hw;
 539         int ret;
 540
 541         rte_spinlock_lock(&hw->lock);
 542         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 543         rte_spinlock_unlock(&hw->lock);
 544         return ret;
 545 }
 546
 547 static int
 548 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 549                              struct hns3_rx_vtag_cfg *vcfg)
 550 {
 551         struct hns3_vport_vtag_rx_cfg_cmd *req;
 552         struct hns3_hw *hw = &hns->hw;
 553         struct hns3_cmd_desc desc;
 554         uint16_t vport_id;
 555         uint8_t bitmap;
 556         int ret;
 557
 558         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 559
 560         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 561         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 562                      vcfg->strip_tag1_en ? 1 : 0);
 563         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 564                      vcfg->strip_tag2_en ? 1 : 0);
 565         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 566                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 567         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 568                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 569
 570         /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */
 571         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 572                      vcfg->strip_tag1_discard_en ? 1 : 0);
 573         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 574                      vcfg->strip_tag2_discard_en ? 1 : 0);
 575         /*
 576          * In current version VF is not supported when PF is driven by DPDK
 577          * driver, just need to configure parameters for PF vport.
 578          */
 579         vport_id = HNS3_PF_FUNC_ID;
 580         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 581         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 582         req->vf_bitmap[req->vf_offset] = bitmap;
 583
 584         ret = hns3_cmd_send(hw, &desc, 1);
 585         if (ret)
 586                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 587         return ret;
 588 }
 589
 590 static int
 591 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 592 {
 593         struct hns3_rx_vtag_cfg rxvlan_cfg;
 594         struct hns3_hw *hw = &hns->hw;
 595         int ret;
 596
 597         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 598                 rxvlan_cfg.strip_tag1_en = false;
 599                 rxvlan_cfg.strip_tag2_en = enable;
 600                 rxvlan_cfg.strip_tag2_discard_en = false;
 601         } else {
 602                 rxvlan_cfg.strip_tag1_en = enable;
 603                 rxvlan_cfg.strip_tag2_en = true;
 604                 rxvlan_cfg.strip_tag2_discard_en = true;
 605         }
 606
 607         rxvlan_cfg.strip_tag1_discard_en = false;
 608         rxvlan_cfg.vlan1_vlan_prionly = false;
 609         rxvlan_cfg.vlan2_vlan_prionly = false;
 610         rxvlan_cfg.rx_vlan_offload_en = enable;
 611
 612         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 613         if (ret) {
 614                 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
 615                                 enable ? "enable" : "disable", ret);
 616                 return ret;
 617         }
 618
 619         memcpy(&hns->pf.vtag_config.rx_vcfg, &rxvlan_cfg,
 620                sizeof(struct hns3_rx_vtag_cfg));
 621
 622         return ret;
 623 }
 624
 625 static int
 626 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 627                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 628 {
 629         struct hns3_vlan_filter_ctrl_cmd *req;
 630         struct hns3_cmd_desc desc;
 631         int ret;
 632
 633         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 634
 635         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 636         req->vlan_type = vlan_type;
 637         req->vlan_fe = filter_en ? fe_type : 0;
 638         req->vf_id = vf_id;
 639
 640         ret = hns3_cmd_send(hw, &desc, 1);
 641         if (ret)
 642                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 643
 644         return ret;
 645 }
 646
 647 static int
 648 hns3_vlan_filter_init(struct hns3_adapter *hns)
 649 {
 650         struct hns3_hw *hw = &hns->hw;
 651         int ret;
 652
 653         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 654                                         HNS3_FILTER_FE_EGRESS, false,
 655                                         HNS3_PF_FUNC_ID);
 656         if (ret) {
 657                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 658                 return ret;
 659         }
 660
 661         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 662                                         HNS3_FILTER_FE_INGRESS, false,
 663                                         HNS3_PF_FUNC_ID);
 664         if (ret)
 665                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 666
 667         return ret;
 668 }
 669
 670 static int
 671 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 672 {
 673         struct hns3_hw *hw = &hns->hw;
 674         int ret;
 675
 676         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 677                                         HNS3_FILTER_FE_INGRESS, enable,
 678                                         HNS3_PF_FUNC_ID);
 679         if (ret)
 680                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 681                          enable ? "enable" : "disable", ret);
 682
 683         return ret;
 684 }
 685
 686 static int
 687 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 688 {
 689         struct hns3_adapter *hns = dev->data->dev_private;
 690         struct hns3_hw *hw = &hns->hw;
 691         struct rte_eth_rxmode *rxmode;
 692         unsigned int tmp_mask;
 693         bool enable;
 694         int ret = 0;
 695
 696         rte_spinlock_lock(&hw->lock);
 697         rxmode = &dev->data->dev_conf.rxmode;
 698         tmp_mask = (unsigned int)mask;
 699         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
 700                 /* ignore vlan filter configuration during promiscuous mode */
 701                 if (!dev->data->promiscuous) {
 702                         /* Enable or disable VLAN filter */
 703                         enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ?
 704                                  true : false;
 705
 706                         ret = hns3_enable_vlan_filter(hns, enable);
 707                         if (ret) {
 708                                 rte_spinlock_unlock(&hw->lock);
 709                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 710                                          enable ? "enable" : "disable", ret);
 711                                 return ret;
 712                         }
 713                 }
 714         }
 715
 716         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
 717                 /* Enable or disable VLAN stripping */
 718                 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ?
 719                     true : false;
 720
 721                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 722                 if (ret) {
 723                         rte_spinlock_unlock(&hw->lock);
 724                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 725                                  enable ? "enable" : "disable", ret);
 726                         return ret;
 727                 }
 728         }
 729
 730         rte_spinlock_unlock(&hw->lock);
 731
 732         return ret;
 733 }
 734
 735 static int
 736 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 737                              struct hns3_tx_vtag_cfg *vcfg)
 738 {
 739         struct hns3_vport_vtag_tx_cfg_cmd *req;
 740         struct hns3_cmd_desc desc;
 741         struct hns3_hw *hw = &hns->hw;
 742         uint16_t vport_id;
 743         uint8_t bitmap;
 744         int ret;
 745
 746         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 747
 748         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 749         req->def_vlan_tag1 = vcfg->default_tag1;
 750         req->def_vlan_tag2 = vcfg->default_tag2;
 751         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 752                      vcfg->accept_tag1 ? 1 : 0);
 753         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 754                      vcfg->accept_untag1 ? 1 : 0);
 755         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 756                      vcfg->accept_tag2 ? 1 : 0);
 757         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 758                      vcfg->accept_untag2 ? 1 : 0);
 759         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 760                      vcfg->insert_tag1_en ? 1 : 0);
 761         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 762                      vcfg->insert_tag2_en ? 1 : 0);
 763         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 764
 765         /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */
 766         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 767                      vcfg->tag_shift_mode_en ? 1 : 0);
 768
 769         /*
 770          * In current version VF is not supported when PF is driven by DPDK
 771          * driver, just need to configure parameters for PF vport.
 772          */
 773         vport_id = HNS3_PF_FUNC_ID;
 774         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 775         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 776         req->vf_bitmap[req->vf_offset] = bitmap;
 777
 778         ret = hns3_cmd_send(hw, &desc, 1);
 779         if (ret)
 780                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 781
 782         return ret;
 783 }
 784
 785 static int
 786 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 787                      uint16_t pvid)
 788 {
 789         struct hns3_hw *hw = &hns->hw;
 790         struct hns3_tx_vtag_cfg txvlan_cfg;
 791         int ret;
 792
 793         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 794                 txvlan_cfg.accept_tag1 = true;
 795                 txvlan_cfg.insert_tag1_en = false;
 796                 txvlan_cfg.default_tag1 = 0;
 797         } else {
 798                 txvlan_cfg.accept_tag1 =
 799                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 800                 txvlan_cfg.insert_tag1_en = true;
 801                 txvlan_cfg.default_tag1 = pvid;
 802         }
 803
 804         txvlan_cfg.accept_untag1 = true;
 805         txvlan_cfg.accept_tag2 = true;
 806         txvlan_cfg.accept_untag2 = true;
 807         txvlan_cfg.insert_tag2_en = false;
 808         txvlan_cfg.default_tag2 = 0;
 809         txvlan_cfg.tag_shift_mode_en = true;
 810
 811         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 812         if (ret) {
 813                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 814                          ret);
 815                 return ret;
 816         }
 817
 818         memcpy(&hns->pf.vtag_config.tx_vcfg, &txvlan_cfg,
 819                sizeof(struct hns3_tx_vtag_cfg));
 820
 821         return ret;
 822 }
 823
 824
 825 static void
 826 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 827 {
 828         struct hns3_user_vlan_table *vlan_entry;
 829         struct hns3_pf *pf = &hns->pf;
 830
 831         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 832                 if (vlan_entry->hd_tbl_status) {
 833                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 834                         vlan_entry->hd_tbl_status = false;
 835                 }
 836         }
 837
 838         if (is_del_list) {
 839                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 840                 while (vlan_entry) {
 841                         LIST_REMOVE(vlan_entry, next);
 842                         rte_free(vlan_entry);
 843                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 844                 }
 845         }
 846 }
 847
 848 static void
 849 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 850 {
 851         struct hns3_user_vlan_table *vlan_entry;
 852         struct hns3_pf *pf = &hns->pf;
 853
 854         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 855                 if (!vlan_entry->hd_tbl_status) {
 856                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 857                         vlan_entry->hd_tbl_status = true;
 858                 }
 859         }
 860 }
 861
 862 static void
 863 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 864 {
 865         struct hns3_hw *hw = &hns->hw;
 866         int ret;
 867
 868         hns3_rm_all_vlan_table(hns, true);
 869         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 870                 ret = hns3_set_port_vlan_filter(hns,
 871                                                 hw->port_base_vlan_cfg.pvid, 0);
 872                 if (ret) {
 873                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 874                                  ret);
 875                         return;
 876                 }
 877         }
 878 }
 879
 880 static int
 881 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 882                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 883 {
 884         struct hns3_hw *hw = &hns->hw;
 885         uint16_t old_pvid;
 886         int ret;
 887
 888         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 889                 old_pvid = hw->port_base_vlan_cfg.pvid;
 890                 if (old_pvid != HNS3_INVALID_PVID) {
 891                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 892                         if (ret) {
 893                                 hns3_err(hw, "failed to remove old pvid %u, "
 894                                                 "ret = %d", old_pvid, ret);
 895                                 return ret;
 896                         }
 897                 }
 898
 899                 hns3_rm_all_vlan_table(hns, false);
 900                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 901                 if (ret) {
 902                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 903                                         new_pvid, ret);
 904                         return ret;
 905                 }
 906         } else {
 907                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 908                 if (ret) {
 909                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 910                                         new_pvid, ret);
 911                         return ret;
 912                 }
 913
 914                 hns3_add_all_vlan_table(hns);
 915         }
 916         return 0;
 917 }
 918
 919 static int
 920 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 921 {
 922         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 923         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 924         bool rx_strip_en;
 925         int ret;
 926
 927         rx_strip_en = old_cfg->rx_vlan_offload_en;
 928         if (on) {
 929                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 930                 rx_vlan_cfg.strip_tag2_en = true;
 931                 rx_vlan_cfg.strip_tag2_discard_en = true;
 932         } else {
 933                 rx_vlan_cfg.strip_tag1_en = false;
 934                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 935                 rx_vlan_cfg.strip_tag2_discard_en = false;
 936         }
 937         rx_vlan_cfg.strip_tag1_discard_en = false;
 938         rx_vlan_cfg.vlan1_vlan_prionly = false;
 939         rx_vlan_cfg.vlan2_vlan_prionly = false;
 940         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 941
 942         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 943         if (ret)
 944                 return ret;
 945
 946         memcpy(&hns->pf.vtag_config.rx_vcfg, &rx_vlan_cfg,
 947                sizeof(struct hns3_rx_vtag_cfg));
 948
 949         return ret;
 950 }
 951
 952 static int
 953 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 954 {
 955         struct hns3_hw *hw = &hns->hw;
 956         uint16_t port_base_vlan_state;
 957         int ret, err;
 958
 959         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 960                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 961                         hns3_warn(hw, "Invalid operation! As current pvid set "
 962                                   "is %u, disable pvid %u is invalid",
 963                                   hw->port_base_vlan_cfg.pvid, pvid);
 964                 return 0;
 965         }
 966
 967         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 968                                     HNS3_PORT_BASE_VLAN_DISABLE;
 969         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 970         if (ret) {
 971                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 972                          ret);
 973                 return ret;
 974         }
 975
 976         ret = hns3_en_pvid_strip(hns, on);
 977         if (ret) {
 978                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 979                          "ret = %d", ret);
 980                 goto pvid_vlan_strip_fail;
 981         }
 982
 983         if (pvid == HNS3_INVALID_PVID)
 984                 goto out;
 985         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 986         if (ret) {
 987                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 988                          ret);
 989                 goto vlan_filter_set_fail;
 990         }
 991
 992 out:
 993         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 994         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 995         return ret;
 996
 997 vlan_filter_set_fail:
 998         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
 999                                         HNS3_PORT_BASE_VLAN_ENABLE);
1000         if (err)
1001                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1002
1003 pvid_vlan_strip_fail:
1004         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1005                                         hw->port_base_vlan_cfg.pvid);
1006         if (err)
1007                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1008
1009         return ret;
1010 }
1011
1012 static int
1013 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1014 {
1015         struct hns3_adapter *hns = dev->data->dev_private;
1016         struct hns3_hw *hw = &hns->hw;
1017         bool pvid_en_state_change;
1018         uint16_t pvid_state;
1019         int ret;
1020
1021         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1022                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1023                          RTE_ETHER_MAX_VLAN_ID);
1024                 return -EINVAL;
1025         }
1026
1027         /*
1028          * If PVID configuration state change, should refresh the PVID
1029          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1030          */
1031         pvid_state = hw->port_base_vlan_cfg.state;
1032         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1033             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1034                 pvid_en_state_change = false;
1035         else
1036                 pvid_en_state_change = true;
1037
1038         rte_spinlock_lock(&hw->lock);
1039         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1040         rte_spinlock_unlock(&hw->lock);
1041         if (ret)
1042                 return ret;
1043         /*
1044          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1045          * need be processed by PMD.
1046          */
1047         if (pvid_en_state_change &&
1048             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1049                 hns3_update_all_queues_pvid_proc_en(hw);
1050
1051         return 0;
1052 }
1053
1054 static int
1055 hns3_default_vlan_config(struct hns3_adapter *hns)
1056 {
1057         struct hns3_hw *hw = &hns->hw;
1058         int ret;
1059
1060         /*
1061          * When vlan filter is enabled, hardware regards packets without vlan
1062          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1063          * table, packets without vlan won't be received. So, add vlan 0 as
1064          * the default vlan.
1065          */
1066         ret = hns3_vlan_filter_configure(hns, 0, 1);
1067         if (ret)
1068                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1069         return ret;
1070 }
1071
1072 static int
1073 hns3_init_vlan_config(struct hns3_adapter *hns)
1074 {
1075         struct hns3_hw *hw = &hns->hw;
1076         int ret;
1077
1078         /*
1079          * This function can be called in the initialization and reset process,
1080          * when in reset process, it means that hardware had been reseted
1081          * successfully and we need to restore the hardware configuration to
1082          * ensure that the hardware configuration remains unchanged before and
1083          * after reset.
1084          */
1085         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1086                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1087                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1088         }
1089
1090         ret = hns3_vlan_filter_init(hns);
1091         if (ret) {
1092                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1093                 return ret;
1094         }
1095
1096         ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER,
1097                                        RTE_ETHER_TYPE_VLAN);
1098         if (ret) {
1099                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1100                 return ret;
1101         }
1102
1103         /*
1104          * When in the reinit dev stage of the reset process, the following
1105          * vlan-related configurations may differ from those at initialization,
1106          * we will restore configurations to hardware in hns3_restore_vlan_table
1107          * and hns3_restore_vlan_conf later.
1108          */
1109         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1110                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1111                 if (ret) {
1112                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1113                         return ret;
1114                 }
1115
1116                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1117                 if (ret) {
1118                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1119                                  ret);
1120                         return ret;
1121                 }
1122         }
1123
1124         return hns3_default_vlan_config(hns);
1125 }
1126
1127 static int
1128 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1129 {
1130         struct hns3_pf *pf = &hns->pf;
1131         struct hns3_hw *hw = &hns->hw;
1132         uint64_t offloads;
1133         bool enable;
1134         int ret;
1135
1136         if (!hw->data->promiscuous) {
1137                 /* restore vlan filter states */
1138                 offloads = hw->data->dev_conf.rxmode.offloads;
1139                 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false;
1140                 ret = hns3_enable_vlan_filter(hns, enable);
1141                 if (ret) {
1142                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1143                                  "ret = %d", ret);
1144                         return ret;
1145                 }
1146         }
1147
1148         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1149         if (ret) {
1150                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1151                 return ret;
1152         }
1153
1154         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1155         if (ret)
1156                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1157
1158         return ret;
1159 }
1160
1161 static int
1162 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1163 {
1164         struct hns3_adapter *hns = dev->data->dev_private;
1165         struct rte_eth_dev_data *data = dev->data;
1166         struct rte_eth_txmode *txmode;
1167         struct hns3_hw *hw = &hns->hw;
1168         int mask;
1169         int ret;
1170
1171         txmode = &data->dev_conf.txmode;
1172         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1173                 hns3_warn(hw,
1174                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1175                           "configuration is not supported! Ignore these two "
1176                           "parameters: hw_vlan_reject_tagged(%u), "
1177                           "hw_vlan_reject_untagged(%u)",
1178                           txmode->hw_vlan_reject_tagged,
1179                           txmode->hw_vlan_reject_untagged);
1180
1181         /* Apply vlan offload setting */
1182         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;
1183         ret = hns3_vlan_offload_set(dev, mask);
1184         if (ret) {
1185                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1186                          ret);
1187                 return ret;
1188         }
1189
1190         /*
1191          * If pvid config is not set in rte_eth_conf, driver needn't to set
1192          * VLAN pvid related configuration to hardware.
1193          */
1194         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1195                 return 0;
1196
1197         /* Apply pvid setting */
1198         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1199                                  txmode->hw_vlan_insert_pvid);
1200         if (ret)
1201                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1202                          txmode->pvid, ret);
1203
1204         return ret;
1205 }
1206
1207 static int
1208 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1209                 unsigned int tso_mss_max)
1210 {
1211         struct hns3_cfg_tso_status_cmd *req;
1212         struct hns3_cmd_desc desc;
1213         uint16_t tso_mss;
1214
1215         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1216
1217         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1218
1219         tso_mss = 0;
1220         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1221                        tso_mss_min);
1222         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1223
1224         tso_mss = 0;
1225         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1226                        tso_mss_max);
1227         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1228
1229         return hns3_cmd_send(hw, &desc, 1);
1230 }
1231
1232 static int
1233 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1234                    uint16_t *allocated_size, bool is_alloc)
1235 {
1236         struct hns3_umv_spc_alc_cmd *req;
1237         struct hns3_cmd_desc desc;
1238         int ret;
1239
1240         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1241         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1242         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1243         req->space_size = rte_cpu_to_le_32(space_size);
1244
1245         ret = hns3_cmd_send(hw, &desc, 1);
1246         if (ret) {
1247                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1248                              is_alloc ? "allocate" : "free", ret);
1249                 return ret;
1250         }
1251
1252         if (is_alloc && allocated_size)
1253                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1254
1255         return 0;
1256 }
1257
1258 static int
1259 hns3_init_umv_space(struct hns3_hw *hw)
1260 {
1261         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1262         struct hns3_pf *pf = &hns->pf;
1263         uint16_t allocated_size = 0;
1264         int ret;
1265
1266         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1267                                  true);
1268         if (ret)
1269                 return ret;
1270
1271         if (allocated_size < pf->wanted_umv_size)
1272                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1273                              pf->wanted_umv_size, allocated_size);
1274
1275         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1276                                                 pf->wanted_umv_size;
1277         pf->used_umv_size = 0;
1278         return 0;
1279 }
1280
1281 static int
1282 hns3_uninit_umv_space(struct hns3_hw *hw)
1283 {
1284         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1285         struct hns3_pf *pf = &hns->pf;
1286         int ret;
1287
1288         if (pf->max_umv_size == 0)
1289                 return 0;
1290
1291         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1292         if (ret)
1293                 return ret;
1294
1295         pf->max_umv_size = 0;
1296
1297         return 0;
1298 }
1299
1300 static bool
1301 hns3_is_umv_space_full(struct hns3_hw *hw)
1302 {
1303         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1304         struct hns3_pf *pf = &hns->pf;
1305         bool is_full;
1306
1307         is_full = (pf->used_umv_size >= pf->max_umv_size);
1308
1309         return is_full;
1310 }
1311
1312 static void
1313 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1314 {
1315         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1316         struct hns3_pf *pf = &hns->pf;
1317
1318         if (is_free) {
1319                 if (pf->used_umv_size > 0)
1320                         pf->used_umv_size--;
1321         } else
1322                 pf->used_umv_size++;
1323 }
1324
1325 static void
1326 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1327                       const uint8_t *addr, bool is_mc)
1328 {
1329         const unsigned char *mac_addr = addr;
1330         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1331                             ((uint32_t)mac_addr[2] << 16) |
1332                             ((uint32_t)mac_addr[1] << 8) |
1333                             (uint32_t)mac_addr[0];
1334         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1335
1336         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1337         if (is_mc) {
1338                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1339                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1340                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1341         }
1342
1343         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1344         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1345 }
1346
1347 static int
1348 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1349                              uint8_t resp_code,
1350                              enum hns3_mac_vlan_tbl_opcode op)
1351 {
1352         if (cmdq_resp) {
1353                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1354                          cmdq_resp);
1355                 return -EIO;
1356         }
1357
1358         if (op == HNS3_MAC_VLAN_ADD) {
1359                 if (resp_code == 0 || resp_code == 1) {
1360                         return 0;
1361                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1362                         hns3_err(hw, "add mac addr failed for uc_overflow");
1363                         return -ENOSPC;
1364                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1365                         hns3_err(hw, "add mac addr failed for mc_overflow");
1366                         return -ENOSPC;
1367                 }
1368
1369                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1370                          resp_code);
1371                 return -EIO;
1372         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1373                 if (resp_code == 0) {
1374                         return 0;
1375                 } else if (resp_code == 1) {
1376                         hns3_dbg(hw, "remove mac addr failed for miss");
1377                         return -ENOENT;
1378                 }
1379
1380                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1381                          resp_code);
1382                 return -EIO;
1383         } else if (op == HNS3_MAC_VLAN_LKUP) {
1384                 if (resp_code == 0) {
1385                         return 0;
1386                 } else if (resp_code == 1) {
1387                         hns3_dbg(hw, "lookup mac addr failed for miss");
1388                         return -ENOENT;
1389                 }
1390
1391                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1392                          resp_code);
1393                 return -EIO;
1394         }
1395
1396         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1397                  op);
1398
1399         return -EINVAL;
1400 }
1401
1402 static int
1403 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1404                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1405                          struct hns3_cmd_desc *desc, uint8_t desc_num)
1406 {
1407         uint8_t resp_code;
1408         uint16_t retval;
1409         int ret;
1410         int i;
1411
1412         if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) {
1413                 for (i = 0; i < desc_num - 1; i++) {
1414                         hns3_cmd_setup_basic_desc(&desc[i],
1415                                                   HNS3_OPC_MAC_VLAN_ADD, true);
1416                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1417                         if (i == 0)
1418                                 memcpy(desc[i].data, req,
1419                                 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1420                 }
1421                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD,
1422                                           true);
1423         } else {
1424                 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD,
1425                                           true);
1426                 memcpy(desc[0].data, req,
1427                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1428         }
1429         ret = hns3_cmd_send(hw, desc, desc_num);
1430         if (ret) {
1431                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1432                          ret);
1433                 return ret;
1434         }
1435         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1436         retval = rte_le_to_cpu_16(desc[0].retval);
1437
1438         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1439                                             HNS3_MAC_VLAN_LKUP);
1440 }
1441
1442 static int
1443 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1444                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1445                       struct hns3_cmd_desc *desc, uint8_t desc_num)
1446 {
1447         uint8_t resp_code;
1448         uint16_t retval;
1449         int cfg_status;
1450         int ret;
1451         int i;
1452
1453         if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) {
1454                 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false);
1455                 memcpy(desc->data, req,
1456                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1457                 ret = hns3_cmd_send(hw, desc, desc_num);
1458                 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff;
1459                 retval = rte_le_to_cpu_16(desc->retval);
1460
1461                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1462                                                           HNS3_MAC_VLAN_ADD);
1463         } else {
1464                 for (i = 0; i < desc_num; i++) {
1465                         hns3_cmd_reuse_desc(&desc[i], false);
1466                         if (i == desc_num - 1)
1467                                 desc[i].flag &=
1468                                         rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1469                         else
1470                                 desc[i].flag |=
1471                                         rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1472                 }
1473                 memcpy(desc[0].data, req,
1474                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1475                 desc[0].retval = 0;
1476                 ret = hns3_cmd_send(hw, desc, desc_num);
1477                 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1478                 retval = rte_le_to_cpu_16(desc[0].retval);
1479
1480                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1481                                                           HNS3_MAC_VLAN_ADD);
1482         }
1483
1484         if (ret) {
1485                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1486                 return ret;
1487         }
1488
1489         return cfg_status;
1490 }
1491
1492 static int
1493 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1494                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1495 {
1496         struct hns3_cmd_desc desc;
1497         uint8_t resp_code;
1498         uint16_t retval;
1499         int ret;
1500
1501         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1502
1503         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1504
1505         ret = hns3_cmd_send(hw, &desc, 1);
1506         if (ret) {
1507                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1508                 return ret;
1509         }
1510         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1511         retval = rte_le_to_cpu_16(desc.retval);
1512
1513         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1514                                             HNS3_MAC_VLAN_REMOVE);
1515 }
1516
1517 static int
1518 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1519 {
1520         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1521         struct hns3_mac_vlan_tbl_entry_cmd req;
1522         struct hns3_pf *pf = &hns->pf;
1523         struct hns3_cmd_desc desc;
1524         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1525         uint16_t egress_port = 0;
1526         uint8_t vf_id;
1527         int ret;
1528
1529         /* check if mac addr is valid */
1530         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1531                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1532                                       mac_addr);
1533                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1534                          mac_str);
1535                 return -EINVAL;
1536         }
1537
1538         memset(&req, 0, sizeof(req));
1539
1540         /*
1541          * In current version VF is not supported when PF is driven by DPDK
1542          * driver, just need to configure parameters for PF vport.
1543          */
1544         vf_id = HNS3_PF_FUNC_ID;
1545         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1546                        HNS3_MAC_EPORT_VFID_S, vf_id);
1547
1548         req.egress_port = rte_cpu_to_le_16(egress_port);
1549
1550         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1551
1552         /*
1553          * Lookup the mac address in the mac_vlan table, and add
1554          * it if the entry is inexistent. Repeated unicast entry
1555          * is not allowed in the mac vlan table.
1556          */
1557         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc,
1558                                         HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1559         if (ret == -ENOENT) {
1560                 if (!hns3_is_umv_space_full(hw)) {
1561                         ret = hns3_add_mac_vlan_tbl(hw, &req, &desc,
1562                                                 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1563                         if (!ret)
1564                                 hns3_update_umv_space(hw, false);
1565                         return ret;
1566                 }
1567
1568                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1569
1570                 return -ENOSPC;
1571         }
1572
1573         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1574
1575         /* check if we just hit the duplicate */
1576         if (ret == 0) {
1577                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1578                 return 0;
1579         }
1580
1581         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1582                  mac_str);
1583
1584         return ret;
1585 }
1586
1587 static int
1588 hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1589 {
1590         struct hns3_mac_vlan_tbl_entry_cmd req;
1591         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1592         int ret;
1593
1594         /* check if mac addr is valid */
1595         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1596                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1597                                       mac_addr);
1598                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1599                          mac_str);
1600                 return -EINVAL;
1601         }
1602
1603         memset(&req, 0, sizeof(req));
1604         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1605         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1606         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1607         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1608                 return 0;
1609         else if (ret == 0)
1610                 hns3_update_umv_space(hw, true);
1611
1612         return ret;
1613 }
1614
1615 static int
1616 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1617                           struct rte_ether_addr *mac_addr)
1618 {
1619         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620         struct rte_ether_addr *oaddr;
1621         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1622         int ret, ret_val;
1623
1624         rte_spinlock_lock(&hw->lock);
1625         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1626         ret = hw->ops.del_uc_mac_addr(hw, oaddr);
1627         if (ret) {
1628                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629                                       oaddr);
1630                 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1631                           mac_str, ret);
1632
1633                 rte_spinlock_unlock(&hw->lock);
1634                 return ret;
1635         }
1636
1637         ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
1638         if (ret) {
1639                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1640                                       mac_addr);
1641                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1642                 goto err_add_uc_addr;
1643         }
1644
1645         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1646         if (ret) {
1647                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1648                 goto err_pause_addr_cfg;
1649         }
1650
1651         rte_ether_addr_copy(mac_addr,
1652                             (struct rte_ether_addr *)hw->mac.mac_addr);
1653         rte_spinlock_unlock(&hw->lock);
1654
1655         return 0;
1656
1657 err_pause_addr_cfg:
1658         ret_val = hw->ops.del_uc_mac_addr(hw, mac_addr);
1659         if (ret_val) {
1660                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1661                                       mac_addr);
1662                 hns3_warn(hw,
1663                           "Failed to roll back to del setted mac addr(%s): %d",
1664                           mac_str, ret_val);
1665         }
1666
1667 err_add_uc_addr:
1668         ret_val = hw->ops.add_uc_mac_addr(hw, oaddr);
1669         if (ret_val) {
1670                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1671                 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1672                                   mac_str, ret_val);
1673         }
1674         rte_spinlock_unlock(&hw->lock);
1675
1676         return ret;
1677 }
1678
1679 static void
1680 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1681 {
1682 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1683         uint8_t word_num;
1684         uint8_t bit_num;
1685
1686         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1687                 word_num = vfid / 32;
1688                 bit_num = vfid % 32;
1689                 if (clr)
1690                         desc[1].data[word_num] &=
1691                             rte_cpu_to_le_32(~(1UL << bit_num));
1692                 else
1693                         desc[1].data[word_num] |=
1694                             rte_cpu_to_le_32(1UL << bit_num);
1695         } else {
1696                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1697                 bit_num = vfid % 32;
1698                 if (clr)
1699                         desc[2].data[word_num] &=
1700                             rte_cpu_to_le_32(~(1UL << bit_num));
1701                 else
1702                         desc[2].data[word_num] |=
1703                             rte_cpu_to_le_32(1UL << bit_num);
1704         }
1705 }
1706
1707 static int
1708 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1709 {
1710         struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM];
1711         struct hns3_mac_vlan_tbl_entry_cmd req;
1712         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1713         uint8_t vf_id;
1714         int ret;
1715
1716         /* Check if mac addr is valid */
1717         if (!rte_is_multicast_ether_addr(mac_addr)) {
1718                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1719                                       mac_addr);
1720                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1721                          mac_str);
1722                 return -EINVAL;
1723         }
1724
1725         memset(&req, 0, sizeof(req));
1726         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1727         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1728         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1729                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1730         if (ret) {
1731                 /* This mac addr do not exist, add new entry for it */
1732                 memset(desc[0].data, 0, sizeof(desc[0].data));
1733                 memset(desc[1].data, 0, sizeof(desc[0].data));
1734                 memset(desc[2].data, 0, sizeof(desc[0].data));
1735         }
1736
1737         /*
1738          * In current version VF is not supported when PF is driven by DPDK
1739          * driver, just need to configure parameters for PF vport.
1740          */
1741         vf_id = HNS3_PF_FUNC_ID;
1742         hns3_update_desc_vfid(desc, vf_id, false);
1743         ret = hns3_add_mac_vlan_tbl(hw, &req, desc,
1744                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1745         if (ret) {
1746                 if (ret == -ENOSPC)
1747                         hns3_err(hw, "mc mac vlan table is full");
1748                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1749                                       mac_addr);
1750                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1751         }
1752
1753         return ret;
1754 }
1755
1756 static int
1757 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1758 {
1759         struct hns3_mac_vlan_tbl_entry_cmd req;
1760         struct hns3_cmd_desc desc[3];
1761         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1762         uint8_t vf_id;
1763         int ret;
1764
1765         /* Check if mac addr is valid */
1766         if (!rte_is_multicast_ether_addr(mac_addr)) {
1767                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1768                                       mac_addr);
1769                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1770                          mac_str);
1771                 return -EINVAL;
1772         }
1773
1774         memset(&req, 0, sizeof(req));
1775         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1776         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1777         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1778                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1779         if (ret == 0) {
1780                 /*
1781                  * This mac addr exist, remove this handle's VFID for it.
1782                  * In current version VF is not supported when PF is driven by
1783                  * DPDK driver, just need to configure parameters for PF vport.
1784                  */
1785                 vf_id = HNS3_PF_FUNC_ID;
1786                 hns3_update_desc_vfid(desc, vf_id, true);
1787
1788                 /* All the vfid is zero, so need to delete this entry */
1789                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1790         } else if (ret == -ENOENT) {
1791                 /* This mac addr doesn't exist. */
1792                 return 0;
1793         }
1794
1795         if (ret) {
1796                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1797                                       mac_addr);
1798                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1799         }
1800
1801         return ret;
1802 }
1803
1804 static int
1805 hns3_check_mq_mode(struct rte_eth_dev *dev)
1806 {
1807         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1808         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1809         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1810         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1811         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1812         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1813         uint8_t num_tc;
1814         int max_tc = 0;
1815         int i;
1816
1817         if (((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) ||
1818             (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB ||
1819              tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) {
1820                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
1821                          rx_mq_mode, tx_mq_mode);
1822                 return -EOPNOTSUPP;
1823         }
1824
1825         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1826         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1827         if ((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
1828                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1829                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1830                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1831                         return -EINVAL;
1832                 }
1833
1834                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1835                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1836                         hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, "
1837                                  "nb_tcs(%d) != %d or %d in rx direction.",
1838                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1839                         return -EINVAL;
1840                 }
1841
1842                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1843                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1844                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1845                         return -EINVAL;
1846                 }
1847
1848                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1849                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1850                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
1851                                          "is not equal to one in tx direction.",
1852                                          i, dcb_rx_conf->dcb_tc[i]);
1853                                 return -EINVAL;
1854                         }
1855                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1856                                 max_tc = dcb_rx_conf->dcb_tc[i];
1857                 }
1858
1859                 num_tc = max_tc + 1;
1860                 if (num_tc > dcb_rx_conf->nb_tcs) {
1861                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1862                                  num_tc, dcb_rx_conf->nb_tcs);
1863                         return -EINVAL;
1864                 }
1865         }
1866
1867         return 0;
1868 }
1869
1870 static int
1871 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
1872                            enum hns3_ring_type queue_type, uint16_t queue_id)
1873 {
1874         struct hns3_cmd_desc desc;
1875         struct hns3_ctrl_vector_chain_cmd *req =
1876                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
1877         enum hns3_opcode_type op;
1878         uint16_t tqp_type_and_id = 0;
1879         uint16_t type;
1880         uint16_t gl;
1881         int ret;
1882
1883         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
1884         hns3_cmd_setup_basic_desc(&desc, op, false);
1885         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
1886                                               HNS3_TQP_INT_ID_L_S);
1887         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
1888                                               HNS3_TQP_INT_ID_H_S);
1889
1890         if (queue_type == HNS3_RING_TYPE_RX)
1891                 gl = HNS3_RING_GL_RX;
1892         else
1893                 gl = HNS3_RING_GL_TX;
1894
1895         type = queue_type;
1896
1897         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
1898                        type);
1899         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
1900         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
1901                        gl);
1902         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
1903         req->int_cause_num = 1;
1904         ret = hns3_cmd_send(hw, &desc, 1);
1905         if (ret) {
1906                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
1907                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
1908                 return ret;
1909         }
1910
1911         return 0;
1912 }
1913
1914 static int
1915 hns3_setup_dcb(struct rte_eth_dev *dev)
1916 {
1917         struct hns3_adapter *hns = dev->data->dev_private;
1918         struct hns3_hw *hw = &hns->hw;
1919         int ret;
1920
1921         if (!hns3_dev_get_support(hw, DCB)) {
1922                 hns3_err(hw, "this port does not support dcb configurations.");
1923                 return -EOPNOTSUPP;
1924         }
1925
1926         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
1927                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
1928                 return -EOPNOTSUPP;
1929         }
1930
1931         ret = hns3_dcb_configure(hns);
1932         if (ret)
1933                 hns3_err(hw, "failed to config dcb: %d", ret);
1934
1935         return ret;
1936 }
1937
1938 static int
1939 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
1940 {
1941         int ret;
1942
1943         /*
1944          * Some hardware doesn't support auto-negotiation, but users may not
1945          * configure link_speeds (default 0), which means auto-negotiation.
1946          * In this case, it should return success.
1947          */
1948         if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG &&
1949             hw->mac.support_autoneg == 0)
1950                 return 0;
1951
1952         if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) {
1953                 ret = hns3_check_port_speed(hw, link_speeds);
1954                 if (ret)
1955                         return ret;
1956         }
1957
1958         return 0;
1959 }
1960
1961 static int
1962 hns3_check_dev_conf(struct rte_eth_dev *dev)
1963 {
1964         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965         struct rte_eth_conf *conf = &dev->data->dev_conf;
1966         int ret;
1967
1968         ret = hns3_check_mq_mode(dev);
1969         if (ret)
1970                 return ret;
1971
1972         return hns3_check_link_speed(hw, conf->link_speeds);
1973 }
1974
1975 static int
1976 hns3_dev_configure(struct rte_eth_dev *dev)
1977 {
1978         struct hns3_adapter *hns = dev->data->dev_private;
1979         struct rte_eth_conf *conf = &dev->data->dev_conf;
1980         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
1981         struct hns3_hw *hw = &hns->hw;
1982         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1983         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1984         struct rte_eth_rss_conf rss_conf;
1985         bool gro_en;
1986         int ret;
1987
1988         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
1989
1990         /*
1991          * Some versions of hardware network engine does not support
1992          * individually enable/disable/reset the Tx or Rx queue. These devices
1993          * must enable/disable/reset Tx and Rx queues at the same time. When the
1994          * numbers of Tx queues allocated by upper applications are not equal to
1995          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
1996          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
1997          * work as usual. But these fake queues are imperceptible, and can not
1998          * be used by upper applications.
1999          */
2000         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2001         if (ret) {
2002                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2003                 hw->cfg_max_queues = 0;
2004                 return ret;
2005         }
2006
2007         hw->adapter_state = HNS3_NIC_CONFIGURING;
2008         ret = hns3_check_dev_conf(dev);
2009         if (ret)
2010                 goto cfg_err;
2011
2012         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2013                 ret = hns3_setup_dcb(dev);
2014                 if (ret)
2015                         goto cfg_err;
2016         }
2017
2018         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2019                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2020                 rss_conf = conf->rx_adv_conf.rss_conf;
2021                 hw->rss_dis_flag = false;
2022                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2023                 if (ret)
2024                         goto cfg_err;
2025         }
2026
2027         ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu);
2028         if (ret != 0)
2029                 goto cfg_err;
2030
2031         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2032         if (ret)
2033                 goto cfg_err;
2034
2035         ret = hns3_dev_configure_vlan(dev);
2036         if (ret)
2037                 goto cfg_err;
2038
2039         /* config hardware GRO */
2040         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
2041         ret = hns3_config_gro(hw, gro_en);
2042         if (ret)
2043                 goto cfg_err;
2044
2045         hns3_init_rx_ptype_tble(dev);
2046         hw->adapter_state = HNS3_NIC_CONFIGURED;
2047
2048         return 0;
2049
2050 cfg_err:
2051         hw->cfg_max_queues = 0;
2052         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2053         hw->adapter_state = HNS3_NIC_INITIALIZED;
2054
2055         return ret;
2056 }
2057
2058 static int
2059 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2060 {
2061         struct hns3_config_max_frm_size_cmd *req;
2062         struct hns3_cmd_desc desc;
2063
2064         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2065
2066         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2067         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2068         req->min_frm_size = RTE_ETHER_MIN_LEN;
2069
2070         return hns3_cmd_send(hw, &desc, 1);
2071 }
2072
2073 static int
2074 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2075 {
2076         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2077         int err;
2078         int ret;
2079
2080         ret = hns3_set_mac_mtu(hw, mps);
2081         if (ret) {
2082                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2083                 return ret;
2084         }
2085
2086         ret = hns3_buffer_alloc(hw);
2087         if (ret) {
2088                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2089                 goto rollback;
2090         }
2091
2092         hns->pf.mps = mps;
2093
2094         return 0;
2095
2096 rollback:
2097         err = hns3_set_mac_mtu(hw, hns->pf.mps);
2098         if (err)
2099                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2100
2101         return ret;
2102 }
2103
2104 static int
2105 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2106 {
2107         struct hns3_adapter *hns = dev->data->dev_private;
2108         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2109         struct hns3_hw *hw = &hns->hw;
2110         int ret;
2111
2112         if (dev->data->dev_started) {
2113                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2114                          "before configuration", dev->data->port_id);
2115                 return -EBUSY;
2116         }
2117
2118         rte_spinlock_lock(&hw->lock);
2119         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2120
2121         /*
2122          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2123          * assign to "uint16_t" type variable.
2124          */
2125         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2126         if (ret) {
2127                 rte_spinlock_unlock(&hw->lock);
2128                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2129                          dev->data->port_id, mtu, ret);
2130                 return ret;
2131         }
2132
2133         rte_spinlock_unlock(&hw->lock);
2134
2135         return 0;
2136 }
2137
2138 static uint32_t
2139 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2140 {
2141         uint32_t speed_capa = 0;
2142
2143         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2144                 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD;
2145         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2146                 speed_capa |= RTE_ETH_LINK_SPEED_10M;
2147         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2148                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
2149         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2150                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
2151         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2152                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2153
2154         return speed_capa;
2155 }
2156
2157 static uint32_t
2158 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2159 {
2160         uint32_t speed_capa = 0;
2161
2162         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2163                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2164         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2165                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
2166         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2167                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
2168         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2169                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
2170         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2171                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
2172         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2173                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
2174         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2175                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
2176
2177         return speed_capa;
2178 }
2179
2180 uint32_t
2181 hns3_get_speed_capa(struct hns3_hw *hw)
2182 {
2183         struct hns3_mac *mac = &hw->mac;
2184         uint32_t speed_capa;
2185
2186         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2187                 speed_capa =
2188                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2189         else
2190                 speed_capa =
2191                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2192
2193         if (mac->support_autoneg == 0)
2194                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
2195
2196         return speed_capa;
2197 }
2198
2199 static int
2200 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2201 {
2202         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2203         int ret;
2204
2205         (void)hns3_update_link_status(hw);
2206
2207         ret = hns3_update_link_info(eth_dev);
2208         if (ret)
2209                 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2210
2211         return ret;
2212 }
2213
2214 static void
2215 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2216                       struct rte_eth_link *new_link)
2217 {
2218         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2219         struct hns3_mac *mac = &hw->mac;
2220
2221         switch (mac->link_speed) {
2222         case RTE_ETH_SPEED_NUM_10M:
2223         case RTE_ETH_SPEED_NUM_100M:
2224         case RTE_ETH_SPEED_NUM_1G:
2225         case RTE_ETH_SPEED_NUM_10G:
2226         case RTE_ETH_SPEED_NUM_25G:
2227         case RTE_ETH_SPEED_NUM_40G:
2228         case RTE_ETH_SPEED_NUM_50G:
2229         case RTE_ETH_SPEED_NUM_100G:
2230         case RTE_ETH_SPEED_NUM_200G:
2231                 if (mac->link_status)
2232                         new_link->link_speed = mac->link_speed;
2233                 break;
2234         default:
2235                 if (mac->link_status)
2236                         new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2237                 break;
2238         }
2239
2240         if (!mac->link_status)
2241                 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2242
2243         new_link->link_duplex = mac->link_duplex;
2244         new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2245         new_link->link_autoneg = mac->link_autoneg;
2246 }
2247
2248 static int
2249 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2250 {
2251 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2252 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2253
2254         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2255         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2256         struct hns3_mac *mac = &hw->mac;
2257         struct rte_eth_link new_link;
2258         int ret;
2259
2260         /* When port is stopped, report link down. */
2261         if (eth_dev->data->dev_started == 0) {
2262                 new_link.link_autoneg = mac->link_autoneg;
2263                 new_link.link_duplex = mac->link_duplex;
2264                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2265                 new_link.link_status = RTE_ETH_LINK_DOWN;
2266                 goto out;
2267         }
2268
2269         do {
2270                 ret = hns3_update_port_link_info(eth_dev);
2271                 if (ret) {
2272                         hns3_err(hw, "failed to get port link info, ret = %d.",
2273                                  ret);
2274                         break;
2275                 }
2276
2277                 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP)
2278                         break;
2279
2280                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2281         } while (retry_cnt--);
2282
2283         memset(&new_link, 0, sizeof(new_link));
2284         hns3_setup_linkstatus(eth_dev, &new_link);
2285
2286 out:
2287         return rte_eth_linkstatus_set(eth_dev, &new_link);
2288 }
2289
2290 static int
2291 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2292 {
2293         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2294         int ret;
2295
2296         /*
2297          * The "tx_pkt_burst" will be restored. But the secondary process does
2298          * not support the mechanism for notifying the primary process.
2299          */
2300         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2301                 hns3_err(hw, "secondary process does not support to set link up.");
2302                 return -ENOTSUP;
2303         }
2304
2305         /*
2306          * If device isn't started Rx/Tx function is still disabled, setting
2307          * link up is not allowed. But it is probably better to return success
2308          * to reduce the impact on the upper layer.
2309          */
2310         if (hw->adapter_state != HNS3_NIC_STARTED) {
2311                 hns3_info(hw, "device isn't started, can't set link up.");
2312                 return 0;
2313         }
2314
2315         if (!hw->set_link_down)
2316                 return 0;
2317
2318         rte_spinlock_lock(&hw->lock);
2319         ret = hns3_cfg_mac_mode(hw, true);
2320         if (ret) {
2321                 rte_spinlock_unlock(&hw->lock);
2322                 hns3_err(hw, "failed to set link up, ret = %d", ret);
2323                 return ret;
2324         }
2325
2326         hw->set_link_down = false;
2327         hns3_start_tx_datapath(dev);
2328         rte_spinlock_unlock(&hw->lock);
2329
2330         return 0;
2331 }
2332
2333 static int
2334 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2335 {
2336         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2337         int ret;
2338
2339         /*
2340          * The "tx_pkt_burst" will be set to dummy function. But the secondary
2341          * process does not support the mechanism for notifying the primary
2342          * process.
2343          */
2344         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2345                 hns3_err(hw, "secondary process does not support to set link down.");
2346                 return -ENOTSUP;
2347         }
2348
2349         /*
2350          * If device isn't started or the API has been called, link status is
2351          * down, return success.
2352          */
2353         if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2354                 return 0;
2355
2356         rte_spinlock_lock(&hw->lock);
2357         hns3_stop_tx_datapath(dev);
2358         ret = hns3_cfg_mac_mode(hw, false);
2359         if (ret) {
2360                 hns3_start_tx_datapath(dev);
2361                 rte_spinlock_unlock(&hw->lock);
2362                 hns3_err(hw, "failed to set link down, ret = %d", ret);
2363                 return ret;
2364         }
2365
2366         hw->set_link_down = true;
2367         rte_spinlock_unlock(&hw->lock);
2368
2369         return 0;
2370 }
2371
2372 static int
2373 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2374 {
2375         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2376         struct hns3_pf *pf = &hns->pf;
2377
2378         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2379                 return -EINVAL;
2380
2381         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2382
2383         return 0;
2384 }
2385
2386 static int
2387 hns3_query_function_status(struct hns3_hw *hw)
2388 {
2389 #define HNS3_QUERY_MAX_CNT              10
2390 #define HNS3_QUERY_SLEEP_MSCOEND        1
2391         struct hns3_func_status_cmd *req;
2392         struct hns3_cmd_desc desc;
2393         int timeout = 0;
2394         int ret;
2395
2396         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2397         req = (struct hns3_func_status_cmd *)desc.data;
2398
2399         do {
2400                 ret = hns3_cmd_send(hw, &desc, 1);
2401                 if (ret) {
2402                         PMD_INIT_LOG(ERR, "query function status failed %d",
2403                                      ret);
2404                         return ret;
2405                 }
2406
2407                 /* Check pf reset is done */
2408                 if (req->pf_state)
2409                         break;
2410
2411                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2412         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2413
2414         return hns3_parse_func_status(hw, req);
2415 }
2416
2417 static int
2418 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2419 {
2420         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2421         struct hns3_pf *pf = &hns->pf;
2422
2423         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2424                 /*
2425                  * The total_tqps_num obtained from firmware is maximum tqp
2426                  * numbers of this port, which should be used for PF and VFs.
2427                  * There is no need for pf to have so many tqp numbers in
2428                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2429                  * coming from config file, is assigned to maximum queue number
2430                  * for the PF of this port by user. So users can modify the
2431                  * maximum queue number of PF according to their own application
2432                  * scenarios, which is more flexible to use. In addition, many
2433                  * memories can be saved due to allocating queue statistics
2434                  * room according to the actual number of queues required. The
2435                  * maximum queue number of PF for network engine with
2436                  * revision_id greater than 0x30 is assigned by config file.
2437                  */
2438                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2439                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2440                                  "must be greater than 0.",
2441                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2442                         return -EINVAL;
2443                 }
2444
2445                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2446                                        hw->total_tqps_num);
2447         } else {
2448                 /*
2449                  * Due to the limitation on the number of PF interrupts
2450                  * available, the maximum queue number assigned to PF on
2451                  * the network engine with revision_id 0x21 is 64.
2452                  */
2453                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2454                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2455         }
2456
2457         return 0;
2458 }
2459
2460 static int
2461 hns3_query_pf_resource(struct hns3_hw *hw)
2462 {
2463         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2464         struct hns3_pf *pf = &hns->pf;
2465         struct hns3_pf_res_cmd *req;
2466         struct hns3_cmd_desc desc;
2467         int ret;
2468
2469         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2470         ret = hns3_cmd_send(hw, &desc, 1);
2471         if (ret) {
2472                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2473                 return ret;
2474         }
2475
2476         req = (struct hns3_pf_res_cmd *)desc.data;
2477         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2478                              rte_le_to_cpu_16(req->ext_tqp_num);
2479         ret = hns3_get_pf_max_tqp_num(hw);
2480         if (ret)
2481                 return ret;
2482
2483         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2484         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2485
2486         if (req->tx_buf_size)
2487                 pf->tx_buf_size =
2488                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2489         else
2490                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2491
2492         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2493
2494         if (req->dv_buf_size)
2495                 pf->dv_buf_size =
2496                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2497         else
2498                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2499
2500         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2501
2502         hw->num_msi =
2503                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2504                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2505
2506         return 0;
2507 }
2508
2509 static void
2510 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2511 {
2512         struct hns3_cfg_param_cmd *req;
2513         uint64_t mac_addr_tmp_high;
2514         uint8_t ext_rss_size_max;
2515         uint64_t mac_addr_tmp;
2516         uint32_t i;
2517
2518         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2519
2520         /* get the configuration */
2521         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2522                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2523
2524         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2525                                        HNS3_CFG_PHY_ADDR_M,
2526                                        HNS3_CFG_PHY_ADDR_S);
2527         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2528                                          HNS3_CFG_MEDIA_TP_M,
2529                                          HNS3_CFG_MEDIA_TP_S);
2530         /* get mac address */
2531         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2532         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2533                                            HNS3_CFG_MAC_ADDR_H_M,
2534                                            HNS3_CFG_MAC_ADDR_H_S);
2535
2536         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2537
2538         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2539                                             HNS3_CFG_DEFAULT_SPEED_M,
2540                                             HNS3_CFG_DEFAULT_SPEED_S);
2541         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2542                                            HNS3_CFG_RSS_SIZE_M,
2543                                            HNS3_CFG_RSS_SIZE_S);
2544
2545         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2546                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2547
2548         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2549         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2550
2551         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2552                                             HNS3_CFG_SPEED_ABILITY_M,
2553                                             HNS3_CFG_SPEED_ABILITY_S);
2554         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2555                                         HNS3_CFG_UMV_TBL_SPACE_M,
2556                                         HNS3_CFG_UMV_TBL_SPACE_S);
2557         if (!cfg->umv_space)
2558                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2559
2560         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2561                                                HNS3_CFG_EXT_RSS_SIZE_M,
2562                                                HNS3_CFG_EXT_RSS_SIZE_S);
2563         /*
2564          * Field ext_rss_size_max obtained from firmware will be more flexible
2565          * for future changes and expansions, which is an exponent of 2, instead
2566          * of reading out directly. If this field is not zero, hns3 PF PMD
2567          * uses it as rss_size_max under one TC. Device, whose revision
2568          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2569          * maximum number of queues supported under a TC through this field.
2570          */
2571         if (ext_rss_size_max)
2572                 cfg->rss_size_max = 1U << ext_rss_size_max;
2573 }
2574
2575 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2576  * @hw: pointer to struct hns3_hw
2577  * @hcfg: the config structure to be getted
2578  */
2579 static int
2580 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2581 {
2582         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2583         struct hns3_cfg_param_cmd *req;
2584         uint32_t offset;
2585         uint32_t i;
2586         int ret;
2587
2588         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2589                 offset = 0;
2590                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2591                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2592                                           true);
2593                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2594                                i * HNS3_CFG_RD_LEN_BYTES);
2595                 /* Len should be divided by 4 when send to hardware */
2596                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2597                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2598                 req->offset = rte_cpu_to_le_32(offset);
2599         }
2600
2601         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2602         if (ret) {
2603                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2604                 return ret;
2605         }
2606
2607         hns3_parse_cfg(hcfg, desc);
2608
2609         return 0;
2610 }
2611
2612 static int
2613 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2614 {
2615         switch (speed_cmd) {
2616         case HNS3_CFG_SPEED_10M:
2617                 *speed = RTE_ETH_SPEED_NUM_10M;
2618                 break;
2619         case HNS3_CFG_SPEED_100M:
2620                 *speed = RTE_ETH_SPEED_NUM_100M;
2621                 break;
2622         case HNS3_CFG_SPEED_1G:
2623                 *speed = RTE_ETH_SPEED_NUM_1G;
2624                 break;
2625         case HNS3_CFG_SPEED_10G:
2626                 *speed = RTE_ETH_SPEED_NUM_10G;
2627                 break;
2628         case HNS3_CFG_SPEED_25G:
2629                 *speed = RTE_ETH_SPEED_NUM_25G;
2630                 break;
2631         case HNS3_CFG_SPEED_40G:
2632                 *speed = RTE_ETH_SPEED_NUM_40G;
2633                 break;
2634         case HNS3_CFG_SPEED_50G:
2635                 *speed = RTE_ETH_SPEED_NUM_50G;
2636                 break;
2637         case HNS3_CFG_SPEED_100G:
2638                 *speed = RTE_ETH_SPEED_NUM_100G;
2639                 break;
2640         case HNS3_CFG_SPEED_200G:
2641                 *speed = RTE_ETH_SPEED_NUM_200G;
2642                 break;
2643         default:
2644                 return -EINVAL;
2645         }
2646
2647         return 0;
2648 }
2649
2650 static void
2651 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2652 {
2653         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2654         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2655         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2656         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2657         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2658 }
2659
2660 static void
2661 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2662 {
2663         struct hns3_dev_specs_0_cmd *req0;
2664
2665         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2666
2667         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2668         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2669         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2670         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2671         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2672 }
2673
2674 static int
2675 hns3_check_dev_specifications(struct hns3_hw *hw)
2676 {
2677         if (hw->rss_ind_tbl_size == 0 ||
2678             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
2679                 hns3_err(hw, "the size of hash lookup table configured (%u)"
2680                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
2681                               HNS3_RSS_IND_TBL_SIZE_MAX);
2682                 return -EINVAL;
2683         }
2684
2685         return 0;
2686 }
2687
2688 static int
2689 hns3_query_dev_specifications(struct hns3_hw *hw)
2690 {
2691         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2692         int ret;
2693         int i;
2694
2695         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2696                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2697                                           true);
2698                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2699         }
2700         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2701
2702         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2703         if (ret)
2704                 return ret;
2705
2706         hns3_parse_dev_specifications(hw, desc);
2707
2708         return hns3_check_dev_specifications(hw);
2709 }
2710
2711 static int
2712 hns3_get_capability(struct hns3_hw *hw)
2713 {
2714         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2715         struct rte_pci_device *pci_dev;
2716         struct hns3_pf *pf = &hns->pf;
2717         struct rte_eth_dev *eth_dev;
2718         uint16_t device_id;
2719         int ret;
2720
2721         eth_dev = &rte_eth_devices[hw->data->port_id];
2722         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2723         device_id = pci_dev->id.device_id;
2724
2725         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2726             device_id == HNS3_DEV_ID_50GE_RDMA ||
2727             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2728             device_id == HNS3_DEV_ID_200G_RDMA)
2729                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2730
2731         ret = hns3_get_pci_revision_id(hw, &hw->revision);
2732         if (ret)
2733                 return ret;
2734
2735         ret = hns3_query_mac_stats_reg_num(hw);
2736         if (ret)
2737                 return ret;
2738
2739         if (hw->revision < PCI_REVISION_ID_HIP09_A) {
2740                 hns3_set_default_dev_specifications(hw);
2741                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2742                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2743                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
2744                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
2745                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
2746                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2747                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
2748                 hw->rss_info.ipv6_sctp_offload_supported = false;
2749                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
2750                 pf->support_multi_tc_pause = false;
2751                 return 0;
2752         }
2753
2754         ret = hns3_query_dev_specifications(hw);
2755         if (ret) {
2756                 PMD_INIT_LOG(ERR,
2757                              "failed to query dev specifications, ret = %d",
2758                              ret);
2759                 return ret;
2760         }
2761
2762         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
2763         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
2764         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
2765         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
2766         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
2767         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
2768         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
2769         hw->rss_info.ipv6_sctp_offload_supported = true;
2770         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
2771         pf->support_multi_tc_pause = true;
2772
2773         return 0;
2774 }
2775
2776 static int
2777 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
2778 {
2779         int ret;
2780
2781         switch (media_type) {
2782         case HNS3_MEDIA_TYPE_COPPER:
2783                 if (!hns3_dev_get_support(hw, COPPER)) {
2784                         PMD_INIT_LOG(ERR,
2785                                      "Media type is copper, not supported.");
2786                         ret = -EOPNOTSUPP;
2787                 } else {
2788                         ret = 0;
2789                 }
2790                 break;
2791         case HNS3_MEDIA_TYPE_FIBER:
2792                 ret = 0;
2793                 break;
2794         case HNS3_MEDIA_TYPE_BACKPLANE:
2795                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
2796                 ret = -EOPNOTSUPP;
2797                 break;
2798         default:
2799                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
2800                 ret = -EINVAL;
2801                 break;
2802         }
2803
2804         return ret;
2805 }
2806
2807 static int
2808 hns3_get_board_configuration(struct hns3_hw *hw)
2809 {
2810         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2811         struct hns3_pf *pf = &hns->pf;
2812         struct hns3_cfg cfg;
2813         int ret;
2814
2815         ret = hns3_get_board_cfg(hw, &cfg);
2816         if (ret) {
2817                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2818                 return ret;
2819         }
2820
2821         ret = hns3_check_media_type(hw, cfg.media_type);
2822         if (ret)
2823                 return ret;
2824
2825         hw->mac.media_type = cfg.media_type;
2826         hw->rss_size_max = cfg.rss_size_max;
2827         hw->rss_dis_flag = false;
2828         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2829         hw->mac.phy_addr = cfg.phy_addr;
2830         hw->dcb_info.num_pg = 1;
2831         hw->dcb_info.hw_pfc_map = 0;
2832
2833         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2834         if (ret) {
2835                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
2836                              cfg.default_speed, ret);
2837                 return ret;
2838         }
2839
2840         pf->tc_max = cfg.tc_num;
2841         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2842                 PMD_INIT_LOG(WARNING,
2843                              "Get TC num(%u) from flash, set TC num to 1",
2844                              pf->tc_max);
2845                 pf->tc_max = 1;
2846         }
2847
2848         /* Dev does not support DCB */
2849         if (!hns3_dev_get_support(hw, DCB)) {
2850                 pf->tc_max = 1;
2851                 pf->pfc_max = 0;
2852         } else
2853                 pf->pfc_max = pf->tc_max;
2854
2855         hw->dcb_info.num_tc = 1;
2856         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2857                                      hw->tqps_num / hw->dcb_info.num_tc);
2858         hns3_set_bit(hw->hw_tc_map, 0, 1);
2859         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2860
2861         pf->wanted_umv_size = cfg.umv_space;
2862
2863         return ret;
2864 }
2865
2866 static int
2867 hns3_get_configuration(struct hns3_hw *hw)
2868 {
2869         int ret;
2870
2871         ret = hns3_query_function_status(hw);
2872         if (ret) {
2873                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2874                 return ret;
2875         }
2876
2877         /* Get device capability */
2878         ret = hns3_get_capability(hw);
2879         if (ret) {
2880                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
2881                 return ret;
2882         }
2883
2884         /* Get pf resource */
2885         ret = hns3_query_pf_resource(hw);
2886         if (ret) {
2887                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2888                 return ret;
2889         }
2890
2891         ret = hns3_get_board_configuration(hw);
2892         if (ret) {
2893                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
2894                 return ret;
2895         }
2896
2897         ret = hns3_query_dev_fec_info(hw);
2898         if (ret)
2899                 PMD_INIT_LOG(ERR,
2900                              "failed to query FEC information, ret = %d", ret);
2901
2902         return ret;
2903 }
2904
2905 static int
2906 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2907                       uint16_t tqp_vid, bool is_pf)
2908 {
2909         struct hns3_tqp_map_cmd *req;
2910         struct hns3_cmd_desc desc;
2911         int ret;
2912
2913         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2914
2915         req = (struct hns3_tqp_map_cmd *)desc.data;
2916         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2917         req->tqp_vf = func_id;
2918         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2919         if (!is_pf)
2920                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2921         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2922
2923         ret = hns3_cmd_send(hw, &desc, 1);
2924         if (ret)
2925                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2926
2927         return ret;
2928 }
2929
2930 static int
2931 hns3_map_tqp(struct hns3_hw *hw)
2932 {
2933         int ret;
2934         int i;
2935
2936         /*
2937          * In current version, VF is not supported when PF is driven by DPDK
2938          * driver, so we assign total tqps_num tqps allocated to this port
2939          * to PF.
2940          */
2941         for (i = 0; i < hw->total_tqps_num; i++) {
2942                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
2943                 if (ret)
2944                         return ret;
2945         }
2946
2947         return 0;
2948 }
2949
2950 static int
2951 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2952 {
2953         struct hns3_config_mac_speed_dup_cmd *req;
2954         struct hns3_cmd_desc desc;
2955         int ret;
2956
2957         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2958
2959         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2960
2961         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2962
2963         switch (speed) {
2964         case RTE_ETH_SPEED_NUM_10M:
2965                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2966                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2967                 break;
2968         case RTE_ETH_SPEED_NUM_100M:
2969                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2970                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2971                 break;
2972         case RTE_ETH_SPEED_NUM_1G:
2973                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2974                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2975                 break;
2976         case RTE_ETH_SPEED_NUM_10G:
2977                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2978                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2979                 break;
2980         case RTE_ETH_SPEED_NUM_25G:
2981                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2982                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2983                 break;
2984         case RTE_ETH_SPEED_NUM_40G:
2985                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2986                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2987                 break;
2988         case RTE_ETH_SPEED_NUM_50G:
2989                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2990                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2991                 break;
2992         case RTE_ETH_SPEED_NUM_100G:
2993                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2994                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2995                 break;
2996         case RTE_ETH_SPEED_NUM_200G:
2997                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2998                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
2999                 break;
3000         default:
3001                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3002                 return -EINVAL;
3003         }
3004
3005         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3006
3007         ret = hns3_cmd_send(hw, &desc, 1);
3008         if (ret)
3009                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3010
3011         return ret;
3012 }
3013
3014 static int
3015 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3016 {
3017         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3018         struct hns3_pf *pf = &hns->pf;
3019         struct hns3_priv_buf *priv;
3020         uint32_t i, total_size;
3021
3022         total_size = pf->pkt_buf_size;
3023
3024         /* alloc tx buffer for all enabled tc */
3025         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3026                 priv = &buf_alloc->priv_buf[i];
3027
3028                 if (hw->hw_tc_map & BIT(i)) {
3029                         if (total_size < pf->tx_buf_size)
3030                                 return -ENOMEM;
3031
3032                         priv->tx_buf_size = pf->tx_buf_size;
3033                 } else
3034                         priv->tx_buf_size = 0;
3035
3036                 total_size -= priv->tx_buf_size;
3037         }
3038
3039         return 0;
3040 }
3041
3042 static int
3043 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3044 {
3045 /* TX buffer size is unit by 128 byte */
3046 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3047 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3048         struct hns3_tx_buff_alloc_cmd *req;
3049         struct hns3_cmd_desc desc;
3050         uint32_t buf_size;
3051         uint32_t i;
3052         int ret;
3053
3054         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3055
3056         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3057         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3058                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3059
3060                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3061                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3062                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3063         }
3064
3065         ret = hns3_cmd_send(hw, &desc, 1);
3066         if (ret)
3067                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3068
3069         return ret;
3070 }
3071
3072 static int
3073 hns3_get_tc_num(struct hns3_hw *hw)
3074 {
3075         int cnt = 0;
3076         uint8_t i;
3077
3078         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3079                 if (hw->hw_tc_map & BIT(i))
3080                         cnt++;
3081         return cnt;
3082 }
3083
3084 static uint32_t
3085 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3086 {
3087         struct hns3_priv_buf *priv;
3088         uint32_t rx_priv = 0;
3089         int i;
3090
3091         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3092                 priv = &buf_alloc->priv_buf[i];
3093                 if (priv->enable)
3094                         rx_priv += priv->buf_size;
3095         }
3096         return rx_priv;
3097 }
3098
3099 static uint32_t
3100 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3101 {
3102         uint32_t total_tx_size = 0;
3103         uint32_t i;
3104
3105         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3106                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3107
3108         return total_tx_size;
3109 }
3110
3111 /* Get the number of pfc enabled TCs, which have private buffer */
3112 static int
3113 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3114 {
3115         struct hns3_priv_buf *priv;
3116         int cnt = 0;
3117         uint8_t i;
3118
3119         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3120                 priv = &buf_alloc->priv_buf[i];
3121                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3122                         cnt++;
3123         }
3124
3125         return cnt;
3126 }
3127
3128 /* Get the number of pfc disabled TCs, which have private buffer */
3129 static int
3130 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3131                          struct hns3_pkt_buf_alloc *buf_alloc)
3132 {
3133         struct hns3_priv_buf *priv;
3134         int cnt = 0;
3135         uint8_t i;
3136
3137         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3138                 priv = &buf_alloc->priv_buf[i];
3139                 if (hw->hw_tc_map & BIT(i) &&
3140                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3141                         cnt++;
3142         }
3143
3144         return cnt;
3145 }
3146
3147 static bool
3148 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3149                   uint32_t rx_all)
3150 {
3151         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3152         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3153         struct hns3_pf *pf = &hns->pf;
3154         uint32_t shared_buf, aligned_mps;
3155         uint32_t rx_priv;
3156         uint8_t tc_num;
3157         uint8_t i;
3158
3159         tc_num = hns3_get_tc_num(hw);
3160         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3161
3162         if (hns3_dev_get_support(hw, DCB))
3163                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3164                                         pf->dv_buf_size;
3165         else
3166                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3167                                         + pf->dv_buf_size;
3168
3169         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3170         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3171                              HNS3_BUF_SIZE_UNIT);
3172
3173         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3174         if (rx_all < rx_priv + shared_std)
3175                 return false;
3176
3177         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3178         buf_alloc->s_buf.buf_size = shared_buf;
3179         if (hns3_dev_get_support(hw, DCB)) {
3180                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3181                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3182                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3183                                   HNS3_BUF_SIZE_UNIT);
3184         } else {
3185                 buf_alloc->s_buf.self.high =
3186                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3187                 buf_alloc->s_buf.self.low = aligned_mps;
3188         }
3189
3190         if (hns3_dev_get_support(hw, DCB)) {
3191                 hi_thrd = shared_buf - pf->dv_buf_size;
3192
3193                 if (tc_num <= NEED_RESERVE_TC_NUM)
3194                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3195                                   BUF_MAX_PERCENT;
3196
3197                 if (tc_num)
3198                         hi_thrd = hi_thrd / tc_num;
3199
3200                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3201                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3202                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3203         } else {
3204                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3205                 lo_thrd = aligned_mps;
3206         }
3207
3208         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3209                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3210                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3211         }
3212
3213         return true;
3214 }
3215
3216 static bool
3217 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3218                      struct hns3_pkt_buf_alloc *buf_alloc)
3219 {
3220         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3221         struct hns3_pf *pf = &hns->pf;
3222         struct hns3_priv_buf *priv;
3223         uint32_t aligned_mps;
3224         uint32_t rx_all;
3225         uint8_t i;
3226
3227         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3228         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3229
3230         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3231                 priv = &buf_alloc->priv_buf[i];
3232
3233                 priv->enable = 0;
3234                 priv->wl.low = 0;
3235                 priv->wl.high = 0;
3236                 priv->buf_size = 0;
3237
3238                 if (!(hw->hw_tc_map & BIT(i)))
3239                         continue;
3240
3241                 priv->enable = 1;
3242                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3243                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3244                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3245                                                 HNS3_BUF_SIZE_UNIT);
3246                 } else {
3247                         priv->wl.low = 0;
3248                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3249                                         aligned_mps;
3250                 }
3251
3252                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3253         }
3254
3255         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3256 }
3257
3258 static bool
3259 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3260                              struct hns3_pkt_buf_alloc *buf_alloc)
3261 {
3262         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3263         struct hns3_pf *pf = &hns->pf;
3264         struct hns3_priv_buf *priv;
3265         int no_pfc_priv_num;
3266         uint32_t rx_all;
3267         uint8_t mask;
3268         int i;
3269
3270         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3271         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3272
3273         /* let the last to be cleared first */
3274         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3275                 priv = &buf_alloc->priv_buf[i];
3276                 mask = BIT((uint8_t)i);
3277                 if (hw->hw_tc_map & mask &&
3278                     !(hw->dcb_info.hw_pfc_map & mask)) {
3279                         /* Clear the no pfc TC private buffer */
3280                         priv->wl.low = 0;
3281                         priv->wl.high = 0;
3282                         priv->buf_size = 0;
3283                         priv->enable = 0;
3284                         no_pfc_priv_num--;
3285                 }
3286
3287                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3288                     no_pfc_priv_num == 0)
3289                         break;
3290         }
3291
3292         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3293 }
3294
3295 static bool
3296 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3297                            struct hns3_pkt_buf_alloc *buf_alloc)
3298 {
3299         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3300         struct hns3_pf *pf = &hns->pf;
3301         struct hns3_priv_buf *priv;
3302         uint32_t rx_all;
3303         int pfc_priv_num;
3304         uint8_t mask;
3305         int i;
3306
3307         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3308         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3309
3310         /* let the last to be cleared first */
3311         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3312                 priv = &buf_alloc->priv_buf[i];
3313                 mask = BIT((uint8_t)i);
3314                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3315                         /* Reduce the number of pfc TC with private buffer */
3316                         priv->wl.low = 0;
3317                         priv->enable = 0;
3318                         priv->wl.high = 0;
3319                         priv->buf_size = 0;
3320                         pfc_priv_num--;
3321                 }
3322                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3323                     pfc_priv_num == 0)
3324                         break;
3325         }
3326
3327         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3328 }
3329
3330 static bool
3331 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3332                           struct hns3_pkt_buf_alloc *buf_alloc)
3333 {
3334 #define COMPENSATE_BUFFER       0x3C00
3335 #define COMPENSATE_HALF_MPS_NUM 5
3336 #define PRIV_WL_GAP             0x1800
3337         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3338         struct hns3_pf *pf = &hns->pf;
3339         uint32_t tc_num = hns3_get_tc_num(hw);
3340         uint32_t half_mps = pf->mps >> 1;
3341         struct hns3_priv_buf *priv;
3342         uint32_t min_rx_priv;
3343         uint32_t rx_priv;
3344         uint8_t i;
3345
3346         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3347         if (tc_num)
3348                 rx_priv = rx_priv / tc_num;
3349
3350         if (tc_num <= NEED_RESERVE_TC_NUM)
3351                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3352
3353         /*
3354          * Minimum value of private buffer in rx direction (min_rx_priv) is
3355          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3356          * buffer if rx_priv is greater than min_rx_priv.
3357          */
3358         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3359                         COMPENSATE_HALF_MPS_NUM * half_mps;
3360         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3361         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3362         if (rx_priv < min_rx_priv)
3363                 return false;
3364
3365         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3366                 priv = &buf_alloc->priv_buf[i];
3367                 priv->enable = 0;
3368                 priv->wl.low = 0;
3369                 priv->wl.high = 0;
3370                 priv->buf_size = 0;
3371
3372                 if (!(hw->hw_tc_map & BIT(i)))
3373                         continue;
3374
3375                 priv->enable = 1;
3376                 priv->buf_size = rx_priv;
3377                 priv->wl.high = rx_priv - pf->dv_buf_size;
3378                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3379         }
3380
3381         buf_alloc->s_buf.buf_size = 0;
3382
3383         return true;
3384 }
3385
3386 /*
3387  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3388  * @hw: pointer to struct hns3_hw
3389  * @buf_alloc: pointer to buffer calculation data
3390  * @return: 0: calculate successful, negative: fail
3391  */
3392 static int
3393 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3394 {
3395         /* When DCB is not supported, rx private buffer is not allocated. */
3396         if (!hns3_dev_get_support(hw, DCB)) {
3397                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3398                 struct hns3_pf *pf = &hns->pf;
3399                 uint32_t rx_all = pf->pkt_buf_size;
3400
3401                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3402                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3403                         return -ENOMEM;
3404
3405                 return 0;
3406         }
3407
3408         /*
3409          * Try to allocate privated packet buffer for all TCs without share
3410          * buffer.
3411          */
3412         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3413                 return 0;
3414
3415         /*
3416          * Try to allocate privated packet buffer for all TCs with share
3417          * buffer.
3418          */
3419         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3420                 return 0;
3421
3422         /*
3423          * For different application scenes, the enabled port number, TC number
3424          * and no_drop TC number are different. In order to obtain the better
3425          * performance, software could allocate the buffer size and configure
3426          * the waterline by trying to decrease the private buffer size according
3427          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
3428          * enabled tc.
3429          */
3430         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3431                 return 0;
3432
3433         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3434                 return 0;
3435
3436         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3437                 return 0;
3438
3439         return -ENOMEM;
3440 }
3441
3442 static int
3443 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3444 {
3445         struct hns3_rx_priv_buff_cmd *req;
3446         struct hns3_cmd_desc desc;
3447         uint32_t buf_size;
3448         int ret;
3449         int i;
3450
3451         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3452         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3453
3454         /* Alloc private buffer TCs */
3455         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3456                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3457
3458                 req->buf_num[i] =
3459                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3460                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3461         }
3462
3463         buf_size = buf_alloc->s_buf.buf_size;
3464         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3465                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3466
3467         ret = hns3_cmd_send(hw, &desc, 1);
3468         if (ret)
3469                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3470
3471         return ret;
3472 }
3473
3474 static int
3475 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3476 {
3477 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3478         struct hns3_rx_priv_wl_buf *req;
3479         struct hns3_priv_buf *priv;
3480         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3481         int i, j;
3482         int ret;
3483
3484         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3485                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3486                                           false);
3487                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3488
3489                 /* The first descriptor set the NEXT bit to 1 */
3490                 if (i == 0)
3491                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3492                 else
3493                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3494
3495                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3496                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3497
3498                         priv = &buf_alloc->priv_buf[idx];
3499                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3500                                                         HNS3_BUF_UNIT_S);
3501                         req->tc_wl[j].high |=
3502                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3503                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3504                                                         HNS3_BUF_UNIT_S);
3505                         req->tc_wl[j].low |=
3506                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3507                 }
3508         }
3509
3510         /* Send 2 descriptor at one time */
3511         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3512         if (ret)
3513                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3514                              ret);
3515         return ret;
3516 }
3517
3518 static int
3519 hns3_common_thrd_config(struct hns3_hw *hw,
3520                         struct hns3_pkt_buf_alloc *buf_alloc)
3521 {
3522 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3523         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3524         struct hns3_rx_com_thrd *req;
3525         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3526         struct hns3_tc_thrd *tc;
3527         int tc_idx;
3528         int i, j;
3529         int ret;
3530
3531         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3532                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3533                                           false);
3534                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3535
3536                 /* The first descriptor set the NEXT bit to 1 */
3537                 if (i == 0)
3538                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3539                 else
3540                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3541
3542                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3543                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3544                         tc = &s_buf->tc_thrd[tc_idx];
3545
3546                         req->com_thrd[j].high =
3547                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3548                         req->com_thrd[j].high |=
3549                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3550                         req->com_thrd[j].low =
3551                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3552                         req->com_thrd[j].low |=
3553                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3554                 }
3555         }
3556
3557         /* Send 2 descriptors at one time */
3558         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3559         if (ret)
3560                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3561
3562         return ret;
3563 }
3564
3565 static int
3566 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3567 {
3568         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3569         struct hns3_rx_com_wl *req;
3570         struct hns3_cmd_desc desc;
3571         int ret;
3572
3573         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3574
3575         req = (struct hns3_rx_com_wl *)desc.data;
3576         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3577         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3578
3579         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3580         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3581
3582         ret = hns3_cmd_send(hw, &desc, 1);
3583         if (ret)
3584                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3585
3586         return ret;
3587 }
3588
3589 int
3590 hns3_buffer_alloc(struct hns3_hw *hw)
3591 {
3592         struct hns3_pkt_buf_alloc pkt_buf;
3593         int ret;
3594
3595         memset(&pkt_buf, 0, sizeof(pkt_buf));
3596         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3597         if (ret) {
3598                 PMD_INIT_LOG(ERR,
3599                              "could not calc tx buffer size for all TCs %d",
3600                              ret);
3601                 return ret;
3602         }
3603
3604         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3605         if (ret) {
3606                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3607                 return ret;
3608         }
3609
3610         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3611         if (ret) {
3612                 PMD_INIT_LOG(ERR,
3613                              "could not calc rx priv buffer size for all TCs %d",
3614                              ret);
3615                 return ret;
3616         }
3617
3618         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3619         if (ret) {
3620                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3621                 return ret;
3622         }
3623
3624         if (hns3_dev_get_support(hw, DCB)) {
3625                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3626                 if (ret) {
3627                         PMD_INIT_LOG(ERR,
3628                                      "could not configure rx private waterline %d",
3629                                      ret);
3630                         return ret;
3631                 }
3632
3633                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3634                 if (ret) {
3635                         PMD_INIT_LOG(ERR,
3636                                      "could not configure common threshold %d",
3637                                      ret);
3638                         return ret;
3639                 }
3640         }
3641
3642         ret = hns3_common_wl_config(hw, &pkt_buf);
3643         if (ret)
3644                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3645                              ret);
3646
3647         return ret;
3648 }
3649
3650 static int
3651 hns3_mac_init(struct hns3_hw *hw)
3652 {
3653         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3654         struct hns3_mac *mac = &hw->mac;
3655         struct hns3_pf *pf = &hns->pf;
3656         int ret;
3657
3658         pf->support_sfp_query = true;
3659         mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3660         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3661         if (ret) {
3662                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3663                 return ret;
3664         }
3665
3666         mac->link_status = RTE_ETH_LINK_DOWN;
3667
3668         return hns3_config_mtu(hw, pf->mps);
3669 }
3670
3671 static int
3672 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3673 {
3674 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3675 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3676 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3677 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3678         int return_status;
3679
3680         if (cmdq_resp) {
3681                 PMD_INIT_LOG(ERR,
3682                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3683                              cmdq_resp);
3684                 return -EIO;
3685         }
3686
3687         switch (resp_code) {
3688         case HNS3_ETHERTYPE_SUCCESS_ADD:
3689         case HNS3_ETHERTYPE_ALREADY_ADD:
3690                 return_status = 0;
3691                 break;
3692         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3693                 PMD_INIT_LOG(ERR,
3694                              "add mac ethertype failed for manager table overflow.");
3695                 return_status = -EIO;
3696                 break;
3697         case HNS3_ETHERTYPE_KEY_CONFLICT:
3698                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3699                 return_status = -EIO;
3700                 break;
3701         default:
3702                 PMD_INIT_LOG(ERR,
3703                              "add mac ethertype failed for undefined, code=%u.",
3704                              resp_code);
3705                 return_status = -EIO;
3706                 break;
3707         }
3708
3709         return return_status;
3710 }
3711
3712 static int
3713 hns3_add_mgr_tbl(struct hns3_hw *hw,
3714                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3715 {
3716         struct hns3_cmd_desc desc;
3717         uint8_t resp_code;
3718         uint16_t retval;
3719         int ret;
3720
3721         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3722         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3723
3724         ret = hns3_cmd_send(hw, &desc, 1);
3725         if (ret) {
3726                 PMD_INIT_LOG(ERR,
3727                              "add mac ethertype failed for cmd_send, ret =%d.",
3728                              ret);
3729                 return ret;
3730         }
3731
3732         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3733         retval = rte_le_to_cpu_16(desc.retval);
3734
3735         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3736 }
3737
3738 static void
3739 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3740                      int *table_item_num)
3741 {
3742         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3743
3744         /*
3745          * In current version, we add one item in management table as below:
3746          * 0x0180C200000E -- LLDP MC address
3747          */
3748         tbl = mgr_table;
3749         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3750         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3751         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3752         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3753         tbl->i_port_bitmap = 0x1;
3754         *table_item_num = 1;
3755 }
3756
3757 static int
3758 hns3_init_mgr_tbl(struct hns3_hw *hw)
3759 {
3760 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3761         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3762         int table_item_num;
3763         int ret;
3764         int i;
3765
3766         memset(mgr_table, 0, sizeof(mgr_table));
3767         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3768         for (i = 0; i < table_item_num; i++) {
3769                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3770                 if (ret) {
3771                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3772                                      ret);
3773                         return ret;
3774                 }
3775         }
3776
3777         return 0;
3778 }
3779
3780 static void
3781 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3782                         bool en_mc, bool en_bc, int vport_id)
3783 {
3784         if (!param)
3785                 return;
3786
3787         memset(param, 0, sizeof(struct hns3_promisc_param));
3788         if (en_uc)
3789                 param->enable = HNS3_PROMISC_EN_UC;
3790         if (en_mc)
3791                 param->enable |= HNS3_PROMISC_EN_MC;
3792         if (en_bc)
3793                 param->enable |= HNS3_PROMISC_EN_BC;
3794         param->vf_id = vport_id;
3795 }
3796
3797 static int
3798 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3799 {
3800         struct hns3_promisc_cfg_cmd *req;
3801         struct hns3_cmd_desc desc;
3802         int ret;
3803
3804         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3805
3806         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3807         req->vf_id = param->vf_id;
3808         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3809             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3810
3811         ret = hns3_cmd_send(hw, &desc, 1);
3812         if (ret)
3813                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3814
3815         return ret;
3816 }
3817
3818 static int
3819 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3820 {
3821         struct hns3_promisc_param param;
3822         bool en_bc_pmc = true;
3823         uint8_t vf_id;
3824
3825         /*
3826          * In current version VF is not supported when PF is driven by DPDK
3827          * driver, just need to configure parameters for PF vport.
3828          */
3829         vf_id = HNS3_PF_FUNC_ID;
3830
3831         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3832         return hns3_cmd_set_promisc_mode(hw, &param);
3833 }
3834
3835 static int
3836 hns3_promisc_init(struct hns3_hw *hw)
3837 {
3838         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3839         struct hns3_pf *pf = &hns->pf;
3840         struct hns3_promisc_param param;
3841         uint16_t func_id;
3842         int ret;
3843
3844         ret = hns3_set_promisc_mode(hw, false, false);
3845         if (ret) {
3846                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3847                 return ret;
3848         }
3849
3850         /*
3851          * In current version VFs are not supported when PF is driven by DPDK
3852          * driver. After PF has been taken over by DPDK, the original VF will
3853          * be invalid. So, there is a possibility of entry residues. It should
3854          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3855          * during init.
3856          */
3857         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3858                 hns3_promisc_param_init(&param, false, false, false, func_id);
3859                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3860                 if (ret) {
3861                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
3862                                         " ret = %d", func_id, ret);
3863                         return ret;
3864                 }
3865         }
3866
3867         return 0;
3868 }
3869
3870 static void
3871 hns3_promisc_uninit(struct hns3_hw *hw)
3872 {
3873         struct hns3_promisc_param param;
3874         uint16_t func_id;
3875         int ret;
3876
3877         func_id = HNS3_PF_FUNC_ID;
3878
3879         /*
3880          * In current version VFs are not supported when PF is driven by
3881          * DPDK driver, and VFs' promisc mode status has been cleared during
3882          * init and their status will not change. So just clear PF's promisc
3883          * mode status during uninit.
3884          */
3885         hns3_promisc_param_init(&param, false, false, false, func_id);
3886         ret = hns3_cmd_set_promisc_mode(hw, &param);
3887         if (ret)
3888                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3889                                 " uninit, ret = %d", ret);
3890 }
3891
3892 static int
3893 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3894 {
3895         bool allmulti = dev->data->all_multicast ? true : false;
3896         struct hns3_adapter *hns = dev->data->dev_private;
3897         struct hns3_hw *hw = &hns->hw;
3898         uint64_t offloads;
3899         int err;
3900         int ret;
3901
3902         rte_spinlock_lock(&hw->lock);
3903         ret = hns3_set_promisc_mode(hw, true, true);
3904         if (ret) {
3905                 rte_spinlock_unlock(&hw->lock);
3906                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3907                          ret);
3908                 return ret;
3909         }
3910
3911         /*
3912          * When promiscuous mode was enabled, disable the vlan filter to let
3913          * all packets coming in in the receiving direction.
3914          */
3915         offloads = dev->data->dev_conf.rxmode.offloads;
3916         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
3917                 ret = hns3_enable_vlan_filter(hns, false);
3918                 if (ret) {
3919                         hns3_err(hw, "failed to enable promiscuous mode due to "
3920                                      "failure to disable vlan filter, ret = %d",
3921                                  ret);
3922                         err = hns3_set_promisc_mode(hw, false, allmulti);
3923                         if (err)
3924                                 hns3_err(hw, "failed to restore promiscuous "
3925                                          "status after disable vlan filter "
3926                                          "failed during enabling promiscuous "
3927                                          "mode, ret = %d", ret);
3928                 }
3929         }
3930
3931         rte_spinlock_unlock(&hw->lock);
3932
3933         return ret;
3934 }
3935
3936 static int
3937 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3938 {
3939         bool allmulti = dev->data->all_multicast ? true : false;
3940         struct hns3_adapter *hns = dev->data->dev_private;
3941         struct hns3_hw *hw = &hns->hw;
3942         uint64_t offloads;
3943         int err;
3944         int ret;
3945
3946         /* If now in all_multicast mode, must remain in all_multicast mode. */
3947         rte_spinlock_lock(&hw->lock);
3948         ret = hns3_set_promisc_mode(hw, false, allmulti);
3949         if (ret) {
3950                 rte_spinlock_unlock(&hw->lock);
3951                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3952                          ret);
3953                 return ret;
3954         }
3955         /* when promiscuous mode was disabled, restore the vlan filter status */
3956         offloads = dev->data->dev_conf.rxmode.offloads;
3957         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
3958                 ret = hns3_enable_vlan_filter(hns, true);
3959                 if (ret) {
3960                         hns3_err(hw, "failed to disable promiscuous mode due to"
3961                                  " failure to restore vlan filter, ret = %d",
3962                                  ret);
3963                         err = hns3_set_promisc_mode(hw, true, true);
3964                         if (err)
3965                                 hns3_err(hw, "failed to restore promiscuous "
3966                                          "status after enabling vlan filter "
3967                                          "failed during disabling promiscuous "
3968                                          "mode, ret = %d", ret);
3969                 }
3970         }
3971         rte_spinlock_unlock(&hw->lock);
3972
3973         return ret;
3974 }
3975
3976 static int
3977 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3978 {
3979         struct hns3_adapter *hns = dev->data->dev_private;
3980         struct hns3_hw *hw = &hns->hw;
3981         int ret;
3982
3983         if (dev->data->promiscuous)
3984                 return 0;
3985
3986         rte_spinlock_lock(&hw->lock);
3987         ret = hns3_set_promisc_mode(hw, false, true);
3988         rte_spinlock_unlock(&hw->lock);
3989         if (ret)
3990                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3991                          ret);
3992
3993         return ret;
3994 }
3995
3996 static int
3997 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3998 {
3999         struct hns3_adapter *hns = dev->data->dev_private;
4000         struct hns3_hw *hw = &hns->hw;
4001         int ret;
4002
4003         /* If now in promiscuous mode, must remain in all_multicast mode. */
4004         if (dev->data->promiscuous)
4005                 return 0;
4006
4007         rte_spinlock_lock(&hw->lock);
4008         ret = hns3_set_promisc_mode(hw, false, false);
4009         rte_spinlock_unlock(&hw->lock);
4010         if (ret)
4011                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4012                          ret);
4013
4014         return ret;
4015 }
4016
4017 static int
4018 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4019 {
4020         struct hns3_hw *hw = &hns->hw;
4021         bool allmulti = hw->data->all_multicast ? true : false;
4022         int ret;
4023
4024         if (hw->data->promiscuous) {
4025                 ret = hns3_set_promisc_mode(hw, true, true);
4026                 if (ret)
4027                         hns3_err(hw, "failed to restore promiscuous mode, "
4028                                  "ret = %d", ret);
4029                 return ret;
4030         }
4031
4032         ret = hns3_set_promisc_mode(hw, false, allmulti);
4033         if (ret)
4034                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4035                          ret);
4036         return ret;
4037 }
4038
4039 static int
4040 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4041 {
4042         struct hns3_sfp_info_cmd *resp;
4043         struct hns3_cmd_desc desc;
4044         int ret;
4045
4046         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4047         resp = (struct hns3_sfp_info_cmd *)desc.data;
4048         resp->query_type = HNS3_ACTIVE_QUERY;
4049
4050         ret = hns3_cmd_send(hw, &desc, 1);
4051         if (ret == -EOPNOTSUPP) {
4052                 hns3_warn(hw, "firmware does not support get SFP info,"
4053                           " ret = %d.", ret);
4054                 return ret;
4055         } else if (ret) {
4056                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4057                 return ret;
4058         }
4059
4060         /*
4061          * In some case, the speed of MAC obtained from firmware may be 0, it
4062          * shouldn't be set to mac->speed.
4063          */
4064         if (!rte_le_to_cpu_32(resp->sfp_speed))
4065                 return 0;
4066
4067         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4068         /*
4069          * if resp->supported_speed is 0, it means it's an old version
4070          * firmware, do not update these params.
4071          */
4072         if (resp->supported_speed) {
4073                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4074                 mac_info->supported_speed =
4075                                         rte_le_to_cpu_32(resp->supported_speed);
4076                 mac_info->support_autoneg = resp->autoneg_ability;
4077                 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED
4078                                         : RTE_ETH_LINK_AUTONEG;
4079         } else {
4080                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4081         }
4082
4083         return 0;
4084 }
4085
4086 static uint8_t
4087 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4088 {
4089         if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M))
4090                 duplex = RTE_ETH_LINK_FULL_DUPLEX;
4091
4092         return duplex;
4093 }
4094
4095 static int
4096 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4097 {
4098         struct hns3_mac *mac = &hw->mac;
4099         int ret;
4100
4101         duplex = hns3_check_speed_dup(duplex, speed);
4102         if (mac->link_speed == speed && mac->link_duplex == duplex)
4103                 return 0;
4104
4105         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4106         if (ret)
4107                 return ret;
4108
4109         ret = hns3_port_shaper_update(hw, speed);
4110         if (ret)
4111                 return ret;
4112
4113         mac->link_speed = speed;
4114         mac->link_duplex = duplex;
4115
4116         return 0;
4117 }
4118
4119 static int
4120 hns3_update_fiber_link_info(struct hns3_hw *hw)
4121 {
4122         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4123         struct hns3_mac *mac = &hw->mac;
4124         struct hns3_mac mac_info;
4125         int ret;
4126
4127         /* If firmware do not support get SFP/qSFP speed, return directly */
4128         if (!pf->support_sfp_query)
4129                 return 0;
4130
4131         memset(&mac_info, 0, sizeof(struct hns3_mac));
4132         ret = hns3_get_sfp_info(hw, &mac_info);
4133         if (ret == -EOPNOTSUPP) {
4134                 pf->support_sfp_query = false;
4135                 return ret;
4136         } else if (ret)
4137                 return ret;
4138
4139         /* Do nothing if no SFP */
4140         if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE)
4141                 return 0;
4142
4143         /*
4144          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4145          * to reconfigure the speed of MAC. Otherwise, it indicates
4146          * that the current firmware only supports to obtain the
4147          * speed of the SFP, and the speed of MAC needs to reconfigure.
4148          */
4149         mac->query_type = mac_info.query_type;
4150         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4151                 if (mac_info.link_speed != mac->link_speed) {
4152                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4153                         if (ret)
4154                                 return ret;
4155                 }
4156
4157                 mac->link_speed = mac_info.link_speed;
4158                 mac->supported_speed = mac_info.supported_speed;
4159                 mac->support_autoneg = mac_info.support_autoneg;
4160                 mac->link_autoneg = mac_info.link_autoneg;
4161
4162                 return 0;
4163         }
4164
4165         /* Config full duplex for SFP */
4166         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4167                                       RTE_ETH_LINK_FULL_DUPLEX);
4168 }
4169
4170 static void
4171 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4172 {
4173 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4174
4175         struct hns3_phy_params_bd0_cmd *req;
4176         uint32_t supported;
4177
4178         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4179         mac->link_speed = rte_le_to_cpu_32(req->speed);
4180         mac->link_duplex = hns3_get_bit(req->duplex,
4181                                            HNS3_PHY_DUPLEX_CFG_B);
4182         mac->link_autoneg = hns3_get_bit(req->autoneg,
4183                                            HNS3_PHY_AUTONEG_CFG_B);
4184         mac->advertising = rte_le_to_cpu_32(req->advertising);
4185         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4186         supported = rte_le_to_cpu_32(req->supported);
4187         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4188         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4189 }
4190
4191 static int
4192 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4193 {
4194         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4195         uint16_t i;
4196         int ret;
4197
4198         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4199                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4200                                           true);
4201                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4202         }
4203         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4204
4205         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4206         if (ret) {
4207                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4208                 return ret;
4209         }
4210
4211         hns3_parse_copper_phy_params(desc, mac);
4212
4213         return 0;
4214 }
4215
4216 static int
4217 hns3_update_copper_link_info(struct hns3_hw *hw)
4218 {
4219         struct hns3_mac *mac = &hw->mac;
4220         struct hns3_mac mac_info;
4221         int ret;
4222
4223         memset(&mac_info, 0, sizeof(struct hns3_mac));
4224         ret = hns3_get_copper_phy_params(hw, &mac_info);
4225         if (ret)
4226                 return ret;
4227
4228         if (mac_info.link_speed != mac->link_speed) {
4229                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4230                 if (ret)
4231                         return ret;
4232         }
4233
4234         mac->link_speed = mac_info.link_speed;
4235         mac->link_duplex = mac_info.link_duplex;
4236         mac->link_autoneg = mac_info.link_autoneg;
4237         mac->supported_speed = mac_info.supported_speed;
4238         mac->advertising = mac_info.advertising;
4239         mac->lp_advertising = mac_info.lp_advertising;
4240         mac->support_autoneg = mac_info.support_autoneg;
4241
4242         return 0;
4243 }
4244
4245 static int
4246 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4247 {
4248         struct hns3_adapter *hns = eth_dev->data->dev_private;
4249         struct hns3_hw *hw = &hns->hw;
4250         int ret = 0;
4251
4252         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4253                 ret = hns3_update_copper_link_info(hw);
4254         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4255                 ret = hns3_update_fiber_link_info(hw);
4256
4257         return ret;
4258 }
4259
4260 static int
4261 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4262 {
4263         struct hns3_config_mac_mode_cmd *req;
4264         struct hns3_cmd_desc desc;
4265         uint32_t loop_en = 0;
4266         uint8_t val = 0;
4267         int ret;
4268
4269         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4270
4271         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4272         if (enable)
4273                 val = 1;
4274         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4275         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4276         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4277         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4278         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4279         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4280         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4281         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4282         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4283         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4284
4285         /*
4286          * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4287          * when receiving frames. Otherwise, CRC will be stripped.
4288          */
4289         if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
4290                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4291         else
4292                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4293         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4294         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4295         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4296         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4297
4298         ret = hns3_cmd_send(hw, &desc, 1);
4299         if (ret)
4300                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4301
4302         return ret;
4303 }
4304
4305 static int
4306 hns3_get_mac_link_status(struct hns3_hw *hw)
4307 {
4308         struct hns3_link_status_cmd *req;
4309         struct hns3_cmd_desc desc;
4310         int link_status;
4311         int ret;
4312
4313         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4314         ret = hns3_cmd_send(hw, &desc, 1);
4315         if (ret) {
4316                 hns3_err(hw, "get link status cmd failed %d", ret);
4317                 return RTE_ETH_LINK_DOWN;
4318         }
4319
4320         req = (struct hns3_link_status_cmd *)desc.data;
4321         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4322
4323         return !!link_status;
4324 }
4325
4326 static bool
4327 hns3_update_link_status(struct hns3_hw *hw)
4328 {
4329         int state;
4330
4331         state = hns3_get_mac_link_status(hw);
4332         if (state != hw->mac.link_status) {
4333                 hw->mac.link_status = state;
4334                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4335                 return true;
4336         }
4337
4338         return false;
4339 }
4340
4341 void
4342 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4343 {
4344         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4345         struct rte_eth_link new_link;
4346         int ret;
4347
4348         if (query)
4349                 hns3_update_port_link_info(dev);
4350
4351         memset(&new_link, 0, sizeof(new_link));
4352         hns3_setup_linkstatus(dev, &new_link);
4353
4354         ret = rte_eth_linkstatus_set(dev, &new_link);
4355         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4356                 hns3_start_report_lse(dev);
4357 }
4358
4359 static void
4360 hns3_service_handler(void *param)
4361 {
4362         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4363         struct hns3_adapter *hns = eth_dev->data->dev_private;
4364         struct hns3_hw *hw = &hns->hw;
4365
4366         if (!hns3_is_reset_pending(hns)) {
4367                 hns3_update_linkstatus_and_event(hw, true);
4368                 hns3_update_hw_stats(hw);
4369         } else {
4370                 hns3_warn(hw, "Cancel the query when reset is pending");
4371         }
4372
4373         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4374 }
4375
4376 static int
4377 hns3_init_hardware(struct hns3_adapter *hns)
4378 {
4379         struct hns3_hw *hw = &hns->hw;
4380         int ret;
4381
4382         /*
4383          * All queue-related HW operations must be performed after the TCAM
4384          * table is configured.
4385          */
4386         ret = hns3_map_tqp(hw);
4387         if (ret) {
4388                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4389                 return ret;
4390         }
4391
4392         ret = hns3_init_umv_space(hw);
4393         if (ret) {
4394                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4395                 return ret;
4396         }
4397
4398         ret = hns3_mac_init(hw);
4399         if (ret) {
4400                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4401                 goto err_mac_init;
4402         }
4403
4404         ret = hns3_init_mgr_tbl(hw);
4405         if (ret) {
4406                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4407                 goto err_mac_init;
4408         }
4409
4410         ret = hns3_promisc_init(hw);
4411         if (ret) {
4412                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4413                              ret);
4414                 goto err_mac_init;
4415         }
4416
4417         ret = hns3_init_vlan_config(hns);
4418         if (ret) {
4419                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4420                 goto err_mac_init;
4421         }
4422
4423         ret = hns3_dcb_init(hw);
4424         if (ret) {
4425                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4426                 goto err_mac_init;
4427         }
4428
4429         ret = hns3_init_fd_config(hns);
4430         if (ret) {
4431                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4432                 goto err_mac_init;
4433         }
4434
4435         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4436         if (ret) {
4437                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4438                 goto err_mac_init;
4439         }
4440
4441         ret = hns3_config_gro(hw, false);
4442         if (ret) {
4443                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4444                 goto err_mac_init;
4445         }
4446
4447         /*
4448          * In the initialization clearing the all hardware mapping relationship
4449          * configurations between queues and interrupt vectors is needed, so
4450          * some error caused by the residual configurations, such as the
4451          * unexpected interrupt, can be avoid.
4452          */
4453         ret = hns3_init_ring_with_vector(hw);
4454         if (ret) {
4455                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4456                 goto err_mac_init;
4457         }
4458
4459         return 0;
4460
4461 err_mac_init:
4462         hns3_uninit_umv_space(hw);
4463         return ret;
4464 }
4465
4466 static int
4467 hns3_clear_hw(struct hns3_hw *hw)
4468 {
4469         struct hns3_cmd_desc desc;
4470         int ret;
4471
4472         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4473
4474         ret = hns3_cmd_send(hw, &desc, 1);
4475         if (ret && ret != -EOPNOTSUPP)
4476                 return ret;
4477
4478         return 0;
4479 }
4480
4481 static void
4482 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4483 {
4484         uint32_t val;
4485
4486         /*
4487          * The new firmware support report more hardware error types by
4488          * msix mode. These errors are defined as RAS errors in hardware
4489          * and belong to a different type from the MSI-x errors processed
4490          * by the network driver.
4491          *
4492          * Network driver should open the new error report on initialization.
4493          */
4494         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4495         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4496         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4497 }
4498
4499 static uint32_t
4500 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
4501 {
4502         struct hns3_mac *mac = &hw->mac;
4503
4504         switch (mac->link_speed) {
4505         case RTE_ETH_SPEED_NUM_1G:
4506                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
4507         case RTE_ETH_SPEED_NUM_10G:
4508                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
4509         case RTE_ETH_SPEED_NUM_25G:
4510                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
4511         case RTE_ETH_SPEED_NUM_40G:
4512                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
4513         case RTE_ETH_SPEED_NUM_50G:
4514                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
4515         case RTE_ETH_SPEED_NUM_100G:
4516                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
4517         case RTE_ETH_SPEED_NUM_200G:
4518                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
4519         default:
4520                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
4521                 return 0;
4522         }
4523 }
4524
4525 /*
4526  * Validity of supported_speed for fiber and copper media type can be
4527  * guaranteed by the following policy:
4528  * Copper:
4529  *       Although the initialization of the phy in the firmware may not be
4530  *       completed, the firmware can guarantees that the supported_speed is
4531  *       an valid value.
4532  * Firber:
4533  *       If the version of firmware supports the active query way of the
4534  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
4535  *       through it. If unsupported, use the SFP's speed as the value of the
4536  *       supported_speed.
4537  */
4538 static int
4539 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
4540 {
4541         struct hns3_adapter *hns = eth_dev->data->dev_private;
4542         struct hns3_hw *hw = &hns->hw;
4543         struct hns3_mac *mac = &hw->mac;
4544         int ret;
4545
4546         ret = hns3_update_link_info(eth_dev);
4547         if (ret)
4548                 return ret;
4549
4550         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
4551                 /*
4552                  * Some firmware does not support the report of supported_speed,
4553                  * and only report the effective speed of SFP. In this case, it
4554                  * is necessary to use the SFP's speed as the supported_speed.
4555                  */
4556                 if (mac->supported_speed == 0)
4557                         mac->supported_speed =
4558                                 hns3_set_firber_default_support_speed(hw);
4559         }
4560
4561         return 0;
4562 }
4563
4564 static void
4565 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
4566 {
4567         struct hns3_mac *mac = &hns->hw.mac;
4568
4569         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
4570                 hns->pf.support_fc_autoneg = true;
4571                 return;
4572         }
4573
4574         /*
4575          * Flow control auto-negotiation requires the cooperation of the driver
4576          * and firmware. Currently, the optical port does not support flow
4577          * control auto-negotiation.
4578          */
4579         hns->pf.support_fc_autoneg = false;
4580 }
4581
4582 static int
4583 hns3_init_pf(struct rte_eth_dev *eth_dev)
4584 {
4585         struct rte_device *dev = eth_dev->device;
4586         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4587         struct hns3_adapter *hns = eth_dev->data->dev_private;
4588         struct hns3_hw *hw = &hns->hw;
4589         int ret;
4590
4591         PMD_INIT_FUNC_TRACE();
4592
4593         /* Get hardware io base address from pcie BAR2 IO space */
4594         hw->io_base = pci_dev->mem_resource[2].addr;
4595
4596         /* Firmware command queue initialize */
4597         ret = hns3_cmd_init_queue(hw);
4598         if (ret) {
4599                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4600                 goto err_cmd_init_queue;
4601         }
4602
4603         hns3_clear_all_event_cause(hw);
4604
4605         /* Firmware command initialize */
4606         ret = hns3_cmd_init(hw);
4607         if (ret) {
4608                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4609                 goto err_cmd_init;
4610         }
4611
4612         hns3_tx_push_init(eth_dev);
4613
4614         /*
4615          * To ensure that the hardware environment is clean during
4616          * initialization, the driver actively clear the hardware environment
4617          * during initialization, including PF and corresponding VFs' vlan, mac,
4618          * flow table configurations, etc.
4619          */
4620         ret = hns3_clear_hw(hw);
4621         if (ret) {
4622                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4623                 goto err_cmd_init;
4624         }
4625
4626         hns3_config_all_msix_error(hw, true);
4627
4628         ret = rte_intr_callback_register(pci_dev->intr_handle,
4629                                          hns3_interrupt_handler,
4630                                          eth_dev);
4631         if (ret) {
4632                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4633                 goto err_intr_callback_register;
4634         }
4635
4636         ret = hns3_ptp_init(hw);
4637         if (ret)
4638                 goto err_get_config;
4639
4640         /* Enable interrupt */
4641         rte_intr_enable(pci_dev->intr_handle);
4642         hns3_pf_enable_irq0(hw);
4643
4644         /* Get configuration */
4645         ret = hns3_get_configuration(hw);
4646         if (ret) {
4647                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4648                 goto err_get_config;
4649         }
4650
4651         ret = hns3_stats_init(hw);
4652         if (ret)
4653                 goto err_get_config;
4654
4655         ret = hns3_init_hardware(hns);
4656         if (ret) {
4657                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4658                 goto err_init_hw;
4659         }
4660
4661         /* Initialize flow director filter list & hash */
4662         ret = hns3_fdir_filter_init(hns);
4663         if (ret) {
4664                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4665                 goto err_fdir;
4666         }
4667
4668         hns3_rss_set_default_args(hw);
4669
4670         ret = hns3_enable_hw_error_intr(hns, true);
4671         if (ret) {
4672                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4673                              ret);
4674                 goto err_enable_intr;
4675         }
4676
4677         ret = hns3_get_port_supported_speed(eth_dev);
4678         if (ret) {
4679                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
4680                              "by device, ret = %d.", ret);
4681                 goto err_supported_speed;
4682         }
4683
4684         hns3_get_fc_autoneg_capability(hns);
4685
4686         hns3_tm_conf_init(eth_dev);
4687
4688         return 0;
4689
4690 err_supported_speed:
4691         (void)hns3_enable_hw_error_intr(hns, false);
4692 err_enable_intr:
4693         hns3_fdir_filter_uninit(hns);
4694 err_fdir:
4695         hns3_uninit_umv_space(hw);
4696 err_init_hw:
4697         hns3_stats_uninit(hw);
4698 err_get_config:
4699         hns3_pf_disable_irq0(hw);
4700         rte_intr_disable(pci_dev->intr_handle);
4701         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
4702                              eth_dev);
4703 err_intr_callback_register:
4704 err_cmd_init:
4705         hns3_cmd_uninit(hw);
4706         hns3_cmd_destroy_queue(hw);
4707 err_cmd_init_queue:
4708         hw->io_base = NULL;
4709
4710         return ret;
4711 }
4712
4713 static void
4714 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4715 {
4716         struct hns3_adapter *hns = eth_dev->data->dev_private;
4717         struct rte_device *dev = eth_dev->device;
4718         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4719         struct hns3_hw *hw = &hns->hw;
4720
4721         PMD_INIT_FUNC_TRACE();
4722
4723         hns3_tm_conf_uninit(eth_dev);
4724         hns3_enable_hw_error_intr(hns, false);
4725         hns3_rss_uninit(hns);
4726         (void)hns3_config_gro(hw, false);
4727         hns3_promisc_uninit(hw);
4728         hns3_flow_uninit(eth_dev);
4729         hns3_fdir_filter_uninit(hns);
4730         hns3_uninit_umv_space(hw);
4731         hns3_stats_uninit(hw);
4732         hns3_config_mac_tnl_int(hw, false);
4733         hns3_pf_disable_irq0(hw);
4734         rte_intr_disable(pci_dev->intr_handle);
4735         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
4736                              eth_dev);
4737         hns3_config_all_msix_error(hw, false);
4738         hns3_cmd_uninit(hw);
4739         hns3_cmd_destroy_queue(hw);
4740         hw->io_base = NULL;
4741 }
4742
4743 static uint32_t
4744 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
4745 {
4746         uint32_t speed_bit;
4747
4748         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
4749         case RTE_ETH_LINK_SPEED_10M:
4750                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
4751                 break;
4752         case RTE_ETH_LINK_SPEED_10M_HD:
4753                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
4754                 break;
4755         case RTE_ETH_LINK_SPEED_100M:
4756                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
4757                 break;
4758         case RTE_ETH_LINK_SPEED_100M_HD:
4759                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
4760                 break;
4761         case RTE_ETH_LINK_SPEED_1G:
4762                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
4763                 break;
4764         default:
4765                 speed_bit = 0;
4766                 break;
4767         }
4768
4769         return speed_bit;
4770 }
4771
4772 static uint32_t
4773 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
4774 {
4775         uint32_t speed_bit;
4776
4777         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
4778         case RTE_ETH_LINK_SPEED_1G:
4779                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
4780                 break;
4781         case RTE_ETH_LINK_SPEED_10G:
4782                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
4783                 break;
4784         case RTE_ETH_LINK_SPEED_25G:
4785                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
4786                 break;
4787         case RTE_ETH_LINK_SPEED_40G:
4788                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
4789                 break;
4790         case RTE_ETH_LINK_SPEED_50G:
4791                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
4792                 break;
4793         case RTE_ETH_LINK_SPEED_100G:
4794                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
4795                 break;
4796         case RTE_ETH_LINK_SPEED_200G:
4797                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
4798                 break;
4799         default:
4800                 speed_bit = 0;
4801                 break;
4802         }
4803
4804         return speed_bit;
4805 }
4806
4807 static int
4808 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
4809 {
4810         struct hns3_mac *mac = &hw->mac;
4811         uint32_t supported_speed = mac->supported_speed;
4812         uint32_t speed_bit = 0;
4813
4814         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
4815                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
4816         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
4817                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
4818
4819         if (!(speed_bit & supported_speed)) {
4820                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
4821                          link_speeds);
4822                 return -EINVAL;
4823         }
4824
4825         return 0;
4826 }
4827
4828 static uint32_t
4829 hns3_get_link_speed(uint32_t link_speeds)
4830 {
4831         uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
4832
4833         if (link_speeds & RTE_ETH_LINK_SPEED_10M ||
4834             link_speeds & RTE_ETH_LINK_SPEED_10M_HD)
4835                 speed = RTE_ETH_SPEED_NUM_10M;
4836         if (link_speeds & RTE_ETH_LINK_SPEED_100M ||
4837             link_speeds & RTE_ETH_LINK_SPEED_100M_HD)
4838                 speed = RTE_ETH_SPEED_NUM_100M;
4839         if (link_speeds & RTE_ETH_LINK_SPEED_1G)
4840                 speed = RTE_ETH_SPEED_NUM_1G;
4841         if (link_speeds & RTE_ETH_LINK_SPEED_10G)
4842                 speed = RTE_ETH_SPEED_NUM_10G;
4843         if (link_speeds & RTE_ETH_LINK_SPEED_25G)
4844                 speed = RTE_ETH_SPEED_NUM_25G;
4845         if (link_speeds & RTE_ETH_LINK_SPEED_40G)
4846                 speed = RTE_ETH_SPEED_NUM_40G;
4847         if (link_speeds & RTE_ETH_LINK_SPEED_50G)
4848                 speed = RTE_ETH_SPEED_NUM_50G;
4849         if (link_speeds & RTE_ETH_LINK_SPEED_100G)
4850                 speed = RTE_ETH_SPEED_NUM_100G;
4851         if (link_speeds & RTE_ETH_LINK_SPEED_200G)
4852                 speed = RTE_ETH_SPEED_NUM_200G;
4853
4854         return speed;
4855 }
4856
4857 static uint8_t
4858 hns3_get_link_duplex(uint32_t link_speeds)
4859 {
4860         if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||
4861             (link_speeds & RTE_ETH_LINK_SPEED_100M_HD))
4862                 return RTE_ETH_LINK_HALF_DUPLEX;
4863         else
4864                 return RTE_ETH_LINK_FULL_DUPLEX;
4865 }
4866
4867 static int
4868 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
4869                                 struct hns3_set_link_speed_cfg *cfg)
4870 {
4871         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4872         struct hns3_phy_params_bd0_cmd *req;
4873         uint16_t i;
4874
4875         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4876                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4877                                           false);
4878                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4879         }
4880         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
4881         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4882         req->autoneg = cfg->autoneg;
4883
4884         /*
4885          * The full speed capability is used to negotiate when
4886          * auto-negotiation is enabled.
4887          */
4888         if (cfg->autoneg) {
4889                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
4890                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
4891                                     HNS3_PHY_LINK_SPEED_100M_BIT |
4892                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
4893                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
4894         } else {
4895                 req->speed = cfg->speed;
4896                 req->duplex = cfg->duplex;
4897         }
4898
4899         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4900 }
4901
4902 static int
4903 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
4904 {
4905         struct hns3_config_auto_neg_cmd *req;
4906         struct hns3_cmd_desc desc;
4907         uint32_t flag = 0;
4908         int ret;
4909
4910         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
4911
4912         req = (struct hns3_config_auto_neg_cmd *)desc.data;
4913         if (enable)
4914                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
4915         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
4916
4917         ret = hns3_cmd_send(hw, &desc, 1);
4918         if (ret)
4919                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
4920
4921         return ret;
4922 }
4923
4924 static int
4925 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
4926                                struct hns3_set_link_speed_cfg *cfg)
4927 {
4928         int ret;
4929
4930         if (hw->mac.support_autoneg) {
4931                 ret = hns3_set_autoneg(hw, cfg->autoneg);
4932                 if (ret) {
4933                         hns3_err(hw, "failed to configure auto-negotiation.");
4934                         return ret;
4935                 }
4936
4937                 /*
4938                  * To enable auto-negotiation, we only need to open the switch
4939                  * of auto-negotiation, then firmware sets all speed
4940                  * capabilities.
4941                  */
4942                 if (cfg->autoneg)
4943                         return 0;
4944         }
4945
4946         /*
4947          * Some hardware doesn't support auto-negotiation, but users may not
4948          * configure link_speeds (default 0), which means auto-negotiation.
4949          * In this case, a warning message need to be printed, instead of
4950          * an error.
4951          */
4952         if (cfg->autoneg) {
4953                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
4954                 return 0;
4955         }
4956
4957         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
4958 }
4959
4960 static int
4961 hns3_set_port_link_speed(struct hns3_hw *hw,
4962                          struct hns3_set_link_speed_cfg *cfg)
4963 {
4964         int ret;
4965
4966         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
4967 #if defined(RTE_HNS3_ONLY_1630_FPGA)
4968                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4969                 if (pf->is_tmp_phy)
4970                         return 0;
4971 #endif
4972
4973                 ret = hns3_set_copper_port_link_speed(hw, cfg);
4974                 if (ret) {
4975                         hns3_err(hw, "failed to set copper port link speed,"
4976                                  "ret = %d.", ret);
4977                         return ret;
4978                 }
4979         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
4980                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
4981                 if (ret) {
4982                         hns3_err(hw, "failed to set fiber port link speed,"
4983                                  "ret = %d.", ret);
4984                         return ret;
4985                 }
4986         }
4987
4988         return 0;
4989 }
4990
4991 static int
4992 hns3_apply_link_speed(struct hns3_hw *hw)
4993 {
4994         struct rte_eth_conf *conf = &hw->data->dev_conf;
4995         struct hns3_set_link_speed_cfg cfg;
4996
4997         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
4998         cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ?
4999                         RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
5000         if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) {
5001                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5002                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5003         }
5004
5005         return hns3_set_port_link_speed(hw, &cfg);
5006 }
5007
5008 static int
5009 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5010 {
5011         struct hns3_hw *hw = &hns->hw;
5012         bool link_en;
5013         int ret;
5014
5015         ret = hns3_update_queue_map_configure(hns);
5016         if (ret) {
5017                 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5018                          ret);
5019                 return ret;
5020         }
5021
5022         /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5023         ret = hns3_tm_conf_update(hw);
5024         if (ret) {
5025                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5026                 return ret;
5027         }
5028
5029         hns3_enable_rxd_adv_layout(hw);
5030
5031         ret = hns3_init_queues(hns, reset_queue);
5032         if (ret) {
5033                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5034                 return ret;
5035         }
5036
5037         link_en = hw->set_link_down ? false : true;
5038         ret = hns3_cfg_mac_mode(hw, link_en);
5039         if (ret) {
5040                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5041                 goto err_config_mac_mode;
5042         }
5043
5044         ret = hns3_apply_link_speed(hw);
5045         if (ret)
5046                 goto err_set_link_speed;
5047
5048         return 0;
5049
5050 err_set_link_speed:
5051         (void)hns3_cfg_mac_mode(hw, false);
5052
5053 err_config_mac_mode:
5054         hns3_dev_release_mbufs(hns);
5055         /*
5056          * Here is exception handling, hns3_reset_all_tqps will have the
5057          * corresponding error message if it is handled incorrectly, so it is
5058          * not necessary to check hns3_reset_all_tqps return value, here keep
5059          * ret as the error code causing the exception.
5060          */
5061         (void)hns3_reset_all_tqps(hns);
5062         return ret;
5063 }
5064
5065 static void
5066 hns3_restore_filter(struct rte_eth_dev *dev)
5067 {
5068         hns3_restore_rss_filter(dev);
5069 }
5070
5071 static int
5072 hns3_dev_start(struct rte_eth_dev *dev)
5073 {
5074         struct hns3_adapter *hns = dev->data->dev_private;
5075         struct hns3_hw *hw = &hns->hw;
5076         bool old_state = hw->set_link_down;
5077         int ret;
5078
5079         PMD_INIT_FUNC_TRACE();
5080         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5081                 return -EBUSY;
5082
5083         rte_spinlock_lock(&hw->lock);
5084         hw->adapter_state = HNS3_NIC_STARTING;
5085
5086         /*
5087          * If the dev_set_link_down() API has been called, the "set_link_down"
5088          * flag can be cleared by dev_start() API. In addition, the flag should
5089          * also be cleared before calling hns3_do_start() so that MAC can be
5090          * enabled in dev_start stage.
5091          */
5092         hw->set_link_down = false;
5093         ret = hns3_do_start(hns, true);
5094         if (ret)
5095                 goto do_start_fail;
5096
5097         ret = hns3_map_rx_interrupt(dev);
5098         if (ret)
5099                 goto map_rx_inter_err;
5100
5101         /*
5102          * There are three register used to control the status of a TQP
5103          * (contains a pair of Tx queue and Rx queue) in the new version network
5104          * engine. One is used to control the enabling of Tx queue, the other is
5105          * used to control the enabling of Rx queue, and the last is the master
5106          * switch used to control the enabling of the tqp. The Tx register and
5107          * TQP register must be enabled at the same time to enable a Tx queue.
5108          * The same applies to the Rx queue. For the older network engine, this
5109          * function only refresh the enabled flag, and it is used to update the
5110          * status of queue in the dpdk framework.
5111          */
5112         ret = hns3_start_all_txqs(dev);
5113         if (ret)
5114                 goto map_rx_inter_err;
5115
5116         ret = hns3_start_all_rxqs(dev);
5117         if (ret)
5118                 goto start_all_rxqs_fail;
5119
5120         hw->adapter_state = HNS3_NIC_STARTED;
5121         rte_spinlock_unlock(&hw->lock);
5122
5123         hns3_rx_scattered_calc(dev);
5124         hns3_set_rxtx_function(dev);
5125         hns3_mp_req_start_rxtx(dev);
5126
5127         hns3_restore_filter(dev);
5128
5129         /* Enable interrupt of all rx queues before enabling queues */
5130         hns3_dev_all_rx_queue_intr_enable(hw, true);
5131
5132         /*
5133          * After finished the initialization, enable tqps to receive/transmit
5134          * packets and refresh all queue status.
5135          */
5136         hns3_start_tqps(hw);
5137
5138         hns3_tm_dev_start_proc(hw);
5139
5140         if (dev->data->dev_conf.intr_conf.lsc != 0)
5141                 hns3_dev_link_update(dev, 0);
5142         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5143
5144         hns3_info(hw, "hns3 dev start successful!");
5145
5146         return 0;
5147
5148 start_all_rxqs_fail:
5149         hns3_stop_all_txqs(dev);
5150 map_rx_inter_err:
5151         (void)hns3_do_stop(hns);
5152 do_start_fail:
5153         hw->set_link_down = old_state;
5154         hw->adapter_state = HNS3_NIC_CONFIGURED;
5155         rte_spinlock_unlock(&hw->lock);
5156
5157         return ret;
5158 }
5159
5160 static int
5161 hns3_do_stop(struct hns3_adapter *hns)
5162 {
5163         struct hns3_hw *hw = &hns->hw;
5164         int ret;
5165
5166         /*
5167          * The "hns3_do_stop" function will also be called by .stop_service to
5168          * prepare reset. At the time of global or IMP reset, the command cannot
5169          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5170          * accessed during the reset process. So the mbuf can not be released
5171          * during reset and is required to be released after the reset is
5172          * completed.
5173          */
5174         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5175                 hns3_dev_release_mbufs(hns);
5176
5177         ret = hns3_cfg_mac_mode(hw, false);
5178         if (ret)
5179                 return ret;
5180         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5181
5182         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5183                 hns3_configure_all_mac_addr(hns, true);
5184                 ret = hns3_reset_all_tqps(hns);
5185                 if (ret) {
5186                         hns3_err(hw, "failed to reset all queues ret = %d.",
5187                                  ret);
5188                         return ret;
5189                 }
5190         }
5191
5192         return 0;
5193 }
5194
5195 static int
5196 hns3_dev_stop(struct rte_eth_dev *dev)
5197 {
5198         struct hns3_adapter *hns = dev->data->dev_private;
5199         struct hns3_hw *hw = &hns->hw;
5200
5201         PMD_INIT_FUNC_TRACE();
5202         dev->data->dev_started = 0;
5203
5204         hw->adapter_state = HNS3_NIC_STOPPING;
5205         hns3_set_rxtx_function(dev);
5206         rte_wmb();
5207         /* Disable datapath on secondary process. */
5208         hns3_mp_req_stop_rxtx(dev);
5209         /* Prevent crashes when queues are still in use. */
5210         rte_delay_ms(hw->cfg_max_queues);
5211
5212         rte_spinlock_lock(&hw->lock);
5213         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5214                 hns3_tm_dev_stop_proc(hw);
5215                 hns3_config_mac_tnl_int(hw, false);
5216                 hns3_stop_tqps(hw);
5217                 hns3_do_stop(hns);
5218                 hns3_unmap_rx_interrupt(dev);
5219                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5220         }
5221         hns3_rx_scattered_reset(dev);
5222         rte_eal_alarm_cancel(hns3_service_handler, dev);
5223         hns3_stop_report_lse(dev);
5224         rte_spinlock_unlock(&hw->lock);
5225
5226         return 0;
5227 }
5228
5229 static int
5230 hns3_dev_close(struct rte_eth_dev *eth_dev)
5231 {
5232         struct hns3_adapter *hns = eth_dev->data->dev_private;
5233         struct hns3_hw *hw = &hns->hw;
5234         int ret = 0;
5235
5236         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5237                 hns3_mp_uninit(eth_dev);
5238                 return 0;
5239         }
5240
5241         if (hw->adapter_state == HNS3_NIC_STARTED)
5242                 ret = hns3_dev_stop(eth_dev);
5243
5244         hw->adapter_state = HNS3_NIC_CLOSING;
5245         hns3_reset_abort(hns);
5246         hw->adapter_state = HNS3_NIC_CLOSED;
5247
5248         hns3_configure_all_mc_mac_addr(hns, true);
5249         hns3_remove_all_vlan_table(hns);
5250         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5251         hns3_uninit_pf(eth_dev);
5252         hns3_free_all_queues(eth_dev);
5253         rte_free(hw->reset.wait_data);
5254         hns3_mp_uninit(eth_dev);
5255         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5256
5257         return ret;
5258 }
5259
5260 static void
5261 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5262                                    bool *tx_pause)
5263 {
5264         struct hns3_mac *mac = &hw->mac;
5265         uint32_t advertising = mac->advertising;
5266         uint32_t lp_advertising = mac->lp_advertising;
5267         *rx_pause = false;
5268         *tx_pause = false;
5269
5270         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5271                 *rx_pause = true;
5272                 *tx_pause = true;
5273         } else if (advertising & lp_advertising &
5274                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5275                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5276                         *rx_pause = true;
5277                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5278                         *tx_pause = true;
5279         }
5280 }
5281
5282 static enum hns3_fc_mode
5283 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5284 {
5285         enum hns3_fc_mode current_mode;
5286         bool rx_pause = false;
5287         bool tx_pause = false;
5288
5289         switch (hw->mac.media_type) {
5290         case HNS3_MEDIA_TYPE_COPPER:
5291                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5292                 break;
5293
5294         /*
5295          * Flow control auto-negotiation is not supported for fiber and
5296          * backplane media type.
5297          */
5298         case HNS3_MEDIA_TYPE_FIBER:
5299         case HNS3_MEDIA_TYPE_BACKPLANE:
5300                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5301                 current_mode = hw->requested_fc_mode;
5302                 goto out;
5303         default:
5304                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5305                          hw->mac.media_type);
5306                 current_mode = HNS3_FC_NONE;
5307                 goto out;
5308         }
5309
5310         if (rx_pause && tx_pause)
5311                 current_mode = HNS3_FC_FULL;
5312         else if (rx_pause)
5313                 current_mode = HNS3_FC_RX_PAUSE;
5314         else if (tx_pause)
5315                 current_mode = HNS3_FC_TX_PAUSE;
5316         else
5317                 current_mode = HNS3_FC_NONE;
5318
5319 out:
5320         return current_mode;
5321 }
5322
5323 static enum hns3_fc_mode
5324 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
5325 {
5326         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5327         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5328         struct hns3_mac *mac = &hw->mac;
5329
5330         /*
5331          * When the flow control mode is obtained, the device may not complete
5332          * auto-negotiation. It is necessary to wait for link establishment.
5333          */
5334         (void)hns3_dev_link_update(dev, 1);
5335
5336         /*
5337          * If the link auto-negotiation of the nic is disabled, or the flow
5338          * control auto-negotiation is not supported, the forced flow control
5339          * mode is used.
5340          */
5341         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
5342                 return hw->requested_fc_mode;
5343
5344         return hns3_get_autoneg_fc_mode(hw);
5345 }
5346
5347 int
5348 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5349 {
5350         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5351         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5352         enum hns3_fc_mode current_mode;
5353
5354         current_mode = hns3_get_current_fc_mode(dev);
5355         switch (current_mode) {
5356         case HNS3_FC_FULL:
5357                 fc_conf->mode = RTE_ETH_FC_FULL;
5358                 break;
5359         case HNS3_FC_TX_PAUSE:
5360                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
5361                 break;
5362         case HNS3_FC_RX_PAUSE:
5363                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
5364                 break;
5365         case HNS3_FC_NONE:
5366         default:
5367                 fc_conf->mode = RTE_ETH_FC_NONE;
5368                 break;
5369         }
5370
5371         fc_conf->pause_time = pf->pause_time;
5372         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
5373
5374         return 0;
5375 }
5376
5377 static int
5378 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
5379 {
5380         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5381
5382         if (!pf->support_fc_autoneg) {
5383                 if (autoneg != 0) {
5384                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
5385                         return -EOPNOTSUPP;
5386                 }
5387
5388                 /*
5389                  * Flow control auto-negotiation of the NIC is not supported,
5390                  * but other auto-negotiation features may be supported.
5391                  */
5392                 if (autoneg != hw->mac.link_autoneg) {
5393                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
5394                         return -EOPNOTSUPP;
5395                 }
5396
5397                 return 0;
5398         }
5399
5400         /*
5401          * If flow control auto-negotiation of the NIC is supported, all
5402          * auto-negotiation features are supported.
5403          */
5404         if (autoneg != hw->mac.link_autoneg) {
5405                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
5406                 return -EOPNOTSUPP;
5407         }
5408
5409         return 0;
5410 }
5411
5412 static int
5413 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5414 {
5415         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5416         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5417         int ret;
5418
5419         if (fc_conf->high_water || fc_conf->low_water ||
5420             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5421                 hns3_err(hw, "Unsupported flow control settings specified, "
5422                          "high_water(%u), low_water(%u), send_xon(%u) and "
5423                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5424                          fc_conf->high_water, fc_conf->low_water,
5425                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5426                 return -EINVAL;
5427         }
5428
5429         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
5430         if (ret)
5431                 return ret;
5432
5433         if (!fc_conf->pause_time) {
5434                 hns3_err(hw, "Invalid pause time %u setting.",
5435                          fc_conf->pause_time);
5436                 return -EINVAL;
5437         }
5438
5439         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5440             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5441                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5442                          "current_fc_status = %d", hw->current_fc_status);
5443                 return -EOPNOTSUPP;
5444         }
5445
5446         if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
5447                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
5448                 return -EOPNOTSUPP;
5449         }
5450
5451         rte_spinlock_lock(&hw->lock);
5452         ret = hns3_fc_enable(dev, fc_conf);
5453         rte_spinlock_unlock(&hw->lock);
5454
5455         return ret;
5456 }
5457
5458 static int
5459 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5460                             struct rte_eth_pfc_conf *pfc_conf)
5461 {
5462         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5463         int ret;
5464
5465         if (!hns3_dev_get_support(hw, DCB)) {
5466                 hns3_err(hw, "This port does not support dcb configurations.");
5467                 return -EOPNOTSUPP;
5468         }
5469
5470         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5471             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5472                 hns3_err(hw, "Unsupported flow control settings specified, "
5473                          "high_water(%u), low_water(%u), send_xon(%u) and "
5474                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5475                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5476                          pfc_conf->fc.send_xon,
5477                          pfc_conf->fc.mac_ctrl_frame_fwd);
5478                 return -EINVAL;
5479         }
5480         if (pfc_conf->fc.autoneg) {
5481                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5482                 return -EINVAL;
5483         }
5484         if (pfc_conf->fc.pause_time == 0) {
5485                 hns3_err(hw, "Invalid pause time %u setting.",
5486                          pfc_conf->fc.pause_time);
5487                 return -EINVAL;
5488         }
5489
5490         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5491             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5492                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5493                              "current_fc_status = %d", hw->current_fc_status);
5494                 return -EOPNOTSUPP;
5495         }
5496
5497         rte_spinlock_lock(&hw->lock);
5498         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5499         rte_spinlock_unlock(&hw->lock);
5500
5501         return ret;
5502 }
5503
5504 static int
5505 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5506 {
5507         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5509         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5510         int i;
5511
5512         rte_spinlock_lock(&hw->lock);
5513         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
5514                 dcb_info->nb_tcs = pf->local_max_tc;
5515         else
5516                 dcb_info->nb_tcs = 1;
5517
5518         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5519                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5520         for (i = 0; i < dcb_info->nb_tcs; i++)
5521                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5522
5523         for (i = 0; i < hw->num_tc; i++) {
5524                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5525                 dcb_info->tc_queue.tc_txq[0][i].base =
5526                                                 hw->tc_queue[i].tqp_offset;
5527                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5528                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5529                                                 hw->tc_queue[i].tqp_count;
5530         }
5531         rte_spinlock_unlock(&hw->lock);
5532
5533         return 0;
5534 }
5535
5536 static int
5537 hns3_reinit_dev(struct hns3_adapter *hns)
5538 {
5539         struct hns3_hw *hw = &hns->hw;
5540         int ret;
5541
5542         ret = hns3_cmd_init(hw);
5543         if (ret) {
5544                 hns3_err(hw, "Failed to init cmd: %d", ret);
5545                 return ret;
5546         }
5547
5548         ret = hns3_init_hardware(hns);
5549         if (ret) {
5550                 hns3_err(hw, "Failed to init hardware: %d", ret);
5551                 return ret;
5552         }
5553
5554         ret = hns3_reset_all_tqps(hns);
5555         if (ret) {
5556                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5557                 return ret;
5558         }
5559
5560         ret = hns3_enable_hw_error_intr(hns, true);
5561         if (ret) {
5562                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5563                              ret);
5564                 return ret;
5565         }
5566         hns3_info(hw, "Reset done, driver initialization finished.");
5567
5568         return 0;
5569 }
5570
5571 static bool
5572 is_pf_reset_done(struct hns3_hw *hw)
5573 {
5574         uint32_t val, reg, reg_bit;
5575
5576         switch (hw->reset.level) {
5577         case HNS3_IMP_RESET:
5578                 reg = HNS3_GLOBAL_RESET_REG;
5579                 reg_bit = HNS3_IMP_RESET_BIT;
5580                 break;
5581         case HNS3_GLOBAL_RESET:
5582                 reg = HNS3_GLOBAL_RESET_REG;
5583                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5584                 break;
5585         case HNS3_FUNC_RESET:
5586                 reg = HNS3_FUN_RST_ING;
5587                 reg_bit = HNS3_FUN_RST_ING_B;
5588                 break;
5589         case HNS3_FLR_RESET:
5590         default:
5591                 hns3_err(hw, "Wait for unsupported reset level: %d",
5592                          hw->reset.level);
5593                 return true;
5594         }
5595         val = hns3_read_dev(hw, reg);
5596         if (hns3_get_bit(val, reg_bit))
5597                 return false;
5598         else
5599                 return true;
5600 }
5601
5602 bool
5603 hns3_is_reset_pending(struct hns3_adapter *hns)
5604 {
5605         struct hns3_hw *hw = &hns->hw;
5606         enum hns3_reset_level reset;
5607
5608         hns3_check_event_cause(hns, NULL);
5609         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5610         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
5611             hw->reset.level < reset) {
5612                 hns3_warn(hw, "High level reset %d is pending", reset);
5613                 return true;
5614         }
5615         reset = hns3_get_reset_level(hns, &hw->reset.request);
5616         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
5617             hw->reset.level < reset) {
5618                 hns3_warn(hw, "High level reset %d is request", reset);
5619                 return true;
5620         }
5621         return false;
5622 }
5623
5624 static int
5625 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5626 {
5627         struct hns3_hw *hw = &hns->hw;
5628         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5629         struct timeval tv;
5630
5631         if (wait_data->result == HNS3_WAIT_SUCCESS)
5632                 return 0;
5633         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5634                 hns3_clock_gettime(&tv);
5635                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5636                           tv.tv_sec, tv.tv_usec);
5637                 return -ETIME;
5638         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5639                 return -EAGAIN;
5640
5641         wait_data->hns = hns;
5642         wait_data->check_completion = is_pf_reset_done;
5643         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5644                                 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
5645         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5646         wait_data->count = HNS3_RESET_WAIT_CNT;
5647         wait_data->result = HNS3_WAIT_REQUEST;
5648         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5649         return -EAGAIN;
5650 }
5651
5652 static int
5653 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5654 {
5655         struct hns3_cmd_desc desc;
5656         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5657
5658         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5659         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5660         req->fun_reset_vfid = func_id;
5661
5662         return hns3_cmd_send(hw, &desc, 1);
5663 }
5664
5665 static int
5666 hns3_imp_reset_cmd(struct hns3_hw *hw)
5667 {
5668         struct hns3_cmd_desc desc;
5669
5670         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5671         desc.data[0] = 0xeedd;
5672
5673         return hns3_cmd_send(hw, &desc, 1);
5674 }
5675
5676 static void
5677 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5678 {
5679         struct hns3_hw *hw = &hns->hw;
5680         struct timeval tv;
5681         uint32_t val;
5682
5683         hns3_clock_gettime(&tv);
5684         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5685             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5686                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5687                           tv.tv_sec, tv.tv_usec);
5688                 return;
5689         }
5690
5691         switch (reset_level) {
5692         case HNS3_IMP_RESET:
5693                 hns3_imp_reset_cmd(hw);
5694                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5695                           tv.tv_sec, tv.tv_usec);
5696                 break;
5697         case HNS3_GLOBAL_RESET:
5698                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5699                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5700                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5701                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5702                           tv.tv_sec, tv.tv_usec);
5703                 break;
5704         case HNS3_FUNC_RESET:
5705                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5706                           tv.tv_sec, tv.tv_usec);
5707                 /* schedule again to check later */
5708                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5709                 hns3_schedule_reset(hns);
5710                 break;
5711         default:
5712                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5713                 return;
5714         }
5715         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5716 }
5717
5718 static enum hns3_reset_level
5719 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5720 {
5721         struct hns3_hw *hw = &hns->hw;
5722         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5723
5724         /* Return the highest priority reset level amongst all */
5725         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5726                 reset_level = HNS3_IMP_RESET;
5727         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5728                 reset_level = HNS3_GLOBAL_RESET;
5729         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5730                 reset_level = HNS3_FUNC_RESET;
5731         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5732                 reset_level = HNS3_FLR_RESET;
5733
5734         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5735                 return HNS3_NONE_RESET;
5736
5737         return reset_level;
5738 }
5739
5740 static void
5741 hns3_record_imp_error(struct hns3_adapter *hns)
5742 {
5743         struct hns3_hw *hw = &hns->hw;
5744         uint32_t reg_val;
5745
5746         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5747         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5748                 hns3_warn(hw, "Detected IMP RD poison!");
5749                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5750                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5751         }
5752
5753         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5754                 hns3_warn(hw, "Detected IMP CMDQ error!");
5755                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5756                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5757         }
5758 }
5759
5760 static int
5761 hns3_prepare_reset(struct hns3_adapter *hns)
5762 {
5763         struct hns3_hw *hw = &hns->hw;
5764         uint32_t reg_val;
5765         int ret;
5766
5767         switch (hw->reset.level) {
5768         case HNS3_FUNC_RESET:
5769                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5770                 if (ret)
5771                         return ret;
5772
5773                 /*
5774                  * After performaning pf reset, it is not necessary to do the
5775                  * mailbox handling or send any command to firmware, because
5776                  * any mailbox handling or command to firmware is only valid
5777                  * after hns3_cmd_init is called.
5778                  */
5779                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5780                 hw->reset.stats.request_cnt++;
5781                 break;
5782         case HNS3_IMP_RESET:
5783                 hns3_record_imp_error(hns);
5784                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5785                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5786                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5787                 break;
5788         default:
5789                 break;
5790         }
5791         return 0;
5792 }
5793
5794 static int
5795 hns3_set_rst_done(struct hns3_hw *hw)
5796 {
5797         struct hns3_pf_rst_done_cmd *req;
5798         struct hns3_cmd_desc desc;
5799
5800         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5801         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5802         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5803         return hns3_cmd_send(hw, &desc, 1);
5804 }
5805
5806 static int
5807 hns3_stop_service(struct hns3_adapter *hns)
5808 {
5809         struct hns3_hw *hw = &hns->hw;
5810         struct rte_eth_dev *eth_dev;
5811
5812         eth_dev = &rte_eth_devices[hw->data->port_id];
5813         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5814         if (hw->adapter_state == HNS3_NIC_STARTED) {
5815                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5816                 hns3_update_linkstatus_and_event(hw, false);
5817         }
5818
5819         hns3_set_rxtx_function(eth_dev);
5820         rte_wmb();
5821         /* Disable datapath on secondary process. */
5822         hns3_mp_req_stop_rxtx(eth_dev);
5823         rte_delay_ms(hw->cfg_max_queues);
5824
5825         rte_spinlock_lock(&hw->lock);
5826         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5827             hw->adapter_state == HNS3_NIC_STOPPING) {
5828                 hns3_enable_all_queues(hw, false);
5829                 hns3_do_stop(hns);
5830                 hw->reset.mbuf_deferred_free = true;
5831         } else
5832                 hw->reset.mbuf_deferred_free = false;
5833
5834         /*
5835          * It is cumbersome for hardware to pick-and-choose entries for deletion
5836          * from table space. Hence, for function reset software intervention is
5837          * required to delete the entries
5838          */
5839         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5840                 hns3_configure_all_mc_mac_addr(hns, true);
5841         rte_spinlock_unlock(&hw->lock);
5842
5843         return 0;
5844 }
5845
5846 static int
5847 hns3_start_service(struct hns3_adapter *hns)
5848 {
5849         struct hns3_hw *hw = &hns->hw;
5850         struct rte_eth_dev *eth_dev;
5851
5852         if (hw->reset.level == HNS3_IMP_RESET ||
5853             hw->reset.level == HNS3_GLOBAL_RESET)
5854                 hns3_set_rst_done(hw);
5855         eth_dev = &rte_eth_devices[hw->data->port_id];
5856         hns3_set_rxtx_function(eth_dev);
5857         hns3_mp_req_start_rxtx(eth_dev);
5858         if (hw->adapter_state == HNS3_NIC_STARTED) {
5859                 /*
5860                  * This API parent function already hold the hns3_hw.lock, the
5861                  * hns3_service_handler may report lse, in bonding application
5862                  * it will call driver's ops which may acquire the hns3_hw.lock
5863                  * again, thus lead to deadlock.
5864                  * We defer calls hns3_service_handler to avoid the deadlock.
5865                  */
5866                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5867                                   hns3_service_handler, eth_dev);
5868
5869                 /* Enable interrupt of all rx queues before enabling queues */
5870                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5871                 /*
5872                  * Enable state of each rxq and txq will be recovered after
5873                  * reset, so we need to restore them before enable all tqps;
5874                  */
5875                 hns3_restore_tqp_enable_state(hw);
5876                 /*
5877                  * When finished the initialization, enable queues to receive
5878                  * and transmit packets.
5879                  */
5880                 hns3_enable_all_queues(hw, true);
5881         }
5882
5883         return 0;
5884 }
5885
5886 static int
5887 hns3_restore_conf(struct hns3_adapter *hns)
5888 {
5889         struct hns3_hw *hw = &hns->hw;
5890         int ret;
5891
5892         ret = hns3_configure_all_mac_addr(hns, false);
5893         if (ret)
5894                 return ret;
5895
5896         ret = hns3_configure_all_mc_mac_addr(hns, false);
5897         if (ret)
5898                 goto err_mc_mac;
5899
5900         ret = hns3_dev_promisc_restore(hns);
5901         if (ret)
5902                 goto err_promisc;
5903
5904         ret = hns3_restore_vlan_table(hns);
5905         if (ret)
5906                 goto err_promisc;
5907
5908         ret = hns3_restore_vlan_conf(hns);
5909         if (ret)
5910                 goto err_promisc;
5911
5912         ret = hns3_restore_all_fdir_filter(hns);
5913         if (ret)
5914                 goto err_promisc;
5915
5916         ret = hns3_restore_ptp(hns);
5917         if (ret)
5918                 goto err_promisc;
5919
5920         ret = hns3_restore_rx_interrupt(hw);
5921         if (ret)
5922                 goto err_promisc;
5923
5924         ret = hns3_restore_gro_conf(hw);
5925         if (ret)
5926                 goto err_promisc;
5927
5928         ret = hns3_restore_fec(hw);
5929         if (ret)
5930                 goto err_promisc;
5931
5932         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5933                 ret = hns3_do_start(hns, false);
5934                 if (ret)
5935                         goto err_promisc;
5936                 hns3_info(hw, "hns3 dev restart successful!");
5937         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5938                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5939         return 0;
5940
5941 err_promisc:
5942         hns3_configure_all_mc_mac_addr(hns, true);
5943 err_mc_mac:
5944         hns3_configure_all_mac_addr(hns, true);
5945         return ret;
5946 }
5947
5948 static void
5949 hns3_reset_service(void *param)
5950 {
5951         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5952         struct hns3_hw *hw = &hns->hw;
5953         enum hns3_reset_level reset_level;
5954         struct timeval tv_delta;
5955         struct timeval tv_start;
5956         struct timeval tv;
5957         uint64_t msec;
5958         int ret;
5959
5960         /*
5961          * The interrupt is not triggered within the delay time.
5962          * The interrupt may have been lost. It is necessary to handle
5963          * the interrupt to recover from the error.
5964          */
5965         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
5966                             SCHEDULE_DEFERRED) {
5967                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
5968                                   __ATOMIC_RELAXED);
5969                 hns3_err(hw, "Handling interrupts in delayed tasks");
5970                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5971                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5972                 if (reset_level == HNS3_NONE_RESET) {
5973                         hns3_err(hw, "No reset level is set, try IMP reset");
5974                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5975                 }
5976         }
5977         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
5978
5979         /*
5980          * Check if there is any ongoing reset in the hardware. This status can
5981          * be checked from reset_pending. If there is then, we need to wait for
5982          * hardware to complete reset.
5983          *    a. If we are able to figure out in reasonable time that hardware
5984          *       has fully resetted then, we can proceed with driver, client
5985          *       reset.
5986          *    b. else, we can come back later to check this status so re-sched
5987          *       now.
5988          */
5989         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5990         if (reset_level != HNS3_NONE_RESET) {
5991                 hns3_clock_gettime(&tv_start);
5992                 ret = hns3_reset_process(hns, reset_level);
5993                 hns3_clock_gettime(&tv);
5994                 timersub(&tv, &tv_start, &tv_delta);
5995                 msec = hns3_clock_calctime_ms(&tv_delta);
5996                 if (msec > HNS3_RESET_PROCESS_MS)
5997                         hns3_err(hw, "%d handle long time delta %" PRIu64
5998                                      " ms time=%ld.%.6ld",
5999                                  hw->reset.level, msec,
6000                                  tv.tv_sec, tv.tv_usec);
6001                 if (ret == -EAGAIN)
6002                         return;
6003         }
6004
6005         /* Check if we got any *new* reset requests to be honored */
6006         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6007         if (reset_level != HNS3_NONE_RESET)
6008                 hns3_msix_process(hns, reset_level);
6009 }
6010
6011 static unsigned int
6012 hns3_get_speed_capa_num(uint16_t device_id)
6013 {
6014         unsigned int num;
6015
6016         switch (device_id) {
6017         case HNS3_DEV_ID_25GE:
6018         case HNS3_DEV_ID_25GE_RDMA:
6019                 num = 2;
6020                 break;
6021         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6022         case HNS3_DEV_ID_200G_RDMA:
6023                 num = 1;
6024                 break;
6025         default:
6026                 num = 0;
6027                 break;
6028         }
6029
6030         return num;
6031 }
6032
6033 static int
6034 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6035                         uint16_t device_id)
6036 {
6037         switch (device_id) {
6038         case HNS3_DEV_ID_25GE:
6039         /* fallthrough */
6040         case HNS3_DEV_ID_25GE_RDMA:
6041                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6042                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6043
6044                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6045                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6046                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6047                 break;
6048         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6049                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6050                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6051                 break;
6052         case HNS3_DEV_ID_200G_RDMA:
6053                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6054                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6055                 break;
6056         default:
6057                 return -ENOTSUP;
6058         }
6059
6060         return 0;
6061 }
6062
6063 static int
6064 hns3_fec_get_capability(struct rte_eth_dev *dev,
6065                         struct rte_eth_fec_capa *speed_fec_capa,
6066                         unsigned int num)
6067 {
6068         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6069         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6070         uint16_t device_id = pci_dev->id.device_id;
6071         unsigned int capa_num;
6072         int ret;
6073
6074         capa_num = hns3_get_speed_capa_num(device_id);
6075         if (capa_num == 0) {
6076                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6077                          device_id);
6078                 return -ENOTSUP;
6079         }
6080
6081         if (speed_fec_capa == NULL || num < capa_num)
6082                 return capa_num;
6083
6084         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6085         if (ret)
6086                 return -ENOTSUP;
6087
6088         return capa_num;
6089 }
6090
6091 static int
6092 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6093 {
6094         struct hns3_config_fec_cmd *req;
6095         struct hns3_cmd_desc desc;
6096         int ret;
6097
6098         /*
6099          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6100          * in device of link speed
6101          * below 10 Gbps.
6102          */
6103         if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) {
6104                 *state = 0;
6105                 return 0;
6106         }
6107
6108         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6109         req = (struct hns3_config_fec_cmd *)desc.data;
6110         ret = hns3_cmd_send(hw, &desc, 1);
6111         if (ret) {
6112                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6113                          ret);
6114                 return ret;
6115         }
6116
6117         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6118         return 0;
6119 }
6120
6121 static int
6122 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6123 {
6124         struct hns3_sfp_info_cmd *resp;
6125         uint32_t tmp_fec_capa;
6126         uint8_t auto_state;
6127         struct hns3_cmd_desc desc;
6128         int ret;
6129
6130         /*
6131          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6132          * configured FEC mode is returned.
6133          * If link is up, current FEC mode is returned.
6134          */
6135         if (hw->mac.link_status == RTE_ETH_LINK_DOWN) {
6136                 ret = get_current_fec_auto_state(hw, &auto_state);
6137                 if (ret)
6138                         return ret;
6139
6140                 if (auto_state == 0x1) {
6141                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6142                         return 0;
6143                 }
6144         }
6145
6146         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6147         resp = (struct hns3_sfp_info_cmd *)desc.data;
6148         resp->query_type = HNS3_ACTIVE_QUERY;
6149
6150         ret = hns3_cmd_send(hw, &desc, 1);
6151         if (ret == -EOPNOTSUPP) {
6152                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6153                 return ret;
6154         } else if (ret) {
6155                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6156                 return ret;
6157         }
6158
6159         /*
6160          * FEC mode order defined in hns3 hardware is inconsistent with
6161          * that defined in the ethdev library. So the sequence needs
6162          * to be converted.
6163          */
6164         switch (resp->active_fec) {
6165         case HNS3_HW_FEC_MODE_NOFEC:
6166                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6167                 break;
6168         case HNS3_HW_FEC_MODE_BASER:
6169                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6170                 break;
6171         case HNS3_HW_FEC_MODE_RS:
6172                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6173                 break;
6174         default:
6175                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6176                 break;
6177         }
6178
6179         *fec_capa = tmp_fec_capa;
6180         return 0;
6181 }
6182
6183 static int
6184 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6185 {
6186         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6187
6188         return hns3_fec_get_internal(hw, fec_capa);
6189 }
6190
6191 static int
6192 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6193 {
6194         struct hns3_config_fec_cmd *req;
6195         struct hns3_cmd_desc desc;
6196         int ret;
6197
6198         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6199
6200         req = (struct hns3_config_fec_cmd *)desc.data;
6201         switch (mode) {
6202         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6203                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6204                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6205                 break;
6206         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6207                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6208                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6209                 break;
6210         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6211                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6212                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6213                 break;
6214         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6215                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6216                 break;
6217         default:
6218                 return 0;
6219         }
6220         ret = hns3_cmd_send(hw, &desc, 1);
6221         if (ret)
6222                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6223
6224         return ret;
6225 }
6226
6227 static uint32_t
6228 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6229 {
6230         struct hns3_mac *mac = &hw->mac;
6231         uint32_t cur_capa;
6232
6233         switch (mac->link_speed) {
6234         case RTE_ETH_SPEED_NUM_10G:
6235                 cur_capa = fec_capa[1].capa;
6236                 break;
6237         case RTE_ETH_SPEED_NUM_25G:
6238         case RTE_ETH_SPEED_NUM_100G:
6239         case RTE_ETH_SPEED_NUM_200G:
6240                 cur_capa = fec_capa[0].capa;
6241                 break;
6242         default:
6243                 cur_capa = 0;
6244                 break;
6245         }
6246
6247         return cur_capa;
6248 }
6249
6250 static bool
6251 is_fec_mode_one_bit_set(uint32_t mode)
6252 {
6253         int cnt = 0;
6254         uint8_t i;
6255
6256         for (i = 0; i < sizeof(mode); i++)
6257                 if (mode >> i & 0x1)
6258                         cnt++;
6259
6260         return cnt == 1 ? true : false;
6261 }
6262
6263 static int
6264 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6265 {
6266 #define FEC_CAPA_NUM 2
6267         struct hns3_adapter *hns = dev->data->dev_private;
6268         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6269         struct hns3_pf *pf = &hns->pf;
6270         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6271         uint32_t cur_capa;
6272         uint32_t num = FEC_CAPA_NUM;
6273         int ret;
6274
6275         ret = hns3_fec_get_capability(dev, fec_capa, num);
6276         if (ret < 0)
6277                 return ret;
6278
6279         /* HNS3 PMD only support one bit set mode, e.g. 0x1, 0x4 */
6280         if (!is_fec_mode_one_bit_set(mode)) {
6281                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6282                              "FEC mode should be only one bit set", mode);
6283                 return -EINVAL;
6284         }
6285
6286         /*
6287          * Check whether the configured mode is within the FEC capability.
6288          * If not, the configured mode will not be supported.
6289          */
6290         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6291         if (!(cur_capa & mode)) {
6292                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6293                 return -EINVAL;
6294         }
6295
6296         rte_spinlock_lock(&hw->lock);
6297         ret = hns3_set_fec_hw(hw, mode);
6298         if (ret) {
6299                 rte_spinlock_unlock(&hw->lock);
6300                 return ret;
6301         }
6302
6303         pf->fec_mode = mode;
6304         rte_spinlock_unlock(&hw->lock);
6305
6306         return 0;
6307 }
6308
6309 static int
6310 hns3_restore_fec(struct hns3_hw *hw)
6311 {
6312         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6313         struct hns3_pf *pf = &hns->pf;
6314         uint32_t mode = pf->fec_mode;
6315         int ret;
6316
6317         ret = hns3_set_fec_hw(hw, mode);
6318         if (ret)
6319                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6320                          mode, ret);
6321
6322         return ret;
6323 }
6324
6325 static int
6326 hns3_query_dev_fec_info(struct hns3_hw *hw)
6327 {
6328         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6329         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6330         int ret;
6331
6332         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6333         if (ret)
6334                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6335
6336         return ret;
6337 }
6338
6339 static bool
6340 hns3_optical_module_existed(struct hns3_hw *hw)
6341 {
6342         struct hns3_cmd_desc desc;
6343         bool existed;
6344         int ret;
6345
6346         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6347         ret = hns3_cmd_send(hw, &desc, 1);
6348         if (ret) {
6349                 hns3_err(hw,
6350                          "fail to get optical module exist state, ret = %d.\n",
6351                          ret);
6352                 return false;
6353         }
6354         existed = !!desc.data[0];
6355
6356         return existed;
6357 }
6358
6359 static int
6360 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6361                                 uint32_t len, uint8_t *data)
6362 {
6363 #define HNS3_SFP_INFO_CMD_NUM 6
6364 #define HNS3_SFP_INFO_MAX_LEN \
6365         (HNS3_SFP_INFO_BD0_LEN + \
6366         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6367         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6368         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6369         uint16_t read_len;
6370         uint16_t copy_len;
6371         int ret;
6372         int i;
6373
6374         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6375                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6376                                           true);
6377                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6378                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6379         }
6380
6381         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6382         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6383         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6384         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6385
6386         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6387         if (ret) {
6388                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6389                                 ret);
6390                 return ret;
6391         }
6392
6393         /* The data format in BD0 is different with the others. */
6394         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6395         memcpy(data, sfp_info_bd0->data, copy_len);
6396         read_len = copy_len;
6397
6398         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6399                 if (read_len >= len)
6400                         break;
6401
6402                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6403                 memcpy(data + read_len, desc[i].data, copy_len);
6404                 read_len += copy_len;
6405         }
6406
6407         return (int)read_len;
6408 }
6409
6410 static int
6411 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6412                        struct rte_dev_eeprom_info *info)
6413 {
6414         struct hns3_adapter *hns = dev->data->dev_private;
6415         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6416         uint32_t offset = info->offset;
6417         uint32_t len = info->length;
6418         uint8_t *data = info->data;
6419         uint32_t read_len = 0;
6420
6421         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6422                 return -ENOTSUP;
6423
6424         if (!hns3_optical_module_existed(hw)) {
6425                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6426                 return -EIO;
6427         }
6428
6429         while (read_len < len) {
6430                 int ret;
6431                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6432                                                   len - read_len,
6433                                                   data + read_len);
6434                 if (ret < 0)
6435                         return -EIO;
6436                 read_len += ret;
6437         }
6438
6439         return 0;
6440 }
6441
6442 static int
6443 hns3_get_module_info(struct rte_eth_dev *dev,
6444                      struct rte_eth_dev_module_info *modinfo)
6445 {
6446 #define HNS3_SFF8024_ID_SFP             0x03
6447 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6448 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6449 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6450 #define HNS3_SFF_8636_V1_3              0x03
6451         struct hns3_adapter *hns = dev->data->dev_private;
6452         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6453         struct rte_dev_eeprom_info info;
6454         struct hns3_sfp_type sfp_type;
6455         int ret;
6456
6457         memset(&sfp_type, 0, sizeof(sfp_type));
6458         memset(&info, 0, sizeof(info));
6459         info.data = (uint8_t *)&sfp_type;
6460         info.length = sizeof(sfp_type);
6461         ret = hns3_get_module_eeprom(dev, &info);
6462         if (ret)
6463                 return ret;
6464
6465         switch (sfp_type.type) {
6466         case HNS3_SFF8024_ID_SFP:
6467                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6468                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6469                 break;
6470         case HNS3_SFF8024_ID_QSFP_8438:
6471                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6472                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6473                 break;
6474         case HNS3_SFF8024_ID_QSFP_8436_8636:
6475                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6476                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6477                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6478                 } else {
6479                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6480                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6481                 }
6482                 break;
6483         case HNS3_SFF8024_ID_QSFP28_8636:
6484                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6485                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6486                 break;
6487         default:
6488                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6489                          sfp_type.type, sfp_type.ext_type);
6490                 return -EINVAL;
6491         }
6492
6493         return 0;
6494 }
6495
6496 static const struct eth_dev_ops hns3_eth_dev_ops = {
6497         .dev_configure      = hns3_dev_configure,
6498         .dev_start          = hns3_dev_start,
6499         .dev_stop           = hns3_dev_stop,
6500         .dev_close          = hns3_dev_close,
6501         .promiscuous_enable = hns3_dev_promiscuous_enable,
6502         .promiscuous_disable = hns3_dev_promiscuous_disable,
6503         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6504         .allmulticast_disable = hns3_dev_allmulticast_disable,
6505         .mtu_set            = hns3_dev_mtu_set,
6506         .stats_get          = hns3_stats_get,
6507         .stats_reset        = hns3_stats_reset,
6508         .xstats_get         = hns3_dev_xstats_get,
6509         .xstats_get_names   = hns3_dev_xstats_get_names,
6510         .xstats_reset       = hns3_dev_xstats_reset,
6511         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6512         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6513         .dev_infos_get          = hns3_dev_infos_get,
6514         .fw_version_get         = hns3_fw_version_get,
6515         .rx_queue_setup         = hns3_rx_queue_setup,
6516         .tx_queue_setup         = hns3_tx_queue_setup,
6517         .rx_queue_release       = hns3_dev_rx_queue_release,
6518         .tx_queue_release       = hns3_dev_tx_queue_release,
6519         .rx_queue_start         = hns3_dev_rx_queue_start,
6520         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6521         .tx_queue_start         = hns3_dev_tx_queue_start,
6522         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6523         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6524         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6525         .rxq_info_get           = hns3_rxq_info_get,
6526         .txq_info_get           = hns3_txq_info_get,
6527         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6528         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6529         .flow_ctrl_get          = hns3_flow_ctrl_get,
6530         .flow_ctrl_set          = hns3_flow_ctrl_set,
6531         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6532         .mac_addr_add           = hns3_add_mac_addr,
6533         .mac_addr_remove        = hns3_remove_mac_addr,
6534         .mac_addr_set           = hns3_set_default_mac_addr,
6535         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6536         .link_update            = hns3_dev_link_update,
6537         .dev_set_link_up        = hns3_dev_set_link_up,
6538         .dev_set_link_down      = hns3_dev_set_link_down,
6539         .rss_hash_update        = hns3_dev_rss_hash_update,
6540         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6541         .reta_update            = hns3_dev_rss_reta_update,
6542         .reta_query             = hns3_dev_rss_reta_query,
6543         .flow_ops_get           = hns3_dev_flow_ops_get,
6544         .vlan_filter_set        = hns3_vlan_filter_set,
6545         .vlan_tpid_set          = hns3_vlan_tpid_set,
6546         .vlan_offload_set       = hns3_vlan_offload_set,
6547         .vlan_pvid_set          = hns3_vlan_pvid_set,
6548         .get_reg                = hns3_get_regs,
6549         .get_module_info        = hns3_get_module_info,
6550         .get_module_eeprom      = hns3_get_module_eeprom,
6551         .get_dcb_info           = hns3_get_dcb_info,
6552         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6553         .fec_get_capability     = hns3_fec_get_capability,
6554         .fec_get                = hns3_fec_get,
6555         .fec_set                = hns3_fec_set,
6556         .tm_ops_get             = hns3_tm_ops_get,
6557         .tx_done_cleanup        = hns3_tx_done_cleanup,
6558         .timesync_enable            = hns3_timesync_enable,
6559         .timesync_disable           = hns3_timesync_disable,
6560         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6561         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6562         .timesync_adjust_time       = hns3_timesync_adjust_time,
6563         .timesync_read_time         = hns3_timesync_read_time,
6564         .timesync_write_time        = hns3_timesync_write_time,
6565         .eth_dev_priv_dump          = hns3_eth_dev_priv_dump,
6566 };
6567
6568 static const struct hns3_reset_ops hns3_reset_ops = {
6569         .reset_service       = hns3_reset_service,
6570         .stop_service        = hns3_stop_service,
6571         .prepare_reset       = hns3_prepare_reset,
6572         .wait_hardware_ready = hns3_wait_hardware_ready,
6573         .reinit_dev          = hns3_reinit_dev,
6574         .restore_conf        = hns3_restore_conf,
6575         .start_service       = hns3_start_service,
6576 };
6577
6578 static void
6579 hns3_init_hw_ops(struct hns3_hw *hw)
6580 {
6581         hw->ops.add_mc_mac_addr = hns3_add_mc_mac_addr;
6582         hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr;
6583         hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr;
6584         hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr;
6585         hw->ops.bind_ring_with_vector = hns3_bind_ring_with_vector;
6586 }
6587
6588 static int
6589 hns3_dev_init(struct rte_eth_dev *eth_dev)
6590 {
6591         struct hns3_adapter *hns = eth_dev->data->dev_private;
6592         struct hns3_hw *hw = &hns->hw;
6593         int ret;
6594
6595         PMD_INIT_FUNC_TRACE();
6596
6597         hns3_flow_init(eth_dev);
6598
6599         hns3_set_rxtx_function(eth_dev);
6600         eth_dev->dev_ops = &hns3_eth_dev_ops;
6601         eth_dev->rx_queue_count = hns3_rx_queue_count;
6602         ret = hns3_mp_init(eth_dev);
6603         if (ret)
6604                 goto err_mp_init;
6605
6606         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6607                 hns3_tx_push_init(eth_dev);
6608                 return 0;
6609         }
6610
6611         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6612         hns->is_vf = false;
6613         hw->data = eth_dev->data;
6614         hns3_parse_devargs(eth_dev);
6615
6616         /*
6617          * Set default max packet size according to the mtu
6618          * default vale in DPDK frame.
6619          */
6620         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6621
6622         ret = hns3_reset_init(hw);
6623         if (ret)
6624                 goto err_init_reset;
6625         hw->reset.ops = &hns3_reset_ops;
6626
6627         hns3_init_hw_ops(hw);
6628         ret = hns3_init_pf(eth_dev);
6629         if (ret) {
6630                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6631                 goto err_init_pf;
6632         }
6633
6634         ret = hns3_init_mac_addrs(eth_dev);
6635         if (ret != 0)
6636                 goto err_init_mac_addrs;
6637
6638         hw->adapter_state = HNS3_NIC_INITIALIZED;
6639
6640         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6641                             SCHEDULE_PENDING) {
6642                 hns3_err(hw, "Reschedule reset service after dev_init");
6643                 hns3_schedule_reset(hns);
6644         } else {
6645                 /* IMP will wait ready flag before reset */
6646                 hns3_notify_reset_ready(hw, false);
6647         }
6648
6649         hns3_info(hw, "hns3 dev initialization successful!");
6650         return 0;
6651
6652 err_init_mac_addrs:
6653         hns3_uninit_pf(eth_dev);
6654
6655 err_init_pf:
6656         rte_free(hw->reset.wait_data);
6657
6658 err_init_reset:
6659         hns3_mp_uninit(eth_dev);
6660
6661 err_mp_init:
6662         eth_dev->dev_ops = NULL;
6663         eth_dev->rx_pkt_burst = NULL;
6664         eth_dev->rx_descriptor_status = NULL;
6665         eth_dev->tx_pkt_burst = NULL;
6666         eth_dev->tx_pkt_prepare = NULL;
6667         eth_dev->tx_descriptor_status = NULL;
6668         return ret;
6669 }
6670
6671 static int
6672 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6673 {
6674         struct hns3_adapter *hns = eth_dev->data->dev_private;
6675         struct hns3_hw *hw = &hns->hw;
6676
6677         PMD_INIT_FUNC_TRACE();
6678
6679         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6680                 hns3_mp_uninit(eth_dev);
6681                 return 0;
6682         }
6683
6684         if (hw->adapter_state < HNS3_NIC_CLOSING)
6685                 hns3_dev_close(eth_dev);
6686
6687         hw->adapter_state = HNS3_NIC_REMOVED;
6688         return 0;
6689 }
6690
6691 static int
6692 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6693                    struct rte_pci_device *pci_dev)
6694 {
6695         return rte_eth_dev_pci_generic_probe(pci_dev,
6696                                              sizeof(struct hns3_adapter),
6697                                              hns3_dev_init);
6698 }
6699
6700 static int
6701 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6702 {
6703         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6704 }
6705
6706 static const struct rte_pci_id pci_id_hns3_map[] = {
6707         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6708         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6709         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6710         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6711         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6712         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6713         { .vendor_id = 0, }, /* sentinel */
6714 };
6715
6716 static struct rte_pci_driver rte_hns3_pmd = {
6717         .id_table = pci_id_hns3_map,
6718         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
6719         .probe = eth_hns3_pci_probe,
6720         .remove = eth_hns3_pci_remove,
6721 };
6722
6723 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6724 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6725 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6726 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6727                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6728                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
6729                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
6730                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
6731 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
6732 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);