1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
20 #define HNS3_SERVICE_QUICK_INTERVAL 10
21 #define HNS3_INVALID_PVID 0xFFFF
23 #define HNS3_FILTER_TYPE_VF 0
24 #define HNS3_FILTER_TYPE_PORT 1
25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
31 | HNS3_FILTER_FE_ROCE_EGRESS_B)
32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
33 | HNS3_FILTER_FE_ROCE_INGRESS_B)
35 /* Reset related Registers */
36 #define HNS3_GLOBAL_RESET_BIT 0
37 #define HNS3_CORE_RESET_BIT 1
38 #define HNS3_IMP_RESET_BIT 2
39 #define HNS3_FUN_RST_ING_B 0
41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
46 #define HNS3_RESET_WAIT_MS 100
47 #define HNS3_RESET_WAIT_CNT 200
49 /* FEC mode order defined in HNS3 hardware */
50 #define HNS3_HW_FEC_MODE_NOFEC 0
51 #define HNS3_HW_FEC_MODE_BASER 1
52 #define HNS3_HW_FEC_MODE_RS 2
55 HNS3_VECTOR0_EVENT_RST,
56 HNS3_VECTOR0_EVENT_MBX,
57 HNS3_VECTOR0_EVENT_ERR,
58 HNS3_VECTOR0_EVENT_PTP,
59 HNS3_VECTOR0_EVENT_OTHER,
62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
63 { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
67 { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
72 { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
76 { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
81 { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
85 { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
96 static bool hns3_update_link_status(struct hns3_hw *hw);
98 static int hns3_add_mc_mac_addr(struct hns3_hw *hw,
99 struct rte_ether_addr *mac_addr);
100 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
101 struct rte_ether_addr *mac_addr);
102 static int hns3_restore_fec(struct hns3_hw *hw);
103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
104 static int hns3_do_stop(struct hns3_adapter *hns);
105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
108 void hns3_ether_format_addr(char *buf, uint16_t size,
109 const struct rte_ether_addr *ether_addr)
111 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
112 ether_addr->addr_bytes[0],
113 ether_addr->addr_bytes[4],
114 ether_addr->addr_bytes[5]);
118 hns3_pf_disable_irq0(struct hns3_hw *hw)
120 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
124 hns3_pf_enable_irq0(struct hns3_hw *hw)
126 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
129 static enum hns3_evt_cause
130 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
133 struct hns3_hw *hw = &hns->hw;
135 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
136 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
137 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
139 hw->reset.stats.imp_cnt++;
140 hns3_warn(hw, "IMP reset detected, clear reset status");
142 hns3_schedule_delayed_reset(hns);
143 hns3_warn(hw, "IMP reset detected, don't clear reset status");
146 return HNS3_VECTOR0_EVENT_RST;
149 static enum hns3_evt_cause
150 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
153 struct hns3_hw *hw = &hns->hw;
155 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
156 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
157 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
159 hw->reset.stats.global_cnt++;
160 hns3_warn(hw, "Global reset detected, clear reset status");
162 hns3_schedule_delayed_reset(hns);
164 "Global reset detected, don't clear reset status");
167 return HNS3_VECTOR0_EVENT_RST;
170 static enum hns3_evt_cause
171 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
173 struct hns3_hw *hw = &hns->hw;
174 uint32_t vector0_int_stats;
175 uint32_t cmdq_src_val;
176 uint32_t hw_err_src_reg;
178 enum hns3_evt_cause ret;
181 /* fetch the events from their corresponding regs */
182 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
183 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
184 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
186 is_delay = clearval == NULL ? true : false;
188 * Assumption: If by any chance reset and mailbox events are reported
189 * together then we will only process reset event and defer the
190 * processing of the mailbox events. Since, we would have not cleared
191 * RX CMDQ event this time we would receive again another interrupt
192 * from H/W just for the mailbox.
194 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
195 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
200 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
201 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
205 /* Check for vector0 1588 event source */
206 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
207 val = BIT(HNS3_VECTOR0_1588_INT_B);
208 ret = HNS3_VECTOR0_EVENT_PTP;
212 /* check for vector0 msix event source */
213 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
214 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
215 val = vector0_int_stats | hw_err_src_reg;
216 ret = HNS3_VECTOR0_EVENT_ERR;
220 /* check for vector0 mailbox(=CMDQ RX) event source */
221 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
222 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
224 ret = HNS3_VECTOR0_EVENT_MBX;
228 val = vector0_int_stats;
229 ret = HNS3_VECTOR0_EVENT_OTHER;
238 hns3_is_1588_event_type(uint32_t event_type)
240 return (event_type == HNS3_VECTOR0_EVENT_PTP);
244 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
246 if (event_type == HNS3_VECTOR0_EVENT_RST ||
247 hns3_is_1588_event_type(event_type))
248 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
249 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
250 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
254 hns3_clear_all_event_cause(struct hns3_hw *hw)
256 uint32_t vector0_int_stats;
258 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
259 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
260 hns3_warn(hw, "Probe during IMP reset interrupt");
262 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
263 hns3_warn(hw, "Probe during Global reset interrupt");
265 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
266 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
267 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
268 BIT(HNS3_VECTOR0_CORERESET_INT_B));
269 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
270 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
271 BIT(HNS3_VECTOR0_1588_INT_B));
275 hns3_handle_mac_tnl(struct hns3_hw *hw)
277 struct hns3_cmd_desc desc;
281 /* query and clear mac tnl interrupt */
282 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
283 ret = hns3_cmd_send(hw, &desc, 1);
285 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
289 status = rte_le_to_cpu_32(desc.data[0]);
291 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
292 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
294 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
295 ret = hns3_cmd_send(hw, &desc, 1);
297 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
303 hns3_interrupt_handler(void *param)
305 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
306 struct hns3_adapter *hns = dev->data->dev_private;
307 struct hns3_hw *hw = &hns->hw;
308 enum hns3_evt_cause event_cause;
309 uint32_t clearval = 0;
310 uint32_t vector0_int;
314 /* Disable interrupt */
315 hns3_pf_disable_irq0(hw);
317 event_cause = hns3_check_event_cause(hns, &clearval);
318 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
319 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
320 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
321 hns3_clear_event_cause(hw, event_cause, clearval);
322 /* vector 0 interrupt is shared with reset and mailbox source events. */
323 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
324 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
325 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
326 vector0_int, ras_int, cmdq_int);
327 hns3_handle_mac_tnl(hw);
328 hns3_handle_error(hns);
329 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
330 hns3_warn(hw, "received reset interrupt");
331 hns3_schedule_reset(hns);
332 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
333 hns3_dev_handle_mbx_msg(hw);
335 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
336 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
337 vector0_int, ras_int, cmdq_int);
340 /* Enable interrupt if it is not cause by reset */
341 hns3_pf_enable_irq0(hw);
345 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
347 #define HNS3_VLAN_ID_OFFSET_STEP 160
348 #define HNS3_VLAN_BYTE_SIZE 8
349 struct hns3_vlan_filter_pf_cfg_cmd *req;
350 struct hns3_hw *hw = &hns->hw;
351 uint8_t vlan_offset_byte_val;
352 struct hns3_cmd_desc desc;
353 uint8_t vlan_offset_byte;
354 uint8_t vlan_offset_base;
357 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
359 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
360 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
362 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
364 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
365 req->vlan_offset = vlan_offset_base;
366 req->vlan_cfg = on ? 0 : 1;
367 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
369 ret = hns3_cmd_send(hw, &desc, 1);
371 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
378 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
380 struct hns3_user_vlan_table *vlan_entry;
381 struct hns3_pf *pf = &hns->pf;
383 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
384 if (vlan_entry->vlan_id == vlan_id) {
385 if (vlan_entry->hd_tbl_status)
386 hns3_set_port_vlan_filter(hns, vlan_id, 0);
387 LIST_REMOVE(vlan_entry, next);
388 rte_free(vlan_entry);
395 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
398 struct hns3_user_vlan_table *vlan_entry;
399 struct hns3_hw *hw = &hns->hw;
400 struct hns3_pf *pf = &hns->pf;
402 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
403 if (vlan_entry->vlan_id == vlan_id)
407 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
408 if (vlan_entry == NULL) {
409 hns3_err(hw, "Failed to malloc hns3 vlan table");
413 vlan_entry->hd_tbl_status = writen_to_tbl;
414 vlan_entry->vlan_id = vlan_id;
416 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
420 hns3_restore_vlan_table(struct hns3_adapter *hns)
422 struct hns3_user_vlan_table *vlan_entry;
423 struct hns3_hw *hw = &hns->hw;
424 struct hns3_pf *pf = &hns->pf;
428 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
429 return hns3_vlan_pvid_configure(hns,
430 hw->port_base_vlan_cfg.pvid, 1);
432 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
433 if (vlan_entry->hd_tbl_status) {
434 vlan_id = vlan_entry->vlan_id;
435 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
445 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
447 struct hns3_hw *hw = &hns->hw;
448 bool writen_to_tbl = false;
452 * When vlan filter is enabled, hardware regards packets without vlan
453 * as packets with vlan 0. So, to receive packets without vlan, vlan id
454 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
456 if (on == 0 && vlan_id == 0)
460 * When port base vlan enabled, we use port base vlan as the vlan
461 * filter condition. In this case, we don't update vlan filter table
462 * when user add new vlan or remove exist vlan, just update the
463 * vlan list. The vlan id in vlan list will be written in vlan filter
464 * table until port base vlan disabled
466 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
467 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
468 writen_to_tbl = true;
473 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
475 hns3_rm_dev_vlan_table(hns, vlan_id);
481 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
483 struct hns3_adapter *hns = dev->data->dev_private;
484 struct hns3_hw *hw = &hns->hw;
487 rte_spinlock_lock(&hw->lock);
488 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
489 rte_spinlock_unlock(&hw->lock);
494 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
497 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
498 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
499 struct hns3_hw *hw = &hns->hw;
500 struct hns3_cmd_desc desc;
503 if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
504 vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) {
505 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
509 if (tpid != RTE_ETHER_TYPE_VLAN) {
510 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
514 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
515 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
517 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
518 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
519 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
520 } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
521 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
522 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
523 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
524 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
527 ret = hns3_cmd_send(hw, &desc, 1);
529 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
534 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
536 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
537 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
538 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
540 ret = hns3_cmd_send(hw, &desc, 1);
542 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
548 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
551 struct hns3_adapter *hns = dev->data->dev_private;
552 struct hns3_hw *hw = &hns->hw;
555 rte_spinlock_lock(&hw->lock);
556 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
557 rte_spinlock_unlock(&hw->lock);
562 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
563 struct hns3_rx_vtag_cfg *vcfg)
565 struct hns3_vport_vtag_rx_cfg_cmd *req;
566 struct hns3_hw *hw = &hns->hw;
567 struct hns3_cmd_desc desc;
572 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
574 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
575 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
576 vcfg->strip_tag1_en ? 1 : 0);
577 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
578 vcfg->strip_tag2_en ? 1 : 0);
579 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
580 vcfg->vlan1_vlan_prionly ? 1 : 0);
581 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
582 vcfg->vlan2_vlan_prionly ? 1 : 0);
584 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
585 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
586 vcfg->strip_tag1_discard_en ? 1 : 0);
587 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
588 vcfg->strip_tag2_discard_en ? 1 : 0);
590 * In current version VF is not supported when PF is driven by DPDK
591 * driver, just need to configure parameters for PF vport.
593 vport_id = HNS3_PF_FUNC_ID;
594 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
595 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
596 req->vf_bitmap[req->vf_offset] = bitmap;
598 ret = hns3_cmd_send(hw, &desc, 1);
600 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
605 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
606 struct hns3_rx_vtag_cfg *vcfg)
608 struct hns3_pf *pf = &hns->pf;
609 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
613 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
614 struct hns3_tx_vtag_cfg *vcfg)
616 struct hns3_pf *pf = &hns->pf;
617 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
621 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
623 struct hns3_rx_vtag_cfg rxvlan_cfg;
624 struct hns3_hw *hw = &hns->hw;
627 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
628 rxvlan_cfg.strip_tag1_en = false;
629 rxvlan_cfg.strip_tag2_en = enable;
630 rxvlan_cfg.strip_tag2_discard_en = false;
632 rxvlan_cfg.strip_tag1_en = enable;
633 rxvlan_cfg.strip_tag2_en = true;
634 rxvlan_cfg.strip_tag2_discard_en = true;
637 rxvlan_cfg.strip_tag1_discard_en = false;
638 rxvlan_cfg.vlan1_vlan_prionly = false;
639 rxvlan_cfg.vlan2_vlan_prionly = false;
640 rxvlan_cfg.rx_vlan_offload_en = enable;
642 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
644 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
645 enable ? "enable" : "disable", ret);
649 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
655 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
656 uint8_t fe_type, bool filter_en, uint8_t vf_id)
658 struct hns3_vlan_filter_ctrl_cmd *req;
659 struct hns3_cmd_desc desc;
662 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
664 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
665 req->vlan_type = vlan_type;
666 req->vlan_fe = filter_en ? fe_type : 0;
669 ret = hns3_cmd_send(hw, &desc, 1);
671 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
677 hns3_vlan_filter_init(struct hns3_adapter *hns)
679 struct hns3_hw *hw = &hns->hw;
682 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
683 HNS3_FILTER_FE_EGRESS, false,
686 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
690 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
691 HNS3_FILTER_FE_INGRESS, false,
694 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
700 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
702 struct hns3_hw *hw = &hns->hw;
705 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
706 HNS3_FILTER_FE_INGRESS, enable,
709 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
710 enable ? "enable" : "disable", ret);
716 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
718 struct hns3_adapter *hns = dev->data->dev_private;
719 struct hns3_hw *hw = &hns->hw;
720 struct rte_eth_rxmode *rxmode;
721 unsigned int tmp_mask;
725 rte_spinlock_lock(&hw->lock);
726 rxmode = &dev->data->dev_conf.rxmode;
727 tmp_mask = (unsigned int)mask;
728 if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
729 /* ignore vlan filter configuration during promiscuous mode */
730 if (!dev->data->promiscuous) {
731 /* Enable or disable VLAN filter */
732 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ?
735 ret = hns3_enable_vlan_filter(hns, enable);
737 rte_spinlock_unlock(&hw->lock);
738 hns3_err(hw, "failed to %s rx filter, ret = %d",
739 enable ? "enable" : "disable", ret);
745 if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
746 /* Enable or disable VLAN stripping */
747 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ?
750 ret = hns3_en_hw_strip_rxvtag(hns, enable);
752 rte_spinlock_unlock(&hw->lock);
753 hns3_err(hw, "failed to %s rx strip, ret = %d",
754 enable ? "enable" : "disable", ret);
759 rte_spinlock_unlock(&hw->lock);
765 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
766 struct hns3_tx_vtag_cfg *vcfg)
768 struct hns3_vport_vtag_tx_cfg_cmd *req;
769 struct hns3_cmd_desc desc;
770 struct hns3_hw *hw = &hns->hw;
775 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
777 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
778 req->def_vlan_tag1 = vcfg->default_tag1;
779 req->def_vlan_tag2 = vcfg->default_tag2;
780 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
781 vcfg->accept_tag1 ? 1 : 0);
782 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
783 vcfg->accept_untag1 ? 1 : 0);
784 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
785 vcfg->accept_tag2 ? 1 : 0);
786 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
787 vcfg->accept_untag2 ? 1 : 0);
788 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
789 vcfg->insert_tag1_en ? 1 : 0);
790 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
791 vcfg->insert_tag2_en ? 1 : 0);
792 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
794 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
795 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
796 vcfg->tag_shift_mode_en ? 1 : 0);
799 * In current version VF is not supported when PF is driven by DPDK
800 * driver, just need to configure parameters for PF vport.
802 vport_id = HNS3_PF_FUNC_ID;
803 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
804 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
805 req->vf_bitmap[req->vf_offset] = bitmap;
807 ret = hns3_cmd_send(hw, &desc, 1);
809 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
815 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
818 struct hns3_hw *hw = &hns->hw;
819 struct hns3_tx_vtag_cfg txvlan_cfg;
822 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
823 txvlan_cfg.accept_tag1 = true;
824 txvlan_cfg.insert_tag1_en = false;
825 txvlan_cfg.default_tag1 = 0;
827 txvlan_cfg.accept_tag1 =
828 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
829 txvlan_cfg.insert_tag1_en = true;
830 txvlan_cfg.default_tag1 = pvid;
833 txvlan_cfg.accept_untag1 = true;
834 txvlan_cfg.accept_tag2 = true;
835 txvlan_cfg.accept_untag2 = true;
836 txvlan_cfg.insert_tag2_en = false;
837 txvlan_cfg.default_tag2 = 0;
838 txvlan_cfg.tag_shift_mode_en = true;
840 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
842 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
847 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
853 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
855 struct hns3_user_vlan_table *vlan_entry;
856 struct hns3_pf *pf = &hns->pf;
858 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
859 if (vlan_entry->hd_tbl_status) {
860 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
861 vlan_entry->hd_tbl_status = false;
866 vlan_entry = LIST_FIRST(&pf->vlan_list);
868 LIST_REMOVE(vlan_entry, next);
869 rte_free(vlan_entry);
870 vlan_entry = LIST_FIRST(&pf->vlan_list);
876 hns3_add_all_vlan_table(struct hns3_adapter *hns)
878 struct hns3_user_vlan_table *vlan_entry;
879 struct hns3_pf *pf = &hns->pf;
881 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
882 if (!vlan_entry->hd_tbl_status) {
883 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
884 vlan_entry->hd_tbl_status = true;
890 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
892 struct hns3_hw *hw = &hns->hw;
895 hns3_rm_all_vlan_table(hns, true);
896 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
897 ret = hns3_set_port_vlan_filter(hns,
898 hw->port_base_vlan_cfg.pvid, 0);
900 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
908 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
909 uint16_t port_base_vlan_state, uint16_t new_pvid)
911 struct hns3_hw *hw = &hns->hw;
915 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
916 old_pvid = hw->port_base_vlan_cfg.pvid;
917 if (old_pvid != HNS3_INVALID_PVID) {
918 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
920 hns3_err(hw, "failed to remove old pvid %u, "
921 "ret = %d", old_pvid, ret);
926 hns3_rm_all_vlan_table(hns, false);
927 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
929 hns3_err(hw, "failed to add new pvid %u, ret = %d",
934 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
936 hns3_err(hw, "failed to remove pvid %u, ret = %d",
941 hns3_add_all_vlan_table(hns);
947 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
949 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
950 struct hns3_rx_vtag_cfg rx_vlan_cfg;
954 rx_strip_en = old_cfg->rx_vlan_offload_en;
956 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
957 rx_vlan_cfg.strip_tag2_en = true;
958 rx_vlan_cfg.strip_tag2_discard_en = true;
960 rx_vlan_cfg.strip_tag1_en = false;
961 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
962 rx_vlan_cfg.strip_tag2_discard_en = false;
964 rx_vlan_cfg.strip_tag1_discard_en = false;
965 rx_vlan_cfg.vlan1_vlan_prionly = false;
966 rx_vlan_cfg.vlan2_vlan_prionly = false;
967 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
969 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
973 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
978 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
980 struct hns3_hw *hw = &hns->hw;
981 uint16_t port_base_vlan_state;
984 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
985 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
986 hns3_warn(hw, "Invalid operation! As current pvid set "
987 "is %u, disable pvid %u is invalid",
988 hw->port_base_vlan_cfg.pvid, pvid);
992 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
993 HNS3_PORT_BASE_VLAN_DISABLE;
994 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
996 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
1001 ret = hns3_en_pvid_strip(hns, on);
1003 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1005 goto pvid_vlan_strip_fail;
1008 if (pvid == HNS3_INVALID_PVID)
1010 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1012 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1014 goto vlan_filter_set_fail;
1018 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1019 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1022 vlan_filter_set_fail:
1023 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1024 HNS3_PORT_BASE_VLAN_ENABLE);
1026 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1028 pvid_vlan_strip_fail:
1029 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1030 hw->port_base_vlan_cfg.pvid);
1032 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1038 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1040 struct hns3_adapter *hns = dev->data->dev_private;
1041 struct hns3_hw *hw = &hns->hw;
1042 bool pvid_en_state_change;
1043 uint16_t pvid_state;
1046 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1047 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1048 RTE_ETHER_MAX_VLAN_ID);
1053 * If PVID configuration state change, should refresh the PVID
1054 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1056 pvid_state = hw->port_base_vlan_cfg.state;
1057 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1058 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1059 pvid_en_state_change = false;
1061 pvid_en_state_change = true;
1063 rte_spinlock_lock(&hw->lock);
1064 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1065 rte_spinlock_unlock(&hw->lock);
1069 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1070 * need be processed by PMD driver.
1072 if (pvid_en_state_change &&
1073 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1074 hns3_update_all_queues_pvid_proc_en(hw);
1080 hns3_default_vlan_config(struct hns3_adapter *hns)
1082 struct hns3_hw *hw = &hns->hw;
1086 * When vlan filter is enabled, hardware regards packets without vlan
1087 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1088 * table, packets without vlan won't be received. So, add vlan 0 as
1091 ret = hns3_vlan_filter_configure(hns, 0, 1);
1093 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1098 hns3_init_vlan_config(struct hns3_adapter *hns)
1100 struct hns3_hw *hw = &hns->hw;
1104 * This function can be called in the initialization and reset process,
1105 * when in reset process, it means that hardware had been reseted
1106 * successfully and we need to restore the hardware configuration to
1107 * ensure that the hardware configuration remains unchanged before and
1110 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1111 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1112 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1115 ret = hns3_vlan_filter_init(hns);
1117 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1121 ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER,
1122 RTE_ETHER_TYPE_VLAN);
1124 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1129 * When in the reinit dev stage of the reset process, the following
1130 * vlan-related configurations may differ from those at initialization,
1131 * we will restore configurations to hardware in hns3_restore_vlan_table
1132 * and hns3_restore_vlan_conf later.
1134 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1135 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1137 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1141 ret = hns3_en_hw_strip_rxvtag(hns, false);
1143 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1149 return hns3_default_vlan_config(hns);
1153 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1155 struct hns3_pf *pf = &hns->pf;
1156 struct hns3_hw *hw = &hns->hw;
1161 if (!hw->data->promiscuous) {
1162 /* restore vlan filter states */
1163 offloads = hw->data->dev_conf.rxmode.offloads;
1164 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false;
1165 ret = hns3_enable_vlan_filter(hns, enable);
1167 hns3_err(hw, "failed to restore vlan rx filter conf, "
1173 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1175 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1179 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1181 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1187 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1189 struct hns3_adapter *hns = dev->data->dev_private;
1190 struct rte_eth_dev_data *data = dev->data;
1191 struct rte_eth_txmode *txmode;
1192 struct hns3_hw *hw = &hns->hw;
1196 txmode = &data->dev_conf.txmode;
1197 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1199 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1200 "configuration is not supported! Ignore these two "
1201 "parameters: hw_vlan_reject_tagged(%u), "
1202 "hw_vlan_reject_untagged(%u)",
1203 txmode->hw_vlan_reject_tagged,
1204 txmode->hw_vlan_reject_untagged);
1206 /* Apply vlan offload setting */
1207 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;
1208 ret = hns3_vlan_offload_set(dev, mask);
1210 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1216 * If pvid config is not set in rte_eth_conf, driver needn't to set
1217 * VLAN pvid related configuration to hardware.
1219 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1222 /* Apply pvid setting */
1223 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1224 txmode->hw_vlan_insert_pvid);
1226 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1233 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1234 unsigned int tso_mss_max)
1236 struct hns3_cfg_tso_status_cmd *req;
1237 struct hns3_cmd_desc desc;
1240 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1242 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1245 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1247 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1250 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1252 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1254 return hns3_cmd_send(hw, &desc, 1);
1258 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1259 uint16_t *allocated_size, bool is_alloc)
1261 struct hns3_umv_spc_alc_cmd *req;
1262 struct hns3_cmd_desc desc;
1265 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1266 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1267 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1268 req->space_size = rte_cpu_to_le_32(space_size);
1270 ret = hns3_cmd_send(hw, &desc, 1);
1272 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1273 is_alloc ? "allocate" : "free", ret);
1277 if (is_alloc && allocated_size)
1278 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1284 hns3_init_umv_space(struct hns3_hw *hw)
1286 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1287 struct hns3_pf *pf = &hns->pf;
1288 uint16_t allocated_size = 0;
1291 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1296 if (allocated_size < pf->wanted_umv_size)
1297 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1298 pf->wanted_umv_size, allocated_size);
1300 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1301 pf->wanted_umv_size;
1302 pf->used_umv_size = 0;
1307 hns3_uninit_umv_space(struct hns3_hw *hw)
1309 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1310 struct hns3_pf *pf = &hns->pf;
1313 if (pf->max_umv_size == 0)
1316 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1320 pf->max_umv_size = 0;
1326 hns3_is_umv_space_full(struct hns3_hw *hw)
1328 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1329 struct hns3_pf *pf = &hns->pf;
1332 is_full = (pf->used_umv_size >= pf->max_umv_size);
1338 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1340 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1341 struct hns3_pf *pf = &hns->pf;
1344 if (pf->used_umv_size > 0)
1345 pf->used_umv_size--;
1347 pf->used_umv_size++;
1351 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1352 const uint8_t *addr, bool is_mc)
1354 const unsigned char *mac_addr = addr;
1355 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1356 ((uint32_t)mac_addr[2] << 16) |
1357 ((uint32_t)mac_addr[1] << 8) |
1358 (uint32_t)mac_addr[0];
1359 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1361 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1363 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1364 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1365 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1368 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1369 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1373 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1375 enum hns3_mac_vlan_tbl_opcode op)
1378 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1383 if (op == HNS3_MAC_VLAN_ADD) {
1384 if (resp_code == 0 || resp_code == 1) {
1386 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1387 hns3_err(hw, "add mac addr failed for uc_overflow");
1389 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1390 hns3_err(hw, "add mac addr failed for mc_overflow");
1394 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1397 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1398 if (resp_code == 0) {
1400 } else if (resp_code == 1) {
1401 hns3_dbg(hw, "remove mac addr failed for miss");
1405 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1408 } else if (op == HNS3_MAC_VLAN_LKUP) {
1409 if (resp_code == 0) {
1411 } else if (resp_code == 1) {
1412 hns3_dbg(hw, "lookup mac addr failed for miss");
1416 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1421 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1428 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1429 struct hns3_mac_vlan_tbl_entry_cmd *req,
1430 struct hns3_cmd_desc *desc, uint8_t desc_num)
1437 if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) {
1438 for (i = 0; i < desc_num - 1; i++) {
1439 hns3_cmd_setup_basic_desc(&desc[i],
1440 HNS3_OPC_MAC_VLAN_ADD, true);
1441 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1443 memcpy(desc[i].data, req,
1444 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1446 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD,
1449 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD,
1451 memcpy(desc[0].data, req,
1452 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1454 ret = hns3_cmd_send(hw, desc, desc_num);
1456 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1460 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1461 retval = rte_le_to_cpu_16(desc[0].retval);
1463 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1464 HNS3_MAC_VLAN_LKUP);
1468 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1469 struct hns3_mac_vlan_tbl_entry_cmd *req,
1470 struct hns3_cmd_desc *desc, uint8_t desc_num)
1478 if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) {
1479 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480 memcpy(desc->data, req,
1481 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482 ret = hns3_cmd_send(hw, desc, desc_num);
1483 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff;
1484 retval = rte_le_to_cpu_16(desc->retval);
1486 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1489 for (i = 0; i < desc_num; i++) {
1490 hns3_cmd_reuse_desc(&desc[i], false);
1491 if (i == desc_num - 1)
1493 rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1496 rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1498 memcpy(desc[0].data, req,
1499 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1501 ret = hns3_cmd_send(hw, desc, desc_num);
1502 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1503 retval = rte_le_to_cpu_16(desc[0].retval);
1505 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1510 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1518 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1519 struct hns3_mac_vlan_tbl_entry_cmd *req)
1521 struct hns3_cmd_desc desc;
1526 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1528 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1530 ret = hns3_cmd_send(hw, &desc, 1);
1532 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1535 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1536 retval = rte_le_to_cpu_16(desc.retval);
1538 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1539 HNS3_MAC_VLAN_REMOVE);
1543 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1545 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1546 struct hns3_mac_vlan_tbl_entry_cmd req;
1547 struct hns3_pf *pf = &hns->pf;
1548 struct hns3_cmd_desc desc;
1549 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1550 uint16_t egress_port = 0;
1554 /* check if mac addr is valid */
1555 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1556 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1558 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1563 memset(&req, 0, sizeof(req));
1566 * In current version VF is not supported when PF is driven by DPDK
1567 * driver, just need to configure parameters for PF vport.
1569 vf_id = HNS3_PF_FUNC_ID;
1570 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1571 HNS3_MAC_EPORT_VFID_S, vf_id);
1573 req.egress_port = rte_cpu_to_le_16(egress_port);
1575 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1578 * Lookup the mac address in the mac_vlan table, and add
1579 * it if the entry is inexistent. Repeated unicast entry
1580 * is not allowed in the mac vlan table.
1582 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc,
1583 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1584 if (ret == -ENOENT) {
1585 if (!hns3_is_umv_space_full(hw)) {
1586 ret = hns3_add_mac_vlan_tbl(hw, &req, &desc,
1587 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1589 hns3_update_umv_space(hw, false);
1593 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1598 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1600 /* check if we just hit the duplicate */
1602 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1606 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1613 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1615 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1616 struct rte_ether_addr *addr;
1620 for (i = 0; i < hw->mc_addrs_num; i++) {
1621 addr = &hw->mc_addrs[i];
1622 /* Check if there are duplicate addresses */
1623 if (rte_is_same_ether_addr(addr, mac_addr)) {
1624 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1626 hns3_err(hw, "failed to add mc mac addr, same addrs"
1627 "(%s) is added by the set_mc_mac_addr_list "
1633 ret = hns3_add_mc_mac_addr(hw, mac_addr);
1635 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1637 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1644 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1646 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1649 ret = hns3_remove_mc_mac_addr(hw, mac_addr);
1651 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1653 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1660 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1661 __rte_unused uint32_t idx, __rte_unused uint32_t pool)
1663 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1667 rte_spinlock_lock(&hw->lock);
1670 * In hns3 network engine adding UC and MC mac address with different
1671 * commands with firmware. We need to determine whether the input
1672 * address is a UC or a MC address to call different commands.
1673 * By the way, it is recommended calling the API function named
1674 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1675 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1676 * may affect the specifications of UC mac addresses.
1678 if (rte_is_multicast_ether_addr(mac_addr))
1679 ret = hns3_add_mc_addr_common(hw, mac_addr);
1681 ret = hns3_add_uc_mac_addr(hw, mac_addr);
1684 rte_spinlock_unlock(&hw->lock);
1685 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1687 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1692 rte_spinlock_unlock(&hw->lock);
1698 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1700 struct hns3_mac_vlan_tbl_entry_cmd req;
1701 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1704 /* check if mac addr is valid */
1705 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1706 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1708 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1713 memset(&req, 0, sizeof(req));
1714 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1715 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1716 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1717 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1720 hns3_update_umv_space(hw, true);
1726 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1728 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729 /* index will be checked by upper level rte interface */
1730 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1731 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1734 rte_spinlock_lock(&hw->lock);
1736 if (rte_is_multicast_ether_addr(mac_addr))
1737 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1739 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1740 rte_spinlock_unlock(&hw->lock);
1742 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1744 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1750 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1751 struct rte_ether_addr *mac_addr)
1753 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754 struct rte_ether_addr *oaddr;
1755 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1758 rte_spinlock_lock(&hw->lock);
1759 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1760 ret = hns3_remove_uc_addr_common(hw, oaddr);
1762 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1764 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1767 rte_spinlock_unlock(&hw->lock);
1771 ret = hns3_add_uc_mac_addr(hw, mac_addr);
1773 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1775 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1776 goto err_add_uc_addr;
1779 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1781 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1782 goto err_pause_addr_cfg;
1785 rte_ether_addr_copy(mac_addr,
1786 (struct rte_ether_addr *)hw->mac.mac_addr);
1787 rte_spinlock_unlock(&hw->lock);
1792 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1794 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1797 "Failed to roll back to del setted mac addr(%s): %d",
1802 ret_val = hns3_add_uc_mac_addr(hw, oaddr);
1804 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1805 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1808 rte_spinlock_unlock(&hw->lock);
1814 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1816 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1817 struct hns3_hw *hw = &hns->hw;
1818 struct rte_ether_addr *addr;
1823 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1824 addr = &hw->data->mac_addrs[i];
1825 if (rte_is_zero_ether_addr(addr))
1827 if (rte_is_multicast_ether_addr(addr))
1828 ret = del ? hns3_remove_mc_mac_addr(hw, addr) :
1829 hns3_add_mc_mac_addr(hw, addr);
1831 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1832 hns3_add_uc_mac_addr(hw, addr);
1836 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1838 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1839 "ret = %d.", del ? "remove" : "restore",
1847 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1849 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1853 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1854 word_num = vfid / 32;
1855 bit_num = vfid % 32;
1857 desc[1].data[word_num] &=
1858 rte_cpu_to_le_32(~(1UL << bit_num));
1860 desc[1].data[word_num] |=
1861 rte_cpu_to_le_32(1UL << bit_num);
1863 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1864 bit_num = vfid % 32;
1866 desc[2].data[word_num] &=
1867 rte_cpu_to_le_32(~(1UL << bit_num));
1869 desc[2].data[word_num] |=
1870 rte_cpu_to_le_32(1UL << bit_num);
1875 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1877 struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM];
1878 struct hns3_mac_vlan_tbl_entry_cmd req;
1879 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1883 /* Check if mac addr is valid */
1884 if (!rte_is_multicast_ether_addr(mac_addr)) {
1885 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1887 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1892 memset(&req, 0, sizeof(req));
1893 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1894 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1895 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1896 HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1898 /* This mac addr do not exist, add new entry for it */
1899 memset(desc[0].data, 0, sizeof(desc[0].data));
1900 memset(desc[1].data, 0, sizeof(desc[0].data));
1901 memset(desc[2].data, 0, sizeof(desc[0].data));
1905 * In current version VF is not supported when PF is driven by DPDK
1906 * driver, just need to configure parameters for PF vport.
1908 vf_id = HNS3_PF_FUNC_ID;
1909 hns3_update_desc_vfid(desc, vf_id, false);
1910 ret = hns3_add_mac_vlan_tbl(hw, &req, desc,
1911 HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1914 hns3_err(hw, "mc mac vlan table is full");
1915 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1917 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1924 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1926 struct hns3_mac_vlan_tbl_entry_cmd req;
1927 struct hns3_cmd_desc desc[3];
1928 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1932 /* Check if mac addr is valid */
1933 if (!rte_is_multicast_ether_addr(mac_addr)) {
1934 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1936 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1941 memset(&req, 0, sizeof(req));
1942 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1943 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1944 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1945 HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1948 * This mac addr exist, remove this handle's VFID for it.
1949 * In current version VF is not supported when PF is driven by
1950 * DPDK driver, just need to configure parameters for PF vport.
1952 vf_id = HNS3_PF_FUNC_ID;
1953 hns3_update_desc_vfid(desc, vf_id, true);
1955 /* All the vfid is zero, so need to delete this entry */
1956 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1957 } else if (ret == -ENOENT) {
1958 /* This mac addr doesn't exist. */
1963 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1965 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1972 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1973 struct rte_ether_addr *mc_addr_set,
1974 uint32_t nb_mc_addr)
1976 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1977 struct rte_ether_addr *addr;
1981 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1982 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1983 "invalid. valid range: 0~%d",
1984 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1988 /* Check if input mac addresses are valid */
1989 for (i = 0; i < nb_mc_addr; i++) {
1990 addr = &mc_addr_set[i];
1991 if (!rte_is_multicast_ether_addr(addr)) {
1992 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1995 "failed to set mc mac addr, addr(%s) invalid.",
2000 /* Check if there are duplicate addresses */
2001 for (j = i + 1; j < nb_mc_addr; j++) {
2002 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2003 hns3_ether_format_addr(mac_str,
2004 RTE_ETHER_ADDR_FMT_SIZE,
2006 hns3_err(hw, "failed to set mc mac addr, "
2007 "addrs invalid. two same addrs(%s).",
2014 * Check if there are duplicate addresses between mac_addrs
2017 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2018 if (rte_is_same_ether_addr(addr,
2019 &hw->data->mac_addrs[j])) {
2020 hns3_ether_format_addr(mac_str,
2021 RTE_ETHER_ADDR_FMT_SIZE,
2023 hns3_err(hw, "failed to set mc mac addr, "
2024 "addrs invalid. addrs(%s) has already "
2025 "configured in mac_addr add API",
2036 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2037 struct rte_ether_addr *mc_addr_set,
2039 struct rte_ether_addr *reserved_addr_list,
2040 int *reserved_addr_num,
2041 struct rte_ether_addr *add_addr_list,
2043 struct rte_ether_addr *rm_addr_list,
2046 struct rte_ether_addr *addr;
2047 int current_addr_num;
2048 int reserved_num = 0;
2056 /* Calculate the mc mac address list that should be removed */
2057 current_addr_num = hw->mc_addrs_num;
2058 for (i = 0; i < current_addr_num; i++) {
2059 addr = &hw->mc_addrs[i];
2061 for (j = 0; j < mc_addr_num; j++) {
2062 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2069 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2072 rte_ether_addr_copy(addr,
2073 &reserved_addr_list[reserved_num]);
2078 /* Calculate the mc mac address list that should be added */
2079 for (i = 0; i < mc_addr_num; i++) {
2080 addr = &mc_addr_set[i];
2082 for (j = 0; j < current_addr_num; j++) {
2083 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2090 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2095 /* Reorder the mc mac address list maintained by driver */
2096 for (i = 0; i < reserved_num; i++)
2097 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2099 for (i = 0; i < rm_num; i++) {
2100 num = reserved_num + i;
2101 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2104 *reserved_addr_num = reserved_num;
2105 *add_addr_num = add_num;
2106 *rm_addr_num = rm_num;
2110 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2111 struct rte_ether_addr *mc_addr_set,
2112 uint32_t nb_mc_addr)
2114 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2116 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2117 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2118 struct rte_ether_addr *addr;
2119 int reserved_addr_num;
2127 /* Check if input parameters are valid */
2128 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2132 rte_spinlock_lock(&hw->lock);
2135 * Calculate the mc mac address lists those should be removed and be
2136 * added, Reorder the mc mac address list maintained by driver.
2138 mc_addr_num = (int)nb_mc_addr;
2139 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2140 reserved_addr_list, &reserved_addr_num,
2141 add_addr_list, &add_addr_num,
2142 rm_addr_list, &rm_addr_num);
2144 /* Remove mc mac addresses */
2145 for (i = 0; i < rm_addr_num; i++) {
2146 num = rm_addr_num - i - 1;
2147 addr = &rm_addr_list[num];
2148 ret = hns3_remove_mc_mac_addr(hw, addr);
2150 rte_spinlock_unlock(&hw->lock);
2156 /* Add mc mac addresses */
2157 for (i = 0; i < add_addr_num; i++) {
2158 addr = &add_addr_list[i];
2159 ret = hns3_add_mc_mac_addr(hw, addr);
2161 rte_spinlock_unlock(&hw->lock);
2165 num = reserved_addr_num + i;
2166 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2169 rte_spinlock_unlock(&hw->lock);
2175 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2177 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2178 struct hns3_hw *hw = &hns->hw;
2179 struct rte_ether_addr *addr;
2184 for (i = 0; i < hw->mc_addrs_num; i++) {
2185 addr = &hw->mc_addrs[i];
2186 if (!rte_is_multicast_ether_addr(addr))
2189 ret = hns3_remove_mc_mac_addr(hw, addr);
2191 ret = hns3_add_mc_mac_addr(hw, addr);
2194 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2196 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2197 del ? "Remove" : "Restore", mac_str, ret);
2204 hns3_check_mq_mode(struct rte_eth_dev *dev)
2206 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2207 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2208 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2209 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2210 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2211 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2216 if ((rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) ||
2217 (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB ||
2218 tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) {
2219 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2220 rx_mq_mode, tx_mq_mode);
2224 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2225 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2226 if (rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2227 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2228 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2229 dcb_rx_conf->nb_tcs, pf->tc_max);
2233 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2234 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2235 hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, "
2236 "nb_tcs(%d) != %d or %d in rx direction.",
2237 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2241 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2242 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2243 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2247 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2248 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2249 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2250 "is not equal to one in tx direction.",
2251 i, dcb_rx_conf->dcb_tc[i]);
2254 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2255 max_tc = dcb_rx_conf->dcb_tc[i];
2258 num_tc = max_tc + 1;
2259 if (num_tc > dcb_rx_conf->nb_tcs) {
2260 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2261 num_tc, dcb_rx_conf->nb_tcs);
2270 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2271 enum hns3_ring_type queue_type, uint16_t queue_id)
2273 struct hns3_cmd_desc desc;
2274 struct hns3_ctrl_vector_chain_cmd *req =
2275 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2276 enum hns3_opcode_type op;
2277 uint16_t tqp_type_and_id = 0;
2282 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2283 hns3_cmd_setup_basic_desc(&desc, op, false);
2284 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2285 HNS3_TQP_INT_ID_L_S);
2286 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2287 HNS3_TQP_INT_ID_H_S);
2289 if (queue_type == HNS3_RING_TYPE_RX)
2290 gl = HNS3_RING_GL_RX;
2292 gl = HNS3_RING_GL_TX;
2296 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2298 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2299 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2301 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2302 req->int_cause_num = 1;
2303 ret = hns3_cmd_send(hw, &desc, 1);
2305 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2306 en ? "Map" : "Unmap", queue_id, vector_id, ret);
2314 hns3_init_ring_with_vector(struct hns3_hw *hw)
2321 * In hns3 network engine, vector 0 is always the misc interrupt of this
2322 * function, vector 1~N can be used respectively for the queues of the
2323 * function. Tx and Rx queues with the same number share the interrupt
2324 * vector. In the initialization clearing the all hardware mapping
2325 * relationship configurations between queues and interrupt vectors is
2326 * needed, so some error caused by the residual configurations, such as
2327 * the unexpected Tx interrupt, can be avoid.
2329 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2330 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2331 vec = vec - 1; /* the last interrupt is reserved */
2332 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2333 for (i = 0; i < hw->intr_tqps_num; i++) {
2335 * Set gap limiter/rate limiter/quanity limiter algorithm
2336 * configuration for interrupt coalesce of queue's interrupt.
2338 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2339 HNS3_TQP_INTR_GL_DEFAULT);
2340 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2341 HNS3_TQP_INTR_GL_DEFAULT);
2342 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2344 * QL(quantity limiter) is not used currently, just set 0 to
2347 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2349 ret = hns3_bind_ring_with_vector(hw, vec, false,
2350 HNS3_RING_TYPE_TX, i);
2352 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2353 "vector: %u, ret=%d", i, vec, ret);
2357 ret = hns3_bind_ring_with_vector(hw, vec, false,
2358 HNS3_RING_TYPE_RX, i);
2360 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2361 "vector: %u, ret=%d", i, vec, ret);
2370 hns3_setup_dcb(struct rte_eth_dev *dev)
2372 struct hns3_adapter *hns = dev->data->dev_private;
2373 struct hns3_hw *hw = &hns->hw;
2376 if (!hns3_dev_get_support(hw, DCB)) {
2377 hns3_err(hw, "this port does not support dcb configurations.");
2381 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2382 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2386 ret = hns3_dcb_configure(hns);
2388 hns3_err(hw, "failed to config dcb: %d", ret);
2394 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2399 * Some hardware doesn't support auto-negotiation, but users may not
2400 * configure link_speeds (default 0), which means auto-negotiation.
2401 * In this case, it should return success.
2403 if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG &&
2404 hw->mac.support_autoneg == 0)
2407 if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) {
2408 ret = hns3_check_port_speed(hw, link_speeds);
2417 hns3_check_dev_conf(struct rte_eth_dev *dev)
2419 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2420 struct rte_eth_conf *conf = &dev->data->dev_conf;
2423 ret = hns3_check_mq_mode(dev);
2427 return hns3_check_link_speed(hw, conf->link_speeds);
2431 hns3_dev_configure(struct rte_eth_dev *dev)
2433 struct hns3_adapter *hns = dev->data->dev_private;
2434 struct rte_eth_conf *conf = &dev->data->dev_conf;
2435 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2436 struct hns3_hw *hw = &hns->hw;
2437 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2438 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2439 struct rte_eth_rss_conf rss_conf;
2443 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2446 * Some versions of hardware network engine does not support
2447 * individually enable/disable/reset the Tx or Rx queue. These devices
2448 * must enable/disable/reset Tx and Rx queues at the same time. When the
2449 * numbers of Tx queues allocated by upper applications are not equal to
2450 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2451 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2452 * work as usual. But these fake queues are imperceptible, and can not
2453 * be used by upper applications.
2455 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2457 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2458 hw->cfg_max_queues = 0;
2462 hw->adapter_state = HNS3_NIC_CONFIGURING;
2463 ret = hns3_check_dev_conf(dev);
2467 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2468 ret = hns3_setup_dcb(dev);
2473 /* When RSS is not configured, redirect the packet queue 0 */
2474 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2475 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2476 rss_conf = conf->rx_adv_conf.rss_conf;
2477 hw->rss_dis_flag = false;
2478 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2483 ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu);
2487 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2491 ret = hns3_dev_configure_vlan(dev);
2495 /* config hardware GRO */
2496 gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
2497 ret = hns3_config_gro(hw, gro_en);
2501 hns3_init_rx_ptype_tble(dev);
2502 hw->adapter_state = HNS3_NIC_CONFIGURED;
2507 hw->cfg_max_queues = 0;
2508 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2509 hw->adapter_state = HNS3_NIC_INITIALIZED;
2515 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2517 struct hns3_config_max_frm_size_cmd *req;
2518 struct hns3_cmd_desc desc;
2520 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2522 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2523 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2524 req->min_frm_size = RTE_ETHER_MIN_LEN;
2526 return hns3_cmd_send(hw, &desc, 1);
2530 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2532 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2533 uint16_t original_mps = hns->pf.mps;
2537 ret = hns3_set_mac_mtu(hw, mps);
2539 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2544 ret = hns3_buffer_alloc(hw);
2546 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2553 err = hns3_set_mac_mtu(hw, original_mps);
2555 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2558 hns->pf.mps = original_mps;
2564 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2566 struct hns3_adapter *hns = dev->data->dev_private;
2567 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2568 struct hns3_hw *hw = &hns->hw;
2571 if (dev->data->dev_started) {
2572 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2573 "before configuration", dev->data->port_id);
2577 rte_spinlock_lock(&hw->lock);
2578 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2581 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2582 * assign to "uint16_t" type variable.
2584 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2586 rte_spinlock_unlock(&hw->lock);
2587 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2588 dev->data->port_id, mtu, ret);
2592 rte_spinlock_unlock(&hw->lock);
2598 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2600 uint32_t speed_capa = 0;
2602 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2603 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD;
2604 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2605 speed_capa |= RTE_ETH_LINK_SPEED_10M;
2606 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2607 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
2608 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2609 speed_capa |= RTE_ETH_LINK_SPEED_100M;
2610 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2611 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2617 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2619 uint32_t speed_capa = 0;
2621 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2622 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2623 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2624 speed_capa |= RTE_ETH_LINK_SPEED_10G;
2625 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2626 speed_capa |= RTE_ETH_LINK_SPEED_25G;
2627 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2628 speed_capa |= RTE_ETH_LINK_SPEED_40G;
2629 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2630 speed_capa |= RTE_ETH_LINK_SPEED_50G;
2631 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2632 speed_capa |= RTE_ETH_LINK_SPEED_100G;
2633 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2634 speed_capa |= RTE_ETH_LINK_SPEED_200G;
2640 hns3_get_speed_capa(struct hns3_hw *hw)
2642 struct hns3_mac *mac = &hw->mac;
2643 uint32_t speed_capa;
2645 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2647 hns3_get_copper_port_speed_capa(mac->supported_speed);
2650 hns3_get_firber_port_speed_capa(mac->supported_speed);
2652 if (mac->support_autoneg == 0)
2653 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
2659 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2661 struct hns3_adapter *hns = eth_dev->data->dev_private;
2662 struct hns3_hw *hw = &hns->hw;
2663 uint16_t queue_num = hw->tqps_num;
2666 * In interrupt mode, 'max_rx_queues' is set based on the number of
2667 * MSI-X interrupt resources of the hardware.
2669 if (hw->data->dev_conf.intr_conf.rxq == 1)
2670 queue_num = hw->intr_tqps_num;
2672 info->max_rx_queues = queue_num;
2673 info->max_tx_queues = hw->tqps_num;
2674 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2675 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2676 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2677 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2678 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2679 info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
2680 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
2681 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
2682 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
2683 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2684 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
2685 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
2686 RTE_ETH_RX_OFFLOAD_SCATTER |
2687 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
2688 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
2689 RTE_ETH_RX_OFFLOAD_RSS_HASH |
2690 RTE_ETH_RX_OFFLOAD_TCP_LRO);
2691 info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2692 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
2693 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
2694 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
2695 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
2696 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
2697 RTE_ETH_TX_OFFLOAD_TCP_TSO |
2698 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
2699 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
2700 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
2701 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
2702 hns3_txvlan_cap_get(hw));
2704 if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
2705 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
2707 if (hns3_dev_get_support(hw, INDEP_TXRX))
2708 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2709 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2711 if (hns3_dev_get_support(hw, PTP))
2712 info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
2714 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2715 .nb_max = HNS3_MAX_RING_DESC,
2716 .nb_min = HNS3_MIN_RING_DESC,
2717 .nb_align = HNS3_ALIGN_RING_DESC,
2720 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2721 .nb_max = HNS3_MAX_RING_DESC,
2722 .nb_min = HNS3_MIN_RING_DESC,
2723 .nb_align = HNS3_ALIGN_RING_DESC,
2724 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2725 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2728 info->speed_capa = hns3_get_speed_capa(hw);
2729 info->default_rxconf = (struct rte_eth_rxconf) {
2730 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2732 * If there are no available Rx buffer descriptors, incoming
2733 * packets are always dropped by hardware based on hns3 network
2739 info->default_txconf = (struct rte_eth_txconf) {
2740 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2744 info->reta_size = hw->rss_ind_tbl_size;
2745 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2746 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2748 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2749 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2750 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2751 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2752 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2753 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2759 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2762 struct hns3_adapter *hns = eth_dev->data->dev_private;
2763 struct hns3_hw *hw = &hns->hw;
2764 uint32_t version = hw->fw_version;
2767 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2768 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2769 HNS3_FW_VERSION_BYTE3_S),
2770 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2771 HNS3_FW_VERSION_BYTE2_S),
2772 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2773 HNS3_FW_VERSION_BYTE1_S),
2774 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2775 HNS3_FW_VERSION_BYTE0_S));
2779 ret += 1; /* add the size of '\0' */
2780 if (fw_size < (size_t)ret)
2787 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2789 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2792 (void)hns3_update_link_status(hw);
2794 ret = hns3_update_link_info(eth_dev);
2796 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2802 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2803 struct rte_eth_link *new_link)
2805 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2806 struct hns3_mac *mac = &hw->mac;
2808 switch (mac->link_speed) {
2809 case RTE_ETH_SPEED_NUM_10M:
2810 case RTE_ETH_SPEED_NUM_100M:
2811 case RTE_ETH_SPEED_NUM_1G:
2812 case RTE_ETH_SPEED_NUM_10G:
2813 case RTE_ETH_SPEED_NUM_25G:
2814 case RTE_ETH_SPEED_NUM_40G:
2815 case RTE_ETH_SPEED_NUM_50G:
2816 case RTE_ETH_SPEED_NUM_100G:
2817 case RTE_ETH_SPEED_NUM_200G:
2818 if (mac->link_status)
2819 new_link->link_speed = mac->link_speed;
2822 if (mac->link_status)
2823 new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2827 if (!mac->link_status)
2828 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2830 new_link->link_duplex = mac->link_duplex;
2831 new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2832 new_link->link_autoneg = mac->link_autoneg;
2836 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2838 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */
2839 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */
2841 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2842 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2843 struct hns3_mac *mac = &hw->mac;
2844 struct rte_eth_link new_link;
2847 /* When port is stopped, report link down. */
2848 if (eth_dev->data->dev_started == 0) {
2849 new_link.link_autoneg = mac->link_autoneg;
2850 new_link.link_duplex = mac->link_duplex;
2851 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2852 new_link.link_status = RTE_ETH_LINK_DOWN;
2857 ret = hns3_update_port_link_info(eth_dev);
2859 hns3_err(hw, "failed to get port link info, ret = %d.",
2864 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP)
2867 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2868 } while (retry_cnt--);
2870 memset(&new_link, 0, sizeof(new_link));
2871 hns3_setup_linkstatus(eth_dev, &new_link);
2874 return rte_eth_linkstatus_set(eth_dev, &new_link);
2878 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2880 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884 * The "tx_pkt_burst" will be restored. But the secondary process does
2885 * not support the mechanism for notifying the primary process.
2887 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2888 hns3_err(hw, "secondary process does not support to set link up.");
2893 * If device isn't started Rx/Tx function is still disabled, setting
2894 * link up is not allowed. But it is probably better to return success
2895 * to reduce the impact on the upper layer.
2897 if (hw->adapter_state != HNS3_NIC_STARTED) {
2898 hns3_info(hw, "device isn't started, can't set link up.");
2902 if (!hw->set_link_down)
2905 rte_spinlock_lock(&hw->lock);
2906 ret = hns3_cfg_mac_mode(hw, true);
2908 rte_spinlock_unlock(&hw->lock);
2909 hns3_err(hw, "failed to set link up, ret = %d", ret);
2913 hw->set_link_down = false;
2914 hns3_start_tx_datapath(dev);
2915 rte_spinlock_unlock(&hw->lock);
2921 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2923 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927 * The "tx_pkt_burst" will be set to dummy function. But the secondary
2928 * process does not support the mechanism for notifying the primary
2931 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2932 hns3_err(hw, "secondary process does not support to set link down.");
2937 * If device isn't started or the API has been called, link status is
2938 * down, return success.
2940 if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2943 rte_spinlock_lock(&hw->lock);
2944 hns3_stop_tx_datapath(dev);
2945 ret = hns3_cfg_mac_mode(hw, false);
2947 hns3_start_tx_datapath(dev);
2948 rte_spinlock_unlock(&hw->lock);
2949 hns3_err(hw, "failed to set link down, ret = %d", ret);
2953 hw->set_link_down = true;
2954 rte_spinlock_unlock(&hw->lock);
2960 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2962 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2963 struct hns3_pf *pf = &hns->pf;
2965 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2968 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2974 hns3_query_function_status(struct hns3_hw *hw)
2976 #define HNS3_QUERY_MAX_CNT 10
2977 #define HNS3_QUERY_SLEEP_MSCOEND 1
2978 struct hns3_func_status_cmd *req;
2979 struct hns3_cmd_desc desc;
2983 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2984 req = (struct hns3_func_status_cmd *)desc.data;
2987 ret = hns3_cmd_send(hw, &desc, 1);
2989 PMD_INIT_LOG(ERR, "query function status failed %d",
2994 /* Check pf reset is done */
2998 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2999 } while (timeout++ < HNS3_QUERY_MAX_CNT);
3001 return hns3_parse_func_status(hw, req);
3005 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
3007 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3008 struct hns3_pf *pf = &hns->pf;
3010 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
3012 * The total_tqps_num obtained from firmware is maximum tqp
3013 * numbers of this port, which should be used for PF and VFs.
3014 * There is no need for pf to have so many tqp numbers in
3015 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3016 * coming from config file, is assigned to maximum queue number
3017 * for the PF of this port by user. So users can modify the
3018 * maximum queue number of PF according to their own application
3019 * scenarios, which is more flexible to use. In addition, many
3020 * memories can be saved due to allocating queue statistics
3021 * room according to the actual number of queues required. The
3022 * maximum queue number of PF for network engine with
3023 * revision_id greater than 0x30 is assigned by config file.
3025 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
3026 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
3027 "must be greater than 0.",
3028 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
3032 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3033 hw->total_tqps_num);
3036 * Due to the limitation on the number of PF interrupts
3037 * available, the maximum queue number assigned to PF on
3038 * the network engine with revision_id 0x21 is 64.
3040 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3041 HNS3_MAX_TQP_NUM_HIP08_PF);
3048 hns3_query_pf_resource(struct hns3_hw *hw)
3050 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3051 struct hns3_pf *pf = &hns->pf;
3052 struct hns3_pf_res_cmd *req;
3053 struct hns3_cmd_desc desc;
3056 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3057 ret = hns3_cmd_send(hw, &desc, 1);
3059 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3063 req = (struct hns3_pf_res_cmd *)desc.data;
3064 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3065 rte_le_to_cpu_16(req->ext_tqp_num);
3066 ret = hns3_get_pf_max_tqp_num(hw);
3070 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3071 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3073 if (req->tx_buf_size)
3075 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3077 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3079 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3081 if (req->dv_buf_size)
3083 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3085 pf->dv_buf_size = HNS3_DEFAULT_DV;
3087 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3090 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3091 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3097 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3099 struct hns3_cfg_param_cmd *req;
3100 uint64_t mac_addr_tmp_high;
3101 uint8_t ext_rss_size_max;
3102 uint64_t mac_addr_tmp;
3105 req = (struct hns3_cfg_param_cmd *)desc[0].data;
3107 /* get the configuration */
3108 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3109 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3110 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3111 HNS3_CFG_TQP_DESC_N_M,
3112 HNS3_CFG_TQP_DESC_N_S);
3114 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3115 HNS3_CFG_PHY_ADDR_M,
3116 HNS3_CFG_PHY_ADDR_S);
3117 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3118 HNS3_CFG_MEDIA_TP_M,
3119 HNS3_CFG_MEDIA_TP_S);
3120 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3121 HNS3_CFG_RX_BUF_LEN_M,
3122 HNS3_CFG_RX_BUF_LEN_S);
3123 /* get mac address */
3124 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3125 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3126 HNS3_CFG_MAC_ADDR_H_M,
3127 HNS3_CFG_MAC_ADDR_H_S);
3129 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3131 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3132 HNS3_CFG_DEFAULT_SPEED_M,
3133 HNS3_CFG_DEFAULT_SPEED_S);
3134 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3135 HNS3_CFG_RSS_SIZE_M,
3136 HNS3_CFG_RSS_SIZE_S);
3138 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3139 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3141 req = (struct hns3_cfg_param_cmd *)desc[1].data;
3142 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3144 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3145 HNS3_CFG_SPEED_ABILITY_M,
3146 HNS3_CFG_SPEED_ABILITY_S);
3147 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3148 HNS3_CFG_UMV_TBL_SPACE_M,
3149 HNS3_CFG_UMV_TBL_SPACE_S);
3150 if (!cfg->umv_space)
3151 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3153 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3154 HNS3_CFG_EXT_RSS_SIZE_M,
3155 HNS3_CFG_EXT_RSS_SIZE_S);
3157 * Field ext_rss_size_max obtained from firmware will be more flexible
3158 * for future changes and expansions, which is an exponent of 2, instead
3159 * of reading out directly. If this field is not zero, hns3 PF PMD
3160 * driver uses it as rss_size_max under one TC. Device, whose revision
3161 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3162 * maximum number of queues supported under a TC through this field.
3164 if (ext_rss_size_max)
3165 cfg->rss_size_max = 1U << ext_rss_size_max;
3168 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3169 * @hw: pointer to struct hns3_hw
3170 * @hcfg: the config structure to be getted
3173 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3175 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3176 struct hns3_cfg_param_cmd *req;
3181 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3183 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3184 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3186 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3187 i * HNS3_CFG_RD_LEN_BYTES);
3188 /* Len should be divided by 4 when send to hardware */
3189 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3190 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3191 req->offset = rte_cpu_to_le_32(offset);
3194 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3196 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3200 hns3_parse_cfg(hcfg, desc);
3206 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3208 switch (speed_cmd) {
3209 case HNS3_CFG_SPEED_10M:
3210 *speed = RTE_ETH_SPEED_NUM_10M;
3212 case HNS3_CFG_SPEED_100M:
3213 *speed = RTE_ETH_SPEED_NUM_100M;
3215 case HNS3_CFG_SPEED_1G:
3216 *speed = RTE_ETH_SPEED_NUM_1G;
3218 case HNS3_CFG_SPEED_10G:
3219 *speed = RTE_ETH_SPEED_NUM_10G;
3221 case HNS3_CFG_SPEED_25G:
3222 *speed = RTE_ETH_SPEED_NUM_25G;
3224 case HNS3_CFG_SPEED_40G:
3225 *speed = RTE_ETH_SPEED_NUM_40G;
3227 case HNS3_CFG_SPEED_50G:
3228 *speed = RTE_ETH_SPEED_NUM_50G;
3230 case HNS3_CFG_SPEED_100G:
3231 *speed = RTE_ETH_SPEED_NUM_100G;
3233 case HNS3_CFG_SPEED_200G:
3234 *speed = RTE_ETH_SPEED_NUM_200G;
3244 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3246 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3247 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3248 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3249 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3250 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3254 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3256 struct hns3_dev_specs_0_cmd *req0;
3258 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3260 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3261 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3262 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3263 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3264 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3268 hns3_check_dev_specifications(struct hns3_hw *hw)
3270 if (hw->rss_ind_tbl_size == 0 ||
3271 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3272 hns3_err(hw, "the size of hash lookup table configured (%u)"
3273 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3274 HNS3_RSS_IND_TBL_SIZE_MAX);
3282 hns3_query_dev_specifications(struct hns3_hw *hw)
3284 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3288 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3289 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3291 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3293 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3295 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3299 hns3_parse_dev_specifications(hw, desc);
3301 return hns3_check_dev_specifications(hw);
3305 hns3_get_capability(struct hns3_hw *hw)
3307 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3308 struct rte_pci_device *pci_dev;
3309 struct hns3_pf *pf = &hns->pf;
3310 struct rte_eth_dev *eth_dev;
3315 eth_dev = &rte_eth_devices[hw->data->port_id];
3316 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3317 device_id = pci_dev->id.device_id;
3319 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3320 device_id == HNS3_DEV_ID_50GE_RDMA ||
3321 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3322 device_id == HNS3_DEV_ID_200G_RDMA)
3323 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3325 /* Get PCI revision id */
3326 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3327 HNS3_PCI_REVISION_ID);
3328 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3329 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3333 hw->revision = revision;
3335 if (revision < PCI_REVISION_ID_HIP09_A) {
3336 hns3_set_default_dev_specifications(hw);
3337 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3338 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3339 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3340 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3341 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3342 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3343 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3344 hw->rss_info.ipv6_sctp_offload_supported = false;
3345 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3346 pf->support_multi_tc_pause = false;
3350 ret = hns3_query_dev_specifications(hw);
3353 "failed to query dev specifications, ret = %d",
3358 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3359 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3360 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3361 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3362 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3363 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3364 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3365 hw->rss_info.ipv6_sctp_offload_supported = true;
3366 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3367 pf->support_multi_tc_pause = true;
3373 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3377 switch (media_type) {
3378 case HNS3_MEDIA_TYPE_COPPER:
3379 if (!hns3_dev_get_support(hw, COPPER)) {
3381 "Media type is copper, not supported.");
3387 case HNS3_MEDIA_TYPE_FIBER:
3390 case HNS3_MEDIA_TYPE_BACKPLANE:
3391 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3395 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3404 hns3_get_board_configuration(struct hns3_hw *hw)
3406 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3407 struct hns3_pf *pf = &hns->pf;
3408 struct hns3_cfg cfg;
3411 ret = hns3_get_board_cfg(hw, &cfg);
3413 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3417 ret = hns3_check_media_type(hw, cfg.media_type);
3421 hw->mac.media_type = cfg.media_type;
3422 hw->rss_size_max = cfg.rss_size_max;
3423 hw->rss_dis_flag = false;
3424 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3425 hw->mac.phy_addr = cfg.phy_addr;
3426 hw->num_tx_desc = cfg.tqp_desc_num;
3427 hw->num_rx_desc = cfg.tqp_desc_num;
3428 hw->dcb_info.num_pg = 1;
3429 hw->dcb_info.hw_pfc_map = 0;
3431 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3433 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3434 cfg.default_speed, ret);
3438 pf->tc_max = cfg.tc_num;
3439 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3440 PMD_INIT_LOG(WARNING,
3441 "Get TC num(%u) from flash, set TC num to 1",
3446 /* Dev does not support DCB */
3447 if (!hns3_dev_get_support(hw, DCB)) {
3451 pf->pfc_max = pf->tc_max;
3453 hw->dcb_info.num_tc = 1;
3454 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3455 hw->tqps_num / hw->dcb_info.num_tc);
3456 hns3_set_bit(hw->hw_tc_map, 0, 1);
3457 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3459 pf->wanted_umv_size = cfg.umv_space;
3465 hns3_get_configuration(struct hns3_hw *hw)
3469 ret = hns3_query_function_status(hw);
3471 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3475 /* Get device capability */
3476 ret = hns3_get_capability(hw);
3478 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3482 /* Get pf resource */
3483 ret = hns3_query_pf_resource(hw);
3485 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3489 ret = hns3_get_board_configuration(hw);
3491 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3495 ret = hns3_query_dev_fec_info(hw);
3498 "failed to query FEC information, ret = %d", ret);
3504 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3505 uint16_t tqp_vid, bool is_pf)
3507 struct hns3_tqp_map_cmd *req;
3508 struct hns3_cmd_desc desc;
3511 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3513 req = (struct hns3_tqp_map_cmd *)desc.data;
3514 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3515 req->tqp_vf = func_id;
3516 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3518 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3519 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3521 ret = hns3_cmd_send(hw, &desc, 1);
3523 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3529 hns3_map_tqp(struct hns3_hw *hw)
3535 * In current version, VF is not supported when PF is driven by DPDK
3536 * driver, so we assign total tqps_num tqps allocated to this port
3539 for (i = 0; i < hw->total_tqps_num; i++) {
3540 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3549 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3551 struct hns3_config_mac_speed_dup_cmd *req;
3552 struct hns3_cmd_desc desc;
3555 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3557 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3559 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3562 case RTE_ETH_SPEED_NUM_10M:
3563 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3564 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3566 case RTE_ETH_SPEED_NUM_100M:
3567 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3568 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3570 case RTE_ETH_SPEED_NUM_1G:
3571 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3572 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3574 case RTE_ETH_SPEED_NUM_10G:
3575 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3576 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3578 case RTE_ETH_SPEED_NUM_25G:
3579 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3580 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3582 case RTE_ETH_SPEED_NUM_40G:
3583 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3584 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3586 case RTE_ETH_SPEED_NUM_50G:
3587 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3588 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3590 case RTE_ETH_SPEED_NUM_100G:
3591 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3592 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3594 case RTE_ETH_SPEED_NUM_200G:
3595 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3596 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3599 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3603 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3605 ret = hns3_cmd_send(hw, &desc, 1);
3607 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3613 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3615 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3616 struct hns3_pf *pf = &hns->pf;
3617 struct hns3_priv_buf *priv;
3618 uint32_t i, total_size;
3620 total_size = pf->pkt_buf_size;
3622 /* alloc tx buffer for all enabled tc */
3623 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3624 priv = &buf_alloc->priv_buf[i];
3626 if (hw->hw_tc_map & BIT(i)) {
3627 if (total_size < pf->tx_buf_size)
3630 priv->tx_buf_size = pf->tx_buf_size;
3632 priv->tx_buf_size = 0;
3634 total_size -= priv->tx_buf_size;
3641 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3643 /* TX buffer size is unit by 128 byte */
3644 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3645 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3646 struct hns3_tx_buff_alloc_cmd *req;
3647 struct hns3_cmd_desc desc;
3652 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3654 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3655 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3656 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3658 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3659 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3660 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3663 ret = hns3_cmd_send(hw, &desc, 1);
3665 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3671 hns3_get_tc_num(struct hns3_hw *hw)
3676 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3677 if (hw->hw_tc_map & BIT(i))
3683 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3685 struct hns3_priv_buf *priv;
3686 uint32_t rx_priv = 0;
3689 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3690 priv = &buf_alloc->priv_buf[i];
3692 rx_priv += priv->buf_size;
3698 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3700 uint32_t total_tx_size = 0;
3703 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3704 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3706 return total_tx_size;
3709 /* Get the number of pfc enabled TCs, which have private buffer */
3711 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3713 struct hns3_priv_buf *priv;
3717 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3718 priv = &buf_alloc->priv_buf[i];
3719 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3726 /* Get the number of pfc disabled TCs, which have private buffer */
3728 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3729 struct hns3_pkt_buf_alloc *buf_alloc)
3731 struct hns3_priv_buf *priv;
3735 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3736 priv = &buf_alloc->priv_buf[i];
3737 if (hw->hw_tc_map & BIT(i) &&
3738 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3746 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3749 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3750 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3751 struct hns3_pf *pf = &hns->pf;
3752 uint32_t shared_buf, aligned_mps;
3757 tc_num = hns3_get_tc_num(hw);
3758 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3760 if (hns3_dev_get_support(hw, DCB))
3761 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3764 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3767 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3768 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3769 HNS3_BUF_SIZE_UNIT);
3771 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3772 if (rx_all < rx_priv + shared_std)
3775 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3776 buf_alloc->s_buf.buf_size = shared_buf;
3777 if (hns3_dev_get_support(hw, DCB)) {
3778 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3779 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3780 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3781 HNS3_BUF_SIZE_UNIT);
3783 buf_alloc->s_buf.self.high =
3784 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3785 buf_alloc->s_buf.self.low = aligned_mps;
3788 if (hns3_dev_get_support(hw, DCB)) {
3789 hi_thrd = shared_buf - pf->dv_buf_size;
3791 if (tc_num <= NEED_RESERVE_TC_NUM)
3792 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3796 hi_thrd = hi_thrd / tc_num;
3798 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3799 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3800 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3802 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3803 lo_thrd = aligned_mps;
3806 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3807 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3808 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3815 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3816 struct hns3_pkt_buf_alloc *buf_alloc)
3818 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3819 struct hns3_pf *pf = &hns->pf;
3820 struct hns3_priv_buf *priv;
3821 uint32_t aligned_mps;
3825 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3826 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3828 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3829 priv = &buf_alloc->priv_buf[i];
3836 if (!(hw->hw_tc_map & BIT(i)))
3840 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3841 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3842 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3843 HNS3_BUF_SIZE_UNIT);
3846 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3850 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3853 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3857 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3858 struct hns3_pkt_buf_alloc *buf_alloc)
3860 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3861 struct hns3_pf *pf = &hns->pf;
3862 struct hns3_priv_buf *priv;
3863 int no_pfc_priv_num;
3868 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3869 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3871 /* let the last to be cleared first */
3872 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3873 priv = &buf_alloc->priv_buf[i];
3874 mask = BIT((uint8_t)i);
3875 if (hw->hw_tc_map & mask &&
3876 !(hw->dcb_info.hw_pfc_map & mask)) {
3877 /* Clear the no pfc TC private buffer */
3885 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3886 no_pfc_priv_num == 0)
3890 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3894 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3895 struct hns3_pkt_buf_alloc *buf_alloc)
3897 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3898 struct hns3_pf *pf = &hns->pf;
3899 struct hns3_priv_buf *priv;
3905 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3906 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3908 /* let the last to be cleared first */
3909 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3910 priv = &buf_alloc->priv_buf[i];
3911 mask = BIT((uint8_t)i);
3912 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3913 /* Reduce the number of pfc TC with private buffer */
3920 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3925 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3929 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3930 struct hns3_pkt_buf_alloc *buf_alloc)
3932 #define COMPENSATE_BUFFER 0x3C00
3933 #define COMPENSATE_HALF_MPS_NUM 5
3934 #define PRIV_WL_GAP 0x1800
3935 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3936 struct hns3_pf *pf = &hns->pf;
3937 uint32_t tc_num = hns3_get_tc_num(hw);
3938 uint32_t half_mps = pf->mps >> 1;
3939 struct hns3_priv_buf *priv;
3940 uint32_t min_rx_priv;
3944 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3946 rx_priv = rx_priv / tc_num;
3948 if (tc_num <= NEED_RESERVE_TC_NUM)
3949 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3952 * Minimum value of private buffer in rx direction (min_rx_priv) is
3953 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3954 * buffer if rx_priv is greater than min_rx_priv.
3956 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3957 COMPENSATE_HALF_MPS_NUM * half_mps;
3958 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3959 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3960 if (rx_priv < min_rx_priv)
3963 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3964 priv = &buf_alloc->priv_buf[i];
3970 if (!(hw->hw_tc_map & BIT(i)))
3974 priv->buf_size = rx_priv;
3975 priv->wl.high = rx_priv - pf->dv_buf_size;
3976 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3979 buf_alloc->s_buf.buf_size = 0;
3985 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3986 * @hw: pointer to struct hns3_hw
3987 * @buf_alloc: pointer to buffer calculation data
3988 * @return: 0: calculate sucessful, negative: fail
3991 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3993 /* When DCB is not supported, rx private buffer is not allocated. */
3994 if (!hns3_dev_get_support(hw, DCB)) {
3995 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3996 struct hns3_pf *pf = &hns->pf;
3997 uint32_t rx_all = pf->pkt_buf_size;
3999 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
4000 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
4007 * Try to allocate privated packet buffer for all TCs without share
4010 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
4014 * Try to allocate privated packet buffer for all TCs with share
4017 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
4021 * For different application scenes, the enabled port number, TC number
4022 * and no_drop TC number are different. In order to obtain the better
4023 * performance, software could allocate the buffer size and configure
4024 * the waterline by trying to decrease the private buffer size according
4025 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
4028 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4031 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4034 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4041 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4043 struct hns3_rx_priv_buff_cmd *req;
4044 struct hns3_cmd_desc desc;
4049 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4050 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4052 /* Alloc private buffer TCs */
4053 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4054 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4057 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4058 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4061 buf_size = buf_alloc->s_buf.buf_size;
4062 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4063 (1 << HNS3_TC0_PRI_BUF_EN_B));
4065 ret = hns3_cmd_send(hw, &desc, 1);
4067 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4073 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4075 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4076 struct hns3_rx_priv_wl_buf *req;
4077 struct hns3_priv_buf *priv;
4078 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4082 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4083 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4085 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4087 /* The first descriptor set the NEXT bit to 1 */
4089 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4091 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4093 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4094 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4096 priv = &buf_alloc->priv_buf[idx];
4097 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4099 req->tc_wl[j].high |=
4100 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4101 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4103 req->tc_wl[j].low |=
4104 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4108 /* Send 2 descriptor at one time */
4109 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4111 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4117 hns3_common_thrd_config(struct hns3_hw *hw,
4118 struct hns3_pkt_buf_alloc *buf_alloc)
4120 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4121 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4122 struct hns3_rx_com_thrd *req;
4123 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4124 struct hns3_tc_thrd *tc;
4129 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4130 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4132 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4134 /* The first descriptor set the NEXT bit to 1 */
4136 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4138 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4140 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4141 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4142 tc = &s_buf->tc_thrd[tc_idx];
4144 req->com_thrd[j].high =
4145 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4146 req->com_thrd[j].high |=
4147 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4148 req->com_thrd[j].low =
4149 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4150 req->com_thrd[j].low |=
4151 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4155 /* Send 2 descriptors at one time */
4156 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4158 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4164 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4166 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4167 struct hns3_rx_com_wl *req;
4168 struct hns3_cmd_desc desc;
4171 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4173 req = (struct hns3_rx_com_wl *)desc.data;
4174 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4175 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4177 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4178 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4180 ret = hns3_cmd_send(hw, &desc, 1);
4182 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4188 hns3_buffer_alloc(struct hns3_hw *hw)
4190 struct hns3_pkt_buf_alloc pkt_buf;
4193 memset(&pkt_buf, 0, sizeof(pkt_buf));
4194 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4197 "could not calc tx buffer size for all TCs %d",
4202 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4204 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4208 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4211 "could not calc rx priv buffer size for all TCs %d",
4216 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4218 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4222 if (hns3_dev_get_support(hw, DCB)) {
4223 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4226 "could not configure rx private waterline %d",
4231 ret = hns3_common_thrd_config(hw, &pkt_buf);
4234 "could not configure common threshold %d",
4240 ret = hns3_common_wl_config(hw, &pkt_buf);
4242 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4249 hns3_mac_init(struct hns3_hw *hw)
4251 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4252 struct hns3_mac *mac = &hw->mac;
4253 struct hns3_pf *pf = &hns->pf;
4256 pf->support_sfp_query = true;
4257 mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
4258 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4260 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4264 mac->link_status = RTE_ETH_LINK_DOWN;
4266 return hns3_config_mtu(hw, pf->mps);
4270 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4272 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4273 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4274 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4275 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4280 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4285 switch (resp_code) {
4286 case HNS3_ETHERTYPE_SUCCESS_ADD:
4287 case HNS3_ETHERTYPE_ALREADY_ADD:
4290 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4292 "add mac ethertype failed for manager table overflow.");
4293 return_status = -EIO;
4295 case HNS3_ETHERTYPE_KEY_CONFLICT:
4296 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4297 return_status = -EIO;
4301 "add mac ethertype failed for undefined, code=%u.",
4303 return_status = -EIO;
4307 return return_status;
4311 hns3_add_mgr_tbl(struct hns3_hw *hw,
4312 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4314 struct hns3_cmd_desc desc;
4319 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4320 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4322 ret = hns3_cmd_send(hw, &desc, 1);
4325 "add mac ethertype failed for cmd_send, ret =%d.",
4330 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4331 retval = rte_le_to_cpu_16(desc.retval);
4333 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4337 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4338 int *table_item_num)
4340 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4343 * In current version, we add one item in management table as below:
4344 * 0x0180C200000E -- LLDP MC address
4347 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4348 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4349 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4350 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4351 tbl->i_port_bitmap = 0x1;
4352 *table_item_num = 1;
4356 hns3_init_mgr_tbl(struct hns3_hw *hw)
4358 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4359 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4364 memset(mgr_table, 0, sizeof(mgr_table));
4365 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4366 for (i = 0; i < table_item_num; i++) {
4367 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4369 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4379 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4380 bool en_mc, bool en_bc, int vport_id)
4385 memset(param, 0, sizeof(struct hns3_promisc_param));
4387 param->enable = HNS3_PROMISC_EN_UC;
4389 param->enable |= HNS3_PROMISC_EN_MC;
4391 param->enable |= HNS3_PROMISC_EN_BC;
4392 param->vf_id = vport_id;
4396 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4398 struct hns3_promisc_cfg_cmd *req;
4399 struct hns3_cmd_desc desc;
4402 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4404 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4405 req->vf_id = param->vf_id;
4406 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4407 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4409 ret = hns3_cmd_send(hw, &desc, 1);
4411 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4417 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4419 struct hns3_promisc_param param;
4420 bool en_bc_pmc = true;
4424 * In current version VF is not supported when PF is driven by DPDK
4425 * driver, just need to configure parameters for PF vport.
4427 vf_id = HNS3_PF_FUNC_ID;
4429 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4430 return hns3_cmd_set_promisc_mode(hw, ¶m);
4434 hns3_promisc_init(struct hns3_hw *hw)
4436 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4437 struct hns3_pf *pf = &hns->pf;
4438 struct hns3_promisc_param param;
4442 ret = hns3_set_promisc_mode(hw, false, false);
4444 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4449 * In current version VFs are not supported when PF is driven by DPDK
4450 * driver. After PF has been taken over by DPDK, the original VF will
4451 * be invalid. So, there is a possibility of entry residues. It should
4452 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4455 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4456 hns3_promisc_param_init(¶m, false, false, false, func_id);
4457 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4459 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4460 " ret = %d", func_id, ret);
4469 hns3_promisc_uninit(struct hns3_hw *hw)
4471 struct hns3_promisc_param param;
4475 func_id = HNS3_PF_FUNC_ID;
4478 * In current version VFs are not supported when PF is driven by
4479 * DPDK driver, and VFs' promisc mode status has been cleared during
4480 * init and their status will not change. So just clear PF's promisc
4481 * mode status during uninit.
4483 hns3_promisc_param_init(¶m, false, false, false, func_id);
4484 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4486 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4487 " uninit, ret = %d", ret);
4491 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4493 bool allmulti = dev->data->all_multicast ? true : false;
4494 struct hns3_adapter *hns = dev->data->dev_private;
4495 struct hns3_hw *hw = &hns->hw;
4500 rte_spinlock_lock(&hw->lock);
4501 ret = hns3_set_promisc_mode(hw, true, true);
4503 rte_spinlock_unlock(&hw->lock);
4504 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4510 * When promiscuous mode was enabled, disable the vlan filter to let
4511 * all packets coming in in the receiving direction.
4513 offloads = dev->data->dev_conf.rxmode.offloads;
4514 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4515 ret = hns3_enable_vlan_filter(hns, false);
4517 hns3_err(hw, "failed to enable promiscuous mode due to "
4518 "failure to disable vlan filter, ret = %d",
4520 err = hns3_set_promisc_mode(hw, false, allmulti);
4522 hns3_err(hw, "failed to restore promiscuous "
4523 "status after disable vlan filter "
4524 "failed during enabling promiscuous "
4525 "mode, ret = %d", ret);
4529 rte_spinlock_unlock(&hw->lock);
4535 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4537 bool allmulti = dev->data->all_multicast ? true : false;
4538 struct hns3_adapter *hns = dev->data->dev_private;
4539 struct hns3_hw *hw = &hns->hw;
4544 /* If now in all_multicast mode, must remain in all_multicast mode. */
4545 rte_spinlock_lock(&hw->lock);
4546 ret = hns3_set_promisc_mode(hw, false, allmulti);
4548 rte_spinlock_unlock(&hw->lock);
4549 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4553 /* when promiscuous mode was disabled, restore the vlan filter status */
4554 offloads = dev->data->dev_conf.rxmode.offloads;
4555 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4556 ret = hns3_enable_vlan_filter(hns, true);
4558 hns3_err(hw, "failed to disable promiscuous mode due to"
4559 " failure to restore vlan filter, ret = %d",
4561 err = hns3_set_promisc_mode(hw, true, true);
4563 hns3_err(hw, "failed to restore promiscuous "
4564 "status after enabling vlan filter "
4565 "failed during disabling promiscuous "
4566 "mode, ret = %d", ret);
4569 rte_spinlock_unlock(&hw->lock);
4575 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4577 struct hns3_adapter *hns = dev->data->dev_private;
4578 struct hns3_hw *hw = &hns->hw;
4581 if (dev->data->promiscuous)
4584 rte_spinlock_lock(&hw->lock);
4585 ret = hns3_set_promisc_mode(hw, false, true);
4586 rte_spinlock_unlock(&hw->lock);
4588 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4595 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4597 struct hns3_adapter *hns = dev->data->dev_private;
4598 struct hns3_hw *hw = &hns->hw;
4601 /* If now in promiscuous mode, must remain in all_multicast mode. */
4602 if (dev->data->promiscuous)
4605 rte_spinlock_lock(&hw->lock);
4606 ret = hns3_set_promisc_mode(hw, false, false);
4607 rte_spinlock_unlock(&hw->lock);
4609 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4616 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4618 struct hns3_hw *hw = &hns->hw;
4619 bool allmulti = hw->data->all_multicast ? true : false;
4622 if (hw->data->promiscuous) {
4623 ret = hns3_set_promisc_mode(hw, true, true);
4625 hns3_err(hw, "failed to restore promiscuous mode, "
4630 ret = hns3_set_promisc_mode(hw, false, allmulti);
4632 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4638 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4640 struct hns3_sfp_info_cmd *resp;
4641 struct hns3_cmd_desc desc;
4644 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4645 resp = (struct hns3_sfp_info_cmd *)desc.data;
4646 resp->query_type = HNS3_ACTIVE_QUERY;
4648 ret = hns3_cmd_send(hw, &desc, 1);
4649 if (ret == -EOPNOTSUPP) {
4650 hns3_warn(hw, "firmware does not support get SFP info,"
4654 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4659 * In some case, the speed of MAC obtained from firmware may be 0, it
4660 * shouldn't be set to mac->speed.
4662 if (!rte_le_to_cpu_32(resp->sfp_speed))
4665 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4667 * if resp->supported_speed is 0, it means it's an old version
4668 * firmware, do not update these params.
4670 if (resp->supported_speed) {
4671 mac_info->query_type = HNS3_ACTIVE_QUERY;
4672 mac_info->supported_speed =
4673 rte_le_to_cpu_32(resp->supported_speed);
4674 mac_info->support_autoneg = resp->autoneg_ability;
4675 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED
4676 : RTE_ETH_LINK_AUTONEG;
4678 mac_info->query_type = HNS3_DEFAULT_QUERY;
4685 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4687 if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M))
4688 duplex = RTE_ETH_LINK_FULL_DUPLEX;
4694 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4696 struct hns3_mac *mac = &hw->mac;
4699 duplex = hns3_check_speed_dup(duplex, speed);
4700 if (mac->link_speed == speed && mac->link_duplex == duplex)
4703 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4707 ret = hns3_port_shaper_update(hw, speed);
4711 mac->link_speed = speed;
4712 mac->link_duplex = duplex;
4718 hns3_update_fiber_link_info(struct hns3_hw *hw)
4720 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4721 struct hns3_mac *mac = &hw->mac;
4722 struct hns3_mac mac_info;
4725 /* If firmware do not support get SFP/qSFP speed, return directly */
4726 if (!pf->support_sfp_query)
4729 memset(&mac_info, 0, sizeof(struct hns3_mac));
4730 ret = hns3_get_sfp_info(hw, &mac_info);
4731 if (ret == -EOPNOTSUPP) {
4732 pf->support_sfp_query = false;
4737 /* Do nothing if no SFP */
4738 if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE)
4742 * If query_type is HNS3_ACTIVE_QUERY, it is no need
4743 * to reconfigure the speed of MAC. Otherwise, it indicates
4744 * that the current firmware only supports to obtain the
4745 * speed of the SFP, and the speed of MAC needs to reconfigure.
4747 mac->query_type = mac_info.query_type;
4748 if (mac->query_type == HNS3_ACTIVE_QUERY) {
4749 if (mac_info.link_speed != mac->link_speed) {
4750 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4755 mac->link_speed = mac_info.link_speed;
4756 mac->supported_speed = mac_info.supported_speed;
4757 mac->support_autoneg = mac_info.support_autoneg;
4758 mac->link_autoneg = mac_info.link_autoneg;
4763 /* Config full duplex for SFP */
4764 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4765 RTE_ETH_LINK_FULL_DUPLEX);
4769 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4771 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f
4773 struct hns3_phy_params_bd0_cmd *req;
4776 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4777 mac->link_speed = rte_le_to_cpu_32(req->speed);
4778 mac->link_duplex = hns3_get_bit(req->duplex,
4779 HNS3_PHY_DUPLEX_CFG_B);
4780 mac->link_autoneg = hns3_get_bit(req->autoneg,
4781 HNS3_PHY_AUTONEG_CFG_B);
4782 mac->advertising = rte_le_to_cpu_32(req->advertising);
4783 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4784 supported = rte_le_to_cpu_32(req->supported);
4785 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4786 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4790 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4792 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4796 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4797 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4799 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4801 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4803 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4805 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4809 hns3_parse_copper_phy_params(desc, mac);
4815 hns3_update_copper_link_info(struct hns3_hw *hw)
4817 struct hns3_mac *mac = &hw->mac;
4818 struct hns3_mac mac_info;
4821 memset(&mac_info, 0, sizeof(struct hns3_mac));
4822 ret = hns3_get_copper_phy_params(hw, &mac_info);
4826 if (mac_info.link_speed != mac->link_speed) {
4827 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4832 mac->link_speed = mac_info.link_speed;
4833 mac->link_duplex = mac_info.link_duplex;
4834 mac->link_autoneg = mac_info.link_autoneg;
4835 mac->supported_speed = mac_info.supported_speed;
4836 mac->advertising = mac_info.advertising;
4837 mac->lp_advertising = mac_info.lp_advertising;
4838 mac->support_autoneg = mac_info.support_autoneg;
4844 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4846 struct hns3_adapter *hns = eth_dev->data->dev_private;
4847 struct hns3_hw *hw = &hns->hw;
4850 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4851 ret = hns3_update_copper_link_info(hw);
4852 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4853 ret = hns3_update_fiber_link_info(hw);
4859 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4861 struct hns3_config_mac_mode_cmd *req;
4862 struct hns3_cmd_desc desc;
4863 uint32_t loop_en = 0;
4867 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4869 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4872 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4873 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4874 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4875 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4876 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4877 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4878 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4879 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4880 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4881 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4884 * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4885 * when receiving frames. Otherwise, CRC will be stripped.
4887 if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
4888 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4890 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4891 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4892 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4893 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4894 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4896 ret = hns3_cmd_send(hw, &desc, 1);
4898 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4904 hns3_get_mac_link_status(struct hns3_hw *hw)
4906 struct hns3_link_status_cmd *req;
4907 struct hns3_cmd_desc desc;
4911 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4912 ret = hns3_cmd_send(hw, &desc, 1);
4914 hns3_err(hw, "get link status cmd failed %d", ret);
4915 return RTE_ETH_LINK_DOWN;
4918 req = (struct hns3_link_status_cmd *)desc.data;
4919 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4921 return !!link_status;
4925 hns3_update_link_status(struct hns3_hw *hw)
4929 state = hns3_get_mac_link_status(hw);
4930 if (state != hw->mac.link_status) {
4931 hw->mac.link_status = state;
4932 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4940 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4942 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4943 struct rte_eth_link new_link;
4947 hns3_update_port_link_info(dev);
4949 memset(&new_link, 0, sizeof(new_link));
4950 hns3_setup_linkstatus(dev, &new_link);
4952 ret = rte_eth_linkstatus_set(dev, &new_link);
4953 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4954 hns3_start_report_lse(dev);
4958 hns3_service_handler(void *param)
4960 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4961 struct hns3_adapter *hns = eth_dev->data->dev_private;
4962 struct hns3_hw *hw = &hns->hw;
4964 if (!hns3_is_reset_pending(hns))
4965 hns3_update_linkstatus_and_event(hw, true);
4967 hns3_warn(hw, "Cancel the query when reset is pending");
4969 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4973 hns3_init_hardware(struct hns3_adapter *hns)
4975 struct hns3_hw *hw = &hns->hw;
4978 ret = hns3_map_tqp(hw);
4980 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4984 ret = hns3_init_umv_space(hw);
4986 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4990 ret = hns3_mac_init(hw);
4992 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4996 ret = hns3_init_mgr_tbl(hw);
4998 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
5002 ret = hns3_promisc_init(hw);
5004 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
5009 ret = hns3_init_vlan_config(hns);
5011 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
5015 ret = hns3_dcb_init(hw);
5017 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
5021 ret = hns3_init_fd_config(hns);
5023 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
5027 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
5029 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5033 ret = hns3_config_gro(hw, false);
5035 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5040 * In the initialization clearing the all hardware mapping relationship
5041 * configurations between queues and interrupt vectors is needed, so
5042 * some error caused by the residual configurations, such as the
5043 * unexpected interrupt, can be avoid.
5045 ret = hns3_init_ring_with_vector(hw);
5047 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5054 hns3_uninit_umv_space(hw);
5059 hns3_clear_hw(struct hns3_hw *hw)
5061 struct hns3_cmd_desc desc;
5064 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5066 ret = hns3_cmd_send(hw, &desc, 1);
5067 if (ret && ret != -EOPNOTSUPP)
5074 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5079 * The new firmware support report more hardware error types by
5080 * msix mode. These errors are defined as RAS errors in hardware
5081 * and belong to a different type from the MSI-x errors processed
5082 * by the network driver.
5084 * Network driver should open the new error report on initialization.
5086 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5087 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5088 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5092 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5094 struct hns3_mac *mac = &hw->mac;
5096 switch (mac->link_speed) {
5097 case RTE_ETH_SPEED_NUM_1G:
5098 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5099 case RTE_ETH_SPEED_NUM_10G:
5100 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5101 case RTE_ETH_SPEED_NUM_25G:
5102 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5103 case RTE_ETH_SPEED_NUM_40G:
5104 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5105 case RTE_ETH_SPEED_NUM_50G:
5106 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5107 case RTE_ETH_SPEED_NUM_100G:
5108 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5109 case RTE_ETH_SPEED_NUM_200G:
5110 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5112 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5118 * Validity of supported_speed for firber and copper media type can be
5119 * guaranteed by the following policy:
5121 * Although the initialization of the phy in the firmware may not be
5122 * completed, the firmware can guarantees that the supported_speed is
5125 * If the version of firmware supports the acitive query way of the
5126 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5127 * through it. If unsupported, use the SFP's speed as the value of the
5131 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5133 struct hns3_adapter *hns = eth_dev->data->dev_private;
5134 struct hns3_hw *hw = &hns->hw;
5135 struct hns3_mac *mac = &hw->mac;
5138 ret = hns3_update_link_info(eth_dev);
5142 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5144 * Some firmware does not support the report of supported_speed,
5145 * and only report the effective speed of SFP. In this case, it
5146 * is necessary to use the SFP's speed as the supported_speed.
5148 if (mac->supported_speed == 0)
5149 mac->supported_speed =
5150 hns3_set_firber_default_support_speed(hw);
5157 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5159 struct hns3_mac *mac = &hns->hw.mac;
5161 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5162 hns->pf.support_fc_autoneg = true;
5167 * Flow control auto-negotiation requires the cooperation of the driver
5168 * and firmware. Currently, the optical port does not support flow
5169 * control auto-negotiation.
5171 hns->pf.support_fc_autoneg = false;
5175 hns3_init_pf(struct rte_eth_dev *eth_dev)
5177 struct rte_device *dev = eth_dev->device;
5178 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5179 struct hns3_adapter *hns = eth_dev->data->dev_private;
5180 struct hns3_hw *hw = &hns->hw;
5183 PMD_INIT_FUNC_TRACE();
5185 /* Get hardware io base address from pcie BAR2 IO space */
5186 hw->io_base = pci_dev->mem_resource[2].addr;
5188 /* Firmware command queue initialize */
5189 ret = hns3_cmd_init_queue(hw);
5191 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5192 goto err_cmd_init_queue;
5195 hns3_clear_all_event_cause(hw);
5197 /* Firmware command initialize */
5198 ret = hns3_cmd_init(hw);
5200 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5204 hns3_tx_push_init(eth_dev);
5207 * To ensure that the hardware environment is clean during
5208 * initialization, the driver actively clear the hardware environment
5209 * during initialization, including PF and corresponding VFs' vlan, mac,
5210 * flow table configurations, etc.
5212 ret = hns3_clear_hw(hw);
5214 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5218 /* Hardware statistics of imissed registers cleared. */
5219 ret = hns3_update_imissed_stats(hw, true);
5221 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5225 hns3_config_all_msix_error(hw, true);
5227 ret = rte_intr_callback_register(pci_dev->intr_handle,
5228 hns3_interrupt_handler,
5231 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5232 goto err_intr_callback_register;
5235 ret = hns3_ptp_init(hw);
5237 goto err_get_config;
5239 /* Enable interrupt */
5240 rte_intr_enable(pci_dev->intr_handle);
5241 hns3_pf_enable_irq0(hw);
5243 /* Get configuration */
5244 ret = hns3_get_configuration(hw);
5246 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5247 goto err_get_config;
5250 ret = hns3_tqp_stats_init(hw);
5252 goto err_get_config;
5254 ret = hns3_init_hardware(hns);
5256 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5260 /* Initialize flow director filter list & hash */
5261 ret = hns3_fdir_filter_init(hns);
5263 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5267 hns3_rss_set_default_args(hw);
5269 ret = hns3_enable_hw_error_intr(hns, true);
5271 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5273 goto err_enable_intr;
5276 ret = hns3_get_port_supported_speed(eth_dev);
5278 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5279 "by device, ret = %d.", ret);
5280 goto err_supported_speed;
5283 hns3_get_fc_autoneg_capability(hns);
5285 hns3_tm_conf_init(eth_dev);
5289 err_supported_speed:
5290 (void)hns3_enable_hw_error_intr(hns, false);
5292 hns3_fdir_filter_uninit(hns);
5294 hns3_uninit_umv_space(hw);
5296 hns3_tqp_stats_uninit(hw);
5298 hns3_pf_disable_irq0(hw);
5299 rte_intr_disable(pci_dev->intr_handle);
5300 hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
5302 err_intr_callback_register:
5304 hns3_cmd_uninit(hw);
5305 hns3_cmd_destroy_queue(hw);
5313 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5315 struct hns3_adapter *hns = eth_dev->data->dev_private;
5316 struct rte_device *dev = eth_dev->device;
5317 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5318 struct hns3_hw *hw = &hns->hw;
5320 PMD_INIT_FUNC_TRACE();
5322 hns3_tm_conf_uninit(eth_dev);
5323 hns3_enable_hw_error_intr(hns, false);
5324 hns3_rss_uninit(hns);
5325 (void)hns3_config_gro(hw, false);
5326 hns3_promisc_uninit(hw);
5327 hns3_flow_uninit(eth_dev);
5328 hns3_fdir_filter_uninit(hns);
5329 hns3_uninit_umv_space(hw);
5330 hns3_tqp_stats_uninit(hw);
5331 hns3_config_mac_tnl_int(hw, false);
5332 hns3_pf_disable_irq0(hw);
5333 rte_intr_disable(pci_dev->intr_handle);
5334 hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
5336 hns3_config_all_msix_error(hw, false);
5337 hns3_cmd_uninit(hw);
5338 hns3_cmd_destroy_queue(hw);
5343 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5347 switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
5348 case RTE_ETH_LINK_SPEED_10M:
5349 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5351 case RTE_ETH_LINK_SPEED_10M_HD:
5352 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5354 case RTE_ETH_LINK_SPEED_100M:
5355 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5357 case RTE_ETH_LINK_SPEED_100M_HD:
5358 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5360 case RTE_ETH_LINK_SPEED_1G:
5361 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5372 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5376 switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
5377 case RTE_ETH_LINK_SPEED_1G:
5378 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5380 case RTE_ETH_LINK_SPEED_10G:
5381 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5383 case RTE_ETH_LINK_SPEED_25G:
5384 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5386 case RTE_ETH_LINK_SPEED_40G:
5387 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5389 case RTE_ETH_LINK_SPEED_50G:
5390 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5392 case RTE_ETH_LINK_SPEED_100G:
5393 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5395 case RTE_ETH_LINK_SPEED_200G:
5396 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5407 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5409 struct hns3_mac *mac = &hw->mac;
5410 uint32_t supported_speed = mac->supported_speed;
5411 uint32_t speed_bit = 0;
5413 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5414 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5415 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5416 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5418 if (!(speed_bit & supported_speed)) {
5419 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5427 static inline uint32_t
5428 hns3_get_link_speed(uint32_t link_speeds)
5430 uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
5432 if (link_speeds & RTE_ETH_LINK_SPEED_10M ||
5433 link_speeds & RTE_ETH_LINK_SPEED_10M_HD)
5434 speed = RTE_ETH_SPEED_NUM_10M;
5435 if (link_speeds & RTE_ETH_LINK_SPEED_100M ||
5436 link_speeds & RTE_ETH_LINK_SPEED_100M_HD)
5437 speed = RTE_ETH_SPEED_NUM_100M;
5438 if (link_speeds & RTE_ETH_LINK_SPEED_1G)
5439 speed = RTE_ETH_SPEED_NUM_1G;
5440 if (link_speeds & RTE_ETH_LINK_SPEED_10G)
5441 speed = RTE_ETH_SPEED_NUM_10G;
5442 if (link_speeds & RTE_ETH_LINK_SPEED_25G)
5443 speed = RTE_ETH_SPEED_NUM_25G;
5444 if (link_speeds & RTE_ETH_LINK_SPEED_40G)
5445 speed = RTE_ETH_SPEED_NUM_40G;
5446 if (link_speeds & RTE_ETH_LINK_SPEED_50G)
5447 speed = RTE_ETH_SPEED_NUM_50G;
5448 if (link_speeds & RTE_ETH_LINK_SPEED_100G)
5449 speed = RTE_ETH_SPEED_NUM_100G;
5450 if (link_speeds & RTE_ETH_LINK_SPEED_200G)
5451 speed = RTE_ETH_SPEED_NUM_200G;
5457 hns3_get_link_duplex(uint32_t link_speeds)
5459 if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||
5460 (link_speeds & RTE_ETH_LINK_SPEED_100M_HD))
5461 return RTE_ETH_LINK_HALF_DUPLEX;
5463 return RTE_ETH_LINK_FULL_DUPLEX;
5467 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5468 struct hns3_set_link_speed_cfg *cfg)
5470 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5471 struct hns3_phy_params_bd0_cmd *req;
5474 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5475 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5477 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5479 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5480 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5481 req->autoneg = cfg->autoneg;
5484 * The full speed capability is used to negotiate when
5485 * auto-negotiation is enabled.
5488 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5489 HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5490 HNS3_PHY_LINK_SPEED_100M_BIT |
5491 HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5492 HNS3_PHY_LINK_SPEED_1000M_BIT;
5494 req->speed = cfg->speed;
5495 req->duplex = cfg->duplex;
5498 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5502 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5504 struct hns3_config_auto_neg_cmd *req;
5505 struct hns3_cmd_desc desc;
5509 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5511 req = (struct hns3_config_auto_neg_cmd *)desc.data;
5513 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5514 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5516 ret = hns3_cmd_send(hw, &desc, 1);
5518 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5524 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5525 struct hns3_set_link_speed_cfg *cfg)
5529 if (hw->mac.support_autoneg) {
5530 ret = hns3_set_autoneg(hw, cfg->autoneg);
5532 hns3_err(hw, "failed to configure auto-negotiation.");
5537 * To enable auto-negotiation, we only need to open the switch
5538 * of auto-negotiation, then firmware sets all speed
5546 * Some hardware doesn't support auto-negotiation, but users may not
5547 * configure link_speeds (default 0), which means auto-negotiation.
5548 * In this case, a warning message need to be printed, instead of
5552 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
5556 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5560 hns3_set_port_link_speed(struct hns3_hw *hw,
5561 struct hns3_set_link_speed_cfg *cfg)
5565 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5566 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5567 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5572 ret = hns3_set_copper_port_link_speed(hw, cfg);
5574 hns3_err(hw, "failed to set copper port link speed,"
5578 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5579 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5581 hns3_err(hw, "failed to set fiber port link speed,"
5591 hns3_apply_link_speed(struct hns3_hw *hw)
5593 struct rte_eth_conf *conf = &hw->data->dev_conf;
5594 struct hns3_set_link_speed_cfg cfg;
5596 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5597 cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ?
5598 RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
5599 if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) {
5600 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5601 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5604 return hns3_set_port_link_speed(hw, &cfg);
5608 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5610 struct hns3_hw *hw = &hns->hw;
5614 ret = hns3_update_queue_map_configure(hns);
5616 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5621 /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5622 ret = hns3_tm_conf_update(hw);
5624 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5628 hns3_enable_rxd_adv_layout(hw);
5630 ret = hns3_init_queues(hns, reset_queue);
5632 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5636 link_en = hw->set_link_down ? false : true;
5637 ret = hns3_cfg_mac_mode(hw, link_en);
5639 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5640 goto err_config_mac_mode;
5643 ret = hns3_apply_link_speed(hw);
5645 goto err_set_link_speed;
5650 (void)hns3_cfg_mac_mode(hw, false);
5652 err_config_mac_mode:
5653 hns3_dev_release_mbufs(hns);
5655 * Here is exception handling, hns3_reset_all_tqps will have the
5656 * corresponding error message if it is handled incorrectly, so it is
5657 * not necessary to check hns3_reset_all_tqps return value, here keep
5658 * ret as the error code causing the exception.
5660 (void)hns3_reset_all_tqps(hns);
5665 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5667 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5668 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5669 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5671 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5672 uint32_t intr_vector;
5677 * hns3 needs a separate interrupt to be used as event interrupt which
5678 * could not be shared with task queue pair, so KERNEL drivers need
5679 * support multiple interrupt vectors.
5681 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5682 !rte_intr_cap_multiple(intr_handle))
5685 rte_intr_disable(intr_handle);
5686 intr_vector = hw->used_rx_queues;
5687 /* creates event fd for each intr vector when MSIX is used */
5688 if (rte_intr_efd_enable(intr_handle, intr_vector))
5691 /* Allocate vector list */
5692 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
5693 hw->used_rx_queues)) {
5694 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5695 hw->used_rx_queues);
5697 goto alloc_intr_vec_error;
5700 if (rte_intr_allow_others(intr_handle)) {
5701 vec = RTE_INTR_VEC_RXTX_OFFSET;
5702 base = RTE_INTR_VEC_RXTX_OFFSET;
5705 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5706 ret = hns3_bind_ring_with_vector(hw, vec, true,
5707 HNS3_RING_TYPE_RX, q_id);
5709 goto bind_vector_error;
5711 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
5712 goto bind_vector_error;
5714 * If there are not enough efds (e.g. not enough interrupt),
5715 * remaining queues will be bond to the last interrupt.
5717 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
5720 rte_intr_enable(intr_handle);
5724 rte_intr_vec_list_free(intr_handle);
5725 alloc_intr_vec_error:
5726 rte_intr_efd_disable(intr_handle);
5731 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5733 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5734 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5735 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5739 if (dev->data->dev_conf.intr_conf.rxq == 0)
5742 if (rte_intr_dp_is_en(intr_handle)) {
5743 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5744 ret = hns3_bind_ring_with_vector(hw,
5745 rte_intr_vec_list_index_get(intr_handle,
5747 true, HNS3_RING_TYPE_RX, q_id);
5757 hns3_restore_filter(struct rte_eth_dev *dev)
5759 hns3_restore_rss_filter(dev);
5763 hns3_dev_start(struct rte_eth_dev *dev)
5765 struct hns3_adapter *hns = dev->data->dev_private;
5766 struct hns3_hw *hw = &hns->hw;
5767 bool old_state = hw->set_link_down;
5770 PMD_INIT_FUNC_TRACE();
5771 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5774 rte_spinlock_lock(&hw->lock);
5775 hw->adapter_state = HNS3_NIC_STARTING;
5778 * If the dev_set_link_down() API has been called, the "set_link_down"
5779 * flag can be cleared by dev_start() API. In addition, the flag should
5780 * also be cleared before calling hns3_do_start() so that MAC can be
5781 * enabled in dev_start stage.
5783 hw->set_link_down = false;
5784 ret = hns3_do_start(hns, true);
5788 ret = hns3_map_rx_interrupt(dev);
5790 goto map_rx_inter_err;
5793 * There are three register used to control the status of a TQP
5794 * (contains a pair of Tx queue and Rx queue) in the new version network
5795 * engine. One is used to control the enabling of Tx queue, the other is
5796 * used to control the enabling of Rx queue, and the last is the master
5797 * switch used to control the enabling of the tqp. The Tx register and
5798 * TQP register must be enabled at the same time to enable a Tx queue.
5799 * The same applies to the Rx queue. For the older network engine, this
5800 * function only refresh the enabled flag, and it is used to update the
5801 * status of queue in the dpdk framework.
5803 ret = hns3_start_all_txqs(dev);
5805 goto map_rx_inter_err;
5807 ret = hns3_start_all_rxqs(dev);
5809 goto start_all_rxqs_fail;
5811 hw->adapter_state = HNS3_NIC_STARTED;
5812 rte_spinlock_unlock(&hw->lock);
5814 hns3_rx_scattered_calc(dev);
5815 hns3_set_rxtx_function(dev);
5816 hns3_mp_req_start_rxtx(dev);
5818 hns3_restore_filter(dev);
5820 /* Enable interrupt of all rx queues before enabling queues */
5821 hns3_dev_all_rx_queue_intr_enable(hw, true);
5824 * After finished the initialization, enable tqps to receive/transmit
5825 * packets and refresh all queue status.
5827 hns3_start_tqps(hw);
5829 hns3_tm_dev_start_proc(hw);
5831 if (dev->data->dev_conf.intr_conf.lsc != 0)
5832 hns3_dev_link_update(dev, 0);
5833 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5835 hns3_info(hw, "hns3 dev start successful!");
5839 start_all_rxqs_fail:
5840 hns3_stop_all_txqs(dev);
5842 (void)hns3_do_stop(hns);
5844 hw->set_link_down = old_state;
5845 hw->adapter_state = HNS3_NIC_CONFIGURED;
5846 rte_spinlock_unlock(&hw->lock);
5852 hns3_do_stop(struct hns3_adapter *hns)
5854 struct hns3_hw *hw = &hns->hw;
5858 * The "hns3_do_stop" function will also be called by .stop_service to
5859 * prepare reset. At the time of global or IMP reset, the command cannot
5860 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5861 * accessed during the reset process. So the mbuf can not be released
5862 * during reset and is required to be released after the reset is
5865 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5866 hns3_dev_release_mbufs(hns);
5868 ret = hns3_cfg_mac_mode(hw, false);
5871 hw->mac.link_status = RTE_ETH_LINK_DOWN;
5873 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5874 hns3_configure_all_mac_addr(hns, true);
5875 ret = hns3_reset_all_tqps(hns);
5877 hns3_err(hw, "failed to reset all queues ret = %d.",
5887 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5889 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5890 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5891 struct hns3_adapter *hns = dev->data->dev_private;
5892 struct hns3_hw *hw = &hns->hw;
5893 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5894 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5897 if (dev->data->dev_conf.intr_conf.rxq == 0)
5900 /* unmap the ring with vector */
5901 if (rte_intr_allow_others(intr_handle)) {
5902 vec = RTE_INTR_VEC_RXTX_OFFSET;
5903 base = RTE_INTR_VEC_RXTX_OFFSET;
5905 if (rte_intr_dp_is_en(intr_handle)) {
5906 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5907 (void)hns3_bind_ring_with_vector(hw, vec, false,
5910 if (vec < base + rte_intr_nb_efd_get(intr_handle)
5915 /* Clean datapath event and queue/vec mapping */
5916 rte_intr_efd_disable(intr_handle);
5917 rte_intr_vec_list_free(intr_handle);
5921 hns3_dev_stop(struct rte_eth_dev *dev)
5923 struct hns3_adapter *hns = dev->data->dev_private;
5924 struct hns3_hw *hw = &hns->hw;
5926 PMD_INIT_FUNC_TRACE();
5927 dev->data->dev_started = 0;
5929 hw->adapter_state = HNS3_NIC_STOPPING;
5930 hns3_set_rxtx_function(dev);
5932 /* Disable datapath on secondary process. */
5933 hns3_mp_req_stop_rxtx(dev);
5934 /* Prevent crashes when queues are still in use. */
5935 rte_delay_ms(hw->cfg_max_queues);
5937 rte_spinlock_lock(&hw->lock);
5938 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5939 hns3_tm_dev_stop_proc(hw);
5940 hns3_config_mac_tnl_int(hw, false);
5943 hns3_unmap_rx_interrupt(dev);
5944 hw->adapter_state = HNS3_NIC_CONFIGURED;
5946 hns3_rx_scattered_reset(dev);
5947 rte_eal_alarm_cancel(hns3_service_handler, dev);
5948 hns3_stop_report_lse(dev);
5949 rte_spinlock_unlock(&hw->lock);
5955 hns3_dev_close(struct rte_eth_dev *eth_dev)
5957 struct hns3_adapter *hns = eth_dev->data->dev_private;
5958 struct hns3_hw *hw = &hns->hw;
5961 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5964 if (hw->adapter_state == HNS3_NIC_STARTED)
5965 ret = hns3_dev_stop(eth_dev);
5967 hw->adapter_state = HNS3_NIC_CLOSING;
5968 hns3_reset_abort(hns);
5969 hw->adapter_state = HNS3_NIC_CLOSED;
5971 hns3_configure_all_mc_mac_addr(hns, true);
5972 hns3_remove_all_vlan_table(hns);
5973 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5974 hns3_uninit_pf(eth_dev);
5975 hns3_free_all_queues(eth_dev);
5976 rte_free(hw->reset.wait_data);
5977 hns3_mp_uninit_primary();
5978 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5984 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5987 struct hns3_mac *mac = &hw->mac;
5988 uint32_t advertising = mac->advertising;
5989 uint32_t lp_advertising = mac->lp_advertising;
5993 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5996 } else if (advertising & lp_advertising &
5997 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5998 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
6000 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
6005 static enum hns3_fc_mode
6006 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
6008 enum hns3_fc_mode current_mode;
6009 bool rx_pause = false;
6010 bool tx_pause = false;
6012 switch (hw->mac.media_type) {
6013 case HNS3_MEDIA_TYPE_COPPER:
6014 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
6018 * Flow control auto-negotiation is not supported for fiber and
6019 * backpalne media type.
6021 case HNS3_MEDIA_TYPE_FIBER:
6022 case HNS3_MEDIA_TYPE_BACKPLANE:
6023 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
6024 current_mode = hw->requested_fc_mode;
6027 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
6028 hw->mac.media_type);
6029 current_mode = HNS3_FC_NONE;
6033 if (rx_pause && tx_pause)
6034 current_mode = HNS3_FC_FULL;
6036 current_mode = HNS3_FC_RX_PAUSE;
6038 current_mode = HNS3_FC_TX_PAUSE;
6040 current_mode = HNS3_FC_NONE;
6043 return current_mode;
6046 static enum hns3_fc_mode
6047 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6049 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6051 struct hns3_mac *mac = &hw->mac;
6054 * When the flow control mode is obtained, the device may not complete
6055 * auto-negotiation. It is necessary to wait for link establishment.
6057 (void)hns3_dev_link_update(dev, 1);
6060 * If the link auto-negotiation of the nic is disabled, or the flow
6061 * control auto-negotiation is not supported, the forced flow control
6064 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6065 return hw->requested_fc_mode;
6067 return hns3_get_autoneg_fc_mode(hw);
6071 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6073 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6074 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6075 enum hns3_fc_mode current_mode;
6077 current_mode = hns3_get_current_fc_mode(dev);
6078 switch (current_mode) {
6080 fc_conf->mode = RTE_ETH_FC_FULL;
6082 case HNS3_FC_TX_PAUSE:
6083 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
6085 case HNS3_FC_RX_PAUSE:
6086 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
6090 fc_conf->mode = RTE_ETH_FC_NONE;
6094 fc_conf->pause_time = pf->pause_time;
6095 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6101 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6103 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6105 if (!pf->support_fc_autoneg) {
6107 hns3_err(hw, "unsupported fc auto-negotiation setting.");
6112 * Flow control auto-negotiation of the NIC is not supported,
6113 * but other auto-negotiation features may be supported.
6115 if (autoneg != hw->mac.link_autoneg) {
6116 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6124 * If flow control auto-negotiation of the NIC is supported, all
6125 * auto-negotiation features are supported.
6127 if (autoneg != hw->mac.link_autoneg) {
6128 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6136 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6138 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6139 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6142 if (fc_conf->high_water || fc_conf->low_water ||
6143 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6144 hns3_err(hw, "Unsupported flow control settings specified, "
6145 "high_water(%u), low_water(%u), send_xon(%u) and "
6146 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6147 fc_conf->high_water, fc_conf->low_water,
6148 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6152 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6156 if (!fc_conf->pause_time) {
6157 hns3_err(hw, "Invalid pause time %u setting.",
6158 fc_conf->pause_time);
6162 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6163 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6164 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6165 "current_fc_status = %d", hw->current_fc_status);
6169 if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
6170 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6174 rte_spinlock_lock(&hw->lock);
6175 ret = hns3_fc_enable(dev, fc_conf);
6176 rte_spinlock_unlock(&hw->lock);
6182 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6183 struct rte_eth_pfc_conf *pfc_conf)
6185 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6188 if (!hns3_dev_get_support(hw, DCB)) {
6189 hns3_err(hw, "This port does not support dcb configurations.");
6193 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6194 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6195 hns3_err(hw, "Unsupported flow control settings specified, "
6196 "high_water(%u), low_water(%u), send_xon(%u) and "
6197 "mac_ctrl_frame_fwd(%u) must be set to '0'",
6198 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6199 pfc_conf->fc.send_xon,
6200 pfc_conf->fc.mac_ctrl_frame_fwd);
6203 if (pfc_conf->fc.autoneg) {
6204 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6207 if (pfc_conf->fc.pause_time == 0) {
6208 hns3_err(hw, "Invalid pause time %u setting.",
6209 pfc_conf->fc.pause_time);
6213 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6214 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6215 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6216 "current_fc_status = %d", hw->current_fc_status);
6220 rte_spinlock_lock(&hw->lock);
6221 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6222 rte_spinlock_unlock(&hw->lock);
6228 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6230 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6231 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6232 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6235 rte_spinlock_lock(&hw->lock);
6236 if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
6237 dcb_info->nb_tcs = pf->local_max_tc;
6239 dcb_info->nb_tcs = 1;
6241 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6242 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6243 for (i = 0; i < dcb_info->nb_tcs; i++)
6244 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6246 for (i = 0; i < hw->num_tc; i++) {
6247 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6248 dcb_info->tc_queue.tc_txq[0][i].base =
6249 hw->tc_queue[i].tqp_offset;
6250 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6251 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6252 hw->tc_queue[i].tqp_count;
6254 rte_spinlock_unlock(&hw->lock);
6260 hns3_reinit_dev(struct hns3_adapter *hns)
6262 struct hns3_hw *hw = &hns->hw;
6265 ret = hns3_cmd_init(hw);
6267 hns3_err(hw, "Failed to init cmd: %d", ret);
6271 ret = hns3_reset_all_tqps(hns);
6273 hns3_err(hw, "Failed to reset all queues: %d", ret);
6277 ret = hns3_init_hardware(hns);
6279 hns3_err(hw, "Failed to init hardware: %d", ret);
6283 ret = hns3_enable_hw_error_intr(hns, true);
6285 hns3_err(hw, "fail to enable hw error interrupts: %d",
6289 hns3_info(hw, "Reset done, driver initialization finished.");
6295 is_pf_reset_done(struct hns3_hw *hw)
6297 uint32_t val, reg, reg_bit;
6299 switch (hw->reset.level) {
6300 case HNS3_IMP_RESET:
6301 reg = HNS3_GLOBAL_RESET_REG;
6302 reg_bit = HNS3_IMP_RESET_BIT;
6304 case HNS3_GLOBAL_RESET:
6305 reg = HNS3_GLOBAL_RESET_REG;
6306 reg_bit = HNS3_GLOBAL_RESET_BIT;
6308 case HNS3_FUNC_RESET:
6309 reg = HNS3_FUN_RST_ING;
6310 reg_bit = HNS3_FUN_RST_ING_B;
6312 case HNS3_FLR_RESET:
6314 hns3_err(hw, "Wait for unsupported reset level: %d",
6318 val = hns3_read_dev(hw, reg);
6319 if (hns3_get_bit(val, reg_bit))
6326 hns3_is_reset_pending(struct hns3_adapter *hns)
6328 struct hns3_hw *hw = &hns->hw;
6329 enum hns3_reset_level reset;
6331 hns3_check_event_cause(hns, NULL);
6332 reset = hns3_get_reset_level(hns, &hw->reset.pending);
6333 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6334 hw->reset.level < reset) {
6335 hns3_warn(hw, "High level reset %d is pending", reset);
6338 reset = hns3_get_reset_level(hns, &hw->reset.request);
6339 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6340 hw->reset.level < reset) {
6341 hns3_warn(hw, "High level reset %d is request", reset);
6348 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6350 struct hns3_hw *hw = &hns->hw;
6351 struct hns3_wait_data *wait_data = hw->reset.wait_data;
6354 if (wait_data->result == HNS3_WAIT_SUCCESS)
6356 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6357 hns3_clock_gettime(&tv);
6358 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6359 tv.tv_sec, tv.tv_usec);
6361 } else if (wait_data->result == HNS3_WAIT_REQUEST)
6364 wait_data->hns = hns;
6365 wait_data->check_completion = is_pf_reset_done;
6366 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6367 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6368 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6369 wait_data->count = HNS3_RESET_WAIT_CNT;
6370 wait_data->result = HNS3_WAIT_REQUEST;
6371 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6376 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6378 struct hns3_cmd_desc desc;
6379 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6381 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6382 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6383 req->fun_reset_vfid = func_id;
6385 return hns3_cmd_send(hw, &desc, 1);
6389 hns3_imp_reset_cmd(struct hns3_hw *hw)
6391 struct hns3_cmd_desc desc;
6393 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6394 desc.data[0] = 0xeedd;
6396 return hns3_cmd_send(hw, &desc, 1);
6400 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6402 struct hns3_hw *hw = &hns->hw;
6406 hns3_clock_gettime(&tv);
6407 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6408 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6409 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6410 tv.tv_sec, tv.tv_usec);
6414 switch (reset_level) {
6415 case HNS3_IMP_RESET:
6416 hns3_imp_reset_cmd(hw);
6417 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6418 tv.tv_sec, tv.tv_usec);
6420 case HNS3_GLOBAL_RESET:
6421 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6422 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6423 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6424 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6425 tv.tv_sec, tv.tv_usec);
6427 case HNS3_FUNC_RESET:
6428 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6429 tv.tv_sec, tv.tv_usec);
6430 /* schedule again to check later */
6431 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6432 hns3_schedule_reset(hns);
6435 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6438 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6441 static enum hns3_reset_level
6442 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6444 struct hns3_hw *hw = &hns->hw;
6445 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6447 /* Return the highest priority reset level amongst all */
6448 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6449 reset_level = HNS3_IMP_RESET;
6450 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6451 reset_level = HNS3_GLOBAL_RESET;
6452 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6453 reset_level = HNS3_FUNC_RESET;
6454 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6455 reset_level = HNS3_FLR_RESET;
6457 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6458 return HNS3_NONE_RESET;
6464 hns3_record_imp_error(struct hns3_adapter *hns)
6466 struct hns3_hw *hw = &hns->hw;
6469 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6470 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6471 hns3_warn(hw, "Detected IMP RD poison!");
6472 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6473 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6476 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6477 hns3_warn(hw, "Detected IMP CMDQ error!");
6478 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6479 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6484 hns3_prepare_reset(struct hns3_adapter *hns)
6486 struct hns3_hw *hw = &hns->hw;
6490 switch (hw->reset.level) {
6491 case HNS3_FUNC_RESET:
6492 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6497 * After performaning pf reset, it is not necessary to do the
6498 * mailbox handling or send any command to firmware, because
6499 * any mailbox handling or command to firmware is only valid
6500 * after hns3_cmd_init is called.
6502 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6503 hw->reset.stats.request_cnt++;
6505 case HNS3_IMP_RESET:
6506 hns3_record_imp_error(hns);
6507 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6508 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6509 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6518 hns3_set_rst_done(struct hns3_hw *hw)
6520 struct hns3_pf_rst_done_cmd *req;
6521 struct hns3_cmd_desc desc;
6523 req = (struct hns3_pf_rst_done_cmd *)desc.data;
6524 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6525 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6526 return hns3_cmd_send(hw, &desc, 1);
6530 hns3_stop_service(struct hns3_adapter *hns)
6532 struct hns3_hw *hw = &hns->hw;
6533 struct rte_eth_dev *eth_dev;
6535 eth_dev = &rte_eth_devices[hw->data->port_id];
6536 hw->mac.link_status = RTE_ETH_LINK_DOWN;
6537 if (hw->adapter_state == HNS3_NIC_STARTED) {
6538 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6539 hns3_update_linkstatus_and_event(hw, false);
6542 hns3_set_rxtx_function(eth_dev);
6544 /* Disable datapath on secondary process. */
6545 hns3_mp_req_stop_rxtx(eth_dev);
6546 rte_delay_ms(hw->cfg_max_queues);
6548 rte_spinlock_lock(&hw->lock);
6549 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6550 hw->adapter_state == HNS3_NIC_STOPPING) {
6551 hns3_enable_all_queues(hw, false);
6553 hw->reset.mbuf_deferred_free = true;
6555 hw->reset.mbuf_deferred_free = false;
6558 * It is cumbersome for hardware to pick-and-choose entries for deletion
6559 * from table space. Hence, for function reset software intervention is
6560 * required to delete the entries
6562 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6563 hns3_configure_all_mc_mac_addr(hns, true);
6564 rte_spinlock_unlock(&hw->lock);
6570 hns3_start_service(struct hns3_adapter *hns)
6572 struct hns3_hw *hw = &hns->hw;
6573 struct rte_eth_dev *eth_dev;
6575 if (hw->reset.level == HNS3_IMP_RESET ||
6576 hw->reset.level == HNS3_GLOBAL_RESET)
6577 hns3_set_rst_done(hw);
6578 eth_dev = &rte_eth_devices[hw->data->port_id];
6579 hns3_set_rxtx_function(eth_dev);
6580 hns3_mp_req_start_rxtx(eth_dev);
6581 if (hw->adapter_state == HNS3_NIC_STARTED) {
6583 * This API parent function already hold the hns3_hw.lock, the
6584 * hns3_service_handler may report lse, in bonding application
6585 * it will call driver's ops which may acquire the hns3_hw.lock
6586 * again, thus lead to deadlock.
6587 * We defer calls hns3_service_handler to avoid the deadlock.
6589 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6590 hns3_service_handler, eth_dev);
6592 /* Enable interrupt of all rx queues before enabling queues */
6593 hns3_dev_all_rx_queue_intr_enable(hw, true);
6595 * Enable state of each rxq and txq will be recovered after
6596 * reset, so we need to restore them before enable all tqps;
6598 hns3_restore_tqp_enable_state(hw);
6600 * When finished the initialization, enable queues to receive
6601 * and transmit packets.
6603 hns3_enable_all_queues(hw, true);
6610 hns3_restore_conf(struct hns3_adapter *hns)
6612 struct hns3_hw *hw = &hns->hw;
6615 ret = hns3_configure_all_mac_addr(hns, false);
6619 ret = hns3_configure_all_mc_mac_addr(hns, false);
6623 ret = hns3_dev_promisc_restore(hns);
6627 ret = hns3_restore_vlan_table(hns);
6631 ret = hns3_restore_vlan_conf(hns);
6635 ret = hns3_restore_all_fdir_filter(hns);
6639 ret = hns3_restore_ptp(hns);
6643 ret = hns3_restore_rx_interrupt(hw);
6647 ret = hns3_restore_gro_conf(hw);
6651 ret = hns3_restore_fec(hw);
6655 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6656 ret = hns3_do_start(hns, false);
6659 hns3_info(hw, "hns3 dev restart successful!");
6660 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6661 hw->adapter_state = HNS3_NIC_CONFIGURED;
6665 hns3_configure_all_mc_mac_addr(hns, true);
6667 hns3_configure_all_mac_addr(hns, true);
6672 hns3_reset_service(void *param)
6674 struct hns3_adapter *hns = (struct hns3_adapter *)param;
6675 struct hns3_hw *hw = &hns->hw;
6676 enum hns3_reset_level reset_level;
6677 struct timeval tv_delta;
6678 struct timeval tv_start;
6684 * The interrupt is not triggered within the delay time.
6685 * The interrupt may have been lost. It is necessary to handle
6686 * the interrupt to recover from the error.
6688 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6689 SCHEDULE_DEFERRED) {
6690 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6692 hns3_err(hw, "Handling interrupts in delayed tasks");
6693 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6694 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6695 if (reset_level == HNS3_NONE_RESET) {
6696 hns3_err(hw, "No reset level is set, try IMP reset");
6697 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6700 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6703 * Check if there is any ongoing reset in the hardware. This status can
6704 * be checked from reset_pending. If there is then, we need to wait for
6705 * hardware to complete reset.
6706 * a. If we are able to figure out in reasonable time that hardware
6707 * has fully resetted then, we can proceed with driver, client
6709 * b. else, we can come back later to check this status so re-sched
6712 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6713 if (reset_level != HNS3_NONE_RESET) {
6714 hns3_clock_gettime(&tv_start);
6715 ret = hns3_reset_process(hns, reset_level);
6716 hns3_clock_gettime(&tv);
6717 timersub(&tv, &tv_start, &tv_delta);
6718 msec = hns3_clock_calctime_ms(&tv_delta);
6719 if (msec > HNS3_RESET_PROCESS_MS)
6720 hns3_err(hw, "%d handle long time delta %" PRIu64
6721 " ms time=%ld.%.6ld",
6722 hw->reset.level, msec,
6723 tv.tv_sec, tv.tv_usec);
6728 /* Check if we got any *new* reset requests to be honored */
6729 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6730 if (reset_level != HNS3_NONE_RESET)
6731 hns3_msix_process(hns, reset_level);
6735 hns3_get_speed_capa_num(uint16_t device_id)
6739 switch (device_id) {
6740 case HNS3_DEV_ID_25GE:
6741 case HNS3_DEV_ID_25GE_RDMA:
6744 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6745 case HNS3_DEV_ID_200G_RDMA:
6757 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6760 switch (device_id) {
6761 case HNS3_DEV_ID_25GE:
6763 case HNS3_DEV_ID_25GE_RDMA:
6764 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6765 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6767 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6768 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6769 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6771 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6772 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6773 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6775 case HNS3_DEV_ID_200G_RDMA:
6776 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6777 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6787 hns3_fec_get_capability(struct rte_eth_dev *dev,
6788 struct rte_eth_fec_capa *speed_fec_capa,
6791 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6792 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6793 uint16_t device_id = pci_dev->id.device_id;
6794 unsigned int capa_num;
6797 capa_num = hns3_get_speed_capa_num(device_id);
6798 if (capa_num == 0) {
6799 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6804 if (speed_fec_capa == NULL || num < capa_num)
6807 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6815 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6817 struct hns3_config_fec_cmd *req;
6818 struct hns3_cmd_desc desc;
6822 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6823 * in device of link speed
6826 if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) {
6831 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6832 req = (struct hns3_config_fec_cmd *)desc.data;
6833 ret = hns3_cmd_send(hw, &desc, 1);
6835 hns3_err(hw, "get current fec auto state failed, ret = %d",
6840 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6845 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6847 struct hns3_sfp_info_cmd *resp;
6848 uint32_t tmp_fec_capa;
6850 struct hns3_cmd_desc desc;
6854 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6855 * configured FEC mode is returned.
6856 * If link is up, current FEC mode is returned.
6858 if (hw->mac.link_status == RTE_ETH_LINK_DOWN) {
6859 ret = get_current_fec_auto_state(hw, &auto_state);
6863 if (auto_state == 0x1) {
6864 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6869 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6870 resp = (struct hns3_sfp_info_cmd *)desc.data;
6871 resp->query_type = HNS3_ACTIVE_QUERY;
6873 ret = hns3_cmd_send(hw, &desc, 1);
6874 if (ret == -EOPNOTSUPP) {
6875 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6878 hns3_err(hw, "get FEC failed, ret = %d", ret);
6883 * FEC mode order defined in hns3 hardware is inconsistend with
6884 * that defined in the ethdev library. So the sequence needs
6887 switch (resp->active_fec) {
6888 case HNS3_HW_FEC_MODE_NOFEC:
6889 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6891 case HNS3_HW_FEC_MODE_BASER:
6892 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6894 case HNS3_HW_FEC_MODE_RS:
6895 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6898 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6902 *fec_capa = tmp_fec_capa;
6907 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6909 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6911 return hns3_fec_get_internal(hw, fec_capa);
6915 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6917 struct hns3_config_fec_cmd *req;
6918 struct hns3_cmd_desc desc;
6921 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6923 req = (struct hns3_config_fec_cmd *)desc.data;
6925 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6926 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6927 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6929 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6930 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6931 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6933 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6934 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6935 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6937 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6938 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6943 ret = hns3_cmd_send(hw, &desc, 1);
6945 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6951 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6953 struct hns3_mac *mac = &hw->mac;
6956 switch (mac->link_speed) {
6957 case RTE_ETH_SPEED_NUM_10G:
6958 cur_capa = fec_capa[1].capa;
6960 case RTE_ETH_SPEED_NUM_25G:
6961 case RTE_ETH_SPEED_NUM_100G:
6962 case RTE_ETH_SPEED_NUM_200G:
6963 cur_capa = fec_capa[0].capa;
6974 is_fec_mode_one_bit_set(uint32_t mode)
6979 for (i = 0; i < sizeof(mode); i++)
6980 if (mode >> i & 0x1)
6983 return cnt == 1 ? true : false;
6987 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6989 #define FEC_CAPA_NUM 2
6990 struct hns3_adapter *hns = dev->data->dev_private;
6991 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6992 struct hns3_pf *pf = &hns->pf;
6994 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6996 uint32_t num = FEC_CAPA_NUM;
6999 ret = hns3_fec_get_capability(dev, fec_capa, num);
7003 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
7004 if (!is_fec_mode_one_bit_set(mode)) {
7005 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
7006 "FEC mode should be only one bit set", mode);
7011 * Check whether the configured mode is within the FEC capability.
7012 * If not, the configured mode will not be supported.
7014 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
7015 if (!(cur_capa & mode)) {
7016 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
7020 rte_spinlock_lock(&hw->lock);
7021 ret = hns3_set_fec_hw(hw, mode);
7023 rte_spinlock_unlock(&hw->lock);
7027 pf->fec_mode = mode;
7028 rte_spinlock_unlock(&hw->lock);
7034 hns3_restore_fec(struct hns3_hw *hw)
7036 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7037 struct hns3_pf *pf = &hns->pf;
7038 uint32_t mode = pf->fec_mode;
7041 ret = hns3_set_fec_hw(hw, mode);
7043 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7050 hns3_query_dev_fec_info(struct hns3_hw *hw)
7052 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7053 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7056 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7058 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7064 hns3_optical_module_existed(struct hns3_hw *hw)
7066 struct hns3_cmd_desc desc;
7070 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7071 ret = hns3_cmd_send(hw, &desc, 1);
7074 "fail to get optical module exist state, ret = %d.\n",
7078 existed = !!desc.data[0];
7084 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7085 uint32_t len, uint8_t *data)
7087 #define HNS3_SFP_INFO_CMD_NUM 6
7088 #define HNS3_SFP_INFO_MAX_LEN \
7089 (HNS3_SFP_INFO_BD0_LEN + \
7090 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7091 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7092 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7098 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7099 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7101 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7102 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7105 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7106 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7107 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7108 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7110 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7112 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7117 /* The data format in BD0 is different with the others. */
7118 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7119 memcpy(data, sfp_info_bd0->data, copy_len);
7120 read_len = copy_len;
7122 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7123 if (read_len >= len)
7126 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7127 memcpy(data + read_len, desc[i].data, copy_len);
7128 read_len += copy_len;
7131 return (int)read_len;
7135 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7136 struct rte_dev_eeprom_info *info)
7138 struct hns3_adapter *hns = dev->data->dev_private;
7139 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7140 uint32_t offset = info->offset;
7141 uint32_t len = info->length;
7142 uint8_t *data = info->data;
7143 uint32_t read_len = 0;
7145 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7148 if (!hns3_optical_module_existed(hw)) {
7149 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7153 while (read_len < len) {
7155 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7167 hns3_get_module_info(struct rte_eth_dev *dev,
7168 struct rte_eth_dev_module_info *modinfo)
7170 #define HNS3_SFF8024_ID_SFP 0x03
7171 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
7172 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
7173 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
7174 #define HNS3_SFF_8636_V1_3 0x03
7175 struct hns3_adapter *hns = dev->data->dev_private;
7176 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7177 struct rte_dev_eeprom_info info;
7178 struct hns3_sfp_type sfp_type;
7181 memset(&sfp_type, 0, sizeof(sfp_type));
7182 memset(&info, 0, sizeof(info));
7183 info.data = (uint8_t *)&sfp_type;
7184 info.length = sizeof(sfp_type);
7185 ret = hns3_get_module_eeprom(dev, &info);
7189 switch (sfp_type.type) {
7190 case HNS3_SFF8024_ID_SFP:
7191 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7192 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7194 case HNS3_SFF8024_ID_QSFP_8438:
7195 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7196 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7198 case HNS3_SFF8024_ID_QSFP_8436_8636:
7199 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7200 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7201 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7203 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7204 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7207 case HNS3_SFF8024_ID_QSFP28_8636:
7208 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7209 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7212 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7213 sfp_type.type, sfp_type.ext_type);
7221 hns3_clock_gettime(struct timeval *tv)
7223 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7224 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7226 #define CLOCK_TYPE CLOCK_MONOTONIC
7228 #define NSEC_TO_USEC_DIV 1000
7230 struct timespec spec;
7231 (void)clock_gettime(CLOCK_TYPE, &spec);
7233 tv->tv_sec = spec.tv_sec;
7234 tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7238 hns3_clock_calctime_ms(struct timeval *tv)
7240 return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7241 tv->tv_usec / USEC_PER_MSEC;
7245 hns3_clock_gettime_ms(void)
7249 hns3_clock_gettime(&tv);
7250 return hns3_clock_calctime_ms(&tv);
7254 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7256 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7260 if (strcmp(value, "vec") == 0)
7261 hint = HNS3_IO_FUNC_HINT_VEC;
7262 else if (strcmp(value, "sve") == 0)
7263 hint = HNS3_IO_FUNC_HINT_SVE;
7264 else if (strcmp(value, "simple") == 0)
7265 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7266 else if (strcmp(value, "common") == 0)
7267 hint = HNS3_IO_FUNC_HINT_COMMON;
7269 /* If the hint is valid then update output parameters */
7270 if (hint != HNS3_IO_FUNC_HINT_NONE)
7271 *(uint32_t *)extra_args = hint;
7277 hns3_get_io_hint_func_name(uint32_t hint)
7280 case HNS3_IO_FUNC_HINT_VEC:
7282 case HNS3_IO_FUNC_HINT_SVE:
7284 case HNS3_IO_FUNC_HINT_SIMPLE:
7286 case HNS3_IO_FUNC_HINT_COMMON:
7294 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7300 val = strtoull(value, NULL, 16);
7301 *(uint64_t *)extra_args = val;
7307 hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args)
7313 val = strtoul(value, NULL, 10);
7316 * 500ms is empirical value in process of mailbox communication. If
7317 * the delay value is set to one lower thanthe empirical value, mailbox
7318 * communication may fail.
7320 if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX)
7321 *(uint16_t *)extra_args = val;
7327 hns3_parse_devargs(struct rte_eth_dev *dev)
7329 uint16_t mbx_time_limit_ms = HNS3_MBX_DEF_TIME_LIMIT_MS;
7330 struct hns3_adapter *hns = dev->data->dev_private;
7331 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7332 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7333 struct hns3_hw *hw = &hns->hw;
7334 uint64_t dev_caps_mask = 0;
7335 struct rte_kvargs *kvlist;
7337 if (dev->device->devargs == NULL)
7340 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7344 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7345 &hns3_parse_io_hint_func, &rx_func_hint);
7346 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7347 &hns3_parse_io_hint_func, &tx_func_hint);
7348 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7349 &hns3_parse_dev_caps_mask, &dev_caps_mask);
7350 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_MBX_TIME_LIMIT_MS,
7351 &hns3_parse_mbx_time_limit, &mbx_time_limit_ms);
7353 rte_kvargs_free(kvlist);
7355 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7356 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7357 hns3_get_io_hint_func_name(rx_func_hint));
7358 hns->rx_func_hint = rx_func_hint;
7359 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7360 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7361 hns3_get_io_hint_func_name(tx_func_hint));
7362 hns->tx_func_hint = tx_func_hint;
7364 if (dev_caps_mask != 0)
7365 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7366 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7367 hns->dev_caps_mask = dev_caps_mask;
7369 if (mbx_time_limit_ms != HNS3_MBX_DEF_TIME_LIMIT_MS)
7370 hns3_warn(hw, "parsed %s = %u.", HNS3_DEVARG_MBX_TIME_LIMIT_MS,
7372 hns->mbx_time_limit_ms = mbx_time_limit_ms;
7375 static const struct eth_dev_ops hns3_eth_dev_ops = {
7376 .dev_configure = hns3_dev_configure,
7377 .dev_start = hns3_dev_start,
7378 .dev_stop = hns3_dev_stop,
7379 .dev_close = hns3_dev_close,
7380 .promiscuous_enable = hns3_dev_promiscuous_enable,
7381 .promiscuous_disable = hns3_dev_promiscuous_disable,
7382 .allmulticast_enable = hns3_dev_allmulticast_enable,
7383 .allmulticast_disable = hns3_dev_allmulticast_disable,
7384 .mtu_set = hns3_dev_mtu_set,
7385 .stats_get = hns3_stats_get,
7386 .stats_reset = hns3_stats_reset,
7387 .xstats_get = hns3_dev_xstats_get,
7388 .xstats_get_names = hns3_dev_xstats_get_names,
7389 .xstats_reset = hns3_dev_xstats_reset,
7390 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
7391 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7392 .dev_infos_get = hns3_dev_infos_get,
7393 .fw_version_get = hns3_fw_version_get,
7394 .rx_queue_setup = hns3_rx_queue_setup,
7395 .tx_queue_setup = hns3_tx_queue_setup,
7396 .rx_queue_release = hns3_dev_rx_queue_release,
7397 .tx_queue_release = hns3_dev_tx_queue_release,
7398 .rx_queue_start = hns3_dev_rx_queue_start,
7399 .rx_queue_stop = hns3_dev_rx_queue_stop,
7400 .tx_queue_start = hns3_dev_tx_queue_start,
7401 .tx_queue_stop = hns3_dev_tx_queue_stop,
7402 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
7403 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
7404 .rxq_info_get = hns3_rxq_info_get,
7405 .txq_info_get = hns3_txq_info_get,
7406 .rx_burst_mode_get = hns3_rx_burst_mode_get,
7407 .tx_burst_mode_get = hns3_tx_burst_mode_get,
7408 .flow_ctrl_get = hns3_flow_ctrl_get,
7409 .flow_ctrl_set = hns3_flow_ctrl_set,
7410 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7411 .mac_addr_add = hns3_add_mac_addr,
7412 .mac_addr_remove = hns3_remove_mac_addr,
7413 .mac_addr_set = hns3_set_default_mac_addr,
7414 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
7415 .link_update = hns3_dev_link_update,
7416 .dev_set_link_up = hns3_dev_set_link_up,
7417 .dev_set_link_down = hns3_dev_set_link_down,
7418 .rss_hash_update = hns3_dev_rss_hash_update,
7419 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
7420 .reta_update = hns3_dev_rss_reta_update,
7421 .reta_query = hns3_dev_rss_reta_query,
7422 .flow_ops_get = hns3_dev_flow_ops_get,
7423 .vlan_filter_set = hns3_vlan_filter_set,
7424 .vlan_tpid_set = hns3_vlan_tpid_set,
7425 .vlan_offload_set = hns3_vlan_offload_set,
7426 .vlan_pvid_set = hns3_vlan_pvid_set,
7427 .get_reg = hns3_get_regs,
7428 .get_module_info = hns3_get_module_info,
7429 .get_module_eeprom = hns3_get_module_eeprom,
7430 .get_dcb_info = hns3_get_dcb_info,
7431 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7432 .fec_get_capability = hns3_fec_get_capability,
7433 .fec_get = hns3_fec_get,
7434 .fec_set = hns3_fec_set,
7435 .tm_ops_get = hns3_tm_ops_get,
7436 .tx_done_cleanup = hns3_tx_done_cleanup,
7437 .timesync_enable = hns3_timesync_enable,
7438 .timesync_disable = hns3_timesync_disable,
7439 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7440 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7441 .timesync_adjust_time = hns3_timesync_adjust_time,
7442 .timesync_read_time = hns3_timesync_read_time,
7443 .timesync_write_time = hns3_timesync_write_time,
7446 static const struct hns3_reset_ops hns3_reset_ops = {
7447 .reset_service = hns3_reset_service,
7448 .stop_service = hns3_stop_service,
7449 .prepare_reset = hns3_prepare_reset,
7450 .wait_hardware_ready = hns3_wait_hardware_ready,
7451 .reinit_dev = hns3_reinit_dev,
7452 .restore_conf = hns3_restore_conf,
7453 .start_service = hns3_start_service,
7457 hns3_dev_init(struct rte_eth_dev *eth_dev)
7459 struct hns3_adapter *hns = eth_dev->data->dev_private;
7460 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7461 struct rte_ether_addr *eth_addr;
7462 struct hns3_hw *hw = &hns->hw;
7465 PMD_INIT_FUNC_TRACE();
7467 hns3_flow_init(eth_dev);
7469 hns3_set_rxtx_function(eth_dev);
7470 eth_dev->dev_ops = &hns3_eth_dev_ops;
7471 eth_dev->rx_queue_count = hns3_rx_queue_count;
7472 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7473 ret = hns3_mp_init_secondary();
7475 PMD_INIT_LOG(ERR, "Failed to init for secondary "
7476 "process, ret = %d", ret);
7477 goto err_mp_init_secondary;
7479 hw->secondary_cnt++;
7480 hns3_tx_push_init(eth_dev);
7484 ret = hns3_mp_init_primary();
7487 "Failed to init for primary process, ret = %d",
7489 goto err_mp_init_primary;
7492 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7494 hw->data = eth_dev->data;
7495 hns3_parse_devargs(eth_dev);
7498 * Set default max packet size according to the mtu
7499 * default vale in DPDK frame.
7501 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7503 ret = hns3_reset_init(hw);
7505 goto err_init_reset;
7506 hw->reset.ops = &hns3_reset_ops;
7508 ret = hns3_init_pf(eth_dev);
7510 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7514 /* Allocate memory for storing MAC addresses */
7515 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7516 sizeof(struct rte_ether_addr) *
7517 HNS3_UC_MACADDR_NUM, 0);
7518 if (eth_dev->data->mac_addrs == NULL) {
7519 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7520 "to store MAC addresses",
7521 sizeof(struct rte_ether_addr) *
7522 HNS3_UC_MACADDR_NUM);
7524 goto err_rte_zmalloc;
7527 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7528 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7529 rte_eth_random_addr(hw->mac.mac_addr);
7530 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7531 (struct rte_ether_addr *)hw->mac.mac_addr);
7532 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7533 "unicast address, using random MAC address %s",
7536 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7537 ð_dev->data->mac_addrs[0]);
7539 hw->adapter_state = HNS3_NIC_INITIALIZED;
7541 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7543 hns3_err(hw, "Reschedule reset service after dev_init");
7544 hns3_schedule_reset(hns);
7546 /* IMP will wait ready flag before reset */
7547 hns3_notify_reset_ready(hw, false);
7550 hns3_info(hw, "hns3 dev initialization successful!");
7554 hns3_uninit_pf(eth_dev);
7557 rte_free(hw->reset.wait_data);
7560 hns3_mp_uninit_primary();
7562 err_mp_init_primary:
7563 err_mp_init_secondary:
7564 eth_dev->dev_ops = NULL;
7565 eth_dev->rx_pkt_burst = NULL;
7566 eth_dev->rx_descriptor_status = NULL;
7567 eth_dev->tx_pkt_burst = NULL;
7568 eth_dev->tx_pkt_prepare = NULL;
7569 eth_dev->tx_descriptor_status = NULL;
7574 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7576 struct hns3_adapter *hns = eth_dev->data->dev_private;
7577 struct hns3_hw *hw = &hns->hw;
7579 PMD_INIT_FUNC_TRACE();
7581 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
7584 if (hw->adapter_state < HNS3_NIC_CLOSING)
7585 hns3_dev_close(eth_dev);
7587 hw->adapter_state = HNS3_NIC_REMOVED;
7592 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7593 struct rte_pci_device *pci_dev)
7595 return rte_eth_dev_pci_generic_probe(pci_dev,
7596 sizeof(struct hns3_adapter),
7601 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7603 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7606 static const struct rte_pci_id pci_id_hns3_map[] = {
7607 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7608 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7609 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7610 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7611 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7612 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7613 { .vendor_id = 0, }, /* sentinel */
7616 static struct rte_pci_driver rte_hns3_pmd = {
7617 .id_table = pci_id_hns3_map,
7618 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7619 .probe = eth_hns3_pci_probe,
7620 .remove = eth_hns3_pci_remove,
7623 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7624 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7625 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7626 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7627 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7628 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7629 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
7630 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
7631 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7632 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);