drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  20 #define HNS3_SERVICE_QUICK_INTERVAL     10
  21 #define HNS3_INVALID_PVID               0xFFFF
  22
  23 #define HNS3_FILTER_TYPE_VF             0
  24 #define HNS3_FILTER_TYPE_PORT           1
  25 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  26 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  27 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  28 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  29 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  30 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  31                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  32 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  34
  35 /* Reset related Registers */
  36 #define HNS3_GLOBAL_RESET_BIT           0
  37 #define HNS3_CORE_RESET_BIT             1
  38 #define HNS3_IMP_RESET_BIT              2
  39 #define HNS3_FUN_RST_ING_B              0
  40
  41 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  43 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  45
  46 #define HNS3_RESET_WAIT_MS      100
  47 #define HNS3_RESET_WAIT_CNT     200
  48
  49 /* FEC mode order defined in HNS3 hardware */
  50 #define HNS3_HW_FEC_MODE_NOFEC  0
  51 #define HNS3_HW_FEC_MODE_BASER  1
  52 #define HNS3_HW_FEC_MODE_RS     2
  53
  54 enum hns3_evt_cause {
  55         HNS3_VECTOR0_EVENT_RST,
  56         HNS3_VECTOR0_EVENT_MBX,
  57         HNS3_VECTOR0_EVENT_ERR,
  58         HNS3_VECTOR0_EVENT_PTP,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  96 static bool hns3_update_link_status(struct hns3_hw *hw);
  97
  98 static int hns3_add_mc_addr(struct hns3_hw *hw,
  99                             struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 101                             struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 104 static int hns3_do_stop(struct hns3_adapter *hns);
 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
 107
 108 void hns3_ether_format_addr(char *buf, uint16_t size,
 109                             const struct rte_ether_addr *ether_addr)
 110 {
 111         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 112                 ether_addr->addr_bytes[0],
 113                 ether_addr->addr_bytes[4],
 114                 ether_addr->addr_bytes[5]);
 115 }
 116
 117 static void
 118 hns3_pf_disable_irq0(struct hns3_hw *hw)
 119 {
 120         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 121 }
 122
 123 static void
 124 hns3_pf_enable_irq0(struct hns3_hw *hw)
 125 {
 126         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 127 }
 128
 129 static enum hns3_evt_cause
 130 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 131                           uint32_t *vec_val)
 132 {
 133         struct hns3_hw *hw = &hns->hw;
 134
 135         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 136         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 137         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 138         if (!is_delay) {
 139                 hw->reset.stats.imp_cnt++;
 140                 hns3_warn(hw, "IMP reset detected, clear reset status");
 141         } else {
 142                 hns3_schedule_delayed_reset(hns);
 143                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 144         }
 145
 146         return HNS3_VECTOR0_EVENT_RST;
 147 }
 148
 149 static enum hns3_evt_cause
 150 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 151                              uint32_t *vec_val)
 152 {
 153         struct hns3_hw *hw = &hns->hw;
 154
 155         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 156         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 157         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 158         if (!is_delay) {
 159                 hw->reset.stats.global_cnt++;
 160                 hns3_warn(hw, "Global reset detected, clear reset status");
 161         } else {
 162                 hns3_schedule_delayed_reset(hns);
 163                 hns3_warn(hw,
 164                           "Global reset detected, don't clear reset status");
 165         }
 166
 167         return HNS3_VECTOR0_EVENT_RST;
 168 }
 169
 170 static enum hns3_evt_cause
 171 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 172 {
 173         struct hns3_hw *hw = &hns->hw;
 174         uint32_t vector0_int_stats;
 175         uint32_t cmdq_src_val;
 176         uint32_t hw_err_src_reg;
 177         uint32_t val;
 178         enum hns3_evt_cause ret;
 179         bool is_delay;
 180
 181         /* fetch the events from their corresponding regs */
 182         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 183         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 184         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 185
 186         is_delay = clearval == NULL ? true : false;
 187         /*
 188          * Assumption: If by any chance reset and mailbox events are reported
 189          * together then we will only process reset event and defer the
 190          * processing of the mailbox events. Since, we would have not cleared
 191          * RX CMDQ event this time we would receive again another interrupt
 192          * from H/W just for the mailbox.
 193          */
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 195                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 196                 goto out;
 197         }
 198
 199         /* Global reset */
 200         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 201                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 202                 goto out;
 203         }
 204
 205         /* Check for vector0 1588 event source */
 206         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 207                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 208                 ret = HNS3_VECTOR0_EVENT_PTP;
 209                 goto out;
 210         }
 211
 212         /* check for vector0 msix event source */
 213         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 214             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 215                 val = vector0_int_stats | hw_err_src_reg;
 216                 ret = HNS3_VECTOR0_EVENT_ERR;
 217                 goto out;
 218         }
 219
 220         /* check for vector0 mailbox(=CMDQ RX) event source */
 221         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 222                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 223                 val = cmdq_src_val;
 224                 ret = HNS3_VECTOR0_EVENT_MBX;
 225                 goto out;
 226         }
 227
 228         val = vector0_int_stats;
 229         ret = HNS3_VECTOR0_EVENT_OTHER;
 230 out:
 231
 232         if (clearval)
 233                 *clearval = val;
 234         return ret;
 235 }
 236
 237 static bool
 238 hns3_is_1588_event_type(uint32_t event_type)
 239 {
 240         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 241 }
 242
 243 static void
 244 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 245 {
 246         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 247             hns3_is_1588_event_type(event_type))
 248                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 249         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 250                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 251 }
 252
 253 static void
 254 hns3_clear_all_event_cause(struct hns3_hw *hw)
 255 {
 256         uint32_t vector0_int_stats;
 257
 258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 259         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 260                 hns3_warn(hw, "Probe during IMP reset interrupt");
 261
 262         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 263                 hns3_warn(hw, "Probe during Global reset interrupt");
 264
 265         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 266                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 267                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 268                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 269         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 271                                 BIT(HNS3_VECTOR0_1588_INT_B));
 272 }
 273
 274 static void
 275 hns3_handle_mac_tnl(struct hns3_hw *hw)
 276 {
 277         struct hns3_cmd_desc desc;
 278         uint32_t status;
 279         int ret;
 280
 281         /* query and clear mac tnl interrupt */
 282         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 283         ret = hns3_cmd_send(hw, &desc, 1);
 284         if (ret) {
 285                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 286                 return;
 287         }
 288
 289         status = rte_le_to_cpu_32(desc.data[0]);
 290         if (status) {
 291                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 292                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 293                                           false);
 294                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 295                 ret = hns3_cmd_send(hw, &desc, 1);
 296                 if (ret)
 297                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 298                                  ret);
 299         }
 300 }
 301
 302 static void
 303 hns3_interrupt_handler(void *param)
 304 {
 305         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 306         struct hns3_adapter *hns = dev->data->dev_private;
 307         struct hns3_hw *hw = &hns->hw;
 308         enum hns3_evt_cause event_cause;
 309         uint32_t clearval = 0;
 310         uint32_t vector0_int;
 311         uint32_t ras_int;
 312         uint32_t cmdq_int;
 313
 314         /* Disable interrupt */
 315         hns3_pf_disable_irq0(hw);
 316
 317         event_cause = hns3_check_event_cause(hns, &clearval);
 318         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 319         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 320         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 321         hns3_clear_event_cause(hw, event_cause, clearval);
 322         /* vector 0 interrupt is shared with reset and mailbox source events. */
 323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 326                           vector0_int, ras_int, cmdq_int);
 327                 hns3_handle_mac_tnl(hw);
 328                 hns3_handle_error(hns);
 329         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 330                 hns3_warn(hw, "received reset interrupt");
 331                 hns3_schedule_reset(hns);
 332         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 333                 hns3_dev_handle_mbx_msg(hw);
 334         } else {
 335                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 336                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 337                           vector0_int, ras_int, cmdq_int);
 338         }
 339
 340         /* Enable interrupt if it is not cause by reset */
 341         hns3_pf_enable_irq0(hw);
 342 }
 343
 344 static int
 345 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 346 {
 347 #define HNS3_VLAN_ID_OFFSET_STEP        160
 348 #define HNS3_VLAN_BYTE_SIZE             8
 349         struct hns3_vlan_filter_pf_cfg_cmd *req;
 350         struct hns3_hw *hw = &hns->hw;
 351         uint8_t vlan_offset_byte_val;
 352         struct hns3_cmd_desc desc;
 353         uint8_t vlan_offset_byte;
 354         uint8_t vlan_offset_base;
 355         int ret;
 356
 357         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 358
 359         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 360         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 361                            HNS3_VLAN_BYTE_SIZE;
 362         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 363
 364         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 365         req->vlan_offset = vlan_offset_base;
 366         req->vlan_cfg = on ? 0 : 1;
 367         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 368
 369         ret = hns3_cmd_send(hw, &desc, 1);
 370         if (ret)
 371                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 372                          vlan_id, ret);
 373
 374         return ret;
 375 }
 376
 377 static void
 378 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 379 {
 380         struct hns3_user_vlan_table *vlan_entry;
 381         struct hns3_pf *pf = &hns->pf;
 382
 383         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 384                 if (vlan_entry->vlan_id == vlan_id) {
 385                         if (vlan_entry->hd_tbl_status)
 386                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 387                         LIST_REMOVE(vlan_entry, next);
 388                         rte_free(vlan_entry);
 389                         break;
 390                 }
 391         }
 392 }
 393
 394 static void
 395 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 396                         bool writen_to_tbl)
 397 {
 398         struct hns3_user_vlan_table *vlan_entry;
 399         struct hns3_hw *hw = &hns->hw;
 400         struct hns3_pf *pf = &hns->pf;
 401
 402         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 403                 if (vlan_entry->vlan_id == vlan_id)
 404                         return;
 405         }
 406
 407         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 408         if (vlan_entry == NULL) {
 409                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 410                 return;
 411         }
 412
 413         vlan_entry->hd_tbl_status = writen_to_tbl;
 414         vlan_entry->vlan_id = vlan_id;
 415
 416         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 417 }
 418
 419 static int
 420 hns3_restore_vlan_table(struct hns3_adapter *hns)
 421 {
 422         struct hns3_user_vlan_table *vlan_entry;
 423         struct hns3_hw *hw = &hns->hw;
 424         struct hns3_pf *pf = &hns->pf;
 425         uint16_t vlan_id;
 426         int ret = 0;
 427
 428         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 429                 return hns3_vlan_pvid_configure(hns,
 430                                                 hw->port_base_vlan_cfg.pvid, 1);
 431
 432         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 433                 if (vlan_entry->hd_tbl_status) {
 434                         vlan_id = vlan_entry->vlan_id;
 435                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 436                         if (ret)
 437                                 break;
 438                 }
 439         }
 440
 441         return ret;
 442 }
 443
 444 static int
 445 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 446 {
 447         struct hns3_hw *hw = &hns->hw;
 448         bool writen_to_tbl = false;
 449         int ret = 0;
 450
 451         /*
 452          * When vlan filter is enabled, hardware regards packets without vlan
 453          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 454          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 455          */
 456         if (on == 0 && vlan_id == 0)
 457                 return 0;
 458
 459         /*
 460          * When port base vlan enabled, we use port base vlan as the vlan
 461          * filter condition. In this case, we don't update vlan filter table
 462          * when user add new vlan or remove exist vlan, just update the
 463          * vlan list. The vlan id in vlan list will be written in vlan filter
 464          * table until port base vlan disabled
 465          */
 466         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 467                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 468                 writen_to_tbl = true;
 469         }
 470
 471         if (ret == 0) {
 472                 if (on)
 473                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 474                 else
 475                         hns3_rm_dev_vlan_table(hns, vlan_id);
 476         }
 477         return ret;
 478 }
 479
 480 static int
 481 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 482 {
 483         struct hns3_adapter *hns = dev->data->dev_private;
 484         struct hns3_hw *hw = &hns->hw;
 485         int ret;
 486
 487         rte_spinlock_lock(&hw->lock);
 488         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 489         rte_spinlock_unlock(&hw->lock);
 490         return ret;
 491 }
 492
 493 static int
 494 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 495                          uint16_t tpid)
 496 {
 497         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 498         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 499         struct hns3_hw *hw = &hns->hw;
 500         struct hns3_cmd_desc desc;
 501         int ret;
 502
 503         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 504              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 505                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 506                 return -EINVAL;
 507         }
 508
 509         if (tpid != RTE_ETHER_TYPE_VLAN) {
 510                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 511                 return -EINVAL;
 512         }
 513
 514         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 515         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 516
 517         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 518                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 519                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 520         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 521                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 522                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 523                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 524                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 525         }
 526
 527         ret = hns3_cmd_send(hw, &desc, 1);
 528         if (ret) {
 529                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 530                          ret);
 531                 return ret;
 532         }
 533
 534         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 535
 536         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 537         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 538         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 539
 540         ret = hns3_cmd_send(hw, &desc, 1);
 541         if (ret)
 542                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 543                          ret);
 544         return ret;
 545 }
 546
 547 static int
 548 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 549                    uint16_t tpid)
 550 {
 551         struct hns3_adapter *hns = dev->data->dev_private;
 552         struct hns3_hw *hw = &hns->hw;
 553         int ret;
 554
 555         rte_spinlock_lock(&hw->lock);
 556         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 557         rte_spinlock_unlock(&hw->lock);
 558         return ret;
 559 }
 560
 561 static int
 562 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 563                              struct hns3_rx_vtag_cfg *vcfg)
 564 {
 565         struct hns3_vport_vtag_rx_cfg_cmd *req;
 566         struct hns3_hw *hw = &hns->hw;
 567         struct hns3_cmd_desc desc;
 568         uint16_t vport_id;
 569         uint8_t bitmap;
 570         int ret;
 571
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 573
 574         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 575         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 576                      vcfg->strip_tag1_en ? 1 : 0);
 577         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 578                      vcfg->strip_tag2_en ? 1 : 0);
 579         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 580                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 581         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 582                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 583
 584         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 585         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 586                      vcfg->strip_tag1_discard_en ? 1 : 0);
 587         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 588                      vcfg->strip_tag2_discard_en ? 1 : 0);
 589         /*
 590          * In current version VF is not supported when PF is driven by DPDK
 591          * driver, just need to configure parameters for PF vport.
 592          */
 593         vport_id = HNS3_PF_FUNC_ID;
 594         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 595         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 596         req->vf_bitmap[req->vf_offset] = bitmap;
 597
 598         ret = hns3_cmd_send(hw, &desc, 1);
 599         if (ret)
 600                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 601         return ret;
 602 }
 603
 604 static void
 605 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 606                            struct hns3_rx_vtag_cfg *vcfg)
 607 {
 608         struct hns3_pf *pf = &hns->pf;
 609         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 610 }
 611
 612 static void
 613 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 614                            struct hns3_tx_vtag_cfg *vcfg)
 615 {
 616         struct hns3_pf *pf = &hns->pf;
 617         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 618 }
 619
 620 static int
 621 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 622 {
 623         struct hns3_rx_vtag_cfg rxvlan_cfg;
 624         struct hns3_hw *hw = &hns->hw;
 625         int ret;
 626
 627         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 628                 rxvlan_cfg.strip_tag1_en = false;
 629                 rxvlan_cfg.strip_tag2_en = enable;
 630                 rxvlan_cfg.strip_tag2_discard_en = false;
 631         } else {
 632                 rxvlan_cfg.strip_tag1_en = enable;
 633                 rxvlan_cfg.strip_tag2_en = true;
 634                 rxvlan_cfg.strip_tag2_discard_en = true;
 635         }
 636
 637         rxvlan_cfg.strip_tag1_discard_en = false;
 638         rxvlan_cfg.vlan1_vlan_prionly = false;
 639         rxvlan_cfg.vlan2_vlan_prionly = false;
 640         rxvlan_cfg.rx_vlan_offload_en = enable;
 641
 642         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 643         if (ret) {
 644                 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
 645                                 enable ? "enable" : "disable", ret);
 646                 return ret;
 647         }
 648
 649         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 656                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 657 {
 658         struct hns3_vlan_filter_ctrl_cmd *req;
 659         struct hns3_cmd_desc desc;
 660         int ret;
 661
 662         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 663
 664         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 665         req->vlan_type = vlan_type;
 666         req->vlan_fe = filter_en ? fe_type : 0;
 667         req->vf_id = vf_id;
 668
 669         ret = hns3_cmd_send(hw, &desc, 1);
 670         if (ret)
 671                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 672
 673         return ret;
 674 }
 675
 676 static int
 677 hns3_vlan_filter_init(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         int ret;
 681
 682         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 683                                         HNS3_FILTER_FE_EGRESS, false,
 684                                         HNS3_PF_FUNC_ID);
 685         if (ret) {
 686                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 687                 return ret;
 688         }
 689
 690         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 691                                         HNS3_FILTER_FE_INGRESS, false,
 692                                         HNS3_PF_FUNC_ID);
 693         if (ret)
 694                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 695
 696         return ret;
 697 }
 698
 699 static int
 700 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 701 {
 702         struct hns3_hw *hw = &hns->hw;
 703         int ret;
 704
 705         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 706                                         HNS3_FILTER_FE_INGRESS, enable,
 707                                         HNS3_PF_FUNC_ID);
 708         if (ret)
 709                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 710                          enable ? "enable" : "disable", ret);
 711
 712         return ret;
 713 }
 714
 715 static int
 716 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 717 {
 718         struct hns3_adapter *hns = dev->data->dev_private;
 719         struct hns3_hw *hw = &hns->hw;
 720         struct rte_eth_rxmode *rxmode;
 721         unsigned int tmp_mask;
 722         bool enable;
 723         int ret = 0;
 724
 725         rte_spinlock_lock(&hw->lock);
 726         rxmode = &dev->data->dev_conf.rxmode;
 727         tmp_mask = (unsigned int)mask;
 728         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 729                 /* ignore vlan filter configuration during promiscuous mode */
 730                 if (!dev->data->promiscuous) {
 731                         /* Enable or disable VLAN filter */
 732                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 733                                  true : false;
 734
 735                         ret = hns3_enable_vlan_filter(hns, enable);
 736                         if (ret) {
 737                                 rte_spinlock_unlock(&hw->lock);
 738                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 739                                          enable ? "enable" : "disable", ret);
 740                                 return ret;
 741                         }
 742                 }
 743         }
 744
 745         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 746                 /* Enable or disable VLAN stripping */
 747                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 748                     true : false;
 749
 750                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 751                 if (ret) {
 752                         rte_spinlock_unlock(&hw->lock);
 753                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 754                                  enable ? "enable" : "disable", ret);
 755                         return ret;
 756                 }
 757         }
 758
 759         rte_spinlock_unlock(&hw->lock);
 760
 761         return ret;
 762 }
 763
 764 static int
 765 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 766                              struct hns3_tx_vtag_cfg *vcfg)
 767 {
 768         struct hns3_vport_vtag_tx_cfg_cmd *req;
 769         struct hns3_cmd_desc desc;
 770         struct hns3_hw *hw = &hns->hw;
 771         uint16_t vport_id;
 772         uint8_t bitmap;
 773         int ret;
 774
 775         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 776
 777         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 778         req->def_vlan_tag1 = vcfg->default_tag1;
 779         req->def_vlan_tag2 = vcfg->default_tag2;
 780         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 781                      vcfg->accept_tag1 ? 1 : 0);
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 783                      vcfg->accept_untag1 ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 785                      vcfg->accept_tag2 ? 1 : 0);
 786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 787                      vcfg->accept_untag2 ? 1 : 0);
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 789                      vcfg->insert_tag1_en ? 1 : 0);
 790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 791                      vcfg->insert_tag2_en ? 1 : 0);
 792         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 793
 794         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 795         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 796                      vcfg->tag_shift_mode_en ? 1 : 0);
 797
 798         /*
 799          * In current version VF is not supported when PF is driven by DPDK
 800          * driver, just need to configure parameters for PF vport.
 801          */
 802         vport_id = HNS3_PF_FUNC_ID;
 803         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 804         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 805         req->vf_bitmap[req->vf_offset] = bitmap;
 806
 807         ret = hns3_cmd_send(hw, &desc, 1);
 808         if (ret)
 809                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 810
 811         return ret;
 812 }
 813
 814 static int
 815 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 816                      uint16_t pvid)
 817 {
 818         struct hns3_hw *hw = &hns->hw;
 819         struct hns3_tx_vtag_cfg txvlan_cfg;
 820         int ret;
 821
 822         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 823                 txvlan_cfg.accept_tag1 = true;
 824                 txvlan_cfg.insert_tag1_en = false;
 825                 txvlan_cfg.default_tag1 = 0;
 826         } else {
 827                 txvlan_cfg.accept_tag1 =
 828                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 829                 txvlan_cfg.insert_tag1_en = true;
 830                 txvlan_cfg.default_tag1 = pvid;
 831         }
 832
 833         txvlan_cfg.accept_untag1 = true;
 834         txvlan_cfg.accept_tag2 = true;
 835         txvlan_cfg.accept_untag2 = true;
 836         txvlan_cfg.insert_tag2_en = false;
 837         txvlan_cfg.default_tag2 = 0;
 838         txvlan_cfg.tag_shift_mode_en = true;
 839
 840         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 841         if (ret) {
 842                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 843                          ret);
 844                 return ret;
 845         }
 846
 847         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 848         return ret;
 849 }
 850
 851
 852 static void
 853 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 854 {
 855         struct hns3_user_vlan_table *vlan_entry;
 856         struct hns3_pf *pf = &hns->pf;
 857
 858         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 859                 if (vlan_entry->hd_tbl_status) {
 860                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 861                         vlan_entry->hd_tbl_status = false;
 862                 }
 863         }
 864
 865         if (is_del_list) {
 866                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 867                 while (vlan_entry) {
 868                         LIST_REMOVE(vlan_entry, next);
 869                         rte_free(vlan_entry);
 870                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 871                 }
 872         }
 873 }
 874
 875 static void
 876 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 877 {
 878         struct hns3_user_vlan_table *vlan_entry;
 879         struct hns3_pf *pf = &hns->pf;
 880
 881         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 882                 if (!vlan_entry->hd_tbl_status) {
 883                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 884                         vlan_entry->hd_tbl_status = true;
 885                 }
 886         }
 887 }
 888
 889 static void
 890 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 891 {
 892         struct hns3_hw *hw = &hns->hw;
 893         int ret;
 894
 895         hns3_rm_all_vlan_table(hns, true);
 896         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 897                 ret = hns3_set_port_vlan_filter(hns,
 898                                                 hw->port_base_vlan_cfg.pvid, 0);
 899                 if (ret) {
 900                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 901                                  ret);
 902                         return;
 903                 }
 904         }
 905 }
 906
 907 static int
 908 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 909                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 910 {
 911         struct hns3_hw *hw = &hns->hw;
 912         uint16_t old_pvid;
 913         int ret;
 914
 915         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 916                 old_pvid = hw->port_base_vlan_cfg.pvid;
 917                 if (old_pvid != HNS3_INVALID_PVID) {
 918                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 919                         if (ret) {
 920                                 hns3_err(hw, "failed to remove old pvid %u, "
 921                                                 "ret = %d", old_pvid, ret);
 922                                 return ret;
 923                         }
 924                 }
 925
 926                 hns3_rm_all_vlan_table(hns, false);
 927                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 928                 if (ret) {
 929                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 930                                         new_pvid, ret);
 931                         return ret;
 932                 }
 933         } else {
 934                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 935                 if (ret) {
 936                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 937                                         new_pvid, ret);
 938                         return ret;
 939                 }
 940
 941                 hns3_add_all_vlan_table(hns);
 942         }
 943         return 0;
 944 }
 945
 946 static int
 947 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 948 {
 949         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 950         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 951         bool rx_strip_en;
 952         int ret;
 953
 954         rx_strip_en = old_cfg->rx_vlan_offload_en;
 955         if (on) {
 956                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 957                 rx_vlan_cfg.strip_tag2_en = true;
 958                 rx_vlan_cfg.strip_tag2_discard_en = true;
 959         } else {
 960                 rx_vlan_cfg.strip_tag1_en = false;
 961                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 962                 rx_vlan_cfg.strip_tag2_discard_en = false;
 963         }
 964         rx_vlan_cfg.strip_tag1_discard_en = false;
 965         rx_vlan_cfg.vlan1_vlan_prionly = false;
 966         rx_vlan_cfg.vlan2_vlan_prionly = false;
 967         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 968
 969         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 970         if (ret)
 971                 return ret;
 972
 973         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 974         return ret;
 975 }
 976
 977 static int
 978 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 979 {
 980         struct hns3_hw *hw = &hns->hw;
 981         uint16_t port_base_vlan_state;
 982         int ret, err;
 983
 984         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 985                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 986                         hns3_warn(hw, "Invalid operation! As current pvid set "
 987                                   "is %u, disable pvid %u is invalid",
 988                                   hw->port_base_vlan_cfg.pvid, pvid);
 989                 return 0;
 990         }
 991
 992         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 993                                     HNS3_PORT_BASE_VLAN_DISABLE;
 994         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 995         if (ret) {
 996                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 997                          ret);
 998                 return ret;
 999         }
1000
1001         ret = hns3_en_pvid_strip(hns, on);
1002         if (ret) {
1003                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1004                          "ret = %d", ret);
1005                 goto pvid_vlan_strip_fail;
1006         }
1007
1008         if (pvid == HNS3_INVALID_PVID)
1009                 goto out;
1010         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1011         if (ret) {
1012                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1013                          ret);
1014                 goto vlan_filter_set_fail;
1015         }
1016
1017 out:
1018         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1019         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1020         return ret;
1021
1022 vlan_filter_set_fail:
1023         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1024                                         HNS3_PORT_BASE_VLAN_ENABLE);
1025         if (err)
1026                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1027
1028 pvid_vlan_strip_fail:
1029         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1030                                         hw->port_base_vlan_cfg.pvid);
1031         if (err)
1032                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1039 {
1040         struct hns3_adapter *hns = dev->data->dev_private;
1041         struct hns3_hw *hw = &hns->hw;
1042         bool pvid_en_state_change;
1043         uint16_t pvid_state;
1044         int ret;
1045
1046         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1047                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1048                          RTE_ETHER_MAX_VLAN_ID);
1049                 return -EINVAL;
1050         }
1051
1052         /*
1053          * If PVID configuration state change, should refresh the PVID
1054          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1055          */
1056         pvid_state = hw->port_base_vlan_cfg.state;
1057         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1058             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1059                 pvid_en_state_change = false;
1060         else
1061                 pvid_en_state_change = true;
1062
1063         rte_spinlock_lock(&hw->lock);
1064         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1065         rte_spinlock_unlock(&hw->lock);
1066         if (ret)
1067                 return ret;
1068         /*
1069          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1070          * need be processed by PMD driver.
1071          */
1072         if (pvid_en_state_change &&
1073             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1074                 hns3_update_all_queues_pvid_proc_en(hw);
1075
1076         return 0;
1077 }
1078
1079 static int
1080 hns3_default_vlan_config(struct hns3_adapter *hns)
1081 {
1082         struct hns3_hw *hw = &hns->hw;
1083         int ret;
1084
1085         /*
1086          * When vlan filter is enabled, hardware regards packets without vlan
1087          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1088          * table, packets without vlan won't be received. So, add vlan 0 as
1089          * the default vlan.
1090          */
1091         ret = hns3_vlan_filter_configure(hns, 0, 1);
1092         if (ret)
1093                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1094         return ret;
1095 }
1096
1097 static int
1098 hns3_init_vlan_config(struct hns3_adapter *hns)
1099 {
1100         struct hns3_hw *hw = &hns->hw;
1101         int ret;
1102
1103         /*
1104          * This function can be called in the initialization and reset process,
1105          * when in reset process, it means that hardware had been reseted
1106          * successfully and we need to restore the hardware configuration to
1107          * ensure that the hardware configuration remains unchanged before and
1108          * after reset.
1109          */
1110         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1111                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1112                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1113         }
1114
1115         ret = hns3_vlan_filter_init(hns);
1116         if (ret) {
1117                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1118                 return ret;
1119         }
1120
1121         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1122                                        RTE_ETHER_TYPE_VLAN);
1123         if (ret) {
1124                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1125                 return ret;
1126         }
1127
1128         /*
1129          * When in the reinit dev stage of the reset process, the following
1130          * vlan-related configurations may differ from those at initialization,
1131          * we will restore configurations to hardware in hns3_restore_vlan_table
1132          * and hns3_restore_vlan_conf later.
1133          */
1134         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1135                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1136                 if (ret) {
1137                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1138                         return ret;
1139                 }
1140
1141                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1142                 if (ret) {
1143                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1144                                  ret);
1145                         return ret;
1146                 }
1147         }
1148
1149         return hns3_default_vlan_config(hns);
1150 }
1151
1152 static int
1153 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1154 {
1155         struct hns3_pf *pf = &hns->pf;
1156         struct hns3_hw *hw = &hns->hw;
1157         uint64_t offloads;
1158         bool enable;
1159         int ret;
1160
1161         if (!hw->data->promiscuous) {
1162                 /* restore vlan filter states */
1163                 offloads = hw->data->dev_conf.rxmode.offloads;
1164                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1165                 ret = hns3_enable_vlan_filter(hns, enable);
1166                 if (ret) {
1167                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1168                                  "ret = %d", ret);
1169                         return ret;
1170                 }
1171         }
1172
1173         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1174         if (ret) {
1175                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1176                 return ret;
1177         }
1178
1179         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1180         if (ret)
1181                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1182
1183         return ret;
1184 }
1185
1186 static int
1187 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1188 {
1189         struct hns3_adapter *hns = dev->data->dev_private;
1190         struct rte_eth_dev_data *data = dev->data;
1191         struct rte_eth_txmode *txmode;
1192         struct hns3_hw *hw = &hns->hw;
1193         int mask;
1194         int ret;
1195
1196         txmode = &data->dev_conf.txmode;
1197         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1198                 hns3_warn(hw,
1199                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1200                           "configuration is not supported! Ignore these two "
1201                           "parameters: hw_vlan_reject_tagged(%u), "
1202                           "hw_vlan_reject_untagged(%u)",
1203                           txmode->hw_vlan_reject_tagged,
1204                           txmode->hw_vlan_reject_untagged);
1205
1206         /* Apply vlan offload setting */
1207         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1208         ret = hns3_vlan_offload_set(dev, mask);
1209         if (ret) {
1210                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1211                          ret);
1212                 return ret;
1213         }
1214
1215         /*
1216          * If pvid config is not set in rte_eth_conf, driver needn't to set
1217          * VLAN pvid related configuration to hardware.
1218          */
1219         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1220                 return 0;
1221
1222         /* Apply pvid setting */
1223         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1224                                  txmode->hw_vlan_insert_pvid);
1225         if (ret)
1226                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1227                          txmode->pvid, ret);
1228
1229         return ret;
1230 }
1231
1232 static int
1233 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1234                 unsigned int tso_mss_max)
1235 {
1236         struct hns3_cfg_tso_status_cmd *req;
1237         struct hns3_cmd_desc desc;
1238         uint16_t tso_mss;
1239
1240         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1241
1242         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1243
1244         tso_mss = 0;
1245         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1246                        tso_mss_min);
1247         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1248
1249         tso_mss = 0;
1250         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1251                        tso_mss_max);
1252         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1253
1254         return hns3_cmd_send(hw, &desc, 1);
1255 }
1256
1257 static int
1258 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1259                    uint16_t *allocated_size, bool is_alloc)
1260 {
1261         struct hns3_umv_spc_alc_cmd *req;
1262         struct hns3_cmd_desc desc;
1263         int ret;
1264
1265         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1266         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1267         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1268         req->space_size = rte_cpu_to_le_32(space_size);
1269
1270         ret = hns3_cmd_send(hw, &desc, 1);
1271         if (ret) {
1272                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1273                              is_alloc ? "allocate" : "free", ret);
1274                 return ret;
1275         }
1276
1277         if (is_alloc && allocated_size)
1278                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 hns3_init_umv_space(struct hns3_hw *hw)
1285 {
1286         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1287         struct hns3_pf *pf = &hns->pf;
1288         uint16_t allocated_size = 0;
1289         int ret;
1290
1291         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1292                                  true);
1293         if (ret)
1294                 return ret;
1295
1296         if (allocated_size < pf->wanted_umv_size)
1297                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1298                              pf->wanted_umv_size, allocated_size);
1299
1300         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1301                                                 pf->wanted_umv_size;
1302         pf->used_umv_size = 0;
1303         return 0;
1304 }
1305
1306 static int
1307 hns3_uninit_umv_space(struct hns3_hw *hw)
1308 {
1309         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1310         struct hns3_pf *pf = &hns->pf;
1311         int ret;
1312
1313         if (pf->max_umv_size == 0)
1314                 return 0;
1315
1316         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1317         if (ret)
1318                 return ret;
1319
1320         pf->max_umv_size = 0;
1321
1322         return 0;
1323 }
1324
1325 static bool
1326 hns3_is_umv_space_full(struct hns3_hw *hw)
1327 {
1328         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1329         struct hns3_pf *pf = &hns->pf;
1330         bool is_full;
1331
1332         is_full = (pf->used_umv_size >= pf->max_umv_size);
1333
1334         return is_full;
1335 }
1336
1337 static void
1338 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1339 {
1340         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1341         struct hns3_pf *pf = &hns->pf;
1342
1343         if (is_free) {
1344                 if (pf->used_umv_size > 0)
1345                         pf->used_umv_size--;
1346         } else
1347                 pf->used_umv_size++;
1348 }
1349
1350 static void
1351 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1352                       const uint8_t *addr, bool is_mc)
1353 {
1354         const unsigned char *mac_addr = addr;
1355         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1356                             ((uint32_t)mac_addr[2] << 16) |
1357                             ((uint32_t)mac_addr[1] << 8) |
1358                             (uint32_t)mac_addr[0];
1359         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1360
1361         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1362         if (is_mc) {
1363                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1364                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1365                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1366         }
1367
1368         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1369         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1370 }
1371
1372 static int
1373 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1374                              uint8_t resp_code,
1375                              enum hns3_mac_vlan_tbl_opcode op)
1376 {
1377         if (cmdq_resp) {
1378                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1379                          cmdq_resp);
1380                 return -EIO;
1381         }
1382
1383         if (op == HNS3_MAC_VLAN_ADD) {
1384                 if (resp_code == 0 || resp_code == 1) {
1385                         return 0;
1386                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1387                         hns3_err(hw, "add mac addr failed for uc_overflow");
1388                         return -ENOSPC;
1389                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1390                         hns3_err(hw, "add mac addr failed for mc_overflow");
1391                         return -ENOSPC;
1392                 }
1393
1394                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1395                          resp_code);
1396                 return -EIO;
1397         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1398                 if (resp_code == 0) {
1399                         return 0;
1400                 } else if (resp_code == 1) {
1401                         hns3_dbg(hw, "remove mac addr failed for miss");
1402                         return -ENOENT;
1403                 }
1404
1405                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1406                          resp_code);
1407                 return -EIO;
1408         } else if (op == HNS3_MAC_VLAN_LKUP) {
1409                 if (resp_code == 0) {
1410                         return 0;
1411                 } else if (resp_code == 1) {
1412                         hns3_dbg(hw, "lookup mac addr failed for miss");
1413                         return -ENOENT;
1414                 }
1415
1416                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1417                          resp_code);
1418                 return -EIO;
1419         }
1420
1421         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1422                  op);
1423
1424         return -EINVAL;
1425 }
1426
1427 static int
1428 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1429                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1430                          struct hns3_cmd_desc *desc, bool is_mc)
1431 {
1432         uint8_t resp_code;
1433         uint16_t retval;
1434         int ret;
1435
1436         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1437         if (is_mc) {
1438                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1439                 memcpy(desc[0].data, req,
1440                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1441                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1442                                           true);
1443                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1444                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1445                                           true);
1446                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1447         } else {
1448                 memcpy(desc[0].data, req,
1449                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1450                 ret = hns3_cmd_send(hw, desc, 1);
1451         }
1452         if (ret) {
1453                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1454                          ret);
1455                 return ret;
1456         }
1457         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1458         retval = rte_le_to_cpu_16(desc[0].retval);
1459
1460         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1461                                             HNS3_MAC_VLAN_LKUP);
1462 }
1463
1464 static int
1465 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1466                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1467                       struct hns3_cmd_desc *mc_desc)
1468 {
1469         uint8_t resp_code;
1470         uint16_t retval;
1471         int cfg_status;
1472         int ret;
1473
1474         if (mc_desc == NULL) {
1475                 struct hns3_cmd_desc desc;
1476
1477                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1478                 memcpy(desc.data, req,
1479                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1480                 ret = hns3_cmd_send(hw, &desc, 1);
1481                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1482                 retval = rte_le_to_cpu_16(desc.retval);
1483
1484                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1485                                                           HNS3_MAC_VLAN_ADD);
1486         } else {
1487                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1488                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1489                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1490                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1491                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1492                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1493                 memcpy(mc_desc[0].data, req,
1494                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1495                 mc_desc[0].retval = 0;
1496                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1497                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1498                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1499
1500                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1501                                                           HNS3_MAC_VLAN_ADD);
1502         }
1503
1504         if (ret) {
1505                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1506                 return ret;
1507         }
1508
1509         return cfg_status;
1510 }
1511
1512 static int
1513 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1514                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1515 {
1516         struct hns3_cmd_desc desc;
1517         uint8_t resp_code;
1518         uint16_t retval;
1519         int ret;
1520
1521         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1522
1523         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1524
1525         ret = hns3_cmd_send(hw, &desc, 1);
1526         if (ret) {
1527                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1528                 return ret;
1529         }
1530         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1531         retval = rte_le_to_cpu_16(desc.retval);
1532
1533         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1534                                             HNS3_MAC_VLAN_REMOVE);
1535 }
1536
1537 static int
1538 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 {
1540         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1541         struct hns3_mac_vlan_tbl_entry_cmd req;
1542         struct hns3_pf *pf = &hns->pf;
1543         struct hns3_cmd_desc desc[3];
1544         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1545         uint16_t egress_port = 0;
1546         uint8_t vf_id;
1547         int ret;
1548
1549         /* check if mac addr is valid */
1550         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1551                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1552                                       mac_addr);
1553                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1554                          mac_str);
1555                 return -EINVAL;
1556         }
1557
1558         memset(&req, 0, sizeof(req));
1559
1560         /*
1561          * In current version VF is not supported when PF is driven by DPDK
1562          * driver, just need to configure parameters for PF vport.
1563          */
1564         vf_id = HNS3_PF_FUNC_ID;
1565         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1566                        HNS3_MAC_EPORT_VFID_S, vf_id);
1567
1568         req.egress_port = rte_cpu_to_le_16(egress_port);
1569
1570         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1571
1572         /*
1573          * Lookup the mac address in the mac_vlan table, and add
1574          * it if the entry is inexistent. Repeated unicast entry
1575          * is not allowed in the mac vlan table.
1576          */
1577         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1578         if (ret == -ENOENT) {
1579                 if (!hns3_is_umv_space_full(hw)) {
1580                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1581                         if (!ret)
1582                                 hns3_update_umv_space(hw, false);
1583                         return ret;
1584                 }
1585
1586                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1587
1588                 return -ENOSPC;
1589         }
1590
1591         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1592
1593         /* check if we just hit the duplicate */
1594         if (ret == 0) {
1595                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1596                 return 0;
1597         }
1598
1599         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1600                  mac_str);
1601
1602         return ret;
1603 }
1604
1605 static int
1606 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1607 {
1608         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1609         struct rte_ether_addr *addr;
1610         int ret;
1611         int i;
1612
1613         for (i = 0; i < hw->mc_addrs_num; i++) {
1614                 addr = &hw->mc_addrs[i];
1615                 /* Check if there are duplicate addresses */
1616                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1617                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1618                                               addr);
1619                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1620                                  "(%s) is added by the set_mc_mac_addr_list "
1621                                  "API", mac_str);
1622                         return -EINVAL;
1623                 }
1624         }
1625
1626         ret = hns3_add_mc_addr(hw, mac_addr);
1627         if (ret) {
1628                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629                                       mac_addr);
1630                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1631                          mac_str, ret);
1632         }
1633         return ret;
1634 }
1635
1636 static int
1637 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1638 {
1639         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1640         int ret;
1641
1642         ret = hns3_remove_mc_addr(hw, mac_addr);
1643         if (ret) {
1644                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1645                                       mac_addr);
1646                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1647                          mac_str, ret);
1648         }
1649         return ret;
1650 }
1651
1652 static int
1653 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1654                   __rte_unused uint32_t idx, __rte_unused uint32_t pool)
1655 {
1656         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1658         int ret;
1659
1660         rte_spinlock_lock(&hw->lock);
1661
1662         /*
1663          * In hns3 network engine adding UC and MC mac address with different
1664          * commands with firmware. We need to determine whether the input
1665          * address is a UC or a MC address to call different commands.
1666          * By the way, it is recommended calling the API function named
1667          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1668          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1669          * may affect the specifications of UC mac addresses.
1670          */
1671         if (rte_is_multicast_ether_addr(mac_addr))
1672                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1673         else
1674                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1675
1676         if (ret) {
1677                 rte_spinlock_unlock(&hw->lock);
1678                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1679                                       mac_addr);
1680                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1681                          ret);
1682                 return ret;
1683         }
1684
1685         rte_spinlock_unlock(&hw->lock);
1686
1687         return ret;
1688 }
1689
1690 static int
1691 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1692 {
1693         struct hns3_mac_vlan_tbl_entry_cmd req;
1694         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1695         int ret;
1696
1697         /* check if mac addr is valid */
1698         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1699                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1700                                       mac_addr);
1701                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1702                          mac_str);
1703                 return -EINVAL;
1704         }
1705
1706         memset(&req, 0, sizeof(req));
1707         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1708         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1709         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1710         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1711                 return 0;
1712         else if (ret == 0)
1713                 hns3_update_umv_space(hw, true);
1714
1715         return ret;
1716 }
1717
1718 static void
1719 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1720 {
1721         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722         /* index will be checked by upper level rte interface */
1723         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1724         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1725         int ret;
1726
1727         rte_spinlock_lock(&hw->lock);
1728
1729         if (rte_is_multicast_ether_addr(mac_addr))
1730                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1731         else
1732                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1733         rte_spinlock_unlock(&hw->lock);
1734         if (ret) {
1735                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1736                                       mac_addr);
1737                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1738                          ret);
1739         }
1740 }
1741
1742 static int
1743 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1744                           struct rte_ether_addr *mac_addr)
1745 {
1746         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747         struct rte_ether_addr *oaddr;
1748         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1749         int ret, ret_val;
1750
1751         rte_spinlock_lock(&hw->lock);
1752         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1753         ret = hns3_remove_uc_addr_common(hw, oaddr);
1754         if (ret) {
1755                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1756                                       oaddr);
1757                 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1758                           mac_str, ret);
1759
1760                 rte_spinlock_unlock(&hw->lock);
1761                 return ret;
1762         }
1763
1764         ret = hns3_add_uc_addr_common(hw, mac_addr);
1765         if (ret) {
1766                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1767                                       mac_addr);
1768                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1769                 goto err_add_uc_addr;
1770         }
1771
1772         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1773         if (ret) {
1774                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1775                 goto err_pause_addr_cfg;
1776         }
1777
1778         rte_ether_addr_copy(mac_addr,
1779                             (struct rte_ether_addr *)hw->mac.mac_addr);
1780         rte_spinlock_unlock(&hw->lock);
1781
1782         return 0;
1783
1784 err_pause_addr_cfg:
1785         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1786         if (ret_val) {
1787                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1788                                       mac_addr);
1789                 hns3_warn(hw,
1790                           "Failed to roll back to del setted mac addr(%s): %d",
1791                           mac_str, ret_val);
1792         }
1793
1794 err_add_uc_addr:
1795         ret_val = hns3_add_uc_addr_common(hw, oaddr);
1796         if (ret_val) {
1797                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1798                 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1799                                   mac_str, ret_val);
1800         }
1801         rte_spinlock_unlock(&hw->lock);
1802
1803         return ret;
1804 }
1805
1806 static int
1807 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1808 {
1809         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1810         struct hns3_hw *hw = &hns->hw;
1811         struct rte_ether_addr *addr;
1812         int err = 0;
1813         int ret;
1814         int i;
1815
1816         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1817                 addr = &hw->data->mac_addrs[i];
1818                 if (rte_is_zero_ether_addr(addr))
1819                         continue;
1820                 if (rte_is_multicast_ether_addr(addr))
1821                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1822                               hns3_add_mc_addr(hw, addr);
1823                 else
1824                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1825                               hns3_add_uc_addr_common(hw, addr);
1826
1827                 if (ret) {
1828                         err = ret;
1829                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1830                                               addr);
1831                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1832                                  "ret = %d.", del ? "remove" : "restore",
1833                                  mac_str, i, ret);
1834                 }
1835         }
1836         return err;
1837 }
1838
1839 static void
1840 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1841 {
1842 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1843         uint8_t word_num;
1844         uint8_t bit_num;
1845
1846         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1847                 word_num = vfid / 32;
1848                 bit_num = vfid % 32;
1849                 if (clr)
1850                         desc[1].data[word_num] &=
1851                             rte_cpu_to_le_32(~(1UL << bit_num));
1852                 else
1853                         desc[1].data[word_num] |=
1854                             rte_cpu_to_le_32(1UL << bit_num);
1855         } else {
1856                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1857                 bit_num = vfid % 32;
1858                 if (clr)
1859                         desc[2].data[word_num] &=
1860                             rte_cpu_to_le_32(~(1UL << bit_num));
1861                 else
1862                         desc[2].data[word_num] |=
1863                             rte_cpu_to_le_32(1UL << bit_num);
1864         }
1865 }
1866
1867 static int
1868 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1869 {
1870         struct hns3_mac_vlan_tbl_entry_cmd req;
1871         struct hns3_cmd_desc desc[3];
1872         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1873         uint8_t vf_id;
1874         int ret;
1875
1876         /* Check if mac addr is valid */
1877         if (!rte_is_multicast_ether_addr(mac_addr)) {
1878                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1879                                       mac_addr);
1880                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1881                          mac_str);
1882                 return -EINVAL;
1883         }
1884
1885         memset(&req, 0, sizeof(req));
1886         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1887         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1888         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1889         if (ret) {
1890                 /* This mac addr do not exist, add new entry for it */
1891                 memset(desc[0].data, 0, sizeof(desc[0].data));
1892                 memset(desc[1].data, 0, sizeof(desc[0].data));
1893                 memset(desc[2].data, 0, sizeof(desc[0].data));
1894         }
1895
1896         /*
1897          * In current version VF is not supported when PF is driven by DPDK
1898          * driver, just need to configure parameters for PF vport.
1899          */
1900         vf_id = HNS3_PF_FUNC_ID;
1901         hns3_update_desc_vfid(desc, vf_id, false);
1902         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1903         if (ret) {
1904                 if (ret == -ENOSPC)
1905                         hns3_err(hw, "mc mac vlan table is full");
1906                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1907                                       mac_addr);
1908                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1909         }
1910
1911         return ret;
1912 }
1913
1914 static int
1915 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1916 {
1917         struct hns3_mac_vlan_tbl_entry_cmd req;
1918         struct hns3_cmd_desc desc[3];
1919         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1920         uint8_t vf_id;
1921         int ret;
1922
1923         /* Check if mac addr is valid */
1924         if (!rte_is_multicast_ether_addr(mac_addr)) {
1925                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1926                                       mac_addr);
1927                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1928                          mac_str);
1929                 return -EINVAL;
1930         }
1931
1932         memset(&req, 0, sizeof(req));
1933         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1934         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1935         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1936         if (ret == 0) {
1937                 /*
1938                  * This mac addr exist, remove this handle's VFID for it.
1939                  * In current version VF is not supported when PF is driven by
1940                  * DPDK driver, just need to configure parameters for PF vport.
1941                  */
1942                 vf_id = HNS3_PF_FUNC_ID;
1943                 hns3_update_desc_vfid(desc, vf_id, true);
1944
1945                 /* All the vfid is zero, so need to delete this entry */
1946                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1947         } else if (ret == -ENOENT) {
1948                 /* This mac addr doesn't exist. */
1949                 return 0;
1950         }
1951
1952         if (ret) {
1953                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1954                                       mac_addr);
1955                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1956         }
1957
1958         return ret;
1959 }
1960
1961 static int
1962 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1963                            struct rte_ether_addr *mc_addr_set,
1964                            uint32_t nb_mc_addr)
1965 {
1966         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1967         struct rte_ether_addr *addr;
1968         uint32_t i;
1969         uint32_t j;
1970
1971         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1972                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1973                          "invalid. valid range: 0~%d",
1974                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1975                 return -EINVAL;
1976         }
1977
1978         /* Check if input mac addresses are valid */
1979         for (i = 0; i < nb_mc_addr; i++) {
1980                 addr = &mc_addr_set[i];
1981                 if (!rte_is_multicast_ether_addr(addr)) {
1982                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1983                                               addr);
1984                         hns3_err(hw,
1985                                  "failed to set mc mac addr, addr(%s) invalid.",
1986                                  mac_str);
1987                         return -EINVAL;
1988                 }
1989
1990                 /* Check if there are duplicate addresses */
1991                 for (j = i + 1; j < nb_mc_addr; j++) {
1992                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1993                                 hns3_ether_format_addr(mac_str,
1994                                                       RTE_ETHER_ADDR_FMT_SIZE,
1995                                                       addr);
1996                                 hns3_err(hw, "failed to set mc mac addr, "
1997                                          "addrs invalid. two same addrs(%s).",
1998                                          mac_str);
1999                                 return -EINVAL;
2000                         }
2001                 }
2002
2003                 /*
2004                  * Check if there are duplicate addresses between mac_addrs
2005                  * and mc_addr_set
2006                  */
2007                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2008                         if (rte_is_same_ether_addr(addr,
2009                                                    &hw->data->mac_addrs[j])) {
2010                                 hns3_ether_format_addr(mac_str,
2011                                                       RTE_ETHER_ADDR_FMT_SIZE,
2012                                                       addr);
2013                                 hns3_err(hw, "failed to set mc mac addr, "
2014                                          "addrs invalid. addrs(%s) has already "
2015                                          "configured in mac_addr add API",
2016                                          mac_str);
2017                                 return -EINVAL;
2018                         }
2019                 }
2020         }
2021
2022         return 0;
2023 }
2024
2025 static void
2026 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2027                            struct rte_ether_addr *mc_addr_set,
2028                            int mc_addr_num,
2029                            struct rte_ether_addr *reserved_addr_list,
2030                            int *reserved_addr_num,
2031                            struct rte_ether_addr *add_addr_list,
2032                            int *add_addr_num,
2033                            struct rte_ether_addr *rm_addr_list,
2034                            int *rm_addr_num)
2035 {
2036         struct rte_ether_addr *addr;
2037         int current_addr_num;
2038         int reserved_num = 0;
2039         int add_num = 0;
2040         int rm_num = 0;
2041         int num;
2042         int i;
2043         int j;
2044         bool same_addr;
2045
2046         /* Calculate the mc mac address list that should be removed */
2047         current_addr_num = hw->mc_addrs_num;
2048         for (i = 0; i < current_addr_num; i++) {
2049                 addr = &hw->mc_addrs[i];
2050                 same_addr = false;
2051                 for (j = 0; j < mc_addr_num; j++) {
2052                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2053                                 same_addr = true;
2054                                 break;
2055                         }
2056                 }
2057
2058                 if (!same_addr) {
2059                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2060                         rm_num++;
2061                 } else {
2062                         rte_ether_addr_copy(addr,
2063                                             &reserved_addr_list[reserved_num]);
2064                         reserved_num++;
2065                 }
2066         }
2067
2068         /* Calculate the mc mac address list that should be added */
2069         for (i = 0; i < mc_addr_num; i++) {
2070                 addr = &mc_addr_set[i];
2071                 same_addr = false;
2072                 for (j = 0; j < current_addr_num; j++) {
2073                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2074                                 same_addr = true;
2075                                 break;
2076                         }
2077                 }
2078
2079                 if (!same_addr) {
2080                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2081                         add_num++;
2082                 }
2083         }
2084
2085         /* Reorder the mc mac address list maintained by driver */
2086         for (i = 0; i < reserved_num; i++)
2087                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2088
2089         for (i = 0; i < rm_num; i++) {
2090                 num = reserved_num + i;
2091                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2092         }
2093
2094         *reserved_addr_num = reserved_num;
2095         *add_addr_num = add_num;
2096         *rm_addr_num = rm_num;
2097 }
2098
2099 static int
2100 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2101                           struct rte_ether_addr *mc_addr_set,
2102                           uint32_t nb_mc_addr)
2103 {
2104         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2106         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2107         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2108         struct rte_ether_addr *addr;
2109         int reserved_addr_num;
2110         int add_addr_num;
2111         int rm_addr_num;
2112         int mc_addr_num;
2113         int num;
2114         int ret;
2115         int i;
2116
2117         /* Check if input parameters are valid */
2118         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2119         if (ret)
2120                 return ret;
2121
2122         rte_spinlock_lock(&hw->lock);
2123
2124         /*
2125          * Calculate the mc mac address lists those should be removed and be
2126          * added, Reorder the mc mac address list maintained by driver.
2127          */
2128         mc_addr_num = (int)nb_mc_addr;
2129         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2130                                    reserved_addr_list, &reserved_addr_num,
2131                                    add_addr_list, &add_addr_num,
2132                                    rm_addr_list, &rm_addr_num);
2133
2134         /* Remove mc mac addresses */
2135         for (i = 0; i < rm_addr_num; i++) {
2136                 num = rm_addr_num - i - 1;
2137                 addr = &rm_addr_list[num];
2138                 ret = hns3_remove_mc_addr(hw, addr);
2139                 if (ret) {
2140                         rte_spinlock_unlock(&hw->lock);
2141                         return ret;
2142                 }
2143                 hw->mc_addrs_num--;
2144         }
2145
2146         /* Add mc mac addresses */
2147         for (i = 0; i < add_addr_num; i++) {
2148                 addr = &add_addr_list[i];
2149                 ret = hns3_add_mc_addr(hw, addr);
2150                 if (ret) {
2151                         rte_spinlock_unlock(&hw->lock);
2152                         return ret;
2153                 }
2154
2155                 num = reserved_addr_num + i;
2156                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2157                 hw->mc_addrs_num++;
2158         }
2159         rte_spinlock_unlock(&hw->lock);
2160
2161         return 0;
2162 }
2163
2164 static int
2165 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2166 {
2167         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2168         struct hns3_hw *hw = &hns->hw;
2169         struct rte_ether_addr *addr;
2170         int err = 0;
2171         int ret;
2172         int i;
2173
2174         for (i = 0; i < hw->mc_addrs_num; i++) {
2175                 addr = &hw->mc_addrs[i];
2176                 if (!rte_is_multicast_ether_addr(addr))
2177                         continue;
2178                 if (del)
2179                         ret = hns3_remove_mc_addr(hw, addr);
2180                 else
2181                         ret = hns3_add_mc_addr(hw, addr);
2182                 if (ret) {
2183                         err = ret;
2184                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2185                                               addr);
2186                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2187                                  del ? "Remove" : "Restore", mac_str, ret);
2188                 }
2189         }
2190         return err;
2191 }
2192
2193 static int
2194 hns3_check_mq_mode(struct rte_eth_dev *dev)
2195 {
2196         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2197         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2198         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2200         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2201         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2202         uint8_t num_tc;
2203         int max_tc = 0;
2204         int i;
2205
2206         if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2207             (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2208              tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2209                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2210                          rx_mq_mode, tx_mq_mode);
2211                 return -EOPNOTSUPP;
2212         }
2213
2214         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2215         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2216         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2217                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2218                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2219                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2220                         return -EINVAL;
2221                 }
2222
2223                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2224                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2225                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2226                                  "nb_tcs(%d) != %d or %d in rx direction.",
2227                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2228                         return -EINVAL;
2229                 }
2230
2231                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2232                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2233                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2234                         return -EINVAL;
2235                 }
2236
2237                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2238                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2239                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2240                                          "is not equal to one in tx direction.",
2241                                          i, dcb_rx_conf->dcb_tc[i]);
2242                                 return -EINVAL;
2243                         }
2244                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2245                                 max_tc = dcb_rx_conf->dcb_tc[i];
2246                 }
2247
2248                 num_tc = max_tc + 1;
2249                 if (num_tc > dcb_rx_conf->nb_tcs) {
2250                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2251                                  num_tc, dcb_rx_conf->nb_tcs);
2252                         return -EINVAL;
2253                 }
2254         }
2255
2256         return 0;
2257 }
2258
2259 static int
2260 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2261                            enum hns3_ring_type queue_type, uint16_t queue_id)
2262 {
2263         struct hns3_cmd_desc desc;
2264         struct hns3_ctrl_vector_chain_cmd *req =
2265                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2266         enum hns3_opcode_type op;
2267         uint16_t tqp_type_and_id = 0;
2268         uint16_t type;
2269         uint16_t gl;
2270         int ret;
2271
2272         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2273         hns3_cmd_setup_basic_desc(&desc, op, false);
2274         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2275                                               HNS3_TQP_INT_ID_L_S);
2276         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2277                                               HNS3_TQP_INT_ID_H_S);
2278
2279         if (queue_type == HNS3_RING_TYPE_RX)
2280                 gl = HNS3_RING_GL_RX;
2281         else
2282                 gl = HNS3_RING_GL_TX;
2283
2284         type = queue_type;
2285
2286         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2287                        type);
2288         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2289         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2290                        gl);
2291         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2292         req->int_cause_num = 1;
2293         ret = hns3_cmd_send(hw, &desc, 1);
2294         if (ret) {
2295                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2296                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2297                 return ret;
2298         }
2299
2300         return 0;
2301 }
2302
2303 static int
2304 hns3_init_ring_with_vector(struct hns3_hw *hw)
2305 {
2306         uint16_t vec;
2307         int ret;
2308         int i;
2309
2310         /*
2311          * In hns3 network engine, vector 0 is always the misc interrupt of this
2312          * function, vector 1~N can be used respectively for the queues of the
2313          * function. Tx and Rx queues with the same number share the interrupt
2314          * vector. In the initialization clearing the all hardware mapping
2315          * relationship configurations between queues and interrupt vectors is
2316          * needed, so some error caused by the residual configurations, such as
2317          * the unexpected Tx interrupt, can be avoid.
2318          */
2319         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2320         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2321                 vec = vec - 1; /* the last interrupt is reserved */
2322         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2323         for (i = 0; i < hw->intr_tqps_num; i++) {
2324                 /*
2325                  * Set gap limiter/rate limiter/quanity limiter algorithm
2326                  * configuration for interrupt coalesce of queue's interrupt.
2327                  */
2328                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2329                                        HNS3_TQP_INTR_GL_DEFAULT);
2330                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2331                                        HNS3_TQP_INTR_GL_DEFAULT);
2332                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2333                 /*
2334                  * QL(quantity limiter) is not used currently, just set 0 to
2335                  * close it.
2336                  */
2337                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2338
2339                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2340                                                  HNS3_RING_TYPE_TX, i);
2341                 if (ret) {
2342                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2343                                           "vector: %u, ret=%d", i, vec, ret);
2344                         return ret;
2345                 }
2346
2347                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2348                                                  HNS3_RING_TYPE_RX, i);
2349                 if (ret) {
2350                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2351                                           "vector: %u, ret=%d", i, vec, ret);
2352                         return ret;
2353                 }
2354         }
2355
2356         return 0;
2357 }
2358
2359 static int
2360 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2361 {
2362         struct hns3_adapter *hns = dev->data->dev_private;
2363         struct hns3_hw *hw = &hns->hw;
2364         uint32_t max_rx_pkt_len;
2365         uint16_t mtu;
2366         int ret;
2367
2368         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2369                 return 0;
2370
2371         /*
2372          * If jumbo frames are enabled, MTU needs to be refreshed
2373          * according to the maximum RX packet length.
2374          */
2375         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2376         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2377             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2378                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2379                          "and no more than %u when jumbo frame enabled.",
2380                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2381                          (uint16_t)HNS3_MAX_FRAME_LEN);
2382                 return -EINVAL;
2383         }
2384
2385         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2386         ret = hns3_dev_mtu_set(dev, mtu);
2387         if (ret)
2388                 return ret;
2389         dev->data->mtu = mtu;
2390
2391         return 0;
2392 }
2393
2394 static int
2395 hns3_setup_dcb(struct rte_eth_dev *dev)
2396 {
2397         struct hns3_adapter *hns = dev->data->dev_private;
2398         struct hns3_hw *hw = &hns->hw;
2399         int ret;
2400
2401         if (!hns3_dev_dcb_supported(hw)) {
2402                 hns3_err(hw, "this port does not support dcb configurations.");
2403                 return -EOPNOTSUPP;
2404         }
2405
2406         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2407                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2408                 return -EOPNOTSUPP;
2409         }
2410
2411         ret = hns3_dcb_configure(hns);
2412         if (ret)
2413                 hns3_err(hw, "failed to config dcb: %d", ret);
2414
2415         return ret;
2416 }
2417
2418 static int
2419 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2420 {
2421         int ret;
2422
2423         /*
2424          * Some hardware doesn't support auto-negotiation, but users may not
2425          * configure link_speeds (default 0), which means auto-negotiation.
2426          * In this case, it should return success.
2427          */
2428         if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2429             hw->mac.support_autoneg == 0)
2430                 return 0;
2431
2432         if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2433                 ret = hns3_check_port_speed(hw, link_speeds);
2434                 if (ret)
2435                         return ret;
2436         }
2437
2438         return 0;
2439 }
2440
2441 static int
2442 hns3_check_dev_conf(struct rte_eth_dev *dev)
2443 {
2444         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445         struct rte_eth_conf *conf = &dev->data->dev_conf;
2446         int ret;
2447
2448         ret = hns3_check_mq_mode(dev);
2449         if (ret)
2450                 return ret;
2451
2452         return hns3_check_link_speed(hw, conf->link_speeds);
2453 }
2454
2455 static int
2456 hns3_dev_configure(struct rte_eth_dev *dev)
2457 {
2458         struct hns3_adapter *hns = dev->data->dev_private;
2459         struct rte_eth_conf *conf = &dev->data->dev_conf;
2460         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2461         struct hns3_hw *hw = &hns->hw;
2462         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2463         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2464         struct rte_eth_rss_conf rss_conf;
2465         bool gro_en;
2466         int ret;
2467
2468         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2469
2470         /*
2471          * Some versions of hardware network engine does not support
2472          * individually enable/disable/reset the Tx or Rx queue. These devices
2473          * must enable/disable/reset Tx and Rx queues at the same time. When the
2474          * numbers of Tx queues allocated by upper applications are not equal to
2475          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2476          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2477          * work as usual. But these fake queues are imperceptible, and can not
2478          * be used by upper applications.
2479          */
2480         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2481         if (ret) {
2482                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2483                 hw->cfg_max_queues = 0;
2484                 return ret;
2485         }
2486
2487         hw->adapter_state = HNS3_NIC_CONFIGURING;
2488         ret = hns3_check_dev_conf(dev);
2489         if (ret)
2490                 goto cfg_err;
2491
2492         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2493                 ret = hns3_setup_dcb(dev);
2494                 if (ret)
2495                         goto cfg_err;
2496         }
2497
2498         /* When RSS is not configured, redirect the packet queue 0 */
2499         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2500                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2501                 rss_conf = conf->rx_adv_conf.rss_conf;
2502                 hw->rss_dis_flag = false;
2503                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2504                 if (ret)
2505                         goto cfg_err;
2506         }
2507
2508         ret = hns3_refresh_mtu(dev, conf);
2509         if (ret)
2510                 goto cfg_err;
2511
2512         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2513         if (ret)
2514                 goto cfg_err;
2515
2516         ret = hns3_dev_configure_vlan(dev);
2517         if (ret)
2518                 goto cfg_err;
2519
2520         /* config hardware GRO */
2521         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2522         ret = hns3_config_gro(hw, gro_en);
2523         if (ret)
2524                 goto cfg_err;
2525
2526         hns3_init_rx_ptype_tble(dev);
2527         hw->adapter_state = HNS3_NIC_CONFIGURED;
2528
2529         return 0;
2530
2531 cfg_err:
2532         hw->cfg_max_queues = 0;
2533         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2534         hw->adapter_state = HNS3_NIC_INITIALIZED;
2535
2536         return ret;
2537 }
2538
2539 static int
2540 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2541 {
2542         struct hns3_config_max_frm_size_cmd *req;
2543         struct hns3_cmd_desc desc;
2544
2545         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2546
2547         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2548         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2549         req->min_frm_size = RTE_ETHER_MIN_LEN;
2550
2551         return hns3_cmd_send(hw, &desc, 1);
2552 }
2553
2554 static int
2555 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2556 {
2557         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2558         uint16_t original_mps = hns->pf.mps;
2559         int err;
2560         int ret;
2561
2562         ret = hns3_set_mac_mtu(hw, mps);
2563         if (ret) {
2564                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2565                 return ret;
2566         }
2567
2568         hns->pf.mps = mps;
2569         ret = hns3_buffer_alloc(hw);
2570         if (ret) {
2571                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2572                 goto rollback;
2573         }
2574
2575         return 0;
2576
2577 rollback:
2578         err = hns3_set_mac_mtu(hw, original_mps);
2579         if (err) {
2580                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2581                 return ret;
2582         }
2583         hns->pf.mps = original_mps;
2584
2585         return ret;
2586 }
2587
2588 static int
2589 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2590 {
2591         struct hns3_adapter *hns = dev->data->dev_private;
2592         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2593         struct hns3_hw *hw = &hns->hw;
2594         bool is_jumbo_frame;
2595         int ret;
2596
2597         if (dev->data->dev_started) {
2598                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2599                          "before configuration", dev->data->port_id);
2600                 return -EBUSY;
2601         }
2602
2603         rte_spinlock_lock(&hw->lock);
2604         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2605         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2606
2607         /*
2608          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2609          * assign to "uint16_t" type variable.
2610          */
2611         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2612         if (ret) {
2613                 rte_spinlock_unlock(&hw->lock);
2614                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2615                          dev->data->port_id, mtu, ret);
2616                 return ret;
2617         }
2618
2619         if (is_jumbo_frame)
2620                 dev->data->dev_conf.rxmode.offloads |=
2621                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2622         else
2623                 dev->data->dev_conf.rxmode.offloads &=
2624                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2625         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2626         rte_spinlock_unlock(&hw->lock);
2627
2628         return 0;
2629 }
2630
2631 static uint32_t
2632 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2633 {
2634         uint32_t speed_capa = 0;
2635
2636         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2637                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2638         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2639                 speed_capa |= ETH_LINK_SPEED_10M;
2640         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2641                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2642         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2643                 speed_capa |= ETH_LINK_SPEED_100M;
2644         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2645                 speed_capa |= ETH_LINK_SPEED_1G;
2646
2647         return speed_capa;
2648 }
2649
2650 static uint32_t
2651 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2652 {
2653         uint32_t speed_capa = 0;
2654
2655         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2656                 speed_capa |= ETH_LINK_SPEED_1G;
2657         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2658                 speed_capa |= ETH_LINK_SPEED_10G;
2659         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2660                 speed_capa |= ETH_LINK_SPEED_25G;
2661         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2662                 speed_capa |= ETH_LINK_SPEED_40G;
2663         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2664                 speed_capa |= ETH_LINK_SPEED_50G;
2665         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2666                 speed_capa |= ETH_LINK_SPEED_100G;
2667         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2668                 speed_capa |= ETH_LINK_SPEED_200G;
2669
2670         return speed_capa;
2671 }
2672
2673 static uint32_t
2674 hns3_get_speed_capa(struct hns3_hw *hw)
2675 {
2676         struct hns3_mac *mac = &hw->mac;
2677         uint32_t speed_capa;
2678
2679         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2680                 speed_capa =
2681                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2682         else
2683                 speed_capa =
2684                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2685
2686         if (mac->support_autoneg == 0)
2687                 speed_capa |= ETH_LINK_SPEED_FIXED;
2688
2689         return speed_capa;
2690 }
2691
2692 int
2693 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2694 {
2695         struct hns3_adapter *hns = eth_dev->data->dev_private;
2696         struct hns3_hw *hw = &hns->hw;
2697         uint16_t queue_num = hw->tqps_num;
2698
2699         /*
2700          * In interrupt mode, 'max_rx_queues' is set based on the number of
2701          * MSI-X interrupt resources of the hardware.
2702          */
2703         if (hw->data->dev_conf.intr_conf.rxq == 1)
2704                 queue_num = hw->intr_tqps_num;
2705
2706         info->max_rx_queues = queue_num;
2707         info->max_tx_queues = hw->tqps_num;
2708         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2709         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2710         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2711         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2712         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2713         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2714                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2715                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2716                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2717                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2718                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2719                                  DEV_RX_OFFLOAD_KEEP_CRC |
2720                                  DEV_RX_OFFLOAD_SCATTER |
2721                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2722                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2723                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2724                                  DEV_RX_OFFLOAD_RSS_HASH |
2725                                  DEV_RX_OFFLOAD_TCP_LRO);
2726         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2727                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2728                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2729                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2730                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2731                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2732                                  DEV_TX_OFFLOAD_TCP_TSO |
2733                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2734                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2735                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2736                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2737                                  hns3_txvlan_cap_get(hw));
2738
2739         if (hns3_dev_outer_udp_cksum_supported(hw))
2740                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2741
2742         if (hns3_dev_indep_txrx_supported(hw))
2743                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2744                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2745
2746         if (hns3_dev_ptp_supported(hw))
2747                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2748
2749         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2750                 .nb_max = HNS3_MAX_RING_DESC,
2751                 .nb_min = HNS3_MIN_RING_DESC,
2752                 .nb_align = HNS3_ALIGN_RING_DESC,
2753         };
2754
2755         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2756                 .nb_max = HNS3_MAX_RING_DESC,
2757                 .nb_min = HNS3_MIN_RING_DESC,
2758                 .nb_align = HNS3_ALIGN_RING_DESC,
2759                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2760                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2761         };
2762
2763         info->speed_capa = hns3_get_speed_capa(hw);
2764         info->default_rxconf = (struct rte_eth_rxconf) {
2765                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2766                 /*
2767                  * If there are no available Rx buffer descriptors, incoming
2768                  * packets are always dropped by hardware based on hns3 network
2769                  * engine.
2770                  */
2771                 .rx_drop_en = 1,
2772                 .offloads = 0,
2773         };
2774         info->default_txconf = (struct rte_eth_txconf) {
2775                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2776                 .offloads = 0,
2777         };
2778
2779         info->reta_size = hw->rss_ind_tbl_size;
2780         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2781         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2782
2783         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2784         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2785         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2786         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2787         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2788         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2789
2790         return 0;
2791 }
2792
2793 static int
2794 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2795                     size_t fw_size)
2796 {
2797         struct hns3_adapter *hns = eth_dev->data->dev_private;
2798         struct hns3_hw *hw = &hns->hw;
2799         uint32_t version = hw->fw_version;
2800         int ret;
2801
2802         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2803                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2804                                       HNS3_FW_VERSION_BYTE3_S),
2805                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2806                                       HNS3_FW_VERSION_BYTE2_S),
2807                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2808                                       HNS3_FW_VERSION_BYTE1_S),
2809                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2810                                       HNS3_FW_VERSION_BYTE0_S));
2811         if (ret < 0)
2812                 return -EINVAL;
2813
2814         ret += 1; /* add the size of '\0' */
2815         if (fw_size < (size_t)ret)
2816                 return ret;
2817         else
2818                 return 0;
2819 }
2820
2821 static int
2822 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2823 {
2824         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2825         int ret;
2826
2827         (void)hns3_update_link_status(hw);
2828
2829         ret = hns3_update_link_info(eth_dev);
2830         if (ret)
2831                 hw->mac.link_status = ETH_LINK_DOWN;
2832
2833         return ret;
2834 }
2835
2836 static void
2837 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2838                       struct rte_eth_link *new_link)
2839 {
2840         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2841         struct hns3_mac *mac = &hw->mac;
2842
2843         switch (mac->link_speed) {
2844         case ETH_SPEED_NUM_10M:
2845         case ETH_SPEED_NUM_100M:
2846         case ETH_SPEED_NUM_1G:
2847         case ETH_SPEED_NUM_10G:
2848         case ETH_SPEED_NUM_25G:
2849         case ETH_SPEED_NUM_40G:
2850         case ETH_SPEED_NUM_50G:
2851         case ETH_SPEED_NUM_100G:
2852         case ETH_SPEED_NUM_200G:
2853                 if (mac->link_status)
2854                         new_link->link_speed = mac->link_speed;
2855                 break;
2856         default:
2857                 if (mac->link_status)
2858                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2859                 break;
2860         }
2861
2862         if (!mac->link_status)
2863                 new_link->link_speed = ETH_SPEED_NUM_NONE;
2864
2865         new_link->link_duplex = mac->link_duplex;
2866         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2867         new_link->link_autoneg = mac->link_autoneg;
2868 }
2869
2870 static int
2871 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2872 {
2873 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2874 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2875
2876         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2877         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2878         struct hns3_mac *mac = &hw->mac;
2879         struct rte_eth_link new_link;
2880         int ret;
2881
2882         /* When port is stopped, report link down. */
2883         if (eth_dev->data->dev_started == 0) {
2884                 new_link.link_autoneg = mac->link_autoneg;
2885                 new_link.link_duplex = mac->link_duplex;
2886                 new_link.link_speed = ETH_SPEED_NUM_NONE;
2887                 new_link.link_status = ETH_LINK_DOWN;
2888                 goto out;
2889         }
2890
2891         do {
2892                 ret = hns3_update_port_link_info(eth_dev);
2893                 if (ret) {
2894                         hns3_err(hw, "failed to get port link info, ret = %d.",
2895                                  ret);
2896                         break;
2897                 }
2898
2899                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2900                         break;
2901
2902                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2903         } while (retry_cnt--);
2904
2905         memset(&new_link, 0, sizeof(new_link));
2906         hns3_setup_linkstatus(eth_dev, &new_link);
2907
2908 out:
2909         return rte_eth_linkstatus_set(eth_dev, &new_link);
2910 }
2911
2912 static int
2913 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2914 {
2915         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916         int ret;
2917
2918         /*
2919          * The "tx_pkt_burst" will be restored. But the secondary process does
2920          * not support the mechanism for notifying the primary process.
2921          */
2922         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2923                 hns3_err(hw, "secondary process does not support to set link up.");
2924                 return -ENOTSUP;
2925         }
2926
2927         /*
2928          * If device isn't started Rx/Tx function is still disabled, setting
2929          * link up is not allowed. But it is probably better to return success
2930          * to reduce the impact on the upper layer.
2931          */
2932         if (hw->adapter_state != HNS3_NIC_STARTED) {
2933                 hns3_info(hw, "device isn't started, can't set link up.");
2934                 return 0;
2935         }
2936
2937         if (!hw->set_link_down)
2938                 return 0;
2939
2940         rte_spinlock_lock(&hw->lock);
2941         ret = hns3_cfg_mac_mode(hw, true);
2942         if (ret) {
2943                 rte_spinlock_unlock(&hw->lock);
2944                 hns3_err(hw, "failed to set link up, ret = %d", ret);
2945                 return ret;
2946         }
2947
2948         hw->set_link_down = false;
2949         hns3_start_tx_datapath(dev);
2950         rte_spinlock_unlock(&hw->lock);
2951
2952         return 0;
2953 }
2954
2955 static int
2956 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2957 {
2958         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2959         int ret;
2960
2961         /*
2962          * The "tx_pkt_burst" will be set to dummy function. But the secondary
2963          * process does not support the mechanism for notifying the primary
2964          * process.
2965          */
2966         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2967                 hns3_err(hw, "secondary process does not support to set link down.");
2968                 return -ENOTSUP;
2969         }
2970
2971         /*
2972          * If device isn't started or the API has been called, link status is
2973          * down, return success.
2974          */
2975         if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2976                 return 0;
2977
2978         rte_spinlock_lock(&hw->lock);
2979         hns3_stop_tx_datapath(dev);
2980         ret = hns3_cfg_mac_mode(hw, false);
2981         if (ret) {
2982                 hns3_start_tx_datapath(dev);
2983                 rte_spinlock_unlock(&hw->lock);
2984                 hns3_err(hw, "failed to set link down, ret = %d", ret);
2985                 return ret;
2986         }
2987
2988         hw->set_link_down = true;
2989         rte_spinlock_unlock(&hw->lock);
2990
2991         return 0;
2992 }
2993
2994 static int
2995 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2996 {
2997         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2998         struct hns3_pf *pf = &hns->pf;
2999
3000         if (!(status->pf_state & HNS3_PF_STATE_DONE))
3001                 return -EINVAL;
3002
3003         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
3004
3005         return 0;
3006 }
3007
3008 static int
3009 hns3_query_function_status(struct hns3_hw *hw)
3010 {
3011 #define HNS3_QUERY_MAX_CNT              10
3012 #define HNS3_QUERY_SLEEP_MSCOEND        1
3013         struct hns3_func_status_cmd *req;
3014         struct hns3_cmd_desc desc;
3015         int timeout = 0;
3016         int ret;
3017
3018         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
3019         req = (struct hns3_func_status_cmd *)desc.data;
3020
3021         do {
3022                 ret = hns3_cmd_send(hw, &desc, 1);
3023                 if (ret) {
3024                         PMD_INIT_LOG(ERR, "query function status failed %d",
3025                                      ret);
3026                         return ret;
3027                 }
3028
3029                 /* Check pf reset is done */
3030                 if (req->pf_state)
3031                         break;
3032
3033                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
3034         } while (timeout++ < HNS3_QUERY_MAX_CNT);
3035
3036         return hns3_parse_func_status(hw, req);
3037 }
3038
3039 static int
3040 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
3041 {
3042         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3043         struct hns3_pf *pf = &hns->pf;
3044
3045         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
3046                 /*
3047                  * The total_tqps_num obtained from firmware is maximum tqp
3048                  * numbers of this port, which should be used for PF and VFs.
3049                  * There is no need for pf to have so many tqp numbers in
3050                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3051                  * coming from config file, is assigned to maximum queue number
3052                  * for the PF of this port by user. So users can modify the
3053                  * maximum queue number of PF according to their own application
3054                  * scenarios, which is more flexible to use. In addition, many
3055                  * memories can be saved due to allocating queue statistics
3056                  * room according to the actual number of queues required. The
3057                  * maximum queue number of PF for network engine with
3058                  * revision_id greater than 0x30 is assigned by config file.
3059                  */
3060                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
3061                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
3062                                  "must be greater than 0.",
3063                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
3064                         return -EINVAL;
3065                 }
3066
3067                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3068                                        hw->total_tqps_num);
3069         } else {
3070                 /*
3071                  * Due to the limitation on the number of PF interrupts
3072                  * available, the maximum queue number assigned to PF on
3073                  * the network engine with revision_id 0x21 is 64.
3074                  */
3075                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3076                                        HNS3_MAX_TQP_NUM_HIP08_PF);
3077         }
3078
3079         return 0;
3080 }
3081
3082 static int
3083 hns3_query_pf_resource(struct hns3_hw *hw)
3084 {
3085         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3086         struct hns3_pf *pf = &hns->pf;
3087         struct hns3_pf_res_cmd *req;
3088         struct hns3_cmd_desc desc;
3089         int ret;
3090
3091         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3092         ret = hns3_cmd_send(hw, &desc, 1);
3093         if (ret) {
3094                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3095                 return ret;
3096         }
3097
3098         req = (struct hns3_pf_res_cmd *)desc.data;
3099         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3100                              rte_le_to_cpu_16(req->ext_tqp_num);
3101         ret = hns3_get_pf_max_tqp_num(hw);
3102         if (ret)
3103                 return ret;
3104
3105         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3106         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3107
3108         if (req->tx_buf_size)
3109                 pf->tx_buf_size =
3110                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3111         else
3112                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3113
3114         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3115
3116         if (req->dv_buf_size)
3117                 pf->dv_buf_size =
3118                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3119         else
3120                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3121
3122         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3123
3124         hw->num_msi =
3125                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3126                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3127
3128         return 0;
3129 }
3130
3131 static void
3132 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3133 {
3134         struct hns3_cfg_param_cmd *req;
3135         uint64_t mac_addr_tmp_high;
3136         uint8_t ext_rss_size_max;
3137         uint64_t mac_addr_tmp;
3138         uint32_t i;
3139
3140         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3141
3142         /* get the configuration */
3143         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3144                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3145         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3146                                            HNS3_CFG_TQP_DESC_N_M,
3147                                            HNS3_CFG_TQP_DESC_N_S);
3148
3149         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3150                                        HNS3_CFG_PHY_ADDR_M,
3151                                        HNS3_CFG_PHY_ADDR_S);
3152         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3153                                          HNS3_CFG_MEDIA_TP_M,
3154                                          HNS3_CFG_MEDIA_TP_S);
3155         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3156                                          HNS3_CFG_RX_BUF_LEN_M,
3157                                          HNS3_CFG_RX_BUF_LEN_S);
3158         /* get mac address */
3159         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3160         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3161                                            HNS3_CFG_MAC_ADDR_H_M,
3162                                            HNS3_CFG_MAC_ADDR_H_S);
3163
3164         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3165
3166         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3167                                             HNS3_CFG_DEFAULT_SPEED_M,
3168                                             HNS3_CFG_DEFAULT_SPEED_S);
3169         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3170                                            HNS3_CFG_RSS_SIZE_M,
3171                                            HNS3_CFG_RSS_SIZE_S);
3172
3173         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3174                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3175
3176         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3177         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3178
3179         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3180                                             HNS3_CFG_SPEED_ABILITY_M,
3181                                             HNS3_CFG_SPEED_ABILITY_S);
3182         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3183                                         HNS3_CFG_UMV_TBL_SPACE_M,
3184                                         HNS3_CFG_UMV_TBL_SPACE_S);
3185         if (!cfg->umv_space)
3186                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3187
3188         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3189                                                HNS3_CFG_EXT_RSS_SIZE_M,
3190                                                HNS3_CFG_EXT_RSS_SIZE_S);
3191         /*
3192          * Field ext_rss_size_max obtained from firmware will be more flexible
3193          * for future changes and expansions, which is an exponent of 2, instead
3194          * of reading out directly. If this field is not zero, hns3 PF PMD
3195          * driver uses it as rss_size_max under one TC. Device, whose revision
3196          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3197          * maximum number of queues supported under a TC through this field.
3198          */
3199         if (ext_rss_size_max)
3200                 cfg->rss_size_max = 1U << ext_rss_size_max;
3201 }
3202
3203 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3204  * @hw: pointer to struct hns3_hw
3205  * @hcfg: the config structure to be getted
3206  */
3207 static int
3208 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3209 {
3210         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3211         struct hns3_cfg_param_cmd *req;
3212         uint32_t offset;
3213         uint32_t i;
3214         int ret;
3215
3216         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3217                 offset = 0;
3218                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3219                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3220                                           true);
3221                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3222                                i * HNS3_CFG_RD_LEN_BYTES);
3223                 /* Len should be divided by 4 when send to hardware */
3224                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3225                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3226                 req->offset = rte_cpu_to_le_32(offset);
3227         }
3228
3229         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3230         if (ret) {
3231                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3232                 return ret;
3233         }
3234
3235         hns3_parse_cfg(hcfg, desc);
3236
3237         return 0;
3238 }
3239
3240 static int
3241 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3242 {
3243         switch (speed_cmd) {
3244         case HNS3_CFG_SPEED_10M:
3245                 *speed = ETH_SPEED_NUM_10M;
3246                 break;
3247         case HNS3_CFG_SPEED_100M:
3248                 *speed = ETH_SPEED_NUM_100M;
3249                 break;
3250         case HNS3_CFG_SPEED_1G:
3251                 *speed = ETH_SPEED_NUM_1G;
3252                 break;
3253         case HNS3_CFG_SPEED_10G:
3254                 *speed = ETH_SPEED_NUM_10G;
3255                 break;
3256         case HNS3_CFG_SPEED_25G:
3257                 *speed = ETH_SPEED_NUM_25G;
3258                 break;
3259         case HNS3_CFG_SPEED_40G:
3260                 *speed = ETH_SPEED_NUM_40G;
3261                 break;
3262         case HNS3_CFG_SPEED_50G:
3263                 *speed = ETH_SPEED_NUM_50G;
3264                 break;
3265         case HNS3_CFG_SPEED_100G:
3266                 *speed = ETH_SPEED_NUM_100G;
3267                 break;
3268         case HNS3_CFG_SPEED_200G:
3269                 *speed = ETH_SPEED_NUM_200G;
3270                 break;
3271         default:
3272                 return -EINVAL;
3273         }
3274
3275         return 0;
3276 }
3277
3278 static void
3279 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3280 {
3281         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3282         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3283         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3284         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3285         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3286 }
3287
3288 static void
3289 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3290 {
3291         struct hns3_dev_specs_0_cmd *req0;
3292
3293         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3294
3295         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3296         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3297         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3298         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3299         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3300 }
3301
3302 static int
3303 hns3_check_dev_specifications(struct hns3_hw *hw)
3304 {
3305         if (hw->rss_ind_tbl_size == 0 ||
3306             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3307                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3308                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3309                               HNS3_RSS_IND_TBL_SIZE_MAX);
3310                 return -EINVAL;
3311         }
3312
3313         return 0;
3314 }
3315
3316 static int
3317 hns3_query_dev_specifications(struct hns3_hw *hw)
3318 {
3319         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3320         int ret;
3321         int i;
3322
3323         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3324                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3325                                           true);
3326                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3327         }
3328         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3329
3330         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3331         if (ret)
3332                 return ret;
3333
3334         hns3_parse_dev_specifications(hw, desc);
3335
3336         return hns3_check_dev_specifications(hw);
3337 }
3338
3339 static int
3340 hns3_get_capability(struct hns3_hw *hw)
3341 {
3342         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3343         struct rte_pci_device *pci_dev;
3344         struct hns3_pf *pf = &hns->pf;
3345         struct rte_eth_dev *eth_dev;
3346         uint16_t device_id;
3347         uint8_t revision;
3348         int ret;
3349
3350         eth_dev = &rte_eth_devices[hw->data->port_id];
3351         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3352         device_id = pci_dev->id.device_id;
3353
3354         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3355             device_id == HNS3_DEV_ID_50GE_RDMA ||
3356             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3357             device_id == HNS3_DEV_ID_200G_RDMA)
3358                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3359
3360         /* Get PCI revision id */
3361         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3362                                   HNS3_PCI_REVISION_ID);
3363         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3364                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3365                              ret);
3366                 return -EIO;
3367         }
3368         hw->revision = revision;
3369
3370         if (revision < PCI_REVISION_ID_HIP09_A) {
3371                 hns3_set_default_dev_specifications(hw);
3372                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3373                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3374                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3375                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3376                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3377                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3378                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3379                 hw->rss_info.ipv6_sctp_offload_supported = false;
3380                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3381                 pf->support_multi_tc_pause = false;
3382                 return 0;
3383         }
3384
3385         ret = hns3_query_dev_specifications(hw);
3386         if (ret) {
3387                 PMD_INIT_LOG(ERR,
3388                              "failed to query dev specifications, ret = %d",
3389                              ret);
3390                 return ret;
3391         }
3392
3393         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3394         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3395         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3396         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3397         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3398         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3399         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3400         hw->rss_info.ipv6_sctp_offload_supported = true;
3401         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3402         pf->support_multi_tc_pause = true;
3403
3404         return 0;
3405 }
3406
3407 static int
3408 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3409 {
3410         int ret;
3411
3412         switch (media_type) {
3413         case HNS3_MEDIA_TYPE_COPPER:
3414                 if (!hns3_dev_copper_supported(hw)) {
3415                         PMD_INIT_LOG(ERR,
3416                                      "Media type is copper, not supported.");
3417                         ret = -EOPNOTSUPP;
3418                 } else {
3419                         ret = 0;
3420                 }
3421                 break;
3422         case HNS3_MEDIA_TYPE_FIBER:
3423                 ret = 0;
3424                 break;
3425         case HNS3_MEDIA_TYPE_BACKPLANE:
3426                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3427                 ret = -EOPNOTSUPP;
3428                 break;
3429         default:
3430                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3431                 ret = -EINVAL;
3432                 break;
3433         }
3434
3435         return ret;
3436 }
3437
3438 static int
3439 hns3_get_board_configuration(struct hns3_hw *hw)
3440 {
3441         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3442         struct hns3_pf *pf = &hns->pf;
3443         struct hns3_cfg cfg;
3444         int ret;
3445
3446         ret = hns3_get_board_cfg(hw, &cfg);
3447         if (ret) {
3448                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3449                 return ret;
3450         }
3451
3452         ret = hns3_check_media_type(hw, cfg.media_type);
3453         if (ret)
3454                 return ret;
3455
3456         hw->mac.media_type = cfg.media_type;
3457         hw->rss_size_max = cfg.rss_size_max;
3458         hw->rss_dis_flag = false;
3459         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3460         hw->mac.phy_addr = cfg.phy_addr;
3461         hw->num_tx_desc = cfg.tqp_desc_num;
3462         hw->num_rx_desc = cfg.tqp_desc_num;
3463         hw->dcb_info.num_pg = 1;
3464         hw->dcb_info.hw_pfc_map = 0;
3465
3466         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3467         if (ret) {
3468                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3469                              cfg.default_speed, ret);
3470                 return ret;
3471         }
3472
3473         pf->tc_max = cfg.tc_num;
3474         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3475                 PMD_INIT_LOG(WARNING,
3476                              "Get TC num(%u) from flash, set TC num to 1",
3477                              pf->tc_max);
3478                 pf->tc_max = 1;
3479         }
3480
3481         /* Dev does not support DCB */
3482         if (!hns3_dev_dcb_supported(hw)) {
3483                 pf->tc_max = 1;
3484                 pf->pfc_max = 0;
3485         } else
3486                 pf->pfc_max = pf->tc_max;
3487
3488         hw->dcb_info.num_tc = 1;
3489         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3490                                      hw->tqps_num / hw->dcb_info.num_tc);
3491         hns3_set_bit(hw->hw_tc_map, 0, 1);
3492         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3493
3494         pf->wanted_umv_size = cfg.umv_space;
3495
3496         return ret;
3497 }
3498
3499 static int
3500 hns3_get_configuration(struct hns3_hw *hw)
3501 {
3502         int ret;
3503
3504         ret = hns3_query_function_status(hw);
3505         if (ret) {
3506                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3507                 return ret;
3508         }
3509
3510         /* Get device capability */
3511         ret = hns3_get_capability(hw);
3512         if (ret) {
3513                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3514                 return ret;
3515         }
3516
3517         /* Get pf resource */
3518         ret = hns3_query_pf_resource(hw);
3519         if (ret) {
3520                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3521                 return ret;
3522         }
3523
3524         ret = hns3_get_board_configuration(hw);
3525         if (ret) {
3526                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3527                 return ret;
3528         }
3529
3530         ret = hns3_query_dev_fec_info(hw);
3531         if (ret)
3532                 PMD_INIT_LOG(ERR,
3533                              "failed to query FEC information, ret = %d", ret);
3534
3535         return ret;
3536 }
3537
3538 static int
3539 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3540                       uint16_t tqp_vid, bool is_pf)
3541 {
3542         struct hns3_tqp_map_cmd *req;
3543         struct hns3_cmd_desc desc;
3544         int ret;
3545
3546         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3547
3548         req = (struct hns3_tqp_map_cmd *)desc.data;
3549         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3550         req->tqp_vf = func_id;
3551         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3552         if (!is_pf)
3553                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3554         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3555
3556         ret = hns3_cmd_send(hw, &desc, 1);
3557         if (ret)
3558                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3559
3560         return ret;
3561 }
3562
3563 static int
3564 hns3_map_tqp(struct hns3_hw *hw)
3565 {
3566         int ret;
3567         int i;
3568
3569         /*
3570          * In current version, VF is not supported when PF is driven by DPDK
3571          * driver, so we assign total tqps_num tqps allocated to this port
3572          * to PF.
3573          */
3574         for (i = 0; i < hw->total_tqps_num; i++) {
3575                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3576                 if (ret)
3577                         return ret;
3578         }
3579
3580         return 0;
3581 }
3582
3583 static int
3584 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3585 {
3586         struct hns3_config_mac_speed_dup_cmd *req;
3587         struct hns3_cmd_desc desc;
3588         int ret;
3589
3590         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3591
3592         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3593
3594         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3595
3596         switch (speed) {
3597         case ETH_SPEED_NUM_10M:
3598                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3599                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3600                 break;
3601         case ETH_SPEED_NUM_100M:
3602                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3603                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3604                 break;
3605         case ETH_SPEED_NUM_1G:
3606                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3607                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3608                 break;
3609         case ETH_SPEED_NUM_10G:
3610                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3611                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3612                 break;
3613         case ETH_SPEED_NUM_25G:
3614                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3615                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3616                 break;
3617         case ETH_SPEED_NUM_40G:
3618                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3619                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3620                 break;
3621         case ETH_SPEED_NUM_50G:
3622                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3623                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3624                 break;
3625         case ETH_SPEED_NUM_100G:
3626                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3627                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3628                 break;
3629         case ETH_SPEED_NUM_200G:
3630                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3631                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3632                 break;
3633         default:
3634                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3635                 return -EINVAL;
3636         }
3637
3638         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3639
3640         ret = hns3_cmd_send(hw, &desc, 1);
3641         if (ret)
3642                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3643
3644         return ret;
3645 }
3646
3647 static int
3648 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3649 {
3650         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3651         struct hns3_pf *pf = &hns->pf;
3652         struct hns3_priv_buf *priv;
3653         uint32_t i, total_size;
3654
3655         total_size = pf->pkt_buf_size;
3656
3657         /* alloc tx buffer for all enabled tc */
3658         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3659                 priv = &buf_alloc->priv_buf[i];
3660
3661                 if (hw->hw_tc_map & BIT(i)) {
3662                         if (total_size < pf->tx_buf_size)
3663                                 return -ENOMEM;
3664
3665                         priv->tx_buf_size = pf->tx_buf_size;
3666                 } else
3667                         priv->tx_buf_size = 0;
3668
3669                 total_size -= priv->tx_buf_size;
3670         }
3671
3672         return 0;
3673 }
3674
3675 static int
3676 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3677 {
3678 /* TX buffer size is unit by 128 byte */
3679 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3680 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3681         struct hns3_tx_buff_alloc_cmd *req;
3682         struct hns3_cmd_desc desc;
3683         uint32_t buf_size;
3684         uint32_t i;
3685         int ret;
3686
3687         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3688
3689         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3690         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3691                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3692
3693                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3694                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3695                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3696         }
3697
3698         ret = hns3_cmd_send(hw, &desc, 1);
3699         if (ret)
3700                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3701
3702         return ret;
3703 }
3704
3705 static int
3706 hns3_get_tc_num(struct hns3_hw *hw)
3707 {
3708         int cnt = 0;
3709         uint8_t i;
3710
3711         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3712                 if (hw->hw_tc_map & BIT(i))
3713                         cnt++;
3714         return cnt;
3715 }
3716
3717 static uint32_t
3718 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3719 {
3720         struct hns3_priv_buf *priv;
3721         uint32_t rx_priv = 0;
3722         int i;
3723
3724         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3725                 priv = &buf_alloc->priv_buf[i];
3726                 if (priv->enable)
3727                         rx_priv += priv->buf_size;
3728         }
3729         return rx_priv;
3730 }
3731
3732 static uint32_t
3733 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3734 {
3735         uint32_t total_tx_size = 0;
3736         uint32_t i;
3737
3738         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3739                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3740
3741         return total_tx_size;
3742 }
3743
3744 /* Get the number of pfc enabled TCs, which have private buffer */
3745 static int
3746 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3747 {
3748         struct hns3_priv_buf *priv;
3749         int cnt = 0;
3750         uint8_t i;
3751
3752         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3753                 priv = &buf_alloc->priv_buf[i];
3754                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3755                         cnt++;
3756         }
3757
3758         return cnt;
3759 }
3760
3761 /* Get the number of pfc disabled TCs, which have private buffer */
3762 static int
3763 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3764                          struct hns3_pkt_buf_alloc *buf_alloc)
3765 {
3766         struct hns3_priv_buf *priv;
3767         int cnt = 0;
3768         uint8_t i;
3769
3770         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3771                 priv = &buf_alloc->priv_buf[i];
3772                 if (hw->hw_tc_map & BIT(i) &&
3773                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3774                         cnt++;
3775         }
3776
3777         return cnt;
3778 }
3779
3780 static bool
3781 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3782                   uint32_t rx_all)
3783 {
3784         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3785         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3786         struct hns3_pf *pf = &hns->pf;
3787         uint32_t shared_buf, aligned_mps;
3788         uint32_t rx_priv;
3789         uint8_t tc_num;
3790         uint8_t i;
3791
3792         tc_num = hns3_get_tc_num(hw);
3793         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3794
3795         if (hns3_dev_dcb_supported(hw))
3796                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3797                                         pf->dv_buf_size;
3798         else
3799                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3800                                         + pf->dv_buf_size;
3801
3802         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3803         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3804                              HNS3_BUF_SIZE_UNIT);
3805
3806         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3807         if (rx_all < rx_priv + shared_std)
3808                 return false;
3809
3810         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3811         buf_alloc->s_buf.buf_size = shared_buf;
3812         if (hns3_dev_dcb_supported(hw)) {
3813                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3814                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3815                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3816                                   HNS3_BUF_SIZE_UNIT);
3817         } else {
3818                 buf_alloc->s_buf.self.high =
3819                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3820                 buf_alloc->s_buf.self.low = aligned_mps;
3821         }
3822
3823         if (hns3_dev_dcb_supported(hw)) {
3824                 hi_thrd = shared_buf - pf->dv_buf_size;
3825
3826                 if (tc_num <= NEED_RESERVE_TC_NUM)
3827                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3828                                   BUF_MAX_PERCENT;
3829
3830                 if (tc_num)
3831                         hi_thrd = hi_thrd / tc_num;
3832
3833                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3834                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3835                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3836         } else {
3837                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3838                 lo_thrd = aligned_mps;
3839         }
3840
3841         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3842                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3843                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3844         }
3845
3846         return true;
3847 }
3848
3849 static bool
3850 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3851                      struct hns3_pkt_buf_alloc *buf_alloc)
3852 {
3853         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3854         struct hns3_pf *pf = &hns->pf;
3855         struct hns3_priv_buf *priv;
3856         uint32_t aligned_mps;
3857         uint32_t rx_all;
3858         uint8_t i;
3859
3860         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3861         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3862
3863         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3864                 priv = &buf_alloc->priv_buf[i];
3865
3866                 priv->enable = 0;
3867                 priv->wl.low = 0;
3868                 priv->wl.high = 0;
3869                 priv->buf_size = 0;
3870
3871                 if (!(hw->hw_tc_map & BIT(i)))
3872                         continue;
3873
3874                 priv->enable = 1;
3875                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3876                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3877                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3878                                                 HNS3_BUF_SIZE_UNIT);
3879                 } else {
3880                         priv->wl.low = 0;
3881                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3882                                         aligned_mps;
3883                 }
3884
3885                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3886         }
3887
3888         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3889 }
3890
3891 static bool
3892 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3893                              struct hns3_pkt_buf_alloc *buf_alloc)
3894 {
3895         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3896         struct hns3_pf *pf = &hns->pf;
3897         struct hns3_priv_buf *priv;
3898         int no_pfc_priv_num;
3899         uint32_t rx_all;
3900         uint8_t mask;
3901         int i;
3902
3903         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3904         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3905
3906         /* let the last to be cleared first */
3907         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3908                 priv = &buf_alloc->priv_buf[i];
3909                 mask = BIT((uint8_t)i);
3910                 if (hw->hw_tc_map & mask &&
3911                     !(hw->dcb_info.hw_pfc_map & mask)) {
3912                         /* Clear the no pfc TC private buffer */
3913                         priv->wl.low = 0;
3914                         priv->wl.high = 0;
3915                         priv->buf_size = 0;
3916                         priv->enable = 0;
3917                         no_pfc_priv_num--;
3918                 }
3919
3920                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3921                     no_pfc_priv_num == 0)
3922                         break;
3923         }
3924
3925         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3926 }
3927
3928 static bool
3929 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3930                            struct hns3_pkt_buf_alloc *buf_alloc)
3931 {
3932         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3933         struct hns3_pf *pf = &hns->pf;
3934         struct hns3_priv_buf *priv;
3935         uint32_t rx_all;
3936         int pfc_priv_num;
3937         uint8_t mask;
3938         int i;
3939
3940         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3941         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3942
3943         /* let the last to be cleared first */
3944         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3945                 priv = &buf_alloc->priv_buf[i];
3946                 mask = BIT((uint8_t)i);
3947                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3948                         /* Reduce the number of pfc TC with private buffer */
3949                         priv->wl.low = 0;
3950                         priv->enable = 0;
3951                         priv->wl.high = 0;
3952                         priv->buf_size = 0;
3953                         pfc_priv_num--;
3954                 }
3955                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3956                     pfc_priv_num == 0)
3957                         break;
3958         }
3959
3960         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3961 }
3962
3963 static bool
3964 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3965                           struct hns3_pkt_buf_alloc *buf_alloc)
3966 {
3967 #define COMPENSATE_BUFFER       0x3C00
3968 #define COMPENSATE_HALF_MPS_NUM 5
3969 #define PRIV_WL_GAP             0x1800
3970         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3971         struct hns3_pf *pf = &hns->pf;
3972         uint32_t tc_num = hns3_get_tc_num(hw);
3973         uint32_t half_mps = pf->mps >> 1;
3974         struct hns3_priv_buf *priv;
3975         uint32_t min_rx_priv;
3976         uint32_t rx_priv;
3977         uint8_t i;
3978
3979         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3980         if (tc_num)
3981                 rx_priv = rx_priv / tc_num;
3982
3983         if (tc_num <= NEED_RESERVE_TC_NUM)
3984                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3985
3986         /*
3987          * Minimum value of private buffer in rx direction (min_rx_priv) is
3988          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3989          * buffer if rx_priv is greater than min_rx_priv.
3990          */
3991         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3992                         COMPENSATE_HALF_MPS_NUM * half_mps;
3993         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3994         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3995         if (rx_priv < min_rx_priv)
3996                 return false;
3997
3998         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3999                 priv = &buf_alloc->priv_buf[i];
4000                 priv->enable = 0;
4001                 priv->wl.low = 0;
4002                 priv->wl.high = 0;
4003                 priv->buf_size = 0;
4004
4005                 if (!(hw->hw_tc_map & BIT(i)))
4006                         continue;
4007
4008                 priv->enable = 1;
4009                 priv->buf_size = rx_priv;
4010                 priv->wl.high = rx_priv - pf->dv_buf_size;
4011                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
4012         }
4013
4014         buf_alloc->s_buf.buf_size = 0;
4015
4016         return true;
4017 }
4018
4019 /*
4020  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
4021  * @hw: pointer to struct hns3_hw
4022  * @buf_alloc: pointer to buffer calculation data
4023  * @return: 0: calculate sucessful, negative: fail
4024  */
4025 static int
4026 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4027 {
4028         /* When DCB is not supported, rx private buffer is not allocated. */
4029         if (!hns3_dev_dcb_supported(hw)) {
4030                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4031                 struct hns3_pf *pf = &hns->pf;
4032                 uint32_t rx_all = pf->pkt_buf_size;
4033
4034                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
4035                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
4036                         return -ENOMEM;
4037
4038                 return 0;
4039         }
4040
4041         /*
4042          * Try to allocate privated packet buffer for all TCs without share
4043          * buffer.
4044          */
4045         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
4046                 return 0;
4047
4048         /*
4049          * Try to allocate privated packet buffer for all TCs with share
4050          * buffer.
4051          */
4052         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
4053                 return 0;
4054
4055         /*
4056          * For different application scenes, the enabled port number, TC number
4057          * and no_drop TC number are different. In order to obtain the better
4058          * performance, software could allocate the buffer size and configure
4059          * the waterline by trying to decrease the private buffer size according
4060          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
4061          * enabled tc.
4062          */
4063         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4064                 return 0;
4065
4066         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4067                 return 0;
4068
4069         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4070                 return 0;
4071
4072         return -ENOMEM;
4073 }
4074
4075 static int
4076 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4077 {
4078         struct hns3_rx_priv_buff_cmd *req;
4079         struct hns3_cmd_desc desc;
4080         uint32_t buf_size;
4081         int ret;
4082         int i;
4083
4084         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4085         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4086
4087         /* Alloc private buffer TCs */
4088         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4089                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4090
4091                 req->buf_num[i] =
4092                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4093                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4094         }
4095
4096         buf_size = buf_alloc->s_buf.buf_size;
4097         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4098                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
4099
4100         ret = hns3_cmd_send(hw, &desc, 1);
4101         if (ret)
4102                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4103
4104         return ret;
4105 }
4106
4107 static int
4108 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4109 {
4110 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4111         struct hns3_rx_priv_wl_buf *req;
4112         struct hns3_priv_buf *priv;
4113         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4114         int i, j;
4115         int ret;
4116
4117         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4118                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4119                                           false);
4120                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4121
4122                 /* The first descriptor set the NEXT bit to 1 */
4123                 if (i == 0)
4124                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4125                 else
4126                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4127
4128                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4129                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4130
4131                         priv = &buf_alloc->priv_buf[idx];
4132                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4133                                                         HNS3_BUF_UNIT_S);
4134                         req->tc_wl[j].high |=
4135                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4136                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4137                                                         HNS3_BUF_UNIT_S);
4138                         req->tc_wl[j].low |=
4139                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4140                 }
4141         }
4142
4143         /* Send 2 descriptor at one time */
4144         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4145         if (ret)
4146                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4147                              ret);
4148         return ret;
4149 }
4150
4151 static int
4152 hns3_common_thrd_config(struct hns3_hw *hw,
4153                         struct hns3_pkt_buf_alloc *buf_alloc)
4154 {
4155 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4156         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4157         struct hns3_rx_com_thrd *req;
4158         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4159         struct hns3_tc_thrd *tc;
4160         int tc_idx;
4161         int i, j;
4162         int ret;
4163
4164         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4165                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4166                                           false);
4167                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4168
4169                 /* The first descriptor set the NEXT bit to 1 */
4170                 if (i == 0)
4171                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4172                 else
4173                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4174
4175                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4176                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4177                         tc = &s_buf->tc_thrd[tc_idx];
4178
4179                         req->com_thrd[j].high =
4180                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4181                         req->com_thrd[j].high |=
4182                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4183                         req->com_thrd[j].low =
4184                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4185                         req->com_thrd[j].low |=
4186                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4187                 }
4188         }
4189
4190         /* Send 2 descriptors at one time */
4191         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4192         if (ret)
4193                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4194
4195         return ret;
4196 }
4197
4198 static int
4199 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4200 {
4201         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4202         struct hns3_rx_com_wl *req;
4203         struct hns3_cmd_desc desc;
4204         int ret;
4205
4206         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4207
4208         req = (struct hns3_rx_com_wl *)desc.data;
4209         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4210         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4211
4212         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4213         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4214
4215         ret = hns3_cmd_send(hw, &desc, 1);
4216         if (ret)
4217                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4218
4219         return ret;
4220 }
4221
4222 int
4223 hns3_buffer_alloc(struct hns3_hw *hw)
4224 {
4225         struct hns3_pkt_buf_alloc pkt_buf;
4226         int ret;
4227
4228         memset(&pkt_buf, 0, sizeof(pkt_buf));
4229         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4230         if (ret) {
4231                 PMD_INIT_LOG(ERR,
4232                              "could not calc tx buffer size for all TCs %d",
4233                              ret);
4234                 return ret;
4235         }
4236
4237         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4238         if (ret) {
4239                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4240                 return ret;
4241         }
4242
4243         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4244         if (ret) {
4245                 PMD_INIT_LOG(ERR,
4246                              "could not calc rx priv buffer size for all TCs %d",
4247                              ret);
4248                 return ret;
4249         }
4250
4251         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4252         if (ret) {
4253                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4254                 return ret;
4255         }
4256
4257         if (hns3_dev_dcb_supported(hw)) {
4258                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4259                 if (ret) {
4260                         PMD_INIT_LOG(ERR,
4261                                      "could not configure rx private waterline %d",
4262                                      ret);
4263                         return ret;
4264                 }
4265
4266                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4267                 if (ret) {
4268                         PMD_INIT_LOG(ERR,
4269                                      "could not configure common threshold %d",
4270                                      ret);
4271                         return ret;
4272                 }
4273         }
4274
4275         ret = hns3_common_wl_config(hw, &pkt_buf);
4276         if (ret)
4277                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4278                              ret);
4279
4280         return ret;
4281 }
4282
4283 static int
4284 hns3_mac_init(struct hns3_hw *hw)
4285 {
4286         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4287         struct hns3_mac *mac = &hw->mac;
4288         struct hns3_pf *pf = &hns->pf;
4289         int ret;
4290
4291         pf->support_sfp_query = true;
4292         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4293         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4294         if (ret) {
4295                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4296                 return ret;
4297         }
4298
4299         mac->link_status = ETH_LINK_DOWN;
4300
4301         return hns3_config_mtu(hw, pf->mps);
4302 }
4303
4304 static int
4305 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4306 {
4307 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4308 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4309 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4310 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4311         int return_status;
4312
4313         if (cmdq_resp) {
4314                 PMD_INIT_LOG(ERR,
4315                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4316                              cmdq_resp);
4317                 return -EIO;
4318         }
4319
4320         switch (resp_code) {
4321         case HNS3_ETHERTYPE_SUCCESS_ADD:
4322         case HNS3_ETHERTYPE_ALREADY_ADD:
4323                 return_status = 0;
4324                 break;
4325         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4326                 PMD_INIT_LOG(ERR,
4327                              "add mac ethertype failed for manager table overflow.");
4328                 return_status = -EIO;
4329                 break;
4330         case HNS3_ETHERTYPE_KEY_CONFLICT:
4331                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4332                 return_status = -EIO;
4333                 break;
4334         default:
4335                 PMD_INIT_LOG(ERR,
4336                              "add mac ethertype failed for undefined, code=%u.",
4337                              resp_code);
4338                 return_status = -EIO;
4339                 break;
4340         }
4341
4342         return return_status;
4343 }
4344
4345 static int
4346 hns3_add_mgr_tbl(struct hns3_hw *hw,
4347                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4348 {
4349         struct hns3_cmd_desc desc;
4350         uint8_t resp_code;
4351         uint16_t retval;
4352         int ret;
4353
4354         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4355         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4356
4357         ret = hns3_cmd_send(hw, &desc, 1);
4358         if (ret) {
4359                 PMD_INIT_LOG(ERR,
4360                              "add mac ethertype failed for cmd_send, ret =%d.",
4361                              ret);
4362                 return ret;
4363         }
4364
4365         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4366         retval = rte_le_to_cpu_16(desc.retval);
4367
4368         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4369 }
4370
4371 static void
4372 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4373                      int *table_item_num)
4374 {
4375         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4376
4377         /*
4378          * In current version, we add one item in management table as below:
4379          * 0x0180C200000E -- LLDP MC address
4380          */
4381         tbl = mgr_table;
4382         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4383         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4384         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4385         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4386         tbl->i_port_bitmap = 0x1;
4387         *table_item_num = 1;
4388 }
4389
4390 static int
4391 hns3_init_mgr_tbl(struct hns3_hw *hw)
4392 {
4393 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4394         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4395         int table_item_num;
4396         int ret;
4397         int i;
4398
4399         memset(mgr_table, 0, sizeof(mgr_table));
4400         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4401         for (i = 0; i < table_item_num; i++) {
4402                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4403                 if (ret) {
4404                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4405                                      ret);
4406                         return ret;
4407                 }
4408         }
4409
4410         return 0;
4411 }
4412
4413 static void
4414 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4415                         bool en_mc, bool en_bc, int vport_id)
4416 {
4417         if (!param)
4418                 return;
4419
4420         memset(param, 0, sizeof(struct hns3_promisc_param));
4421         if (en_uc)
4422                 param->enable = HNS3_PROMISC_EN_UC;
4423         if (en_mc)
4424                 param->enable |= HNS3_PROMISC_EN_MC;
4425         if (en_bc)
4426                 param->enable |= HNS3_PROMISC_EN_BC;
4427         param->vf_id = vport_id;
4428 }
4429
4430 static int
4431 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4432 {
4433         struct hns3_promisc_cfg_cmd *req;
4434         struct hns3_cmd_desc desc;
4435         int ret;
4436
4437         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4438
4439         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4440         req->vf_id = param->vf_id;
4441         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4442             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4443
4444         ret = hns3_cmd_send(hw, &desc, 1);
4445         if (ret)
4446                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4447
4448         return ret;
4449 }
4450
4451 static int
4452 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4453 {
4454         struct hns3_promisc_param param;
4455         bool en_bc_pmc = true;
4456         uint8_t vf_id;
4457
4458         /*
4459          * In current version VF is not supported when PF is driven by DPDK
4460          * driver, just need to configure parameters for PF vport.
4461          */
4462         vf_id = HNS3_PF_FUNC_ID;
4463
4464         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4465         return hns3_cmd_set_promisc_mode(hw, &param);
4466 }
4467
4468 static int
4469 hns3_promisc_init(struct hns3_hw *hw)
4470 {
4471         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4472         struct hns3_pf *pf = &hns->pf;
4473         struct hns3_promisc_param param;
4474         uint16_t func_id;
4475         int ret;
4476
4477         ret = hns3_set_promisc_mode(hw, false, false);
4478         if (ret) {
4479                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4480                 return ret;
4481         }
4482
4483         /*
4484          * In current version VFs are not supported when PF is driven by DPDK
4485          * driver. After PF has been taken over by DPDK, the original VF will
4486          * be invalid. So, there is a possibility of entry residues. It should
4487          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4488          * during init.
4489          */
4490         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4491                 hns3_promisc_param_init(&param, false, false, false, func_id);
4492                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4493                 if (ret) {
4494                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4495                                         " ret = %d", func_id, ret);
4496                         return ret;
4497                 }
4498         }
4499
4500         return 0;
4501 }
4502
4503 static void
4504 hns3_promisc_uninit(struct hns3_hw *hw)
4505 {
4506         struct hns3_promisc_param param;
4507         uint16_t func_id;
4508         int ret;
4509
4510         func_id = HNS3_PF_FUNC_ID;
4511
4512         /*
4513          * In current version VFs are not supported when PF is driven by
4514          * DPDK driver, and VFs' promisc mode status has been cleared during
4515          * init and their status will not change. So just clear PF's promisc
4516          * mode status during uninit.
4517          */
4518         hns3_promisc_param_init(&param, false, false, false, func_id);
4519         ret = hns3_cmd_set_promisc_mode(hw, &param);
4520         if (ret)
4521                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4522                                 " uninit, ret = %d", ret);
4523 }
4524
4525 static int
4526 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4527 {
4528         bool allmulti = dev->data->all_multicast ? true : false;
4529         struct hns3_adapter *hns = dev->data->dev_private;
4530         struct hns3_hw *hw = &hns->hw;
4531         uint64_t offloads;
4532         int err;
4533         int ret;
4534
4535         rte_spinlock_lock(&hw->lock);
4536         ret = hns3_set_promisc_mode(hw, true, true);
4537         if (ret) {
4538                 rte_spinlock_unlock(&hw->lock);
4539                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4540                          ret);
4541                 return ret;
4542         }
4543
4544         /*
4545          * When promiscuous mode was enabled, disable the vlan filter to let
4546          * all packets coming in in the receiving direction.
4547          */
4548         offloads = dev->data->dev_conf.rxmode.offloads;
4549         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4550                 ret = hns3_enable_vlan_filter(hns, false);
4551                 if (ret) {
4552                         hns3_err(hw, "failed to enable promiscuous mode due to "
4553                                      "failure to disable vlan filter, ret = %d",
4554                                  ret);
4555                         err = hns3_set_promisc_mode(hw, false, allmulti);
4556                         if (err)
4557                                 hns3_err(hw, "failed to restore promiscuous "
4558                                          "status after disable vlan filter "
4559                                          "failed during enabling promiscuous "
4560                                          "mode, ret = %d", ret);
4561                 }
4562         }
4563
4564         rte_spinlock_unlock(&hw->lock);
4565
4566         return ret;
4567 }
4568
4569 static int
4570 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4571 {
4572         bool allmulti = dev->data->all_multicast ? true : false;
4573         struct hns3_adapter *hns = dev->data->dev_private;
4574         struct hns3_hw *hw = &hns->hw;
4575         uint64_t offloads;
4576         int err;
4577         int ret;
4578
4579         /* If now in all_multicast mode, must remain in all_multicast mode. */
4580         rte_spinlock_lock(&hw->lock);
4581         ret = hns3_set_promisc_mode(hw, false, allmulti);
4582         if (ret) {
4583                 rte_spinlock_unlock(&hw->lock);
4584                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4585                          ret);
4586                 return ret;
4587         }
4588         /* when promiscuous mode was disabled, restore the vlan filter status */
4589         offloads = dev->data->dev_conf.rxmode.offloads;
4590         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4591                 ret = hns3_enable_vlan_filter(hns, true);
4592                 if (ret) {
4593                         hns3_err(hw, "failed to disable promiscuous mode due to"
4594                                  " failure to restore vlan filter, ret = %d",
4595                                  ret);
4596                         err = hns3_set_promisc_mode(hw, true, true);
4597                         if (err)
4598                                 hns3_err(hw, "failed to restore promiscuous "
4599                                          "status after enabling vlan filter "
4600                                          "failed during disabling promiscuous "
4601                                          "mode, ret = %d", ret);
4602                 }
4603         }
4604         rte_spinlock_unlock(&hw->lock);
4605
4606         return ret;
4607 }
4608
4609 static int
4610 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4611 {
4612         struct hns3_adapter *hns = dev->data->dev_private;
4613         struct hns3_hw *hw = &hns->hw;
4614         int ret;
4615
4616         if (dev->data->promiscuous)
4617                 return 0;
4618
4619         rte_spinlock_lock(&hw->lock);
4620         ret = hns3_set_promisc_mode(hw, false, true);
4621         rte_spinlock_unlock(&hw->lock);
4622         if (ret)
4623                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4624                          ret);
4625
4626         return ret;
4627 }
4628
4629 static int
4630 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4631 {
4632         struct hns3_adapter *hns = dev->data->dev_private;
4633         struct hns3_hw *hw = &hns->hw;
4634         int ret;
4635
4636         /* If now in promiscuous mode, must remain in all_multicast mode. */
4637         if (dev->data->promiscuous)
4638                 return 0;
4639
4640         rte_spinlock_lock(&hw->lock);
4641         ret = hns3_set_promisc_mode(hw, false, false);
4642         rte_spinlock_unlock(&hw->lock);
4643         if (ret)
4644                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4645                          ret);
4646
4647         return ret;
4648 }
4649
4650 static int
4651 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4652 {
4653         struct hns3_hw *hw = &hns->hw;
4654         bool allmulti = hw->data->all_multicast ? true : false;
4655         int ret;
4656
4657         if (hw->data->promiscuous) {
4658                 ret = hns3_set_promisc_mode(hw, true, true);
4659                 if (ret)
4660                         hns3_err(hw, "failed to restore promiscuous mode, "
4661                                  "ret = %d", ret);
4662                 return ret;
4663         }
4664
4665         ret = hns3_set_promisc_mode(hw, false, allmulti);
4666         if (ret)
4667                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4668                          ret);
4669         return ret;
4670 }
4671
4672 static int
4673 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4674 {
4675         struct hns3_sfp_info_cmd *resp;
4676         struct hns3_cmd_desc desc;
4677         int ret;
4678
4679         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4680         resp = (struct hns3_sfp_info_cmd *)desc.data;
4681         resp->query_type = HNS3_ACTIVE_QUERY;
4682
4683         ret = hns3_cmd_send(hw, &desc, 1);
4684         if (ret == -EOPNOTSUPP) {
4685                 hns3_warn(hw, "firmware does not support get SFP info,"
4686                           " ret = %d.", ret);
4687                 return ret;
4688         } else if (ret) {
4689                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4690                 return ret;
4691         }
4692
4693         /*
4694          * In some case, the speed of MAC obtained from firmware may be 0, it
4695          * shouldn't be set to mac->speed.
4696          */
4697         if (!rte_le_to_cpu_32(resp->sfp_speed))
4698                 return 0;
4699
4700         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4701         /*
4702          * if resp->supported_speed is 0, it means it's an old version
4703          * firmware, do not update these params.
4704          */
4705         if (resp->supported_speed) {
4706                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4707                 mac_info->supported_speed =
4708                                         rte_le_to_cpu_32(resp->supported_speed);
4709                 mac_info->support_autoneg = resp->autoneg_ability;
4710                 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4711                                         : ETH_LINK_AUTONEG;
4712         } else {
4713                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4714         }
4715
4716         return 0;
4717 }
4718
4719 static uint8_t
4720 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4721 {
4722         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4723                 duplex = ETH_LINK_FULL_DUPLEX;
4724
4725         return duplex;
4726 }
4727
4728 static int
4729 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4730 {
4731         struct hns3_mac *mac = &hw->mac;
4732         int ret;
4733
4734         duplex = hns3_check_speed_dup(duplex, speed);
4735         if (mac->link_speed == speed && mac->link_duplex == duplex)
4736                 return 0;
4737
4738         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4739         if (ret)
4740                 return ret;
4741
4742         ret = hns3_port_shaper_update(hw, speed);
4743         if (ret)
4744                 return ret;
4745
4746         mac->link_speed = speed;
4747         mac->link_duplex = duplex;
4748
4749         return 0;
4750 }
4751
4752 static int
4753 hns3_update_fiber_link_info(struct hns3_hw *hw)
4754 {
4755         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4756         struct hns3_mac *mac = &hw->mac;
4757         struct hns3_mac mac_info;
4758         int ret;
4759
4760         /* If firmware do not support get SFP/qSFP speed, return directly */
4761         if (!pf->support_sfp_query)
4762                 return 0;
4763
4764         memset(&mac_info, 0, sizeof(struct hns3_mac));
4765         ret = hns3_get_sfp_info(hw, &mac_info);
4766         if (ret == -EOPNOTSUPP) {
4767                 pf->support_sfp_query = false;
4768                 return ret;
4769         } else if (ret)
4770                 return ret;
4771
4772         /* Do nothing if no SFP */
4773         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4774                 return 0;
4775
4776         /*
4777          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4778          * to reconfigure the speed of MAC. Otherwise, it indicates
4779          * that the current firmware only supports to obtain the
4780          * speed of the SFP, and the speed of MAC needs to reconfigure.
4781          */
4782         mac->query_type = mac_info.query_type;
4783         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4784                 if (mac_info.link_speed != mac->link_speed) {
4785                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4786                         if (ret)
4787                                 return ret;
4788                 }
4789
4790                 mac->link_speed = mac_info.link_speed;
4791                 mac->supported_speed = mac_info.supported_speed;
4792                 mac->support_autoneg = mac_info.support_autoneg;
4793                 mac->link_autoneg = mac_info.link_autoneg;
4794
4795                 return 0;
4796         }
4797
4798         /* Config full duplex for SFP */
4799         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4800                                       ETH_LINK_FULL_DUPLEX);
4801 }
4802
4803 static void
4804 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4805 {
4806 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4807
4808         struct hns3_phy_params_bd0_cmd *req;
4809         uint32_t supported;
4810
4811         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4812         mac->link_speed = rte_le_to_cpu_32(req->speed);
4813         mac->link_duplex = hns3_get_bit(req->duplex,
4814                                            HNS3_PHY_DUPLEX_CFG_B);
4815         mac->link_autoneg = hns3_get_bit(req->autoneg,
4816                                            HNS3_PHY_AUTONEG_CFG_B);
4817         mac->advertising = rte_le_to_cpu_32(req->advertising);
4818         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4819         supported = rte_le_to_cpu_32(req->supported);
4820         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4821         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4822 }
4823
4824 static int
4825 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4826 {
4827         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4828         uint16_t i;
4829         int ret;
4830
4831         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4832                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4833                                           true);
4834                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4835         }
4836         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4837
4838         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4839         if (ret) {
4840                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4841                 return ret;
4842         }
4843
4844         hns3_parse_copper_phy_params(desc, mac);
4845
4846         return 0;
4847 }
4848
4849 static int
4850 hns3_update_copper_link_info(struct hns3_hw *hw)
4851 {
4852         struct hns3_mac *mac = &hw->mac;
4853         struct hns3_mac mac_info;
4854         int ret;
4855
4856         memset(&mac_info, 0, sizeof(struct hns3_mac));
4857         ret = hns3_get_copper_phy_params(hw, &mac_info);
4858         if (ret)
4859                 return ret;
4860
4861         if (mac_info.link_speed != mac->link_speed) {
4862                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4863                 if (ret)
4864                         return ret;
4865         }
4866
4867         mac->link_speed = mac_info.link_speed;
4868         mac->link_duplex = mac_info.link_duplex;
4869         mac->link_autoneg = mac_info.link_autoneg;
4870         mac->supported_speed = mac_info.supported_speed;
4871         mac->advertising = mac_info.advertising;
4872         mac->lp_advertising = mac_info.lp_advertising;
4873         mac->support_autoneg = mac_info.support_autoneg;
4874
4875         return 0;
4876 }
4877
4878 static int
4879 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4880 {
4881         struct hns3_adapter *hns = eth_dev->data->dev_private;
4882         struct hns3_hw *hw = &hns->hw;
4883         int ret = 0;
4884
4885         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4886                 ret = hns3_update_copper_link_info(hw);
4887         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4888                 ret = hns3_update_fiber_link_info(hw);
4889
4890         return ret;
4891 }
4892
4893 static int
4894 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4895 {
4896         struct hns3_config_mac_mode_cmd *req;
4897         struct hns3_cmd_desc desc;
4898         uint32_t loop_en = 0;
4899         uint8_t val = 0;
4900         int ret;
4901
4902         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4903
4904         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4905         if (enable)
4906                 val = 1;
4907         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4908         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4909         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4910         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4911         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4912         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4913         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4914         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4915         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4916         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4917
4918         /*
4919          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4920          * when receiving frames. Otherwise, CRC will be stripped.
4921          */
4922         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4923                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4924         else
4925                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4926         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4927         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4928         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4929         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4930
4931         ret = hns3_cmd_send(hw, &desc, 1);
4932         if (ret)
4933                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4934
4935         return ret;
4936 }
4937
4938 static int
4939 hns3_get_mac_link_status(struct hns3_hw *hw)
4940 {
4941         struct hns3_link_status_cmd *req;
4942         struct hns3_cmd_desc desc;
4943         int link_status;
4944         int ret;
4945
4946         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4947         ret = hns3_cmd_send(hw, &desc, 1);
4948         if (ret) {
4949                 hns3_err(hw, "get link status cmd failed %d", ret);
4950                 return ETH_LINK_DOWN;
4951         }
4952
4953         req = (struct hns3_link_status_cmd *)desc.data;
4954         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4955
4956         return !!link_status;
4957 }
4958
4959 static bool
4960 hns3_update_link_status(struct hns3_hw *hw)
4961 {
4962         int state;
4963
4964         state = hns3_get_mac_link_status(hw);
4965         if (state != hw->mac.link_status) {
4966                 hw->mac.link_status = state;
4967                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4968                 return true;
4969         }
4970
4971         return false;
4972 }
4973
4974 void
4975 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4976 {
4977         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4978         struct rte_eth_link new_link;
4979         int ret;
4980
4981         if (query)
4982                 hns3_update_port_link_info(dev);
4983
4984         memset(&new_link, 0, sizeof(new_link));
4985         hns3_setup_linkstatus(dev, &new_link);
4986
4987         ret = rte_eth_linkstatus_set(dev, &new_link);
4988         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4989                 hns3_start_report_lse(dev);
4990 }
4991
4992 static void
4993 hns3_service_handler(void *param)
4994 {
4995         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4996         struct hns3_adapter *hns = eth_dev->data->dev_private;
4997         struct hns3_hw *hw = &hns->hw;
4998
4999         if (!hns3_is_reset_pending(hns))
5000                 hns3_update_linkstatus_and_event(hw, true);
5001         else
5002                 hns3_warn(hw, "Cancel the query when reset is pending");
5003
5004         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
5005 }
5006
5007 static int
5008 hns3_init_hardware(struct hns3_adapter *hns)
5009 {
5010         struct hns3_hw *hw = &hns->hw;
5011         int ret;
5012
5013         ret = hns3_map_tqp(hw);
5014         if (ret) {
5015                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
5016                 return ret;
5017         }
5018
5019         ret = hns3_init_umv_space(hw);
5020         if (ret) {
5021                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
5022                 return ret;
5023         }
5024
5025         ret = hns3_mac_init(hw);
5026         if (ret) {
5027                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
5028                 goto err_mac_init;
5029         }
5030
5031         ret = hns3_init_mgr_tbl(hw);
5032         if (ret) {
5033                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
5034                 goto err_mac_init;
5035         }
5036
5037         ret = hns3_promisc_init(hw);
5038         if (ret) {
5039                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
5040                              ret);
5041                 goto err_mac_init;
5042         }
5043
5044         ret = hns3_init_vlan_config(hns);
5045         if (ret) {
5046                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
5047                 goto err_mac_init;
5048         }
5049
5050         ret = hns3_dcb_init(hw);
5051         if (ret) {
5052                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
5053                 goto err_mac_init;
5054         }
5055
5056         ret = hns3_init_fd_config(hns);
5057         if (ret) {
5058                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
5059                 goto err_mac_init;
5060         }
5061
5062         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
5063         if (ret) {
5064                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5065                 goto err_mac_init;
5066         }
5067
5068         ret = hns3_config_gro(hw, false);
5069         if (ret) {
5070                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5071                 goto err_mac_init;
5072         }
5073
5074         /*
5075          * In the initialization clearing the all hardware mapping relationship
5076          * configurations between queues and interrupt vectors is needed, so
5077          * some error caused by the residual configurations, such as the
5078          * unexpected interrupt, can be avoid.
5079          */
5080         ret = hns3_init_ring_with_vector(hw);
5081         if (ret) {
5082                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5083                 goto err_mac_init;
5084         }
5085
5086         return 0;
5087
5088 err_mac_init:
5089         hns3_uninit_umv_space(hw);
5090         return ret;
5091 }
5092
5093 static int
5094 hns3_clear_hw(struct hns3_hw *hw)
5095 {
5096         struct hns3_cmd_desc desc;
5097         int ret;
5098
5099         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5100
5101         ret = hns3_cmd_send(hw, &desc, 1);
5102         if (ret && ret != -EOPNOTSUPP)
5103                 return ret;
5104
5105         return 0;
5106 }
5107
5108 static void
5109 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5110 {
5111         uint32_t val;
5112
5113         /*
5114          * The new firmware support report more hardware error types by
5115          * msix mode. These errors are defined as RAS errors in hardware
5116          * and belong to a different type from the MSI-x errors processed
5117          * by the network driver.
5118          *
5119          * Network driver should open the new error report on initialization.
5120          */
5121         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5122         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5123         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5124 }
5125
5126 static uint32_t
5127 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5128 {
5129         struct hns3_mac *mac = &hw->mac;
5130
5131         switch (mac->link_speed) {
5132         case ETH_SPEED_NUM_1G:
5133                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5134         case ETH_SPEED_NUM_10G:
5135                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5136         case ETH_SPEED_NUM_25G:
5137                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5138         case ETH_SPEED_NUM_40G:
5139                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5140         case ETH_SPEED_NUM_50G:
5141                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5142         case ETH_SPEED_NUM_100G:
5143                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5144         case ETH_SPEED_NUM_200G:
5145                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5146         default:
5147                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5148                 return 0;
5149         }
5150 }
5151
5152 /*
5153  * Validity of supported_speed for firber and copper media type can be
5154  * guaranteed by the following policy:
5155  * Copper:
5156  *       Although the initialization of the phy in the firmware may not be
5157  *       completed, the firmware can guarantees that the supported_speed is
5158  *       an valid value.
5159  * Firber:
5160  *       If the version of firmware supports the acitive query way of the
5161  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5162  *       through it. If unsupported, use the SFP's speed as the value of the
5163  *       supported_speed.
5164  */
5165 static int
5166 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5167 {
5168         struct hns3_adapter *hns = eth_dev->data->dev_private;
5169         struct hns3_hw *hw = &hns->hw;
5170         struct hns3_mac *mac = &hw->mac;
5171         int ret;
5172
5173         ret = hns3_update_link_info(eth_dev);
5174         if (ret)
5175                 return ret;
5176
5177         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5178                 /*
5179                  * Some firmware does not support the report of supported_speed,
5180                  * and only report the effective speed of SFP. In this case, it
5181                  * is necessary to use the SFP's speed as the supported_speed.
5182                  */
5183                 if (mac->supported_speed == 0)
5184                         mac->supported_speed =
5185                                 hns3_set_firber_default_support_speed(hw);
5186         }
5187
5188         return 0;
5189 }
5190
5191 static void
5192 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5193 {
5194         struct hns3_mac *mac = &hns->hw.mac;
5195
5196         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5197                 hns->pf.support_fc_autoneg = true;
5198                 return;
5199         }
5200
5201         /*
5202          * Flow control auto-negotiation requires the cooperation of the driver
5203          * and firmware. Currently, the optical port does not support flow
5204          * control auto-negotiation.
5205          */
5206         hns->pf.support_fc_autoneg = false;
5207 }
5208
5209 static int
5210 hns3_init_pf(struct rte_eth_dev *eth_dev)
5211 {
5212         struct rte_device *dev = eth_dev->device;
5213         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5214         struct hns3_adapter *hns = eth_dev->data->dev_private;
5215         struct hns3_hw *hw = &hns->hw;
5216         int ret;
5217
5218         PMD_INIT_FUNC_TRACE();
5219
5220         /* Get hardware io base address from pcie BAR2 IO space */
5221         hw->io_base = pci_dev->mem_resource[2].addr;
5222
5223         /* Firmware command queue initialize */
5224         ret = hns3_cmd_init_queue(hw);
5225         if (ret) {
5226                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5227                 goto err_cmd_init_queue;
5228         }
5229
5230         hns3_clear_all_event_cause(hw);
5231
5232         /* Firmware command initialize */
5233         ret = hns3_cmd_init(hw);
5234         if (ret) {
5235                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5236                 goto err_cmd_init;
5237         }
5238
5239         hns3_tx_push_init(eth_dev);
5240
5241         /*
5242          * To ensure that the hardware environment is clean during
5243          * initialization, the driver actively clear the hardware environment
5244          * during initialization, including PF and corresponding VFs' vlan, mac,
5245          * flow table configurations, etc.
5246          */
5247         ret = hns3_clear_hw(hw);
5248         if (ret) {
5249                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5250                 goto err_cmd_init;
5251         }
5252
5253         /* Hardware statistics of imissed registers cleared. */
5254         ret = hns3_update_imissed_stats(hw, true);
5255         if (ret) {
5256                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5257                 goto err_cmd_init;
5258         }
5259
5260         hns3_config_all_msix_error(hw, true);
5261
5262         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5263                                          hns3_interrupt_handler,
5264                                          eth_dev);
5265         if (ret) {
5266                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5267                 goto err_intr_callback_register;
5268         }
5269
5270         ret = hns3_ptp_init(hw);
5271         if (ret)
5272                 goto err_get_config;
5273
5274         /* Enable interrupt */
5275         rte_intr_enable(&pci_dev->intr_handle);
5276         hns3_pf_enable_irq0(hw);
5277
5278         /* Get configuration */
5279         ret = hns3_get_configuration(hw);
5280         if (ret) {
5281                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5282                 goto err_get_config;
5283         }
5284
5285         ret = hns3_tqp_stats_init(hw);
5286         if (ret)
5287                 goto err_get_config;
5288
5289         ret = hns3_init_hardware(hns);
5290         if (ret) {
5291                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5292                 goto err_init_hw;
5293         }
5294
5295         /* Initialize flow director filter list & hash */
5296         ret = hns3_fdir_filter_init(hns);
5297         if (ret) {
5298                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5299                 goto err_fdir;
5300         }
5301
5302         hns3_rss_set_default_args(hw);
5303
5304         ret = hns3_enable_hw_error_intr(hns, true);
5305         if (ret) {
5306                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5307                              ret);
5308                 goto err_enable_intr;
5309         }
5310
5311         ret = hns3_get_port_supported_speed(eth_dev);
5312         if (ret) {
5313                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5314                              "by device, ret = %d.", ret);
5315                 goto err_supported_speed;
5316         }
5317
5318         hns3_get_fc_autoneg_capability(hns);
5319
5320         hns3_tm_conf_init(eth_dev);
5321
5322         return 0;
5323
5324 err_supported_speed:
5325         (void)hns3_enable_hw_error_intr(hns, false);
5326 err_enable_intr:
5327         hns3_fdir_filter_uninit(hns);
5328 err_fdir:
5329         hns3_uninit_umv_space(hw);
5330 err_init_hw:
5331         hns3_tqp_stats_uninit(hw);
5332 err_get_config:
5333         hns3_pf_disable_irq0(hw);
5334         rte_intr_disable(&pci_dev->intr_handle);
5335         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5336                              eth_dev);
5337 err_intr_callback_register:
5338 err_cmd_init:
5339         hns3_cmd_uninit(hw);
5340         hns3_cmd_destroy_queue(hw);
5341 err_cmd_init_queue:
5342         hw->io_base = NULL;
5343
5344         return ret;
5345 }
5346
5347 static void
5348 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5349 {
5350         struct hns3_adapter *hns = eth_dev->data->dev_private;
5351         struct rte_device *dev = eth_dev->device;
5352         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5353         struct hns3_hw *hw = &hns->hw;
5354
5355         PMD_INIT_FUNC_TRACE();
5356
5357         hns3_tm_conf_uninit(eth_dev);
5358         hns3_enable_hw_error_intr(hns, false);
5359         hns3_rss_uninit(hns);
5360         (void)hns3_config_gro(hw, false);
5361         hns3_promisc_uninit(hw);
5362         hns3_flow_uninit(eth_dev);
5363         hns3_fdir_filter_uninit(hns);
5364         hns3_uninit_umv_space(hw);
5365         hns3_tqp_stats_uninit(hw);
5366         hns3_config_mac_tnl_int(hw, false);
5367         hns3_pf_disable_irq0(hw);
5368         rte_intr_disable(&pci_dev->intr_handle);
5369         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5370                              eth_dev);
5371         hns3_config_all_msix_error(hw, false);
5372         hns3_cmd_uninit(hw);
5373         hns3_cmd_destroy_queue(hw);
5374         hw->io_base = NULL;
5375 }
5376
5377 static uint32_t
5378 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5379 {
5380         uint32_t speed_bit;
5381
5382         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5383         case ETH_LINK_SPEED_10M:
5384                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5385                 break;
5386         case ETH_LINK_SPEED_10M_HD:
5387                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5388                 break;
5389         case ETH_LINK_SPEED_100M:
5390                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5391                 break;
5392         case ETH_LINK_SPEED_100M_HD:
5393                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5394                 break;
5395         case ETH_LINK_SPEED_1G:
5396                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5397                 break;
5398         default:
5399                 speed_bit = 0;
5400                 break;
5401         }
5402
5403         return speed_bit;
5404 }
5405
5406 static uint32_t
5407 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5408 {
5409         uint32_t speed_bit;
5410
5411         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5412         case ETH_LINK_SPEED_1G:
5413                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5414                 break;
5415         case ETH_LINK_SPEED_10G:
5416                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5417                 break;
5418         case ETH_LINK_SPEED_25G:
5419                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5420                 break;
5421         case ETH_LINK_SPEED_40G:
5422                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5423                 break;
5424         case ETH_LINK_SPEED_50G:
5425                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5426                 break;
5427         case ETH_LINK_SPEED_100G:
5428                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5429                 break;
5430         case ETH_LINK_SPEED_200G:
5431                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5432                 break;
5433         default:
5434                 speed_bit = 0;
5435                 break;
5436         }
5437
5438         return speed_bit;
5439 }
5440
5441 static int
5442 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5443 {
5444         struct hns3_mac *mac = &hw->mac;
5445         uint32_t supported_speed = mac->supported_speed;
5446         uint32_t speed_bit = 0;
5447
5448         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5449                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5450         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5451                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5452
5453         if (!(speed_bit & supported_speed)) {
5454                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5455                          link_speeds);
5456                 return -EINVAL;
5457         }
5458
5459         return 0;
5460 }
5461
5462 static inline uint32_t
5463 hns3_get_link_speed(uint32_t link_speeds)
5464 {
5465         uint32_t speed = ETH_SPEED_NUM_NONE;
5466
5467         if (link_speeds & ETH_LINK_SPEED_10M ||
5468             link_speeds & ETH_LINK_SPEED_10M_HD)
5469                 speed = ETH_SPEED_NUM_10M;
5470         if (link_speeds & ETH_LINK_SPEED_100M ||
5471             link_speeds & ETH_LINK_SPEED_100M_HD)
5472                 speed = ETH_SPEED_NUM_100M;
5473         if (link_speeds & ETH_LINK_SPEED_1G)
5474                 speed = ETH_SPEED_NUM_1G;
5475         if (link_speeds & ETH_LINK_SPEED_10G)
5476                 speed = ETH_SPEED_NUM_10G;
5477         if (link_speeds & ETH_LINK_SPEED_25G)
5478                 speed = ETH_SPEED_NUM_25G;
5479         if (link_speeds & ETH_LINK_SPEED_40G)
5480                 speed = ETH_SPEED_NUM_40G;
5481         if (link_speeds & ETH_LINK_SPEED_50G)
5482                 speed = ETH_SPEED_NUM_50G;
5483         if (link_speeds & ETH_LINK_SPEED_100G)
5484                 speed = ETH_SPEED_NUM_100G;
5485         if (link_speeds & ETH_LINK_SPEED_200G)
5486                 speed = ETH_SPEED_NUM_200G;
5487
5488         return speed;
5489 }
5490
5491 static uint8_t
5492 hns3_get_link_duplex(uint32_t link_speeds)
5493 {
5494         if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5495             (link_speeds & ETH_LINK_SPEED_100M_HD))
5496                 return ETH_LINK_HALF_DUPLEX;
5497         else
5498                 return ETH_LINK_FULL_DUPLEX;
5499 }
5500
5501 static int
5502 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5503                                 struct hns3_set_link_speed_cfg *cfg)
5504 {
5505         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5506         struct hns3_phy_params_bd0_cmd *req;
5507         uint16_t i;
5508
5509         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5510                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5511                                           false);
5512                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5513         }
5514         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5515         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5516         req->autoneg = cfg->autoneg;
5517
5518         /*
5519          * The full speed capability is used to negotiate when
5520          * auto-negotiation is enabled.
5521          */
5522         if (cfg->autoneg) {
5523                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5524                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5525                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5526                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5527                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5528         } else {
5529                 req->speed = cfg->speed;
5530                 req->duplex = cfg->duplex;
5531         }
5532
5533         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5534 }
5535
5536 static int
5537 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5538 {
5539         struct hns3_config_auto_neg_cmd *req;
5540         struct hns3_cmd_desc desc;
5541         uint32_t flag = 0;
5542         int ret;
5543
5544         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5545
5546         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5547         if (enable)
5548                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5549         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5550
5551         ret = hns3_cmd_send(hw, &desc, 1);
5552         if (ret)
5553                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5554
5555         return ret;
5556 }
5557
5558 static int
5559 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5560                                struct hns3_set_link_speed_cfg *cfg)
5561 {
5562         int ret;
5563
5564         if (hw->mac.support_autoneg) {
5565                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5566                 if (ret) {
5567                         hns3_err(hw, "failed to configure auto-negotiation.");
5568                         return ret;
5569                 }
5570
5571                 /*
5572                  * To enable auto-negotiation, we only need to open the switch
5573                  * of auto-negotiation, then firmware sets all speed
5574                  * capabilities.
5575                  */
5576                 if (cfg->autoneg)
5577                         return 0;
5578         }
5579
5580         /*
5581          * Some hardware doesn't support auto-negotiation, but users may not
5582          * configure link_speeds (default 0), which means auto-negotiation.
5583          * In this case, a warning message need to be printed, instead of
5584          * an error.
5585          */
5586         if (cfg->autoneg) {
5587                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
5588                 return 0;
5589         }
5590
5591         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5592 }
5593
5594 static int
5595 hns3_set_port_link_speed(struct hns3_hw *hw,
5596                          struct hns3_set_link_speed_cfg *cfg)
5597 {
5598         int ret;
5599
5600         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5601 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5602                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5603                 if (pf->is_tmp_phy)
5604                         return 0;
5605 #endif
5606
5607                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5608                 if (ret) {
5609                         hns3_err(hw, "failed to set copper port link speed,"
5610                                  "ret = %d.", ret);
5611                         return ret;
5612                 }
5613         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5614                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5615                 if (ret) {
5616                         hns3_err(hw, "failed to set fiber port link speed,"
5617                                  "ret = %d.", ret);
5618                         return ret;
5619                 }
5620         }
5621
5622         return 0;
5623 }
5624
5625 static int
5626 hns3_apply_link_speed(struct hns3_hw *hw)
5627 {
5628         struct rte_eth_conf *conf = &hw->data->dev_conf;
5629         struct hns3_set_link_speed_cfg cfg;
5630
5631         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5632         cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5633                         ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5634         if (cfg.autoneg != ETH_LINK_AUTONEG) {
5635                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5636                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5637         }
5638
5639         return hns3_set_port_link_speed(hw, &cfg);
5640 }
5641
5642 static int
5643 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5644 {
5645         struct hns3_hw *hw = &hns->hw;
5646         bool link_en;
5647         int ret;
5648
5649         ret = hns3_update_queue_map_configure(hns);
5650         if (ret) {
5651                 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5652                          ret);
5653                 return ret;
5654         }
5655
5656         /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5657         ret = hns3_tm_conf_update(hw);
5658         if (ret) {
5659                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5660                 return ret;
5661         }
5662
5663         hns3_enable_rxd_adv_layout(hw);
5664
5665         ret = hns3_init_queues(hns, reset_queue);
5666         if (ret) {
5667                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5668                 return ret;
5669         }
5670
5671         link_en = hw->set_link_down ? false : true;
5672         ret = hns3_cfg_mac_mode(hw, link_en);
5673         if (ret) {
5674                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5675                 goto err_config_mac_mode;
5676         }
5677
5678         ret = hns3_apply_link_speed(hw);
5679         if (ret)
5680                 goto err_set_link_speed;
5681
5682         return 0;
5683
5684 err_set_link_speed:
5685         (void)hns3_cfg_mac_mode(hw, false);
5686
5687 err_config_mac_mode:
5688         hns3_dev_release_mbufs(hns);
5689         /*
5690          * Here is exception handling, hns3_reset_all_tqps will have the
5691          * corresponding error message if it is handled incorrectly, so it is
5692          * not necessary to check hns3_reset_all_tqps return value, here keep
5693          * ret as the error code causing the exception.
5694          */
5695         (void)hns3_reset_all_tqps(hns);
5696         return ret;
5697 }
5698
5699 static int
5700 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5701 {
5702         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5703         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5704         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5706         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5707         uint32_t intr_vector;
5708         uint16_t q_id;
5709         int ret;
5710
5711         /*
5712          * hns3 needs a separate interrupt to be used as event interrupt which
5713          * could not be shared with task queue pair, so KERNEL drivers need
5714          * support multiple interrupt vectors.
5715          */
5716         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5717             !rte_intr_cap_multiple(intr_handle))
5718                 return 0;
5719
5720         rte_intr_disable(intr_handle);
5721         intr_vector = hw->used_rx_queues;
5722         /* creates event fd for each intr vector when MSIX is used */
5723         if (rte_intr_efd_enable(intr_handle, intr_vector))
5724                 return -EINVAL;
5725
5726         if (intr_handle->intr_vec == NULL) {
5727                 intr_handle->intr_vec =
5728                         rte_zmalloc("intr_vec",
5729                                     hw->used_rx_queues * sizeof(int), 0);
5730                 if (intr_handle->intr_vec == NULL) {
5731                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5732                                         hw->used_rx_queues);
5733                         ret = -ENOMEM;
5734                         goto alloc_intr_vec_error;
5735                 }
5736         }
5737
5738         if (rte_intr_allow_others(intr_handle)) {
5739                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5740                 base = RTE_INTR_VEC_RXTX_OFFSET;
5741         }
5742
5743         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5744                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5745                                                  HNS3_RING_TYPE_RX, q_id);
5746                 if (ret)
5747                         goto bind_vector_error;
5748                 intr_handle->intr_vec[q_id] = vec;
5749                 /*
5750                  * If there are not enough efds (e.g. not enough interrupt),
5751                  * remaining queues will be bond to the last interrupt.
5752                  */
5753                 if (vec < base + intr_handle->nb_efd - 1)
5754                         vec++;
5755         }
5756         rte_intr_enable(intr_handle);
5757         return 0;
5758
5759 bind_vector_error:
5760         rte_free(intr_handle->intr_vec);
5761         intr_handle->intr_vec = NULL;
5762 alloc_intr_vec_error:
5763         rte_intr_efd_disable(intr_handle);
5764         return ret;
5765 }
5766
5767 static int
5768 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5769 {
5770         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5771         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5772         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5773         uint16_t q_id;
5774         int ret;
5775
5776         if (dev->data->dev_conf.intr_conf.rxq == 0)
5777                 return 0;
5778
5779         if (rte_intr_dp_is_en(intr_handle)) {
5780                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5781                         ret = hns3_bind_ring_with_vector(hw,
5782                                         intr_handle->intr_vec[q_id], true,
5783                                         HNS3_RING_TYPE_RX, q_id);
5784                         if (ret)
5785                                 return ret;
5786                 }
5787         }
5788
5789         return 0;
5790 }
5791
5792 static void
5793 hns3_restore_filter(struct rte_eth_dev *dev)
5794 {
5795         hns3_restore_rss_filter(dev);
5796 }
5797
5798 static int
5799 hns3_dev_start(struct rte_eth_dev *dev)
5800 {
5801         struct hns3_adapter *hns = dev->data->dev_private;
5802         struct hns3_hw *hw = &hns->hw;
5803         bool old_state = hw->set_link_down;
5804         int ret;
5805
5806         PMD_INIT_FUNC_TRACE();
5807         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5808                 return -EBUSY;
5809
5810         rte_spinlock_lock(&hw->lock);
5811         hw->adapter_state = HNS3_NIC_STARTING;
5812
5813         /*
5814          * If the dev_set_link_down() API has been called, the "set_link_down"
5815          * flag can be cleared by dev_start() API. In addition, the flag should
5816          * also be cleared before calling hns3_do_start() so that MAC can be
5817          * enabled in dev_start stage.
5818          */
5819         hw->set_link_down = false;
5820         ret = hns3_do_start(hns, true);
5821         if (ret)
5822                 goto do_start_fail;
5823
5824         ret = hns3_map_rx_interrupt(dev);
5825         if (ret)
5826                 goto map_rx_inter_err;
5827
5828         /*
5829          * There are three register used to control the status of a TQP
5830          * (contains a pair of Tx queue and Rx queue) in the new version network
5831          * engine. One is used to control the enabling of Tx queue, the other is
5832          * used to control the enabling of Rx queue, and the last is the master
5833          * switch used to control the enabling of the tqp. The Tx register and
5834          * TQP register must be enabled at the same time to enable a Tx queue.
5835          * The same applies to the Rx queue. For the older network engine, this
5836          * function only refresh the enabled flag, and it is used to update the
5837          * status of queue in the dpdk framework.
5838          */
5839         ret = hns3_start_all_txqs(dev);
5840         if (ret)
5841                 goto map_rx_inter_err;
5842
5843         ret = hns3_start_all_rxqs(dev);
5844         if (ret)
5845                 goto start_all_rxqs_fail;
5846
5847         hw->adapter_state = HNS3_NIC_STARTED;
5848         rte_spinlock_unlock(&hw->lock);
5849
5850         hns3_rx_scattered_calc(dev);
5851         hns3_set_rxtx_function(dev);
5852         hns3_mp_req_start_rxtx(dev);
5853
5854         hns3_restore_filter(dev);
5855
5856         /* Enable interrupt of all rx queues before enabling queues */
5857         hns3_dev_all_rx_queue_intr_enable(hw, true);
5858
5859         /*
5860          * After finished the initialization, enable tqps to receive/transmit
5861          * packets and refresh all queue status.
5862          */
5863         hns3_start_tqps(hw);
5864
5865         hns3_tm_dev_start_proc(hw);
5866
5867         if (dev->data->dev_conf.intr_conf.lsc != 0)
5868                 hns3_dev_link_update(dev, 0);
5869         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5870
5871         hns3_info(hw, "hns3 dev start successful!");
5872
5873         return 0;
5874
5875 start_all_rxqs_fail:
5876         hns3_stop_all_txqs(dev);
5877 map_rx_inter_err:
5878         (void)hns3_do_stop(hns);
5879 do_start_fail:
5880         hw->set_link_down = old_state;
5881         hw->adapter_state = HNS3_NIC_CONFIGURED;
5882         rte_spinlock_unlock(&hw->lock);
5883
5884         return ret;
5885 }
5886
5887 static int
5888 hns3_do_stop(struct hns3_adapter *hns)
5889 {
5890         struct hns3_hw *hw = &hns->hw;
5891         int ret;
5892
5893         /*
5894          * The "hns3_do_stop" function will also be called by .stop_service to
5895          * prepare reset. At the time of global or IMP reset, the command cannot
5896          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5897          * accessed during the reset process. So the mbuf can not be released
5898          * during reset and is required to be released after the reset is
5899          * completed.
5900          */
5901         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5902                 hns3_dev_release_mbufs(hns);
5903
5904         ret = hns3_cfg_mac_mode(hw, false);
5905         if (ret)
5906                 return ret;
5907         hw->mac.link_status = ETH_LINK_DOWN;
5908
5909         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5910                 hns3_configure_all_mac_addr(hns, true);
5911                 ret = hns3_reset_all_tqps(hns);
5912                 if (ret) {
5913                         hns3_err(hw, "failed to reset all queues ret = %d.",
5914                                  ret);
5915                         return ret;
5916                 }
5917         }
5918
5919         return 0;
5920 }
5921
5922 static void
5923 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5924 {
5925         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5926         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5927         struct hns3_adapter *hns = dev->data->dev_private;
5928         struct hns3_hw *hw = &hns->hw;
5929         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5930         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5931         uint16_t q_id;
5932
5933         if (dev->data->dev_conf.intr_conf.rxq == 0)
5934                 return;
5935
5936         /* unmap the ring with vector */
5937         if (rte_intr_allow_others(intr_handle)) {
5938                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5939                 base = RTE_INTR_VEC_RXTX_OFFSET;
5940         }
5941         if (rte_intr_dp_is_en(intr_handle)) {
5942                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5943                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5944                                                          HNS3_RING_TYPE_RX,
5945                                                          q_id);
5946                         if (vec < base + intr_handle->nb_efd - 1)
5947                                 vec++;
5948                 }
5949         }
5950         /* Clean datapath event and queue/vec mapping */
5951         rte_intr_efd_disable(intr_handle);
5952         if (intr_handle->intr_vec) {
5953                 rte_free(intr_handle->intr_vec);
5954                 intr_handle->intr_vec = NULL;
5955         }
5956 }
5957
5958 static int
5959 hns3_dev_stop(struct rte_eth_dev *dev)
5960 {
5961         struct hns3_adapter *hns = dev->data->dev_private;
5962         struct hns3_hw *hw = &hns->hw;
5963
5964         PMD_INIT_FUNC_TRACE();
5965         dev->data->dev_started = 0;
5966
5967         hw->adapter_state = HNS3_NIC_STOPPING;
5968         hns3_set_rxtx_function(dev);
5969         rte_wmb();
5970         /* Disable datapath on secondary process. */
5971         hns3_mp_req_stop_rxtx(dev);
5972         /* Prevent crashes when queues are still in use. */
5973         rte_delay_ms(hw->cfg_max_queues);
5974
5975         rte_spinlock_lock(&hw->lock);
5976         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5977                 hns3_tm_dev_stop_proc(hw);
5978                 hns3_config_mac_tnl_int(hw, false);
5979                 hns3_stop_tqps(hw);
5980                 hns3_do_stop(hns);
5981                 hns3_unmap_rx_interrupt(dev);
5982                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5983         }
5984         hns3_rx_scattered_reset(dev);
5985         rte_eal_alarm_cancel(hns3_service_handler, dev);
5986         hns3_stop_report_lse(dev);
5987         rte_spinlock_unlock(&hw->lock);
5988
5989         return 0;
5990 }
5991
5992 static int
5993 hns3_dev_close(struct rte_eth_dev *eth_dev)
5994 {
5995         struct hns3_adapter *hns = eth_dev->data->dev_private;
5996         struct hns3_hw *hw = &hns->hw;
5997         int ret = 0;
5998
5999         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6000                 return 0;
6001
6002         if (hw->adapter_state == HNS3_NIC_STARTED)
6003                 ret = hns3_dev_stop(eth_dev);
6004
6005         hw->adapter_state = HNS3_NIC_CLOSING;
6006         hns3_reset_abort(hns);
6007         hw->adapter_state = HNS3_NIC_CLOSED;
6008
6009         hns3_configure_all_mc_mac_addr(hns, true);
6010         hns3_remove_all_vlan_table(hns);
6011         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
6012         hns3_uninit_pf(eth_dev);
6013         hns3_free_all_queues(eth_dev);
6014         rte_free(hw->reset.wait_data);
6015         hns3_mp_uninit_primary();
6016         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
6017
6018         return ret;
6019 }
6020
6021 static void
6022 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
6023                                    bool *tx_pause)
6024 {
6025         struct hns3_mac *mac = &hw->mac;
6026         uint32_t advertising = mac->advertising;
6027         uint32_t lp_advertising = mac->lp_advertising;
6028         *rx_pause = false;
6029         *tx_pause = false;
6030
6031         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
6032                 *rx_pause = true;
6033                 *tx_pause = true;
6034         } else if (advertising & lp_advertising &
6035                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
6036                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
6037                         *rx_pause = true;
6038                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
6039                         *tx_pause = true;
6040         }
6041 }
6042
6043 static enum hns3_fc_mode
6044 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
6045 {
6046         enum hns3_fc_mode current_mode;
6047         bool rx_pause = false;
6048         bool tx_pause = false;
6049
6050         switch (hw->mac.media_type) {
6051         case HNS3_MEDIA_TYPE_COPPER:
6052                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
6053                 break;
6054
6055         /*
6056          * Flow control auto-negotiation is not supported for fiber and
6057          * backpalne media type.
6058          */
6059         case HNS3_MEDIA_TYPE_FIBER:
6060         case HNS3_MEDIA_TYPE_BACKPLANE:
6061                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
6062                 current_mode = hw->requested_fc_mode;
6063                 goto out;
6064         default:
6065                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
6066                          hw->mac.media_type);
6067                 current_mode = HNS3_FC_NONE;
6068                 goto out;
6069         }
6070
6071         if (rx_pause && tx_pause)
6072                 current_mode = HNS3_FC_FULL;
6073         else if (rx_pause)
6074                 current_mode = HNS3_FC_RX_PAUSE;
6075         else if (tx_pause)
6076                 current_mode = HNS3_FC_TX_PAUSE;
6077         else
6078                 current_mode = HNS3_FC_NONE;
6079
6080 out:
6081         return current_mode;
6082 }
6083
6084 static enum hns3_fc_mode
6085 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6086 {
6087         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6088         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6089         struct hns3_mac *mac = &hw->mac;
6090
6091         /*
6092          * When the flow control mode is obtained, the device may not complete
6093          * auto-negotiation. It is necessary to wait for link establishment.
6094          */
6095         (void)hns3_dev_link_update(dev, 1);
6096
6097         /*
6098          * If the link auto-negotiation of the nic is disabled, or the flow
6099          * control auto-negotiation is not supported, the forced flow control
6100          * mode is used.
6101          */
6102         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6103                 return hw->requested_fc_mode;
6104
6105         return hns3_get_autoneg_fc_mode(hw);
6106 }
6107
6108 static int
6109 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6110 {
6111         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6112         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6113         enum hns3_fc_mode current_mode;
6114
6115         current_mode = hns3_get_current_fc_mode(dev);
6116         switch (current_mode) {
6117         case HNS3_FC_FULL:
6118                 fc_conf->mode = RTE_FC_FULL;
6119                 break;
6120         case HNS3_FC_TX_PAUSE:
6121                 fc_conf->mode = RTE_FC_TX_PAUSE;
6122                 break;
6123         case HNS3_FC_RX_PAUSE:
6124                 fc_conf->mode = RTE_FC_RX_PAUSE;
6125                 break;
6126         case HNS3_FC_NONE:
6127         default:
6128                 fc_conf->mode = RTE_FC_NONE;
6129                 break;
6130         }
6131
6132         fc_conf->pause_time = pf->pause_time;
6133         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6134
6135         return 0;
6136 }
6137
6138 static int
6139 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6140 {
6141         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6142
6143         if (!pf->support_fc_autoneg) {
6144                 if (autoneg != 0) {
6145                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6146                         return -EOPNOTSUPP;
6147                 }
6148
6149                 /*
6150                  * Flow control auto-negotiation of the NIC is not supported,
6151                  * but other auto-negotiation features may be supported.
6152                  */
6153                 if (autoneg != hw->mac.link_autoneg) {
6154                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6155                         return -EOPNOTSUPP;
6156                 }
6157
6158                 return 0;
6159         }
6160
6161         /*
6162          * If flow control auto-negotiation of the NIC is supported, all
6163          * auto-negotiation features are supported.
6164          */
6165         if (autoneg != hw->mac.link_autoneg) {
6166                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6167                 return -EOPNOTSUPP;
6168         }
6169
6170         return 0;
6171 }
6172
6173 static int
6174 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6175 {
6176         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6177         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6178         int ret;
6179
6180         if (fc_conf->high_water || fc_conf->low_water ||
6181             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6182                 hns3_err(hw, "Unsupported flow control settings specified, "
6183                          "high_water(%u), low_water(%u), send_xon(%u) and "
6184                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6185                          fc_conf->high_water, fc_conf->low_water,
6186                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6187                 return -EINVAL;
6188         }
6189
6190         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6191         if (ret)
6192                 return ret;
6193
6194         if (!fc_conf->pause_time) {
6195                 hns3_err(hw, "Invalid pause time %u setting.",
6196                          fc_conf->pause_time);
6197                 return -EINVAL;
6198         }
6199
6200         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6201             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6202                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6203                          "current_fc_status = %d", hw->current_fc_status);
6204                 return -EOPNOTSUPP;
6205         }
6206
6207         if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
6208                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6209                 return -EOPNOTSUPP;
6210         }
6211
6212         rte_spinlock_lock(&hw->lock);
6213         ret = hns3_fc_enable(dev, fc_conf);
6214         rte_spinlock_unlock(&hw->lock);
6215
6216         return ret;
6217 }
6218
6219 static int
6220 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6221                             struct rte_eth_pfc_conf *pfc_conf)
6222 {
6223         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6224         int ret;
6225
6226         if (!hns3_dev_dcb_supported(hw)) {
6227                 hns3_err(hw, "This port does not support dcb configurations.");
6228                 return -EOPNOTSUPP;
6229         }
6230
6231         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6232             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6233                 hns3_err(hw, "Unsupported flow control settings specified, "
6234                          "high_water(%u), low_water(%u), send_xon(%u) and "
6235                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6236                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6237                          pfc_conf->fc.send_xon,
6238                          pfc_conf->fc.mac_ctrl_frame_fwd);
6239                 return -EINVAL;
6240         }
6241         if (pfc_conf->fc.autoneg) {
6242                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6243                 return -EINVAL;
6244         }
6245         if (pfc_conf->fc.pause_time == 0) {
6246                 hns3_err(hw, "Invalid pause time %u setting.",
6247                          pfc_conf->fc.pause_time);
6248                 return -EINVAL;
6249         }
6250
6251         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6252             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6253                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6254                              "current_fc_status = %d", hw->current_fc_status);
6255                 return -EOPNOTSUPP;
6256         }
6257
6258         rte_spinlock_lock(&hw->lock);
6259         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6260         rte_spinlock_unlock(&hw->lock);
6261
6262         return ret;
6263 }
6264
6265 static int
6266 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6267 {
6268         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6269         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6270         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6271         int i;
6272
6273         rte_spinlock_lock(&hw->lock);
6274         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6275                 dcb_info->nb_tcs = pf->local_max_tc;
6276         else
6277                 dcb_info->nb_tcs = 1;
6278
6279         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6280                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6281         for (i = 0; i < dcb_info->nb_tcs; i++)
6282                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6283
6284         for (i = 0; i < hw->num_tc; i++) {
6285                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6286                 dcb_info->tc_queue.tc_txq[0][i].base =
6287                                                 hw->tc_queue[i].tqp_offset;
6288                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6289                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6290                                                 hw->tc_queue[i].tqp_count;
6291         }
6292         rte_spinlock_unlock(&hw->lock);
6293
6294         return 0;
6295 }
6296
6297 static int
6298 hns3_reinit_dev(struct hns3_adapter *hns)
6299 {
6300         struct hns3_hw *hw = &hns->hw;
6301         int ret;
6302
6303         ret = hns3_cmd_init(hw);
6304         if (ret) {
6305                 hns3_err(hw, "Failed to init cmd: %d", ret);
6306                 return ret;
6307         }
6308
6309         ret = hns3_reset_all_tqps(hns);
6310         if (ret) {
6311                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6312                 return ret;
6313         }
6314
6315         ret = hns3_init_hardware(hns);
6316         if (ret) {
6317                 hns3_err(hw, "Failed to init hardware: %d", ret);
6318                 return ret;
6319         }
6320
6321         ret = hns3_enable_hw_error_intr(hns, true);
6322         if (ret) {
6323                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6324                              ret);
6325                 return ret;
6326         }
6327         hns3_info(hw, "Reset done, driver initialization finished.");
6328
6329         return 0;
6330 }
6331
6332 static bool
6333 is_pf_reset_done(struct hns3_hw *hw)
6334 {
6335         uint32_t val, reg, reg_bit;
6336
6337         switch (hw->reset.level) {
6338         case HNS3_IMP_RESET:
6339                 reg = HNS3_GLOBAL_RESET_REG;
6340                 reg_bit = HNS3_IMP_RESET_BIT;
6341                 break;
6342         case HNS3_GLOBAL_RESET:
6343                 reg = HNS3_GLOBAL_RESET_REG;
6344                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6345                 break;
6346         case HNS3_FUNC_RESET:
6347                 reg = HNS3_FUN_RST_ING;
6348                 reg_bit = HNS3_FUN_RST_ING_B;
6349                 break;
6350         case HNS3_FLR_RESET:
6351         default:
6352                 hns3_err(hw, "Wait for unsupported reset level: %d",
6353                          hw->reset.level);
6354                 return true;
6355         }
6356         val = hns3_read_dev(hw, reg);
6357         if (hns3_get_bit(val, reg_bit))
6358                 return false;
6359         else
6360                 return true;
6361 }
6362
6363 bool
6364 hns3_is_reset_pending(struct hns3_adapter *hns)
6365 {
6366         struct hns3_hw *hw = &hns->hw;
6367         enum hns3_reset_level reset;
6368
6369         hns3_check_event_cause(hns, NULL);
6370         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6371         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6372             hw->reset.level < reset) {
6373                 hns3_warn(hw, "High level reset %d is pending", reset);
6374                 return true;
6375         }
6376         reset = hns3_get_reset_level(hns, &hw->reset.request);
6377         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6378             hw->reset.level < reset) {
6379                 hns3_warn(hw, "High level reset %d is request", reset);
6380                 return true;
6381         }
6382         return false;
6383 }
6384
6385 static int
6386 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6387 {
6388         struct hns3_hw *hw = &hns->hw;
6389         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6390         struct timeval tv;
6391
6392         if (wait_data->result == HNS3_WAIT_SUCCESS)
6393                 return 0;
6394         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6395                 hns3_clock_gettime(&tv);
6396                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6397                           tv.tv_sec, tv.tv_usec);
6398                 return -ETIME;
6399         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6400                 return -EAGAIN;
6401
6402         wait_data->hns = hns;
6403         wait_data->check_completion = is_pf_reset_done;
6404         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6405                                 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6406         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6407         wait_data->count = HNS3_RESET_WAIT_CNT;
6408         wait_data->result = HNS3_WAIT_REQUEST;
6409         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6410         return -EAGAIN;
6411 }
6412
6413 static int
6414 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6415 {
6416         struct hns3_cmd_desc desc;
6417         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6418
6419         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6420         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6421         req->fun_reset_vfid = func_id;
6422
6423         return hns3_cmd_send(hw, &desc, 1);
6424 }
6425
6426 static int
6427 hns3_imp_reset_cmd(struct hns3_hw *hw)
6428 {
6429         struct hns3_cmd_desc desc;
6430
6431         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6432         desc.data[0] = 0xeedd;
6433
6434         return hns3_cmd_send(hw, &desc, 1);
6435 }
6436
6437 static void
6438 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6439 {
6440         struct hns3_hw *hw = &hns->hw;
6441         struct timeval tv;
6442         uint32_t val;
6443
6444         hns3_clock_gettime(&tv);
6445         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6446             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6447                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6448                           tv.tv_sec, tv.tv_usec);
6449                 return;
6450         }
6451
6452         switch (reset_level) {
6453         case HNS3_IMP_RESET:
6454                 hns3_imp_reset_cmd(hw);
6455                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6456                           tv.tv_sec, tv.tv_usec);
6457                 break;
6458         case HNS3_GLOBAL_RESET:
6459                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6460                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6461                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6462                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6463                           tv.tv_sec, tv.tv_usec);
6464                 break;
6465         case HNS3_FUNC_RESET:
6466                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6467                           tv.tv_sec, tv.tv_usec);
6468                 /* schedule again to check later */
6469                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6470                 hns3_schedule_reset(hns);
6471                 break;
6472         default:
6473                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6474                 return;
6475         }
6476         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6477 }
6478
6479 static enum hns3_reset_level
6480 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6481 {
6482         struct hns3_hw *hw = &hns->hw;
6483         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6484
6485         /* Return the highest priority reset level amongst all */
6486         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6487                 reset_level = HNS3_IMP_RESET;
6488         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6489                 reset_level = HNS3_GLOBAL_RESET;
6490         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6491                 reset_level = HNS3_FUNC_RESET;
6492         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6493                 reset_level = HNS3_FLR_RESET;
6494
6495         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6496                 return HNS3_NONE_RESET;
6497
6498         return reset_level;
6499 }
6500
6501 static void
6502 hns3_record_imp_error(struct hns3_adapter *hns)
6503 {
6504         struct hns3_hw *hw = &hns->hw;
6505         uint32_t reg_val;
6506
6507         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6508         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6509                 hns3_warn(hw, "Detected IMP RD poison!");
6510                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6511                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6512         }
6513
6514         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6515                 hns3_warn(hw, "Detected IMP CMDQ error!");
6516                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6517                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6518         }
6519 }
6520
6521 static int
6522 hns3_prepare_reset(struct hns3_adapter *hns)
6523 {
6524         struct hns3_hw *hw = &hns->hw;
6525         uint32_t reg_val;
6526         int ret;
6527
6528         switch (hw->reset.level) {
6529         case HNS3_FUNC_RESET:
6530                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6531                 if (ret)
6532                         return ret;
6533
6534                 /*
6535                  * After performaning pf reset, it is not necessary to do the
6536                  * mailbox handling or send any command to firmware, because
6537                  * any mailbox handling or command to firmware is only valid
6538                  * after hns3_cmd_init is called.
6539                  */
6540                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6541                 hw->reset.stats.request_cnt++;
6542                 break;
6543         case HNS3_IMP_RESET:
6544                 hns3_record_imp_error(hns);
6545                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6546                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6547                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6548                 break;
6549         default:
6550                 break;
6551         }
6552         return 0;
6553 }
6554
6555 static int
6556 hns3_set_rst_done(struct hns3_hw *hw)
6557 {
6558         struct hns3_pf_rst_done_cmd *req;
6559         struct hns3_cmd_desc desc;
6560
6561         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6562         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6563         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6564         return hns3_cmd_send(hw, &desc, 1);
6565 }
6566
6567 static int
6568 hns3_stop_service(struct hns3_adapter *hns)
6569 {
6570         struct hns3_hw *hw = &hns->hw;
6571         struct rte_eth_dev *eth_dev;
6572
6573         eth_dev = &rte_eth_devices[hw->data->port_id];
6574         hw->mac.link_status = ETH_LINK_DOWN;
6575         if (hw->adapter_state == HNS3_NIC_STARTED) {
6576                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6577                 hns3_update_linkstatus_and_event(hw, false);
6578         }
6579
6580         hns3_set_rxtx_function(eth_dev);
6581         rte_wmb();
6582         /* Disable datapath on secondary process. */
6583         hns3_mp_req_stop_rxtx(eth_dev);
6584         rte_delay_ms(hw->cfg_max_queues);
6585
6586         rte_spinlock_lock(&hw->lock);
6587         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6588             hw->adapter_state == HNS3_NIC_STOPPING) {
6589                 hns3_enable_all_queues(hw, false);
6590                 hns3_do_stop(hns);
6591                 hw->reset.mbuf_deferred_free = true;
6592         } else
6593                 hw->reset.mbuf_deferred_free = false;
6594
6595         /*
6596          * It is cumbersome for hardware to pick-and-choose entries for deletion
6597          * from table space. Hence, for function reset software intervention is
6598          * required to delete the entries
6599          */
6600         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6601                 hns3_configure_all_mc_mac_addr(hns, true);
6602         rte_spinlock_unlock(&hw->lock);
6603
6604         return 0;
6605 }
6606
6607 static int
6608 hns3_start_service(struct hns3_adapter *hns)
6609 {
6610         struct hns3_hw *hw = &hns->hw;
6611         struct rte_eth_dev *eth_dev;
6612
6613         if (hw->reset.level == HNS3_IMP_RESET ||
6614             hw->reset.level == HNS3_GLOBAL_RESET)
6615                 hns3_set_rst_done(hw);
6616         eth_dev = &rte_eth_devices[hw->data->port_id];
6617         hns3_set_rxtx_function(eth_dev);
6618         hns3_mp_req_start_rxtx(eth_dev);
6619         if (hw->adapter_state == HNS3_NIC_STARTED) {
6620                 /*
6621                  * This API parent function already hold the hns3_hw.lock, the
6622                  * hns3_service_handler may report lse, in bonding application
6623                  * it will call driver's ops which may acquire the hns3_hw.lock
6624                  * again, thus lead to deadlock.
6625                  * We defer calls hns3_service_handler to avoid the deadlock.
6626                  */
6627                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6628                                   hns3_service_handler, eth_dev);
6629
6630                 /* Enable interrupt of all rx queues before enabling queues */
6631                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6632                 /*
6633                  * Enable state of each rxq and txq will be recovered after
6634                  * reset, so we need to restore them before enable all tqps;
6635                  */
6636                 hns3_restore_tqp_enable_state(hw);
6637                 /*
6638                  * When finished the initialization, enable queues to receive
6639                  * and transmit packets.
6640                  */
6641                 hns3_enable_all_queues(hw, true);
6642         }
6643
6644         return 0;
6645 }
6646
6647 static int
6648 hns3_restore_conf(struct hns3_adapter *hns)
6649 {
6650         struct hns3_hw *hw = &hns->hw;
6651         int ret;
6652
6653         ret = hns3_configure_all_mac_addr(hns, false);
6654         if (ret)
6655                 return ret;
6656
6657         ret = hns3_configure_all_mc_mac_addr(hns, false);
6658         if (ret)
6659                 goto err_mc_mac;
6660
6661         ret = hns3_dev_promisc_restore(hns);
6662         if (ret)
6663                 goto err_promisc;
6664
6665         ret = hns3_restore_vlan_table(hns);
6666         if (ret)
6667                 goto err_promisc;
6668
6669         ret = hns3_restore_vlan_conf(hns);
6670         if (ret)
6671                 goto err_promisc;
6672
6673         ret = hns3_restore_all_fdir_filter(hns);
6674         if (ret)
6675                 goto err_promisc;
6676
6677         ret = hns3_restore_ptp(hns);
6678         if (ret)
6679                 goto err_promisc;
6680
6681         ret = hns3_restore_rx_interrupt(hw);
6682         if (ret)
6683                 goto err_promisc;
6684
6685         ret = hns3_restore_gro_conf(hw);
6686         if (ret)
6687                 goto err_promisc;
6688
6689         ret = hns3_restore_fec(hw);
6690         if (ret)
6691                 goto err_promisc;
6692
6693         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6694                 ret = hns3_do_start(hns, false);
6695                 if (ret)
6696                         goto err_promisc;
6697                 hns3_info(hw, "hns3 dev restart successful!");
6698         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6699                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6700         return 0;
6701
6702 err_promisc:
6703         hns3_configure_all_mc_mac_addr(hns, true);
6704 err_mc_mac:
6705         hns3_configure_all_mac_addr(hns, true);
6706         return ret;
6707 }
6708
6709 static void
6710 hns3_reset_service(void *param)
6711 {
6712         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6713         struct hns3_hw *hw = &hns->hw;
6714         enum hns3_reset_level reset_level;
6715         struct timeval tv_delta;
6716         struct timeval tv_start;
6717         struct timeval tv;
6718         uint64_t msec;
6719         int ret;
6720
6721         /*
6722          * The interrupt is not triggered within the delay time.
6723          * The interrupt may have been lost. It is necessary to handle
6724          * the interrupt to recover from the error.
6725          */
6726         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6727                             SCHEDULE_DEFERRED) {
6728                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6729                                   __ATOMIC_RELAXED);
6730                 hns3_err(hw, "Handling interrupts in delayed tasks");
6731                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6732                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6733                 if (reset_level == HNS3_NONE_RESET) {
6734                         hns3_err(hw, "No reset level is set, try IMP reset");
6735                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6736                 }
6737         }
6738         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6739
6740         /*
6741          * Check if there is any ongoing reset in the hardware. This status can
6742          * be checked from reset_pending. If there is then, we need to wait for
6743          * hardware to complete reset.
6744          *    a. If we are able to figure out in reasonable time that hardware
6745          *       has fully resetted then, we can proceed with driver, client
6746          *       reset.
6747          *    b. else, we can come back later to check this status so re-sched
6748          *       now.
6749          */
6750         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6751         if (reset_level != HNS3_NONE_RESET) {
6752                 hns3_clock_gettime(&tv_start);
6753                 ret = hns3_reset_process(hns, reset_level);
6754                 hns3_clock_gettime(&tv);
6755                 timersub(&tv, &tv_start, &tv_delta);
6756                 msec = hns3_clock_calctime_ms(&tv_delta);
6757                 if (msec > HNS3_RESET_PROCESS_MS)
6758                         hns3_err(hw, "%d handle long time delta %" PRIu64
6759                                      " ms time=%ld.%.6ld",
6760                                  hw->reset.level, msec,
6761                                  tv.tv_sec, tv.tv_usec);
6762                 if (ret == -EAGAIN)
6763                         return;
6764         }
6765
6766         /* Check if we got any *new* reset requests to be honored */
6767         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6768         if (reset_level != HNS3_NONE_RESET)
6769                 hns3_msix_process(hns, reset_level);
6770 }
6771
6772 static unsigned int
6773 hns3_get_speed_capa_num(uint16_t device_id)
6774 {
6775         unsigned int num;
6776
6777         switch (device_id) {
6778         case HNS3_DEV_ID_25GE:
6779         case HNS3_DEV_ID_25GE_RDMA:
6780                 num = 2;
6781                 break;
6782         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6783         case HNS3_DEV_ID_200G_RDMA:
6784                 num = 1;
6785                 break;
6786         default:
6787                 num = 0;
6788                 break;
6789         }
6790
6791         return num;
6792 }
6793
6794 static int
6795 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6796                         uint16_t device_id)
6797 {
6798         switch (device_id) {
6799         case HNS3_DEV_ID_25GE:
6800         /* fallthrough */
6801         case HNS3_DEV_ID_25GE_RDMA:
6802                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6803                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6804
6805                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6806                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6807                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6808                 break;
6809         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6810                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6811                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6812                 break;
6813         case HNS3_DEV_ID_200G_RDMA:
6814                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6815                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6816                 break;
6817         default:
6818                 return -ENOTSUP;
6819         }
6820
6821         return 0;
6822 }
6823
6824 static int
6825 hns3_fec_get_capability(struct rte_eth_dev *dev,
6826                         struct rte_eth_fec_capa *speed_fec_capa,
6827                         unsigned int num)
6828 {
6829         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6830         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6831         uint16_t device_id = pci_dev->id.device_id;
6832         unsigned int capa_num;
6833         int ret;
6834
6835         capa_num = hns3_get_speed_capa_num(device_id);
6836         if (capa_num == 0) {
6837                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6838                          device_id);
6839                 return -ENOTSUP;
6840         }
6841
6842         if (speed_fec_capa == NULL || num < capa_num)
6843                 return capa_num;
6844
6845         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6846         if (ret)
6847                 return -ENOTSUP;
6848
6849         return capa_num;
6850 }
6851
6852 static int
6853 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6854 {
6855         struct hns3_config_fec_cmd *req;
6856         struct hns3_cmd_desc desc;
6857         int ret;
6858
6859         /*
6860          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6861          * in device of link speed
6862          * below 10 Gbps.
6863          */
6864         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6865                 *state = 0;
6866                 return 0;
6867         }
6868
6869         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6870         req = (struct hns3_config_fec_cmd *)desc.data;
6871         ret = hns3_cmd_send(hw, &desc, 1);
6872         if (ret) {
6873                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6874                          ret);
6875                 return ret;
6876         }
6877
6878         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6879         return 0;
6880 }
6881
6882 static int
6883 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6884 {
6885         struct hns3_sfp_info_cmd *resp;
6886         uint32_t tmp_fec_capa;
6887         uint8_t auto_state;
6888         struct hns3_cmd_desc desc;
6889         int ret;
6890
6891         /*
6892          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6893          * configured FEC mode is returned.
6894          * If link is up, current FEC mode is returned.
6895          */
6896         if (hw->mac.link_status == ETH_LINK_DOWN) {
6897                 ret = get_current_fec_auto_state(hw, &auto_state);
6898                 if (ret)
6899                         return ret;
6900
6901                 if (auto_state == 0x1) {
6902                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6903                         return 0;
6904                 }
6905         }
6906
6907         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6908         resp = (struct hns3_sfp_info_cmd *)desc.data;
6909         resp->query_type = HNS3_ACTIVE_QUERY;
6910
6911         ret = hns3_cmd_send(hw, &desc, 1);
6912         if (ret == -EOPNOTSUPP) {
6913                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6914                 return ret;
6915         } else if (ret) {
6916                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6917                 return ret;
6918         }
6919
6920         /*
6921          * FEC mode order defined in hns3 hardware is inconsistend with
6922          * that defined in the ethdev library. So the sequence needs
6923          * to be converted.
6924          */
6925         switch (resp->active_fec) {
6926         case HNS3_HW_FEC_MODE_NOFEC:
6927                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6928                 break;
6929         case HNS3_HW_FEC_MODE_BASER:
6930                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6931                 break;
6932         case HNS3_HW_FEC_MODE_RS:
6933                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6934                 break;
6935         default:
6936                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6937                 break;
6938         }
6939
6940         *fec_capa = tmp_fec_capa;
6941         return 0;
6942 }
6943
6944 static int
6945 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6946 {
6947         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6948
6949         return hns3_fec_get_internal(hw, fec_capa);
6950 }
6951
6952 static int
6953 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6954 {
6955         struct hns3_config_fec_cmd *req;
6956         struct hns3_cmd_desc desc;
6957         int ret;
6958
6959         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6960
6961         req = (struct hns3_config_fec_cmd *)desc.data;
6962         switch (mode) {
6963         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6964                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6965                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6966                 break;
6967         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6968                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6969                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6970                 break;
6971         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6972                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6973                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6974                 break;
6975         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6976                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6977                 break;
6978         default:
6979                 return 0;
6980         }
6981         ret = hns3_cmd_send(hw, &desc, 1);
6982         if (ret)
6983                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6984
6985         return ret;
6986 }
6987
6988 static uint32_t
6989 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6990 {
6991         struct hns3_mac *mac = &hw->mac;
6992         uint32_t cur_capa;
6993
6994         switch (mac->link_speed) {
6995         case ETH_SPEED_NUM_10G:
6996                 cur_capa = fec_capa[1].capa;
6997                 break;
6998         case ETH_SPEED_NUM_25G:
6999         case ETH_SPEED_NUM_100G:
7000         case ETH_SPEED_NUM_200G:
7001                 cur_capa = fec_capa[0].capa;
7002                 break;
7003         default:
7004                 cur_capa = 0;
7005                 break;
7006         }
7007
7008         return cur_capa;
7009 }
7010
7011 static bool
7012 is_fec_mode_one_bit_set(uint32_t mode)
7013 {
7014         int cnt = 0;
7015         uint8_t i;
7016
7017         for (i = 0; i < sizeof(mode); i++)
7018                 if (mode >> i & 0x1)
7019                         cnt++;
7020
7021         return cnt == 1 ? true : false;
7022 }
7023
7024 static int
7025 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
7026 {
7027 #define FEC_CAPA_NUM 2
7028         struct hns3_adapter *hns = dev->data->dev_private;
7029         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7030         struct hns3_pf *pf = &hns->pf;
7031
7032         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
7033         uint32_t cur_capa;
7034         uint32_t num = FEC_CAPA_NUM;
7035         int ret;
7036
7037         ret = hns3_fec_get_capability(dev, fec_capa, num);
7038         if (ret < 0)
7039                 return ret;
7040
7041         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
7042         if (!is_fec_mode_one_bit_set(mode)) {
7043                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
7044                              "FEC mode should be only one bit set", mode);
7045                 return -EINVAL;
7046         }
7047
7048         /*
7049          * Check whether the configured mode is within the FEC capability.
7050          * If not, the configured mode will not be supported.
7051          */
7052         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
7053         if (!(cur_capa & mode)) {
7054                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
7055                 return -EINVAL;
7056         }
7057
7058         rte_spinlock_lock(&hw->lock);
7059         ret = hns3_set_fec_hw(hw, mode);
7060         if (ret) {
7061                 rte_spinlock_unlock(&hw->lock);
7062                 return ret;
7063         }
7064
7065         pf->fec_mode = mode;
7066         rte_spinlock_unlock(&hw->lock);
7067
7068         return 0;
7069 }
7070
7071 static int
7072 hns3_restore_fec(struct hns3_hw *hw)
7073 {
7074         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7075         struct hns3_pf *pf = &hns->pf;
7076         uint32_t mode = pf->fec_mode;
7077         int ret;
7078
7079         ret = hns3_set_fec_hw(hw, mode);
7080         if (ret)
7081                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7082                          mode, ret);
7083
7084         return ret;
7085 }
7086
7087 static int
7088 hns3_query_dev_fec_info(struct hns3_hw *hw)
7089 {
7090         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7091         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7092         int ret;
7093
7094         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7095         if (ret)
7096                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7097
7098         return ret;
7099 }
7100
7101 static bool
7102 hns3_optical_module_existed(struct hns3_hw *hw)
7103 {
7104         struct hns3_cmd_desc desc;
7105         bool existed;
7106         int ret;
7107
7108         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7109         ret = hns3_cmd_send(hw, &desc, 1);
7110         if (ret) {
7111                 hns3_err(hw,
7112                          "fail to get optical module exist state, ret = %d.\n",
7113                          ret);
7114                 return false;
7115         }
7116         existed = !!desc.data[0];
7117
7118         return existed;
7119 }
7120
7121 static int
7122 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7123                                 uint32_t len, uint8_t *data)
7124 {
7125 #define HNS3_SFP_INFO_CMD_NUM 6
7126 #define HNS3_SFP_INFO_MAX_LEN \
7127         (HNS3_SFP_INFO_BD0_LEN + \
7128         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7129         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7130         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7131         uint16_t read_len;
7132         uint16_t copy_len;
7133         int ret;
7134         int i;
7135
7136         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7137                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7138                                           true);
7139                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7140                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7141         }
7142
7143         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7144         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7145         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7146         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7147
7148         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7149         if (ret) {
7150                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7151                                 ret);
7152                 return ret;
7153         }
7154
7155         /* The data format in BD0 is different with the others. */
7156         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7157         memcpy(data, sfp_info_bd0->data, copy_len);
7158         read_len = copy_len;
7159
7160         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7161                 if (read_len >= len)
7162                         break;
7163
7164                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7165                 memcpy(data + read_len, desc[i].data, copy_len);
7166                 read_len += copy_len;
7167         }
7168
7169         return (int)read_len;
7170 }
7171
7172 static int
7173 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7174                        struct rte_dev_eeprom_info *info)
7175 {
7176         struct hns3_adapter *hns = dev->data->dev_private;
7177         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7178         uint32_t offset = info->offset;
7179         uint32_t len = info->length;
7180         uint8_t *data = info->data;
7181         uint32_t read_len = 0;
7182
7183         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7184                 return -ENOTSUP;
7185
7186         if (!hns3_optical_module_existed(hw)) {
7187                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7188                 return -EIO;
7189         }
7190
7191         while (read_len < len) {
7192                 int ret;
7193                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7194                                                   len - read_len,
7195                                                   data + read_len);
7196                 if (ret < 0)
7197                         return -EIO;
7198                 read_len += ret;
7199         }
7200
7201         return 0;
7202 }
7203
7204 static int
7205 hns3_get_module_info(struct rte_eth_dev *dev,
7206                      struct rte_eth_dev_module_info *modinfo)
7207 {
7208 #define HNS3_SFF8024_ID_SFP             0x03
7209 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7210 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7211 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7212 #define HNS3_SFF_8636_V1_3              0x03
7213         struct hns3_adapter *hns = dev->data->dev_private;
7214         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7215         struct rte_dev_eeprom_info info;
7216         struct hns3_sfp_type sfp_type;
7217         int ret;
7218
7219         memset(&sfp_type, 0, sizeof(sfp_type));
7220         memset(&info, 0, sizeof(info));
7221         info.data = (uint8_t *)&sfp_type;
7222         info.length = sizeof(sfp_type);
7223         ret = hns3_get_module_eeprom(dev, &info);
7224         if (ret)
7225                 return ret;
7226
7227         switch (sfp_type.type) {
7228         case HNS3_SFF8024_ID_SFP:
7229                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7230                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7231                 break;
7232         case HNS3_SFF8024_ID_QSFP_8438:
7233                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7234                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7235                 break;
7236         case HNS3_SFF8024_ID_QSFP_8436_8636:
7237                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7238                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7239                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7240                 } else {
7241                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7242                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7243                 }
7244                 break;
7245         case HNS3_SFF8024_ID_QSFP28_8636:
7246                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7247                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7248                 break;
7249         default:
7250                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7251                          sfp_type.type, sfp_type.ext_type);
7252                 return -EINVAL;
7253         }
7254
7255         return 0;
7256 }
7257
7258 void
7259 hns3_clock_gettime(struct timeval *tv)
7260 {
7261 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7262 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7263 #else
7264 #define CLOCK_TYPE CLOCK_MONOTONIC
7265 #endif
7266 #define NSEC_TO_USEC_DIV 1000
7267
7268         struct timespec spec;
7269         (void)clock_gettime(CLOCK_TYPE, &spec);
7270
7271         tv->tv_sec = spec.tv_sec;
7272         tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7273 }
7274
7275 uint64_t
7276 hns3_clock_calctime_ms(struct timeval *tv)
7277 {
7278         return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7279                 tv->tv_usec / USEC_PER_MSEC;
7280 }
7281
7282 uint64_t
7283 hns3_clock_gettime_ms(void)
7284 {
7285         struct timeval tv;
7286
7287         hns3_clock_gettime(&tv);
7288         return hns3_clock_calctime_ms(&tv);
7289 }
7290
7291 static int
7292 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7293 {
7294         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7295
7296         RTE_SET_USED(key);
7297
7298         if (strcmp(value, "vec") == 0)
7299                 hint = HNS3_IO_FUNC_HINT_VEC;
7300         else if (strcmp(value, "sve") == 0)
7301                 hint = HNS3_IO_FUNC_HINT_SVE;
7302         else if (strcmp(value, "simple") == 0)
7303                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7304         else if (strcmp(value, "common") == 0)
7305                 hint = HNS3_IO_FUNC_HINT_COMMON;
7306
7307         /* If the hint is valid then update output parameters */
7308         if (hint != HNS3_IO_FUNC_HINT_NONE)
7309                 *(uint32_t *)extra_args = hint;
7310
7311         return 0;
7312 }
7313
7314 static const char *
7315 hns3_get_io_hint_func_name(uint32_t hint)
7316 {
7317         switch (hint) {
7318         case HNS3_IO_FUNC_HINT_VEC:
7319                 return "vec";
7320         case HNS3_IO_FUNC_HINT_SVE:
7321                 return "sve";
7322         case HNS3_IO_FUNC_HINT_SIMPLE:
7323                 return "simple";
7324         case HNS3_IO_FUNC_HINT_COMMON:
7325                 return "common";
7326         default:
7327                 return "none";
7328         }
7329 }
7330
7331 static int
7332 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7333 {
7334         uint64_t val;
7335
7336         RTE_SET_USED(key);
7337
7338         val = strtoull(value, NULL, 16);
7339         *(uint64_t *)extra_args = val;
7340
7341         return 0;
7342 }
7343
7344 void
7345 hns3_parse_devargs(struct rte_eth_dev *dev)
7346 {
7347         struct hns3_adapter *hns = dev->data->dev_private;
7348         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7349         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7350         struct hns3_hw *hw = &hns->hw;
7351         uint64_t dev_caps_mask = 0;
7352         struct rte_kvargs *kvlist;
7353
7354         if (dev->device->devargs == NULL)
7355                 return;
7356
7357         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7358         if (!kvlist)
7359                 return;
7360
7361         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7362                            &hns3_parse_io_hint_func, &rx_func_hint);
7363         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7364                            &hns3_parse_io_hint_func, &tx_func_hint);
7365         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7366                            &hns3_parse_dev_caps_mask, &dev_caps_mask);
7367         rte_kvargs_free(kvlist);
7368
7369         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7370                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7371                           hns3_get_io_hint_func_name(rx_func_hint));
7372         hns->rx_func_hint = rx_func_hint;
7373         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7374                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7375                           hns3_get_io_hint_func_name(tx_func_hint));
7376         hns->tx_func_hint = tx_func_hint;
7377
7378         if (dev_caps_mask != 0)
7379                 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7380                           HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7381         hns->dev_caps_mask = dev_caps_mask;
7382 }
7383
7384 static const struct eth_dev_ops hns3_eth_dev_ops = {
7385         .dev_configure      = hns3_dev_configure,
7386         .dev_start          = hns3_dev_start,
7387         .dev_stop           = hns3_dev_stop,
7388         .dev_close          = hns3_dev_close,
7389         .promiscuous_enable = hns3_dev_promiscuous_enable,
7390         .promiscuous_disable = hns3_dev_promiscuous_disable,
7391         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7392         .allmulticast_disable = hns3_dev_allmulticast_disable,
7393         .mtu_set            = hns3_dev_mtu_set,
7394         .stats_get          = hns3_stats_get,
7395         .stats_reset        = hns3_stats_reset,
7396         .xstats_get         = hns3_dev_xstats_get,
7397         .xstats_get_names   = hns3_dev_xstats_get_names,
7398         .xstats_reset       = hns3_dev_xstats_reset,
7399         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7400         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7401         .dev_infos_get          = hns3_dev_infos_get,
7402         .fw_version_get         = hns3_fw_version_get,
7403         .rx_queue_setup         = hns3_rx_queue_setup,
7404         .tx_queue_setup         = hns3_tx_queue_setup,
7405         .rx_queue_release       = hns3_dev_rx_queue_release,
7406         .tx_queue_release       = hns3_dev_tx_queue_release,
7407         .rx_queue_start         = hns3_dev_rx_queue_start,
7408         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7409         .tx_queue_start         = hns3_dev_tx_queue_start,
7410         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7411         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7412         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7413         .rxq_info_get           = hns3_rxq_info_get,
7414         .txq_info_get           = hns3_txq_info_get,
7415         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7416         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7417         .flow_ctrl_get          = hns3_flow_ctrl_get,
7418         .flow_ctrl_set          = hns3_flow_ctrl_set,
7419         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7420         .mac_addr_add           = hns3_add_mac_addr,
7421         .mac_addr_remove        = hns3_remove_mac_addr,
7422         .mac_addr_set           = hns3_set_default_mac_addr,
7423         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7424         .link_update            = hns3_dev_link_update,
7425         .dev_set_link_up        = hns3_dev_set_link_up,
7426         .dev_set_link_down      = hns3_dev_set_link_down,
7427         .rss_hash_update        = hns3_dev_rss_hash_update,
7428         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7429         .reta_update            = hns3_dev_rss_reta_update,
7430         .reta_query             = hns3_dev_rss_reta_query,
7431         .flow_ops_get           = hns3_dev_flow_ops_get,
7432         .vlan_filter_set        = hns3_vlan_filter_set,
7433         .vlan_tpid_set          = hns3_vlan_tpid_set,
7434         .vlan_offload_set       = hns3_vlan_offload_set,
7435         .vlan_pvid_set          = hns3_vlan_pvid_set,
7436         .get_reg                = hns3_get_regs,
7437         .get_module_info        = hns3_get_module_info,
7438         .get_module_eeprom      = hns3_get_module_eeprom,
7439         .get_dcb_info           = hns3_get_dcb_info,
7440         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7441         .fec_get_capability     = hns3_fec_get_capability,
7442         .fec_get                = hns3_fec_get,
7443         .fec_set                = hns3_fec_set,
7444         .tm_ops_get             = hns3_tm_ops_get,
7445         .tx_done_cleanup        = hns3_tx_done_cleanup,
7446         .timesync_enable            = hns3_timesync_enable,
7447         .timesync_disable           = hns3_timesync_disable,
7448         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7449         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7450         .timesync_adjust_time       = hns3_timesync_adjust_time,
7451         .timesync_read_time         = hns3_timesync_read_time,
7452         .timesync_write_time        = hns3_timesync_write_time,
7453 };
7454
7455 static const struct hns3_reset_ops hns3_reset_ops = {
7456         .reset_service       = hns3_reset_service,
7457         .stop_service        = hns3_stop_service,
7458         .prepare_reset       = hns3_prepare_reset,
7459         .wait_hardware_ready = hns3_wait_hardware_ready,
7460         .reinit_dev          = hns3_reinit_dev,
7461         .restore_conf        = hns3_restore_conf,
7462         .start_service       = hns3_start_service,
7463 };
7464
7465 static int
7466 hns3_dev_init(struct rte_eth_dev *eth_dev)
7467 {
7468         struct hns3_adapter *hns = eth_dev->data->dev_private;
7469         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7470         struct rte_ether_addr *eth_addr;
7471         struct hns3_hw *hw = &hns->hw;
7472         int ret;
7473
7474         PMD_INIT_FUNC_TRACE();
7475
7476         hns3_flow_init(eth_dev);
7477
7478         hns3_set_rxtx_function(eth_dev);
7479         eth_dev->dev_ops = &hns3_eth_dev_ops;
7480         eth_dev->rx_queue_count = hns3_rx_queue_count;
7481         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7482                 ret = hns3_mp_init_secondary();
7483                 if (ret) {
7484                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7485                                      "process, ret = %d", ret);
7486                         goto err_mp_init_secondary;
7487                 }
7488                 hw->secondary_cnt++;
7489                 hns3_tx_push_init(eth_dev);
7490                 return 0;
7491         }
7492
7493         ret = hns3_mp_init_primary();
7494         if (ret) {
7495                 PMD_INIT_LOG(ERR,
7496                              "Failed to init for primary process, ret = %d",
7497                              ret);
7498                 goto err_mp_init_primary;
7499         }
7500
7501         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7502         hns->is_vf = false;
7503         hw->data = eth_dev->data;
7504         hns3_parse_devargs(eth_dev);
7505
7506         /*
7507          * Set default max packet size according to the mtu
7508          * default vale in DPDK frame.
7509          */
7510         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7511
7512         ret = hns3_reset_init(hw);
7513         if (ret)
7514                 goto err_init_reset;
7515         hw->reset.ops = &hns3_reset_ops;
7516
7517         ret = hns3_init_pf(eth_dev);
7518         if (ret) {
7519                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7520                 goto err_init_pf;
7521         }
7522
7523         /* Allocate memory for storing MAC addresses */
7524         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7525                                                sizeof(struct rte_ether_addr) *
7526                                                HNS3_UC_MACADDR_NUM, 0);
7527         if (eth_dev->data->mac_addrs == NULL) {
7528                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7529                              "to store MAC addresses",
7530                              sizeof(struct rte_ether_addr) *
7531                              HNS3_UC_MACADDR_NUM);
7532                 ret = -ENOMEM;
7533                 goto err_rte_zmalloc;
7534         }
7535
7536         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7537         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7538                 rte_eth_random_addr(hw->mac.mac_addr);
7539                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7540                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7541                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7542                           "unicast address, using random MAC address %s",
7543                           mac_str);
7544         }
7545         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7546                             &eth_dev->data->mac_addrs[0]);
7547
7548         hw->adapter_state = HNS3_NIC_INITIALIZED;
7549
7550         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7551                             SCHEDULE_PENDING) {
7552                 hns3_err(hw, "Reschedule reset service after dev_init");
7553                 hns3_schedule_reset(hns);
7554         } else {
7555                 /* IMP will wait ready flag before reset */
7556                 hns3_notify_reset_ready(hw, false);
7557         }
7558
7559         hns3_info(hw, "hns3 dev initialization successful!");
7560         return 0;
7561
7562 err_rte_zmalloc:
7563         hns3_uninit_pf(eth_dev);
7564
7565 err_init_pf:
7566         rte_free(hw->reset.wait_data);
7567
7568 err_init_reset:
7569         hns3_mp_uninit_primary();
7570
7571 err_mp_init_primary:
7572 err_mp_init_secondary:
7573         eth_dev->dev_ops = NULL;
7574         eth_dev->rx_pkt_burst = NULL;
7575         eth_dev->rx_descriptor_status = NULL;
7576         eth_dev->tx_pkt_burst = NULL;
7577         eth_dev->tx_pkt_prepare = NULL;
7578         eth_dev->tx_descriptor_status = NULL;
7579         return ret;
7580 }
7581
7582 static int
7583 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7584 {
7585         struct hns3_adapter *hns = eth_dev->data->dev_private;
7586         struct hns3_hw *hw = &hns->hw;
7587
7588         PMD_INIT_FUNC_TRACE();
7589
7590         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
7591                 return 0;
7592
7593         if (hw->adapter_state < HNS3_NIC_CLOSING)
7594                 hns3_dev_close(eth_dev);
7595
7596         hw->adapter_state = HNS3_NIC_REMOVED;
7597         return 0;
7598 }
7599
7600 static int
7601 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7602                    struct rte_pci_device *pci_dev)
7603 {
7604         return rte_eth_dev_pci_generic_probe(pci_dev,
7605                                              sizeof(struct hns3_adapter),
7606                                              hns3_dev_init);
7607 }
7608
7609 static int
7610 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7611 {
7612         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7613 }
7614
7615 static const struct rte_pci_id pci_id_hns3_map[] = {
7616         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7617         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7618         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7619         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7620         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7621         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7622         { .vendor_id = 0, }, /* sentinel */
7623 };
7624
7625 static struct rte_pci_driver rte_hns3_pmd = {
7626         .id_table = pci_id_hns3_map,
7627         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7628         .probe = eth_hns3_pci_probe,
7629         .remove = eth_hns3_pci_remove,
7630 };
7631
7632 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7633 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7634 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7635 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7636                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7637                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7638                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7639 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7640 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);