drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_bus_pci.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_dev.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_regs.h"
  27
  28 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  29 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  30
  31 int hns3_logtype_init;
  32 int hns3_logtype_driver;
  33
  34 static int
  35 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
  36                 unsigned int tso_mss_max)
  37 {
  38         struct hns3_cfg_tso_status_cmd *req;
  39         struct hns3_cmd_desc desc;
  40         uint16_t tso_mss;
  41
  42         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
  43
  44         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
  45
  46         tso_mss = 0;
  47         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  48                        tso_mss_min);
  49         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
  50
  51         tso_mss = 0;
  52         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  53                        tso_mss_max);
  54         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
  55
  56         return hns3_cmd_send(hw, &desc, 1);
  57 }
  58
  59 int
  60 hns3_config_gro(struct hns3_hw *hw, bool en)
  61 {
  62         struct hns3_cfg_gro_status_cmd *req;
  63         struct hns3_cmd_desc desc;
  64         int ret;
  65
  66         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
  67         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
  68
  69         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
  70
  71         ret = hns3_cmd_send(hw, &desc, 1);
  72         if (ret)
  73                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
  74
  75         return ret;
  76 }
  77
  78 static int
  79 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
  80                    uint16_t *allocated_size, bool is_alloc)
  81 {
  82         struct hns3_umv_spc_alc_cmd *req;
  83         struct hns3_cmd_desc desc;
  84         int ret;
  85
  86         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
  87         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
  88         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
  89         req->space_size = rte_cpu_to_le_32(space_size);
  90
  91         ret = hns3_cmd_send(hw, &desc, 1);
  92         if (ret) {
  93                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
  94                              is_alloc ? "allocate" : "free", ret);
  95                 return ret;
  96         }
  97
  98         if (is_alloc && allocated_size)
  99                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
 100
 101         return 0;
 102 }
 103
 104 static int
 105 hns3_init_umv_space(struct hns3_hw *hw)
 106 {
 107         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 108         struct hns3_pf *pf = &hns->pf;
 109         uint16_t allocated_size = 0;
 110         int ret;
 111
 112         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
 113                                  true);
 114         if (ret)
 115                 return ret;
 116
 117         if (allocated_size < pf->wanted_umv_size)
 118                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
 119                              pf->wanted_umv_size, allocated_size);
 120
 121         pf->max_umv_size = (!!allocated_size) ? allocated_size :
 122                                                 pf->wanted_umv_size;
 123         pf->used_umv_size = 0;
 124         return 0;
 125 }
 126
 127 static int
 128 hns3_uninit_umv_space(struct hns3_hw *hw)
 129 {
 130         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 131         struct hns3_pf *pf = &hns->pf;
 132         int ret;
 133
 134         if (pf->max_umv_size == 0)
 135                 return 0;
 136
 137         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
 138         if (ret)
 139                 return ret;
 140
 141         pf->max_umv_size = 0;
 142
 143         return 0;
 144 }
 145
 146 static bool
 147 hns3_is_umv_space_full(struct hns3_hw *hw)
 148 {
 149         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 150         struct hns3_pf *pf = &hns->pf;
 151         bool is_full;
 152
 153         is_full = (pf->used_umv_size >= pf->max_umv_size);
 154
 155         return is_full;
 156 }
 157
 158 static void
 159 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
 160 {
 161         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 162         struct hns3_pf *pf = &hns->pf;
 163
 164         if (is_free) {
 165                 if (pf->used_umv_size > 0)
 166                         pf->used_umv_size--;
 167         } else
 168                 pf->used_umv_size++;
 169 }
 170
 171 static void
 172 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
 173                       const uint8_t *addr, bool is_mc)
 174 {
 175         const unsigned char *mac_addr = addr;
 176         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
 177                             ((uint32_t)mac_addr[2] << 16) |
 178                             ((uint32_t)mac_addr[1] << 8) |
 179                             (uint32_t)mac_addr[0];
 180         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
 181
 182         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 183         if (is_mc) {
 184                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 185                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
 186                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 187         }
 188
 189         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
 190         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
 191 }
 192
 193 static int
 194 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
 195                              uint8_t resp_code,
 196                              enum hns3_mac_vlan_tbl_opcode op)
 197 {
 198         if (cmdq_resp) {
 199                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
 200                          cmdq_resp);
 201                 return -EIO;
 202         }
 203
 204         if (op == HNS3_MAC_VLAN_ADD) {
 205                 if (resp_code == 0 || resp_code == 1) {
 206                         return 0;
 207                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
 208                         hns3_err(hw, "add mac addr failed for uc_overflow");
 209                         return -ENOSPC;
 210                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
 211                         hns3_err(hw, "add mac addr failed for mc_overflow");
 212                         return -ENOSPC;
 213                 }
 214
 215                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
 216                          resp_code);
 217                 return -EIO;
 218         } else if (op == HNS3_MAC_VLAN_REMOVE) {
 219                 if (resp_code == 0) {
 220                         return 0;
 221                 } else if (resp_code == 1) {
 222                         hns3_dbg(hw, "remove mac addr failed for miss");
 223                         return -ENOENT;
 224                 }
 225
 226                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
 227                          resp_code);
 228                 return -EIO;
 229         } else if (op == HNS3_MAC_VLAN_LKUP) {
 230                 if (resp_code == 0) {
 231                         return 0;
 232                 } else if (resp_code == 1) {
 233                         hns3_dbg(hw, "lookup mac addr failed for miss");
 234                         return -ENOENT;
 235                 }
 236
 237                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
 238                          resp_code);
 239                 return -EIO;
 240         }
 241
 242         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
 243                  op);
 244
 245         return -EINVAL;
 246 }
 247
 248 static int
 249 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
 250                          struct hns3_mac_vlan_tbl_entry_cmd *req,
 251                          struct hns3_cmd_desc *desc, bool is_mc)
 252 {
 253         uint8_t resp_code;
 254         uint16_t retval;
 255         int ret;
 256
 257         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
 258         if (is_mc) {
 259                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 260                 memcpy(desc[0].data, req,
 261                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 262                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
 263                                           true);
 264                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 265                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
 266                                           true);
 267                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 268         } else {
 269                 memcpy(desc[0].data, req,
 270                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 271                 ret = hns3_cmd_send(hw, desc, 1);
 272         }
 273         if (ret) {
 274                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
 275                          ret);
 276                 return ret;
 277         }
 278         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
 279         retval = rte_le_to_cpu_16(desc[0].retval);
 280
 281         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 282                                             HNS3_MAC_VLAN_LKUP);
 283 }
 284
 285 static int
 286 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
 287                       struct hns3_mac_vlan_tbl_entry_cmd *req,
 288                       struct hns3_cmd_desc *mc_desc)
 289 {
 290         uint8_t resp_code;
 291         uint16_t retval;
 292         int cfg_status;
 293         int ret;
 294
 295         if (mc_desc == NULL) {
 296                 struct hns3_cmd_desc desc;
 297
 298                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
 299                 memcpy(desc.data, req,
 300                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 301                 ret = hns3_cmd_send(hw, &desc, 1);
 302                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 303                 retval = rte_le_to_cpu_16(desc.retval);
 304
 305                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 306                                                           HNS3_MAC_VLAN_ADD);
 307         } else {
 308                 hns3_cmd_reuse_desc(&mc_desc[0], false);
 309                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 310                 hns3_cmd_reuse_desc(&mc_desc[1], false);
 311                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 312                 hns3_cmd_reuse_desc(&mc_desc[2], false);
 313                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
 314                 memcpy(mc_desc[0].data, req,
 315                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 316                 mc_desc[0].retval = 0;
 317                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 318                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
 319                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
 320
 321                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 322                                                           HNS3_MAC_VLAN_ADD);
 323         }
 324
 325         if (ret) {
 326                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
 327                 return ret;
 328         }
 329
 330         return cfg_status;
 331 }
 332
 333 static int
 334 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
 335                          struct hns3_mac_vlan_tbl_entry_cmd *req)
 336 {
 337         struct hns3_cmd_desc desc;
 338         uint8_t resp_code;
 339         uint16_t retval;
 340         int ret;
 341
 342         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
 343
 344         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 345
 346         ret = hns3_cmd_send(hw, &desc, 1);
 347         if (ret) {
 348                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
 349                 return ret;
 350         }
 351         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 352         retval = rte_le_to_cpu_16(desc.retval);
 353
 354         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 355                                             HNS3_MAC_VLAN_REMOVE);
 356 }
 357
 358 static int
 359 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 360 {
 361         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 362         struct hns3_mac_vlan_tbl_entry_cmd req;
 363         struct hns3_pf *pf = &hns->pf;
 364         struct hns3_cmd_desc desc;
 365         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 366         uint16_t egress_port = 0;
 367         uint8_t vf_id;
 368         int ret;
 369
 370         /* check if mac addr is valid */
 371         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 372                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 373                                       mac_addr);
 374                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
 375                          mac_str);
 376                 return -EINVAL;
 377         }
 378
 379         memset(&req, 0, sizeof(req));
 380
 381         /*
 382          * In current version VF is not supported when PF is driven by DPDK
 383          * driver, the PF-related vf_id is 0, just need to configure parameters
 384          * for vf_id 0.
 385          */
 386         vf_id = 0;
 387         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
 388                        HNS3_MAC_EPORT_VFID_S, vf_id);
 389
 390         req.egress_port = rte_cpu_to_le_16(egress_port);
 391
 392         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 393
 394         /*
 395          * Lookup the mac address in the mac_vlan table, and add
 396          * it if the entry is inexistent. Repeated unicast entry
 397          * is not allowed in the mac vlan table.
 398          */
 399         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
 400         if (ret == -ENOENT) {
 401                 if (!hns3_is_umv_space_full(hw)) {
 402                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
 403                         if (!ret)
 404                                 hns3_update_umv_space(hw, false);
 405                         return ret;
 406                 }
 407
 408                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
 409
 410                 return -ENOSPC;
 411         }
 412
 413         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
 414
 415         /* check if we just hit the duplicate */
 416         if (ret == 0) {
 417                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
 418                 return 0;
 419         }
 420
 421         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
 422                  mac_str);
 423
 424         return ret;
 425 }
 426
 427 static int
 428 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 429                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
 430 {
 431         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 432         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 433         int ret;
 434
 435         rte_spinlock_lock(&hw->lock);
 436         ret = hns3_add_uc_addr_common(hw, mac_addr);
 437         if (ret) {
 438                 rte_spinlock_unlock(&hw->lock);
 439                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 440                                       mac_addr);
 441                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
 442                 return ret;
 443         }
 444
 445         if (idx == 0)
 446                 hw->mac.default_addr_setted = true;
 447         rte_spinlock_unlock(&hw->lock);
 448
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 454 {
 455         struct hns3_mac_vlan_tbl_entry_cmd req;
 456         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 457         int ret;
 458
 459         /* check if mac addr is valid */
 460         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 461                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 462                                       mac_addr);
 463                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
 464                          mac_str);
 465                 return -EINVAL;
 466         }
 467
 468         memset(&req, 0, sizeof(req));
 469         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 470         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 471         ret = hns3_remove_mac_vlan_tbl(hw, &req);
 472         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
 473                 return 0;
 474         else if (ret == 0)
 475                 hns3_update_umv_space(hw, true);
 476
 477         return ret;
 478 }
 479
 480 static void
 481 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 482 {
 483         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 484         /* index will be checked by upper level rte interface */
 485         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 486         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 487         int ret;
 488
 489         rte_spinlock_lock(&hw->lock);
 490         ret = hns3_remove_uc_addr_common(hw, mac_addr);
 491         if (ret) {
 492                 rte_spinlock_unlock(&hw->lock);
 493                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 494                                       mac_addr);
 495                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
 496                 return;
 497         }
 498
 499         if (idx == 0)
 500                 hw->mac.default_addr_setted = false;
 501         rte_spinlock_unlock(&hw->lock);
 502 }
 503
 504 static int
 505 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
 506                           struct rte_ether_addr *mac_addr)
 507 {
 508         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 509         struct rte_ether_addr *oaddr;
 510         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 511         bool default_addr_setted;
 512         bool rm_succes = false;
 513         int ret, ret_val;
 514
 515         /* check if mac addr is valid */
 516         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 517                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 518                                       mac_addr);
 519                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
 520                          mac_str);
 521                 return -EINVAL;
 522         }
 523
 524         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
 525         default_addr_setted = hw->mac.default_addr_setted;
 526         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
 527                 return 0;
 528
 529         rte_spinlock_lock(&hw->lock);
 530         if (default_addr_setted) {
 531                 ret = hns3_remove_uc_addr_common(hw, oaddr);
 532                 if (ret) {
 533                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 534                                               oaddr);
 535                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
 536                                   mac_str, ret);
 537                         rm_succes = false;
 538                 } else
 539                         rm_succes = true;
 540         }
 541
 542         ret = hns3_add_uc_addr_common(hw, mac_addr);
 543         if (ret) {
 544                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 545                                       mac_addr);
 546                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
 547                 goto err_add_uc_addr;
 548         }
 549
 550         rte_ether_addr_copy(mac_addr,
 551                             (struct rte_ether_addr *)hw->mac.mac_addr);
 552         hw->mac.default_addr_setted = true;
 553         rte_spinlock_unlock(&hw->lock);
 554
 555         return 0;
 556
 557 err_add_uc_addr:
 558         if (rm_succes) {
 559                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
 560                 if (ret_val) {
 561                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 562                                               oaddr);
 563                         hns3_warn(hw,
 564                                   "Failed to restore old uc mac addr(%s): %d",
 565                                   mac_str, ret_val);
 566                         hw->mac.default_addr_setted = false;
 567                 }
 568         }
 569         rte_spinlock_unlock(&hw->lock);
 570
 571         return ret;
 572 }
 573
 574 static void
 575 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
 576 {
 577 #define HNS3_VF_NUM_IN_FIRST_DESC 192
 578         uint8_t word_num;
 579         uint8_t bit_num;
 580
 581         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
 582                 word_num = vfid / 32;
 583                 bit_num = vfid % 32;
 584                 if (clr)
 585                         desc[1].data[word_num] &=
 586                             rte_cpu_to_le_32(~(1UL << bit_num));
 587                 else
 588                         desc[1].data[word_num] |=
 589                             rte_cpu_to_le_32(1UL << bit_num);
 590         } else {
 591                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
 592                 bit_num = vfid % 32;
 593                 if (clr)
 594                         desc[2].data[word_num] &=
 595                             rte_cpu_to_le_32(~(1UL << bit_num));
 596                 else
 597                         desc[2].data[word_num] |=
 598                             rte_cpu_to_le_32(1UL << bit_num);
 599         }
 600 }
 601
 602 static int
 603 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 604 {
 605         struct hns3_mac_vlan_tbl_entry_cmd req;
 606         struct hns3_cmd_desc desc[3];
 607         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 608         uint8_t vf_id;
 609         int ret;
 610
 611         /* Check if mac addr is valid */
 612         if (!rte_is_multicast_ether_addr(mac_addr)) {
 613                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 614                                       mac_addr);
 615                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
 616                          mac_str);
 617                 return -EINVAL;
 618         }
 619
 620         memset(&req, 0, sizeof(req));
 621         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 622         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 623         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 624         if (ret) {
 625                 /* This mac addr do not exist, add new entry for it */
 626                 memset(desc[0].data, 0, sizeof(desc[0].data));
 627                 memset(desc[1].data, 0, sizeof(desc[0].data));
 628                 memset(desc[2].data, 0, sizeof(desc[0].data));
 629         }
 630
 631         /*
 632          * In current version VF is not supported when PF is driven by DPDK
 633          * driver, the PF-related vf_id is 0, just need to configure parameters
 634          * for vf_id 0.
 635          */
 636         vf_id = 0;
 637         hns3_update_desc_vfid(desc, vf_id, false);
 638         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
 639         if (ret) {
 640                 if (ret == -ENOSPC)
 641                         hns3_err(hw, "mc mac vlan table is full");
 642                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 643                                       mac_addr);
 644                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
 645         }
 646
 647         return ret;
 648 }
 649
 650 static int
 651 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 652 {
 653         struct hns3_mac_vlan_tbl_entry_cmd req;
 654         struct hns3_cmd_desc desc[3];
 655         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 656         uint8_t vf_id;
 657         int ret;
 658
 659         /* Check if mac addr is valid */
 660         if (!rte_is_multicast_ether_addr(mac_addr)) {
 661                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 662                                       mac_addr);
 663                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
 664                          mac_str);
 665                 return -EINVAL;
 666         }
 667
 668         memset(&req, 0, sizeof(req));
 669         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 670         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 671         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 672         if (ret == 0) {
 673                 /*
 674                  * This mac addr exist, remove this handle's VFID for it.
 675                  * In current version VF is not supported when PF is driven by
 676                  * DPDK driver, the PF-related vf_id is 0, just need to
 677                  * configure parameters for vf_id 0.
 678                  */
 679                 vf_id = 0;
 680                 hns3_update_desc_vfid(desc, vf_id, true);
 681
 682                 /* All the vfid is zero, so need to delete this entry */
 683                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
 684         } else if (ret == -ENOENT) {
 685                 /* This mac addr doesn't exist. */
 686                 return 0;
 687         }
 688
 689         if (ret) {
 690                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 691                                       mac_addr);
 692                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
 693         }
 694
 695         return ret;
 696 }
 697
 698 static int
 699 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
 700                            struct rte_ether_addr *mc_addr_set,
 701                            uint32_t nb_mc_addr)
 702 {
 703         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 704         struct rte_ether_addr *addr;
 705         uint32_t i;
 706         uint32_t j;
 707
 708         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 709                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 710                          "invalid. valid range: 0~%d",
 711                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 712                 return -EINVAL;
 713         }
 714
 715         /* Check if input mac addresses are valid */
 716         for (i = 0; i < nb_mc_addr; i++) {
 717                 addr = &mc_addr_set[i];
 718                 if (!rte_is_multicast_ether_addr(addr)) {
 719                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 720                                               addr);
 721                         hns3_err(hw,
 722                                  "Failed to set mc mac addr, addr(%s) invalid.",
 723                                  mac_str);
 724                         return -EINVAL;
 725                 }
 726
 727                 /* Check if there are duplicate addresses */
 728                 for (j = i + 1; j < nb_mc_addr; j++) {
 729                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 730                                 rte_ether_format_addr(mac_str,
 731                                                       RTE_ETHER_ADDR_FMT_SIZE,
 732                                                       addr);
 733                                 hns3_err(hw, "Failed to set mc mac addr, "
 734                                          "addrs invalid. two same addrs(%s).",
 735                                          mac_str);
 736                                 return -EINVAL;
 737                         }
 738                 }
 739         }
 740
 741         return 0;
 742 }
 743
 744 static void
 745 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
 746                            struct rte_ether_addr *mc_addr_set,
 747                            int mc_addr_num,
 748                            struct rte_ether_addr *reserved_addr_list,
 749                            int *reserved_addr_num,
 750                            struct rte_ether_addr *add_addr_list,
 751                            int *add_addr_num,
 752                            struct rte_ether_addr *rm_addr_list,
 753                            int *rm_addr_num)
 754 {
 755         struct rte_ether_addr *addr;
 756         int current_addr_num;
 757         int reserved_num = 0;
 758         int add_num = 0;
 759         int rm_num = 0;
 760         int num;
 761         int i;
 762         int j;
 763         bool same_addr;
 764
 765         /* Calculate the mc mac address list that should be removed */
 766         current_addr_num = hw->mc_addrs_num;
 767         for (i = 0; i < current_addr_num; i++) {
 768                 addr = &hw->mc_addrs[i];
 769                 same_addr = false;
 770                 for (j = 0; j < mc_addr_num; j++) {
 771                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 772                                 same_addr = true;
 773                                 break;
 774                         }
 775                 }
 776
 777                 if (!same_addr) {
 778                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
 779                         rm_num++;
 780                 } else {
 781                         rte_ether_addr_copy(addr,
 782                                             &reserved_addr_list[reserved_num]);
 783                         reserved_num++;
 784                 }
 785         }
 786
 787         /* Calculate the mc mac address list that should be added */
 788         for (i = 0; i < mc_addr_num; i++) {
 789                 addr = &mc_addr_set[i];
 790                 same_addr = false;
 791                 for (j = 0; j < current_addr_num; j++) {
 792                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
 793                                 same_addr = true;
 794                                 break;
 795                         }
 796                 }
 797
 798                 if (!same_addr) {
 799                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
 800                         add_num++;
 801                 }
 802         }
 803
 804         /* Reorder the mc mac address list maintained by driver */
 805         for (i = 0; i < reserved_num; i++)
 806                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
 807
 808         for (i = 0; i < rm_num; i++) {
 809                 num = reserved_num + i;
 810                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
 811         }
 812
 813         *reserved_addr_num = reserved_num;
 814         *add_addr_num = add_num;
 815         *rm_addr_num = rm_num;
 816 }
 817
 818 static int
 819 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 820                           struct rte_ether_addr *mc_addr_set,
 821                           uint32_t nb_mc_addr)
 822 {
 823         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 824         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
 825         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
 826         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
 827         struct rte_ether_addr *addr;
 828         int reserved_addr_num;
 829         int add_addr_num;
 830         int rm_addr_num;
 831         int mc_addr_num;
 832         int num;
 833         int ret;
 834         int i;
 835
 836         /* Check if input parameters are valid */
 837         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 838         if (ret)
 839                 return ret;
 840
 841         rte_spinlock_lock(&hw->lock);
 842
 843         /*
 844          * Calculate the mc mac address lists those should be removed and be
 845          * added, Reorder the mc mac address list maintained by driver.
 846          */
 847         mc_addr_num = (int)nb_mc_addr;
 848         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
 849                                    reserved_addr_list, &reserved_addr_num,
 850                                    add_addr_list, &add_addr_num,
 851                                    rm_addr_list, &rm_addr_num);
 852
 853         /* Remove mc mac addresses */
 854         for (i = 0; i < rm_addr_num; i++) {
 855                 num = rm_addr_num - i - 1;
 856                 addr = &rm_addr_list[num];
 857                 ret = hns3_remove_mc_addr(hw, addr);
 858                 if (ret) {
 859                         rte_spinlock_unlock(&hw->lock);
 860                         return ret;
 861                 }
 862                 hw->mc_addrs_num--;
 863         }
 864
 865         /* Add mc mac addresses */
 866         for (i = 0; i < add_addr_num; i++) {
 867                 addr = &add_addr_list[i];
 868                 ret = hns3_add_mc_addr(hw, addr);
 869                 if (ret) {
 870                         rte_spinlock_unlock(&hw->lock);
 871                         return ret;
 872                 }
 873
 874                 num = reserved_addr_num + i;
 875                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
 876                 hw->mc_addrs_num++;
 877         }
 878         rte_spinlock_unlock(&hw->lock);
 879
 880         return 0;
 881 }
 882
 883 static int
 884 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 885 {
 886         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 887         struct hns3_hw *hw = &hns->hw;
 888         struct rte_ether_addr *addr;
 889         int err = 0;
 890         int ret;
 891         int i;
 892
 893         for (i = 0; i < hw->mc_addrs_num; i++) {
 894                 addr = &hw->mc_addrs[i];
 895                 if (!rte_is_multicast_ether_addr(addr))
 896                         continue;
 897                 if (del)
 898                         ret = hns3_remove_mc_addr(hw, addr);
 899                 else
 900                         ret = hns3_add_mc_addr(hw, addr);
 901                 if (ret) {
 902                         err = ret;
 903                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 904                                               addr);
 905                         hns3_dbg(hw, "%s mc mac addr: %s failed",
 906                                  del ? "Remove" : "Restore", mac_str);
 907                 }
 908         }
 909         return err;
 910 }
 911
 912 static int
 913 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
 914 {
 915         struct hns3_config_max_frm_size_cmd *req;
 916         struct hns3_cmd_desc desc;
 917
 918         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
 919
 920         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
 921         req->max_frm_size = rte_cpu_to_le_16(new_mps);
 922         req->min_frm_size = HNS3_MIN_FRAME_LEN;
 923
 924         return hns3_cmd_send(hw, &desc, 1);
 925 }
 926
 927 static int
 928 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
 929 {
 930         int ret;
 931
 932         ret = hns3_set_mac_mtu(hw, mps);
 933         if (ret) {
 934                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
 935                 return ret;
 936         }
 937
 938         ret = hns3_buffer_alloc(hw);
 939         if (ret) {
 940                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
 941                 return ret;
 942         }
 943
 944         return 0;
 945 }
 946
 947 static int
 948 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 949 {
 950         struct hns3_adapter *hns = dev->data->dev_private;
 951         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 952         struct hns3_hw *hw = &hns->hw;
 953         bool is_jumbo_frame;
 954         int ret;
 955
 956         if (dev->data->dev_started) {
 957                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
 958                          "before configuration", dev->data->port_id);
 959                 return -EBUSY;
 960         }
 961
 962         rte_spinlock_lock(&hw->lock);
 963         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
 964         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
 965
 966         /*
 967          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
 968          * assign to "uint16_t" type variable.
 969          */
 970         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
 971         if (ret) {
 972                 rte_spinlock_unlock(&hw->lock);
 973                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
 974                          dev->data->port_id, mtu, ret);
 975                 return ret;
 976         }
 977         hns->pf.mps = (uint16_t)frame_size;
 978         if (is_jumbo_frame)
 979                 dev->data->dev_conf.rxmode.offloads |=
 980                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 981         else
 982                 dev->data->dev_conf.rxmode.offloads &=
 983                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 984         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 985         rte_spinlock_unlock(&hw->lock);
 986
 987         return 0;
 988 }
 989
 990 static int
 991 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 992 {
 993         struct hns3_adapter *hns = eth_dev->data->dev_private;
 994         struct hns3_hw *hw = &hns->hw;
 995
 996         info->max_rx_queues = hw->tqps_num;
 997         info->max_tx_queues = hw->tqps_num;
 998         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 999         info->min_rx_bufsize = hw->rx_buf_len;
1000         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
1001         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
1002         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1003                                  DEV_RX_OFFLOAD_TCP_CKSUM |
1004                                  DEV_RX_OFFLOAD_UDP_CKSUM |
1005                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
1006                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1007                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1008                                  DEV_RX_OFFLOAD_KEEP_CRC |
1009                                  DEV_RX_OFFLOAD_SCATTER |
1010                                  DEV_RX_OFFLOAD_VLAN_STRIP |
1011                                  DEV_RX_OFFLOAD_QINQ_STRIP |
1012                                  DEV_RX_OFFLOAD_VLAN_FILTER |
1013                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
1014                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
1015         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1016         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1017                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
1018                                  DEV_TX_OFFLOAD_TCP_CKSUM |
1019                                  DEV_TX_OFFLOAD_UDP_CKSUM |
1020                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
1021                                  DEV_TX_OFFLOAD_VLAN_INSERT |
1022                                  DEV_TX_OFFLOAD_QINQ_INSERT |
1023                                  DEV_TX_OFFLOAD_MULTI_SEGS |
1024                                  info->tx_queue_offload_capa);
1025
1026         info->vmdq_queue_num = 0;
1027
1028         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1029         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1030         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1031         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1032
1033         return 0;
1034 }
1035
1036 static int
1037 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1038                     size_t fw_size)
1039 {
1040         struct hns3_adapter *hns = eth_dev->data->dev_private;
1041         struct hns3_hw *hw = &hns->hw;
1042         int ret;
1043
1044         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
1045         ret += 1; /* add the size of '\0' */
1046         if (fw_size < (uint32_t)ret)
1047                 return ret;
1048         else
1049                 return 0;
1050 }
1051
1052 static int
1053 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
1054 {
1055         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1056         struct hns3_pf *pf = &hns->pf;
1057
1058         if (!(status->pf_state & HNS3_PF_STATE_DONE))
1059                 return -EINVAL;
1060
1061         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
1062
1063         return 0;
1064 }
1065
1066 static int
1067 hns3_query_function_status(struct hns3_hw *hw)
1068 {
1069 #define HNS3_QUERY_MAX_CNT              10
1070 #define HNS3_QUERY_SLEEP_MSCOEND        1
1071         struct hns3_func_status_cmd *req;
1072         struct hns3_cmd_desc desc;
1073         int timeout = 0;
1074         int ret;
1075
1076         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
1077         req = (struct hns3_func_status_cmd *)desc.data;
1078
1079         do {
1080                 ret = hns3_cmd_send(hw, &desc, 1);
1081                 if (ret) {
1082                         PMD_INIT_LOG(ERR, "query function status failed %d",
1083                                      ret);
1084                         return ret;
1085                 }
1086
1087                 /* Check pf reset is done */
1088                 if (req->pf_state)
1089                         break;
1090
1091                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
1092         } while (timeout++ < HNS3_QUERY_MAX_CNT);
1093
1094         return hns3_parse_func_status(hw, req);
1095 }
1096
1097 static int
1098 hns3_query_pf_resource(struct hns3_hw *hw)
1099 {
1100         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1101         struct hns3_pf *pf = &hns->pf;
1102         struct hns3_pf_res_cmd *req;
1103         struct hns3_cmd_desc desc;
1104         int ret;
1105
1106         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
1107         ret = hns3_cmd_send(hw, &desc, 1);
1108         if (ret) {
1109                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
1110                 return ret;
1111         }
1112
1113         req = (struct hns3_pf_res_cmd *)desc.data;
1114         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
1115         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
1116         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1117
1118         if (req->tx_buf_size)
1119                 pf->tx_buf_size =
1120                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
1121         else
1122                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
1123
1124         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
1125
1126         if (req->dv_buf_size)
1127                 pf->dv_buf_size =
1128                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
1129         else
1130                 pf->dv_buf_size = HNS3_DEFAULT_DV;
1131
1132         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
1133
1134         hw->num_msi =
1135             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
1136                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
1137
1138         return 0;
1139 }
1140
1141 static void
1142 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
1143 {
1144         struct hns3_cfg_param_cmd *req;
1145         uint64_t mac_addr_tmp_high;
1146         uint64_t mac_addr_tmp;
1147         uint32_t i;
1148
1149         req = (struct hns3_cfg_param_cmd *)desc[0].data;
1150
1151         /* get the configuration */
1152         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1153                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
1154         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1155                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
1156         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1157                                            HNS3_CFG_TQP_DESC_N_M,
1158                                            HNS3_CFG_TQP_DESC_N_S);
1159
1160         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1161                                        HNS3_CFG_PHY_ADDR_M,
1162                                        HNS3_CFG_PHY_ADDR_S);
1163         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1164                                          HNS3_CFG_MEDIA_TP_M,
1165                                          HNS3_CFG_MEDIA_TP_S);
1166         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1167                                          HNS3_CFG_RX_BUF_LEN_M,
1168                                          HNS3_CFG_RX_BUF_LEN_S);
1169         /* get mac address */
1170         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
1171         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1172                                            HNS3_CFG_MAC_ADDR_H_M,
1173                                            HNS3_CFG_MAC_ADDR_H_S);
1174
1175         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1176
1177         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1178                                             HNS3_CFG_DEFAULT_SPEED_M,
1179                                             HNS3_CFG_DEFAULT_SPEED_S);
1180         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1181                                            HNS3_CFG_RSS_SIZE_M,
1182                                            HNS3_CFG_RSS_SIZE_S);
1183
1184         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
1185                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1186
1187         req = (struct hns3_cfg_param_cmd *)desc[1].data;
1188         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
1189
1190         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1191                                             HNS3_CFG_SPEED_ABILITY_M,
1192                                             HNS3_CFG_SPEED_ABILITY_S);
1193         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1194                                         HNS3_CFG_UMV_TBL_SPACE_M,
1195                                         HNS3_CFG_UMV_TBL_SPACE_S);
1196         if (!cfg->umv_space)
1197                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
1198 }
1199
1200 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
1201  * @hw: pointer to struct hns3_hw
1202  * @hcfg: the config structure to be getted
1203  */
1204 static int
1205 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
1206 {
1207         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
1208         struct hns3_cfg_param_cmd *req;
1209         uint32_t offset;
1210         uint32_t i;
1211         int ret;
1212
1213         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
1214                 offset = 0;
1215                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
1216                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
1217                                           true);
1218                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
1219                                i * HNS3_CFG_RD_LEN_BYTES);
1220                 /* Len should be divided by 4 when send to hardware */
1221                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
1222                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
1223                 req->offset = rte_cpu_to_le_32(offset);
1224         }
1225
1226         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
1227         if (ret) {
1228                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
1229                 return ret;
1230         }
1231
1232         hns3_parse_cfg(hcfg, desc);
1233
1234         return 0;
1235 }
1236
1237 static int
1238 hns3_parse_speed(int speed_cmd, uint32_t *speed)
1239 {
1240         switch (speed_cmd) {
1241         case HNS3_CFG_SPEED_10M:
1242                 *speed = ETH_SPEED_NUM_10M;
1243                 break;
1244         case HNS3_CFG_SPEED_100M:
1245                 *speed = ETH_SPEED_NUM_100M;
1246                 break;
1247         case HNS3_CFG_SPEED_1G:
1248                 *speed = ETH_SPEED_NUM_1G;
1249                 break;
1250         case HNS3_CFG_SPEED_10G:
1251                 *speed = ETH_SPEED_NUM_10G;
1252                 break;
1253         case HNS3_CFG_SPEED_25G:
1254                 *speed = ETH_SPEED_NUM_25G;
1255                 break;
1256         case HNS3_CFG_SPEED_40G:
1257                 *speed = ETH_SPEED_NUM_40G;
1258                 break;
1259         case HNS3_CFG_SPEED_50G:
1260                 *speed = ETH_SPEED_NUM_50G;
1261                 break;
1262         case HNS3_CFG_SPEED_100G:
1263                 *speed = ETH_SPEED_NUM_100G;
1264                 break;
1265         default:
1266                 return -EINVAL;
1267         }
1268
1269         return 0;
1270 }
1271
1272 static int
1273 hns3_get_board_configuration(struct hns3_hw *hw)
1274 {
1275         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1276         struct hns3_pf *pf = &hns->pf;
1277         struct hns3_cfg cfg;
1278         int ret;
1279
1280         ret = hns3_get_board_cfg(hw, &cfg);
1281         if (ret) {
1282                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
1283                 return ret;
1284         }
1285
1286         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
1287                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
1288                 return -EOPNOTSUPP;
1289         }
1290
1291         hw->mac.media_type = cfg.media_type;
1292         hw->rss_size_max = cfg.rss_size_max;
1293         hw->rx_buf_len = cfg.rx_buf_len;
1294         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
1295         hw->mac.phy_addr = cfg.phy_addr;
1296         hw->mac.default_addr_setted = false;
1297         hw->num_tx_desc = cfg.tqp_desc_num;
1298         hw->num_rx_desc = cfg.tqp_desc_num;
1299         hw->dcb_info.num_pg = 1;
1300         hw->dcb_info.hw_pfc_map = 0;
1301
1302         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
1303         if (ret) {
1304                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
1305                              cfg.default_speed, ret);
1306                 return ret;
1307         }
1308
1309         pf->tc_max = cfg.tc_num;
1310         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
1311                 PMD_INIT_LOG(WARNING,
1312                              "Get TC num(%u) from flash, set TC num to 1",
1313                              pf->tc_max);
1314                 pf->tc_max = 1;
1315         }
1316
1317         /* Dev does not support DCB */
1318         if (!hns3_dev_dcb_supported(hw)) {
1319                 pf->tc_max = 1;
1320                 pf->pfc_max = 0;
1321         } else
1322                 pf->pfc_max = pf->tc_max;
1323
1324         hw->dcb_info.num_tc = 1;
1325         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
1326                                      hw->tqps_num / hw->dcb_info.num_tc);
1327         hns3_set_bit(hw->hw_tc_map, 0, 1);
1328         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
1329
1330         pf->wanted_umv_size = cfg.umv_space;
1331
1332         return ret;
1333 }
1334
1335 static int
1336 hns3_get_configuration(struct hns3_hw *hw)
1337 {
1338         int ret;
1339
1340         ret = hns3_query_function_status(hw);
1341         if (ret) {
1342                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
1343                 return ret;
1344         }
1345
1346         /* Get pf resource */
1347         ret = hns3_query_pf_resource(hw);
1348         if (ret) {
1349                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
1350                 return ret;
1351         }
1352
1353         ret = hns3_get_board_configuration(hw);
1354         if (ret) {
1355                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
1356                 return ret;
1357         }
1358
1359         return 0;
1360 }
1361
1362 static int
1363 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
1364                       uint16_t tqp_vid, bool is_pf)
1365 {
1366         struct hns3_tqp_map_cmd *req;
1367         struct hns3_cmd_desc desc;
1368         int ret;
1369
1370         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
1371
1372         req = (struct hns3_tqp_map_cmd *)desc.data;
1373         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
1374         req->tqp_vf = func_id;
1375         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
1376         if (!is_pf)
1377                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
1378         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
1379
1380         ret = hns3_cmd_send(hw, &desc, 1);
1381         if (ret)
1382                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
1383
1384         return ret;
1385 }
1386
1387 static int
1388 hns3_map_tqp(struct hns3_hw *hw)
1389 {
1390         uint16_t tqps_num = hw->total_tqps_num;
1391         uint16_t func_id;
1392         uint16_t tqp_id;
1393         int num;
1394         int ret;
1395         int i;
1396
1397         /*
1398          * In current version VF is not supported when PF is driven by DPDK
1399          * driver, so we allocate tqps to PF as much as possible.
1400          */
1401         tqp_id = 0;
1402         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1403         for (func_id = 0; func_id < num; func_id++) {
1404                 for (i = 0;
1405                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
1406                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
1407                                                     true);
1408                         if (ret)
1409                                 return ret;
1410                 }
1411         }
1412
1413         return 0;
1414 }
1415
1416 static int
1417 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
1418 {
1419         struct hns3_config_mac_speed_dup_cmd *req;
1420         struct hns3_cmd_desc desc;
1421         int ret;
1422
1423         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
1424
1425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
1426
1427         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
1428
1429         switch (speed) {
1430         case ETH_SPEED_NUM_10M:
1431                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1432                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
1433                 break;
1434         case ETH_SPEED_NUM_100M:
1435                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1436                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
1437                 break;
1438         case ETH_SPEED_NUM_1G:
1439                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1440                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
1441                 break;
1442         case ETH_SPEED_NUM_10G:
1443                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1444                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
1445                 break;
1446         case ETH_SPEED_NUM_25G:
1447                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1448                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
1449                 break;
1450         case ETH_SPEED_NUM_40G:
1451                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1452                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
1453                 break;
1454         case ETH_SPEED_NUM_50G:
1455                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1456                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
1457                 break;
1458         case ETH_SPEED_NUM_100G:
1459                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1460                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
1461                 break;
1462         default:
1463                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
1464                 return -EINVAL;
1465         }
1466
1467         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
1468
1469         ret = hns3_cmd_send(hw, &desc, 1);
1470         if (ret)
1471                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
1472
1473         return ret;
1474 }
1475
1476 static int
1477 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1478 {
1479         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1480         struct hns3_pf *pf = &hns->pf;
1481         struct hns3_priv_buf *priv;
1482         uint32_t i, total_size;
1483
1484         total_size = pf->pkt_buf_size;
1485
1486         /* alloc tx buffer for all enabled tc */
1487         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1488                 priv = &buf_alloc->priv_buf[i];
1489
1490                 if (hw->hw_tc_map & BIT(i)) {
1491                         if (total_size < pf->tx_buf_size)
1492                                 return -ENOMEM;
1493
1494                         priv->tx_buf_size = pf->tx_buf_size;
1495                 } else
1496                         priv->tx_buf_size = 0;
1497
1498                 total_size -= priv->tx_buf_size;
1499         }
1500
1501         return 0;
1502 }
1503
1504 static int
1505 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1506 {
1507 /* TX buffer size is unit by 128 byte */
1508 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
1509 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
1510         struct hns3_tx_buff_alloc_cmd *req;
1511         struct hns3_cmd_desc desc;
1512         uint32_t buf_size;
1513         uint32_t i;
1514         int ret;
1515
1516         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
1517
1518         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
1519         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1520                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1521
1522                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
1523                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
1524                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
1525         }
1526
1527         ret = hns3_cmd_send(hw, &desc, 1);
1528         if (ret)
1529                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
1530
1531         return ret;
1532 }
1533
1534 static int
1535 hns3_get_tc_num(struct hns3_hw *hw)
1536 {
1537         int cnt = 0;
1538         uint8_t i;
1539
1540         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1541                 if (hw->hw_tc_map & BIT(i))
1542                         cnt++;
1543         return cnt;
1544 }
1545
1546 static uint32_t
1547 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1548 {
1549         struct hns3_priv_buf *priv;
1550         uint32_t rx_priv = 0;
1551         int i;
1552
1553         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1554                 priv = &buf_alloc->priv_buf[i];
1555                 if (priv->enable)
1556                         rx_priv += priv->buf_size;
1557         }
1558         return rx_priv;
1559 }
1560
1561 static uint32_t
1562 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1563 {
1564         uint32_t total_tx_size = 0;
1565         uint32_t i;
1566
1567         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1568                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1569
1570         return total_tx_size;
1571 }
1572
1573 /* Get the number of pfc enabled TCs, which have private buffer */
1574 static int
1575 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1576 {
1577         struct hns3_priv_buf *priv;
1578         int cnt = 0;
1579         uint8_t i;
1580
1581         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1582                 priv = &buf_alloc->priv_buf[i];
1583                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1584                         cnt++;
1585         }
1586
1587         return cnt;
1588 }
1589
1590 /* Get the number of pfc disabled TCs, which have private buffer */
1591 static int
1592 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
1593                          struct hns3_pkt_buf_alloc *buf_alloc)
1594 {
1595         struct hns3_priv_buf *priv;
1596         int cnt = 0;
1597         uint8_t i;
1598
1599         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1600                 priv = &buf_alloc->priv_buf[i];
1601                 if (hw->hw_tc_map & BIT(i) &&
1602                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1603                         cnt++;
1604         }
1605
1606         return cnt;
1607 }
1608
1609 static bool
1610 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
1611                   uint32_t rx_all)
1612 {
1613         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
1614         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1615         struct hns3_pf *pf = &hns->pf;
1616         uint32_t shared_buf, aligned_mps;
1617         uint32_t rx_priv;
1618         uint8_t tc_num;
1619         uint8_t i;
1620
1621         tc_num = hns3_get_tc_num(hw);
1622         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1623
1624         if (hns3_dev_dcb_supported(hw))
1625                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
1626                                         pf->dv_buf_size;
1627         else
1628                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
1629                                         + pf->dv_buf_size;
1630
1631         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
1632         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
1633                              HNS3_BUF_SIZE_UNIT);
1634
1635         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
1636         if (rx_all < rx_priv + shared_std)
1637                 return false;
1638
1639         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
1640         buf_alloc->s_buf.buf_size = shared_buf;
1641         if (hns3_dev_dcb_supported(hw)) {
1642                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
1643                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1644                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
1645                                   HNS3_BUF_SIZE_UNIT);
1646         } else {
1647                 buf_alloc->s_buf.self.high =
1648                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1649                 buf_alloc->s_buf.self.low = aligned_mps;
1650         }
1651
1652         if (hns3_dev_dcb_supported(hw)) {
1653                 hi_thrd = shared_buf - pf->dv_buf_size;
1654
1655                 if (tc_num <= NEED_RESERVE_TC_NUM)
1656                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
1657                                         / BUF_MAX_PERCENT;
1658
1659                 if (tc_num)
1660                         hi_thrd = hi_thrd / tc_num;
1661
1662                 hi_thrd = max_t(uint32_t, hi_thrd,
1663                                 HNS3_BUF_MUL_BY * aligned_mps);
1664                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
1665                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
1666         } else {
1667                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1668                 lo_thrd = aligned_mps;
1669         }
1670
1671         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1672                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
1673                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
1674         }
1675
1676         return true;
1677 }
1678
1679 static bool
1680 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
1681                      struct hns3_pkt_buf_alloc *buf_alloc)
1682 {
1683         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1684         struct hns3_pf *pf = &hns->pf;
1685         struct hns3_priv_buf *priv;
1686         uint32_t aligned_mps;
1687         uint32_t rx_all;
1688         uint8_t i;
1689
1690         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1691         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1692
1693         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1694                 priv = &buf_alloc->priv_buf[i];
1695
1696                 priv->enable = 0;
1697                 priv->wl.low = 0;
1698                 priv->wl.high = 0;
1699                 priv->buf_size = 0;
1700
1701                 if (!(hw->hw_tc_map & BIT(i)))
1702                         continue;
1703
1704                 priv->enable = 1;
1705                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
1706                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
1707                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
1708                                                 HNS3_BUF_SIZE_UNIT);
1709                 } else {
1710                         priv->wl.low = 0;
1711                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
1712                                         aligned_mps;
1713                 }
1714
1715                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
1716         }
1717
1718         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1719 }
1720
1721 static bool
1722 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
1723                              struct hns3_pkt_buf_alloc *buf_alloc)
1724 {
1725         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1726         struct hns3_pf *pf = &hns->pf;
1727         struct hns3_priv_buf *priv;
1728         int no_pfc_priv_num;
1729         uint32_t rx_all;
1730         uint8_t mask;
1731         int i;
1732
1733         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1734         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
1735
1736         /* let the last to be cleared first */
1737         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1738                 priv = &buf_alloc->priv_buf[i];
1739                 mask = BIT((uint8_t)i);
1740
1741                 if (hw->hw_tc_map & mask &&
1742                     !(hw->dcb_info.hw_pfc_map & mask)) {
1743                         /* Clear the no pfc TC private buffer */
1744                         priv->wl.low = 0;
1745                         priv->wl.high = 0;
1746                         priv->buf_size = 0;
1747                         priv->enable = 0;
1748                         no_pfc_priv_num--;
1749                 }
1750
1751                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1752                     no_pfc_priv_num == 0)
1753                         break;
1754         }
1755
1756         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1757 }
1758
1759 static bool
1760 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
1761                            struct hns3_pkt_buf_alloc *buf_alloc)
1762 {
1763         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1764         struct hns3_pf *pf = &hns->pf;
1765         struct hns3_priv_buf *priv;
1766         uint32_t rx_all;
1767         int pfc_priv_num;
1768         uint8_t mask;
1769         int i;
1770
1771         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1772         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
1773
1774         /* let the last to be cleared first */
1775         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1776                 priv = &buf_alloc->priv_buf[i];
1777                 mask = BIT((uint8_t)i);
1778
1779                 if (hw->hw_tc_map & mask &&
1780                     hw->dcb_info.hw_pfc_map & mask) {
1781                         /* Reduce the number of pfc TC with private buffer */
1782                         priv->wl.low = 0;
1783                         priv->enable = 0;
1784                         priv->wl.high = 0;
1785                         priv->buf_size = 0;
1786                         pfc_priv_num--;
1787                 }
1788                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1789                     pfc_priv_num == 0)
1790                         break;
1791         }
1792
1793         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1794 }
1795
1796 static bool
1797 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
1798                           struct hns3_pkt_buf_alloc *buf_alloc)
1799 {
1800 #define COMPENSATE_BUFFER       0x3C00
1801 #define COMPENSATE_HALF_MPS_NUM 5
1802 #define PRIV_WL_GAP             0x1800
1803         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1804         struct hns3_pf *pf = &hns->pf;
1805         uint32_t tc_num = hns3_get_tc_num(hw);
1806         uint32_t half_mps = pf->mps >> 1;
1807         struct hns3_priv_buf *priv;
1808         uint32_t min_rx_priv;
1809         uint32_t rx_priv;
1810         uint8_t i;
1811
1812         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1813         if (tc_num)
1814                 rx_priv = rx_priv / tc_num;
1815
1816         if (tc_num <= NEED_RESERVE_TC_NUM)
1817                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
1818
1819         /*
1820          * Minimum value of private buffer in rx direction (min_rx_priv) is
1821          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
1822          * buffer if rx_priv is greater than min_rx_priv.
1823          */
1824         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
1825                         COMPENSATE_HALF_MPS_NUM * half_mps;
1826         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
1827         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
1828
1829         if (rx_priv < min_rx_priv)
1830                 return false;
1831
1832         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1833                 priv = &buf_alloc->priv_buf[i];
1834
1835                 priv->enable = 0;
1836                 priv->wl.low = 0;
1837                 priv->wl.high = 0;
1838                 priv->buf_size = 0;
1839
1840                 if (!(hw->hw_tc_map & BIT(i)))
1841                         continue;
1842
1843                 priv->enable = 1;
1844                 priv->buf_size = rx_priv;
1845                 priv->wl.high = rx_priv - pf->dv_buf_size;
1846                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
1847         }
1848
1849         buf_alloc->s_buf.buf_size = 0;
1850
1851         return true;
1852 }
1853
1854 /*
1855  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
1856  * @hw: pointer to struct hns3_hw
1857  * @buf_alloc: pointer to buffer calculation data
1858  * @return: 0: calculate sucessful, negative: fail
1859  */
1860 static int
1861 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1862 {
1863         /* When DCB is not supported, rx private buffer is not allocated. */
1864         if (!hns3_dev_dcb_supported(hw)) {
1865                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1866                 struct hns3_pf *pf = &hns->pf;
1867                 uint32_t rx_all = pf->pkt_buf_size;
1868
1869                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
1870                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
1871                         return -ENOMEM;
1872
1873                 return 0;
1874         }
1875
1876         /*
1877          * Try to allocate privated packet buffer for all TCs without share
1878          * buffer.
1879          */
1880         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
1881                 return 0;
1882
1883         /*
1884          * Try to allocate privated packet buffer for all TCs with share
1885          * buffer.
1886          */
1887         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
1888                 return 0;
1889
1890         /*
1891          * For different application scenes, the enabled port number, TC number
1892          * and no_drop TC number are different. In order to obtain the better
1893          * performance, software could allocate the buffer size and configure
1894          * the waterline by tring to decrease the private buffer size according
1895          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
1896          * enabled tc.
1897          */
1898         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
1899                 return 0;
1900
1901         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
1902                 return 0;
1903
1904         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
1905                 return 0;
1906
1907         return -ENOMEM;
1908 }
1909
1910 static int
1911 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1912 {
1913         struct hns3_rx_priv_buff_cmd *req;
1914         struct hns3_cmd_desc desc;
1915         uint32_t buf_size;
1916         int ret;
1917         int i;
1918
1919         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
1920         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
1921
1922         /* Alloc private buffer TCs */
1923         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1924                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
1925
1926                 req->buf_num[i] =
1927                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
1928                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
1929         }
1930
1931         buf_size = buf_alloc->s_buf.buf_size;
1932         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
1933                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
1934
1935         ret = hns3_cmd_send(hw, &desc, 1);
1936         if (ret)
1937                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
1938
1939         return ret;
1940 }
1941
1942 static int
1943 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1944 {
1945 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
1946         struct hns3_rx_priv_wl_buf *req;
1947         struct hns3_priv_buf *priv;
1948         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
1949         int i, j;
1950         int ret;
1951
1952         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
1953                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
1954                                           false);
1955                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
1956
1957                 /* The first descriptor set the NEXT bit to 1 */
1958                 if (i == 0)
1959                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1960                 else
1961                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1962
1963                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
1964                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
1965
1966                         priv = &buf_alloc->priv_buf[idx];
1967                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
1968                                                         HNS3_BUF_UNIT_S);
1969                         req->tc_wl[j].high |=
1970                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
1971                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
1972                                                         HNS3_BUF_UNIT_S);
1973                         req->tc_wl[j].low |=
1974                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
1975                 }
1976         }
1977
1978         /* Send 2 descriptor at one time */
1979         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
1980         if (ret)
1981                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
1982                              ret);
1983         return ret;
1984 }
1985
1986 static int
1987 hns3_common_thrd_config(struct hns3_hw *hw,
1988                         struct hns3_pkt_buf_alloc *buf_alloc)
1989 {
1990 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
1991         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
1992         struct hns3_rx_com_thrd *req;
1993         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
1994         struct hns3_tc_thrd *tc;
1995         int tc_idx;
1996         int i, j;
1997         int ret;
1998
1999         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
2000                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
2001                                           false);
2002                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
2003
2004                 /* The first descriptor set the NEXT bit to 1 */
2005                 if (i == 0)
2006                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2007                 else
2008                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2009
2010                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2011                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
2012                         tc = &s_buf->tc_thrd[tc_idx];
2013
2014                         req->com_thrd[j].high =
2015                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
2016                         req->com_thrd[j].high |=
2017                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2018                         req->com_thrd[j].low =
2019                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
2020                         req->com_thrd[j].low |=
2021                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2022                 }
2023         }
2024
2025         /* Send 2 descriptors at one time */
2026         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
2027         if (ret)
2028                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
2029
2030         return ret;
2031 }
2032
2033 static int
2034 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2035 {
2036         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
2037         struct hns3_rx_com_wl *req;
2038         struct hns3_cmd_desc desc;
2039         int ret;
2040
2041         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
2042
2043         req = (struct hns3_rx_com_wl *)desc.data;
2044         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
2045         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2046
2047         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
2048         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2049
2050         ret = hns3_cmd_send(hw, &desc, 1);
2051         if (ret)
2052                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
2053
2054         return ret;
2055 }
2056
2057 int
2058 hns3_buffer_alloc(struct hns3_hw *hw)
2059 {
2060         struct hns3_pkt_buf_alloc pkt_buf;
2061         int ret;
2062
2063         memset(&pkt_buf, 0, sizeof(pkt_buf));
2064         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
2065         if (ret) {
2066                 PMD_INIT_LOG(ERR,
2067                              "could not calc tx buffer size for all TCs %d",
2068                              ret);
2069                 return ret;
2070         }
2071
2072         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
2073         if (ret) {
2074                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
2075                 return ret;
2076         }
2077
2078         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
2079         if (ret) {
2080                 PMD_INIT_LOG(ERR,
2081                              "could not calc rx priv buffer size for all TCs %d",
2082                              ret);
2083                 return ret;
2084         }
2085
2086         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
2087         if (ret) {
2088                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
2089                 return ret;
2090         }
2091
2092         if (hns3_dev_dcb_supported(hw)) {
2093                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
2094                 if (ret) {
2095                         PMD_INIT_LOG(ERR,
2096                                      "could not configure rx private waterline %d",
2097                                      ret);
2098                         return ret;
2099                 }
2100
2101                 ret = hns3_common_thrd_config(hw, &pkt_buf);
2102                 if (ret) {
2103                         PMD_INIT_LOG(ERR,
2104                                      "could not configure common threshold %d",
2105                                      ret);
2106                         return ret;
2107                 }
2108         }
2109
2110         ret = hns3_common_wl_config(hw, &pkt_buf);
2111         if (ret)
2112                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
2113                              ret);
2114
2115         return ret;
2116 }
2117
2118 static int
2119 hns3_mac_init(struct hns3_hw *hw)
2120 {
2121         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2122         struct hns3_mac *mac = &hw->mac;
2123         struct hns3_pf *pf = &hns->pf;
2124         int ret;
2125
2126         pf->support_sfp_query = true;
2127         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
2128         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
2129         if (ret) {
2130                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
2131                 return ret;
2132         }
2133
2134         mac->link_status = ETH_LINK_DOWN;
2135
2136         return hns3_config_mtu(hw, pf->mps);
2137 }
2138
2139 static int
2140 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
2141 {
2142 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
2143 #define HNS3_ETHERTYPE_ALREADY_ADD              1
2144 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
2145 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
2146         int return_status;
2147
2148         if (cmdq_resp) {
2149                 PMD_INIT_LOG(ERR,
2150                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
2151                              cmdq_resp);
2152                 return -EIO;
2153         }
2154
2155         switch (resp_code) {
2156         case HNS3_ETHERTYPE_SUCCESS_ADD:
2157         case HNS3_ETHERTYPE_ALREADY_ADD:
2158                 return_status = 0;
2159                 break;
2160         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
2161                 PMD_INIT_LOG(ERR,
2162                              "add mac ethertype failed for manager table overflow.");
2163                 return_status = -EIO;
2164                 break;
2165         case HNS3_ETHERTYPE_KEY_CONFLICT:
2166                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
2167                 return_status = -EIO;
2168                 break;
2169         default:
2170                 PMD_INIT_LOG(ERR,
2171                              "add mac ethertype failed for undefined, code=%d.",
2172                              resp_code);
2173                 return_status = -EIO;
2174         }
2175
2176         return return_status;
2177 }
2178
2179 static int
2180 hns3_add_mgr_tbl(struct hns3_hw *hw,
2181                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
2182 {
2183         struct hns3_cmd_desc desc;
2184         uint8_t resp_code;
2185         uint16_t retval;
2186         int ret;
2187
2188         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
2189         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
2190
2191         ret = hns3_cmd_send(hw, &desc, 1);
2192         if (ret) {
2193                 PMD_INIT_LOG(ERR,
2194                              "add mac ethertype failed for cmd_send, ret =%d.",
2195                              ret);
2196                 return ret;
2197         }
2198
2199         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
2200         retval = rte_le_to_cpu_16(desc.retval);
2201
2202         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
2203 }
2204
2205 static void
2206 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
2207                      int *table_item_num)
2208 {
2209         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
2210
2211         /*
2212          * In current version, we add one item in management table as below:
2213          * 0x0180C200000E -- LLDP MC address
2214          */
2215         tbl = mgr_table;
2216         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
2217         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
2218         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
2219         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
2220         tbl->i_port_bitmap = 0x1;
2221         *table_item_num = 1;
2222 }
2223
2224 static int
2225 hns3_init_mgr_tbl(struct hns3_hw *hw)
2226 {
2227 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
2228         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
2229         int table_item_num;
2230         int ret;
2231         int i;
2232
2233         memset(mgr_table, 0, sizeof(mgr_table));
2234         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
2235         for (i = 0; i < table_item_num; i++) {
2236                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
2237                 if (ret) {
2238                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
2239                                      ret);
2240                         return ret;
2241                 }
2242         }
2243
2244         return 0;
2245 }
2246
2247 static void
2248 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
2249                         bool en_mc, bool en_bc, int vport_id)
2250 {
2251         if (!param)
2252                 return;
2253
2254         memset(param, 0, sizeof(struct hns3_promisc_param));
2255         if (en_uc)
2256                 param->enable = HNS3_PROMISC_EN_UC;
2257         if (en_mc)
2258                 param->enable |= HNS3_PROMISC_EN_MC;
2259         if (en_bc)
2260                 param->enable |= HNS3_PROMISC_EN_BC;
2261         param->vf_id = vport_id;
2262 }
2263
2264 static int
2265 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
2266 {
2267         struct hns3_promisc_cfg_cmd *req;
2268         struct hns3_cmd_desc desc;
2269         int ret;
2270
2271         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
2272
2273         req = (struct hns3_promisc_cfg_cmd *)desc.data;
2274         req->vf_id = param->vf_id;
2275         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
2276             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
2277
2278         ret = hns3_cmd_send(hw, &desc, 1);
2279         if (ret)
2280                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
2281
2282         return ret;
2283 }
2284
2285 static int
2286 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
2287 {
2288         struct hns3_promisc_param param;
2289         bool en_bc_pmc = true;
2290         uint8_t vf_id;
2291         int ret;
2292
2293         /*
2294          * In current version VF is not supported when PF is driven by DPDK
2295          * driver, the PF-related vf_id is 0, just need to configure parameters
2296          * for vf_id 0.
2297          */
2298         vf_id = 0;
2299
2300         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
2301         ret = hns3_cmd_set_promisc_mode(hw, &param);
2302         if (ret)
2303                 return ret;
2304
2305         return 0;
2306 }
2307
2308 static int
2309 hns3_init_hardware(struct hns3_adapter *hns)
2310 {
2311         struct hns3_hw *hw = &hns->hw;
2312         int ret;
2313
2314         ret = hns3_map_tqp(hw);
2315         if (ret) {
2316                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
2317                 return ret;
2318         }
2319
2320         ret = hns3_init_umv_space(hw);
2321         if (ret) {
2322                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
2323                 return ret;
2324         }
2325
2326         ret = hns3_mac_init(hw);
2327         if (ret) {
2328                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
2329                 goto err_mac_init;
2330         }
2331
2332         ret = hns3_init_mgr_tbl(hw);
2333         if (ret) {
2334                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
2335                 goto err_mac_init;
2336         }
2337
2338         ret = hns3_set_promisc_mode(hw, false, false);
2339         if (ret) {
2340                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
2341                 goto err_mac_init;
2342         }
2343
2344         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
2345         if (ret) {
2346                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
2347                 goto err_mac_init;
2348         }
2349
2350         ret = hns3_config_gro(hw, false);
2351         if (ret) {
2352                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
2353                 goto err_mac_init;
2354         }
2355         return 0;
2356
2357 err_mac_init:
2358         hns3_uninit_umv_space(hw);
2359         return ret;
2360 }
2361
2362 static int
2363 hns3_init_pf(struct rte_eth_dev *eth_dev)
2364 {
2365         struct rte_device *dev = eth_dev->device;
2366         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2367         struct hns3_adapter *hns = eth_dev->data->dev_private;
2368         struct hns3_hw *hw = &hns->hw;
2369         int ret;
2370
2371         PMD_INIT_FUNC_TRACE();
2372
2373         /* Get hardware io base address from pcie BAR2 IO space */
2374         hw->io_base = pci_dev->mem_resource[2].addr;
2375
2376         /* Firmware command queue initialize */
2377         ret = hns3_cmd_init_queue(hw);
2378         if (ret) {
2379                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
2380                 goto err_cmd_init_queue;
2381         }
2382
2383         /* Firmware command initialize */
2384         ret = hns3_cmd_init(hw);
2385         if (ret) {
2386                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
2387                 goto err_cmd_init;
2388         }
2389
2390         /* Get configuration */
2391         ret = hns3_get_configuration(hw);
2392         if (ret) {
2393                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
2394                 goto err_get_config;
2395         }
2396
2397         ret = hns3_init_hardware(hns);
2398         if (ret) {
2399                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
2400                 goto err_get_config;
2401         }
2402
2403         return 0;
2404
2405 err_get_config:
2406         hns3_cmd_uninit(hw);
2407
2408 err_cmd_init:
2409         hns3_cmd_destroy_queue(hw);
2410
2411 err_cmd_init_queue:
2412         hw->io_base = NULL;
2413
2414         return ret;
2415 }
2416
2417 static void
2418 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
2419 {
2420         struct hns3_adapter *hns = eth_dev->data->dev_private;
2421         struct hns3_hw *hw = &hns->hw;
2422
2423         PMD_INIT_FUNC_TRACE();
2424
2425         hns3_uninit_umv_space(hw);
2426         hns3_cmd_uninit(hw);
2427         hns3_cmd_destroy_queue(hw);
2428         hw->io_base = NULL;
2429 }
2430
2431 static void
2432 hns3_dev_close(struct rte_eth_dev *eth_dev)
2433 {
2434         struct hns3_adapter *hns = eth_dev->data->dev_private;
2435         struct hns3_hw *hw = &hns->hw;
2436
2437         hw->adapter_state = HNS3_NIC_CLOSING;
2438
2439         hns3_configure_all_mc_mac_addr(hns, true);
2440         hns3_uninit_pf(eth_dev);
2441         hw->adapter_state = HNS3_NIC_CLOSED;
2442 }
2443
2444 static const struct eth_dev_ops hns3_eth_dev_ops = {
2445         .dev_close          = hns3_dev_close,
2446         .mtu_set            = hns3_dev_mtu_set,
2447         .dev_infos_get          = hns3_dev_infos_get,
2448         .fw_version_get         = hns3_fw_version_get,
2449         .mac_addr_add           = hns3_add_mac_addr,
2450         .mac_addr_remove        = hns3_remove_mac_addr,
2451         .mac_addr_set           = hns3_set_default_mac_addr,
2452         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
2453 };
2454
2455 static int
2456 hns3_dev_init(struct rte_eth_dev *eth_dev)
2457 {
2458         struct hns3_adapter *hns = eth_dev->data->dev_private;
2459         struct hns3_hw *hw = &hns->hw;
2460         int ret;
2461
2462         PMD_INIT_FUNC_TRACE();
2463
2464         eth_dev->dev_ops = &hns3_eth_dev_ops;
2465         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2466                 return 0;
2467
2468         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2469         hns->is_vf = false;
2470         hw->data = eth_dev->data;
2471
2472         /*
2473          * Set default max packet size according to the mtu
2474          * default vale in DPDK frame.
2475          */
2476         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
2477
2478         ret = hns3_init_pf(eth_dev);
2479         if (ret) {
2480                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
2481                 goto err_init_pf;
2482         }
2483
2484         /* Allocate memory for storing MAC addresses */
2485         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
2486                                                sizeof(struct rte_ether_addr) *
2487                                                HNS3_UC_MACADDR_NUM, 0);
2488         if (eth_dev->data->mac_addrs == NULL) {
2489                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2490                              "to store MAC addresses",
2491                              sizeof(struct rte_ether_addr) *
2492                              HNS3_UC_MACADDR_NUM);
2493                 ret = -ENOMEM;
2494                 goto err_rte_zmalloc;
2495         }
2496
2497         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2498                             &eth_dev->data->mac_addrs[0]);
2499
2500         hw->adapter_state = HNS3_NIC_INITIALIZED;
2501         /*
2502          * Pass the information to the rte_eth_dev_close() that it should also
2503          * release the private port resources.
2504          */
2505         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2506
2507         hns3_info(hw, "hns3 dev initialization successful!");
2508         return 0;
2509
2510 err_rte_zmalloc:
2511         hns3_uninit_pf(eth_dev);
2512
2513 err_init_pf:
2514         eth_dev->dev_ops = NULL;
2515         eth_dev->rx_pkt_burst = NULL;
2516         eth_dev->tx_pkt_burst = NULL;
2517         eth_dev->tx_pkt_prepare = NULL;
2518         return ret;
2519 }
2520
2521 static int
2522 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
2523 {
2524         struct hns3_adapter *hns = eth_dev->data->dev_private;
2525         struct hns3_hw *hw = &hns->hw;
2526
2527         PMD_INIT_FUNC_TRACE();
2528
2529         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2530                 return -EPERM;
2531
2532         eth_dev->dev_ops = NULL;
2533         eth_dev->rx_pkt_burst = NULL;
2534         eth_dev->tx_pkt_burst = NULL;
2535         eth_dev->tx_pkt_prepare = NULL;
2536         if (hw->adapter_state < HNS3_NIC_CLOSING)
2537                 hns3_dev_close(eth_dev);
2538
2539         hw->adapter_state = HNS3_NIC_REMOVED;
2540         return 0;
2541 }
2542
2543 static int
2544 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2545                    struct rte_pci_device *pci_dev)
2546 {
2547         return rte_eth_dev_pci_generic_probe(pci_dev,
2548                                              sizeof(struct hns3_adapter),
2549                                              hns3_dev_init);
2550 }
2551
2552 static int
2553 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
2554 {
2555         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
2556 }
2557
2558 static const struct rte_pci_id pci_id_hns3_map[] = {
2559         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
2560         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
2561         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
2562         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
2563         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
2564         { .vendor_id = 0, /* sentinel */ },
2565 };
2566
2567 static struct rte_pci_driver rte_hns3_pmd = {
2568         .id_table = pci_id_hns3_map,
2569         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2570         .probe = eth_hns3_pci_probe,
2571         .remove = eth_hns3_pci_remove,
2572 };
2573
2574 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
2575 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
2576 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
2577
2578 RTE_INIT(hns3_init_log)
2579 {
2580         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
2581         if (hns3_logtype_init >= 0)
2582                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
2583         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
2584         if (hns3_logtype_driver >= 0)
2585                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
2586 }