drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8
   9 #include "hns3_ethdev.h"
  10 #include "hns3_common.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17 #include "hns3_flow.h"
  18
  19 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  20 #define HNS3_SERVICE_QUICK_INTERVAL     10
  21 #define HNS3_INVALID_PVID               0xFFFF
  22
  23 #define HNS3_FILTER_TYPE_VF             0
  24 #define HNS3_FILTER_TYPE_PORT           1
  25 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  26 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  27 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  28 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  29 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  30 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  31                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  32 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  34
  35 /* Reset related Registers */
  36 #define HNS3_GLOBAL_RESET_BIT           0
  37 #define HNS3_CORE_RESET_BIT             1
  38 #define HNS3_IMP_RESET_BIT              2
  39 #define HNS3_FUN_RST_ING_B              0
  40
  41 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  43 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  45
  46 #define HNS3_RESET_WAIT_MS      100
  47 #define HNS3_RESET_WAIT_CNT     200
  48
  49 /* FEC mode order defined in HNS3 hardware */
  50 #define HNS3_HW_FEC_MODE_NOFEC  0
  51 #define HNS3_HW_FEC_MODE_BASER  1
  52 #define HNS3_HW_FEC_MODE_RS     2
  53
  54 enum hns3_evt_cause {
  55         HNS3_VECTOR0_EVENT_RST,
  56         HNS3_VECTOR0_EVENT_MBX,
  57         HNS3_VECTOR0_EVENT_ERR,
  58         HNS3_VECTOR0_EVENT_PTP,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  96 static bool hns3_update_link_status(struct hns3_hw *hw);
  97
  98 static int hns3_add_mc_mac_addr(struct hns3_hw *hw,
  99                                 struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 101                                    struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 104 static int hns3_do_stop(struct hns3_adapter *hns);
 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
 107
 108
 109 static void
 110 hns3_pf_disable_irq0(struct hns3_hw *hw)
 111 {
 112         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 113 }
 114
 115 static void
 116 hns3_pf_enable_irq0(struct hns3_hw *hw)
 117 {
 118         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 119 }
 120
 121 static enum hns3_evt_cause
 122 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 123                           uint32_t *vec_val)
 124 {
 125         struct hns3_hw *hw = &hns->hw;
 126
 127         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 128         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 129         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 130         if (!is_delay) {
 131                 hw->reset.stats.imp_cnt++;
 132                 hns3_warn(hw, "IMP reset detected, clear reset status");
 133         } else {
 134                 hns3_schedule_delayed_reset(hns);
 135                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 136         }
 137
 138         return HNS3_VECTOR0_EVENT_RST;
 139 }
 140
 141 static enum hns3_evt_cause
 142 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 143                              uint32_t *vec_val)
 144 {
 145         struct hns3_hw *hw = &hns->hw;
 146
 147         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 148         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 149         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 150         if (!is_delay) {
 151                 hw->reset.stats.global_cnt++;
 152                 hns3_warn(hw, "Global reset detected, clear reset status");
 153         } else {
 154                 hns3_schedule_delayed_reset(hns);
 155                 hns3_warn(hw,
 156                           "Global reset detected, don't clear reset status");
 157         }
 158
 159         return HNS3_VECTOR0_EVENT_RST;
 160 }
 161
 162 static enum hns3_evt_cause
 163 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 164 {
 165         struct hns3_hw *hw = &hns->hw;
 166         uint32_t vector0_int_stats;
 167         uint32_t cmdq_src_val;
 168         uint32_t hw_err_src_reg;
 169         uint32_t val;
 170         enum hns3_evt_cause ret;
 171         bool is_delay;
 172
 173         /* fetch the events from their corresponding regs */
 174         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 175         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 176         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 177
 178         is_delay = clearval == NULL ? true : false;
 179         /*
 180          * Assumption: If by any chance reset and mailbox events are reported
 181          * together then we will only process reset event and defer the
 182          * processing of the mailbox events. Since, we would have not cleared
 183          * RX CMDQ event this time we would receive again another interrupt
 184          * from H/W just for the mailbox.
 185          */
 186         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 187                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 188                 goto out;
 189         }
 190
 191         /* Global reset */
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 193                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 194                 goto out;
 195         }
 196
 197         /* Check for vector0 1588 event source */
 198         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 199                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 200                 ret = HNS3_VECTOR0_EVENT_PTP;
 201                 goto out;
 202         }
 203
 204         /* check for vector0 msix event source */
 205         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 206             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 207                 val = vector0_int_stats | hw_err_src_reg;
 208                 ret = HNS3_VECTOR0_EVENT_ERR;
 209                 goto out;
 210         }
 211
 212         /* check for vector0 mailbox(=CMDQ RX) event source */
 213         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 214                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 215                 val = cmdq_src_val;
 216                 ret = HNS3_VECTOR0_EVENT_MBX;
 217                 goto out;
 218         }
 219
 220         val = vector0_int_stats;
 221         ret = HNS3_VECTOR0_EVENT_OTHER;
 222 out:
 223
 224         if (clearval)
 225                 *clearval = val;
 226         return ret;
 227 }
 228
 229 static void
 230 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 231 {
 232         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 233             event_type == HNS3_VECTOR0_EVENT_PTP)
 234                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 235         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 236                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 237 }
 238
 239 static void
 240 hns3_clear_all_event_cause(struct hns3_hw *hw)
 241 {
 242         uint32_t vector0_int_stats;
 243
 244         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 245         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 246                 hns3_warn(hw, "Probe during IMP reset interrupt");
 247
 248         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 249                 hns3_warn(hw, "Probe during Global reset interrupt");
 250
 251         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 252                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 253                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 254                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 255         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 256         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 257                                 BIT(HNS3_VECTOR0_1588_INT_B));
 258 }
 259
 260 static void
 261 hns3_handle_mac_tnl(struct hns3_hw *hw)
 262 {
 263         struct hns3_cmd_desc desc;
 264         uint32_t status;
 265         int ret;
 266
 267         /* query and clear mac tnl interrupt */
 268         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 269         ret = hns3_cmd_send(hw, &desc, 1);
 270         if (ret) {
 271                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 272                 return;
 273         }
 274
 275         status = rte_le_to_cpu_32(desc.data[0]);
 276         if (status) {
 277                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 278                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 279                                           false);
 280                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 281                 ret = hns3_cmd_send(hw, &desc, 1);
 282                 if (ret)
 283                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 284                                  ret);
 285         }
 286 }
 287
 288 static void
 289 hns3_interrupt_handler(void *param)
 290 {
 291         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 292         struct hns3_adapter *hns = dev->data->dev_private;
 293         struct hns3_hw *hw = &hns->hw;
 294         enum hns3_evt_cause event_cause;
 295         uint32_t clearval = 0;
 296         uint32_t vector0_int;
 297         uint32_t ras_int;
 298         uint32_t cmdq_int;
 299
 300         /* Disable interrupt */
 301         hns3_pf_disable_irq0(hw);
 302
 303         event_cause = hns3_check_event_cause(hns, &clearval);
 304         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 305         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 306         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 307         hns3_clear_event_cause(hw, event_cause, clearval);
 308         /* vector 0 interrupt is shared with reset and mailbox source events. */
 309         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 310                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 311                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 312                           vector0_int, ras_int, cmdq_int);
 313                 hns3_handle_mac_tnl(hw);
 314                 hns3_handle_error(hns);
 315         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 316                 hns3_warn(hw, "received reset interrupt");
 317                 hns3_schedule_reset(hns);
 318         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 319                 hns3_dev_handle_mbx_msg(hw);
 320         } else {
 321                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 322                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 323                           vector0_int, ras_int, cmdq_int);
 324         }
 325
 326         /* Enable interrupt if it is not cause by reset */
 327         hns3_pf_enable_irq0(hw);
 328 }
 329
 330 static int
 331 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 332 {
 333 #define HNS3_VLAN_ID_OFFSET_STEP        160
 334 #define HNS3_VLAN_BYTE_SIZE             8
 335         struct hns3_vlan_filter_pf_cfg_cmd *req;
 336         struct hns3_hw *hw = &hns->hw;
 337         uint8_t vlan_offset_byte_val;
 338         struct hns3_cmd_desc desc;
 339         uint8_t vlan_offset_byte;
 340         uint8_t vlan_offset_base;
 341         int ret;
 342
 343         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 344
 345         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 346         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 347                            HNS3_VLAN_BYTE_SIZE;
 348         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 349
 350         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 351         req->vlan_offset = vlan_offset_base;
 352         req->vlan_cfg = on ? 0 : 1;
 353         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 354
 355         ret = hns3_cmd_send(hw, &desc, 1);
 356         if (ret)
 357                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 358                          vlan_id, ret);
 359
 360         return ret;
 361 }
 362
 363 static void
 364 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 365 {
 366         struct hns3_user_vlan_table *vlan_entry;
 367         struct hns3_pf *pf = &hns->pf;
 368
 369         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 370                 if (vlan_entry->vlan_id == vlan_id) {
 371                         if (vlan_entry->hd_tbl_status)
 372                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 373                         LIST_REMOVE(vlan_entry, next);
 374                         rte_free(vlan_entry);
 375                         break;
 376                 }
 377         }
 378 }
 379
 380 static void
 381 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 382                         bool writen_to_tbl)
 383 {
 384         struct hns3_user_vlan_table *vlan_entry;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_pf *pf = &hns->pf;
 387
 388         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 389                 if (vlan_entry->vlan_id == vlan_id)
 390                         return;
 391         }
 392
 393         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 394         if (vlan_entry == NULL) {
 395                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 396                 return;
 397         }
 398
 399         vlan_entry->hd_tbl_status = writen_to_tbl;
 400         vlan_entry->vlan_id = vlan_id;
 401
 402         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 403 }
 404
 405 static int
 406 hns3_restore_vlan_table(struct hns3_adapter *hns)
 407 {
 408         struct hns3_user_vlan_table *vlan_entry;
 409         struct hns3_hw *hw = &hns->hw;
 410         struct hns3_pf *pf = &hns->pf;
 411         uint16_t vlan_id;
 412         int ret = 0;
 413
 414         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 415                 return hns3_vlan_pvid_configure(hns,
 416                                                 hw->port_base_vlan_cfg.pvid, 1);
 417
 418         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 419                 if (vlan_entry->hd_tbl_status) {
 420                         vlan_id = vlan_entry->vlan_id;
 421                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 422                         if (ret)
 423                                 break;
 424                 }
 425         }
 426
 427         return ret;
 428 }
 429
 430 static int
 431 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 432 {
 433         struct hns3_hw *hw = &hns->hw;
 434         bool writen_to_tbl = false;
 435         int ret = 0;
 436
 437         /*
 438          * When vlan filter is enabled, hardware regards packets without vlan
 439          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 440          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 441          */
 442         if (on == 0 && vlan_id == 0)
 443                 return 0;
 444
 445         /*
 446          * When port base vlan enabled, we use port base vlan as the vlan
 447          * filter condition. In this case, we don't update vlan filter table
 448          * when user add new vlan or remove exist vlan, just update the
 449          * vlan list. The vlan id in vlan list will be written in vlan filter
 450          * table until port base vlan disabled
 451          */
 452         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 453                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 454                 writen_to_tbl = true;
 455         }
 456
 457         if (ret == 0) {
 458                 if (on)
 459                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 460                 else
 461                         hns3_rm_dev_vlan_table(hns, vlan_id);
 462         }
 463         return ret;
 464 }
 465
 466 static int
 467 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 468 {
 469         struct hns3_adapter *hns = dev->data->dev_private;
 470         struct hns3_hw *hw = &hns->hw;
 471         int ret;
 472
 473         rte_spinlock_lock(&hw->lock);
 474         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 475         rte_spinlock_unlock(&hw->lock);
 476         return ret;
 477 }
 478
 479 static int
 480 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 481                          uint16_t tpid)
 482 {
 483         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 484         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 485         struct hns3_hw *hw = &hns->hw;
 486         struct hns3_cmd_desc desc;
 487         int ret;
 488
 489         if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
 490              vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) {
 491                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 492                 return -EINVAL;
 493         }
 494
 495         if (tpid != RTE_ETHER_TYPE_VLAN) {
 496                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 497                 return -EINVAL;
 498         }
 499
 500         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 501         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 502
 503         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
 504                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 505                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 506         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
 507                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 508                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 509                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 510                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 511         }
 512
 513         ret = hns3_cmd_send(hw, &desc, 1);
 514         if (ret) {
 515                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 516                          ret);
 517                 return ret;
 518         }
 519
 520         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 521
 522         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 523         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 524         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 525
 526         ret = hns3_cmd_send(hw, &desc, 1);
 527         if (ret)
 528                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 529                          ret);
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 535                    uint16_t tpid)
 536 {
 537         struct hns3_adapter *hns = dev->data->dev_private;
 538         struct hns3_hw *hw = &hns->hw;
 539         int ret;
 540
 541         rte_spinlock_lock(&hw->lock);
 542         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 543         rte_spinlock_unlock(&hw->lock);
 544         return ret;
 545 }
 546
 547 static int
 548 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 549                              struct hns3_rx_vtag_cfg *vcfg)
 550 {
 551         struct hns3_vport_vtag_rx_cfg_cmd *req;
 552         struct hns3_hw *hw = &hns->hw;
 553         struct hns3_cmd_desc desc;
 554         uint16_t vport_id;
 555         uint8_t bitmap;
 556         int ret;
 557
 558         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 559
 560         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 561         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 562                      vcfg->strip_tag1_en ? 1 : 0);
 563         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 564                      vcfg->strip_tag2_en ? 1 : 0);
 565         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 566                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 567         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 568                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 569
 570         /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */
 571         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 572                      vcfg->strip_tag1_discard_en ? 1 : 0);
 573         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 574                      vcfg->strip_tag2_discard_en ? 1 : 0);
 575         /*
 576          * In current version VF is not supported when PF is driven by DPDK
 577          * driver, just need to configure parameters for PF vport.
 578          */
 579         vport_id = HNS3_PF_FUNC_ID;
 580         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 581         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 582         req->vf_bitmap[req->vf_offset] = bitmap;
 583
 584         ret = hns3_cmd_send(hw, &desc, 1);
 585         if (ret)
 586                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 587         return ret;
 588 }
 589
 590 static int
 591 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 592 {
 593         struct hns3_rx_vtag_cfg rxvlan_cfg;
 594         struct hns3_hw *hw = &hns->hw;
 595         int ret;
 596
 597         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 598                 rxvlan_cfg.strip_tag1_en = false;
 599                 rxvlan_cfg.strip_tag2_en = enable;
 600                 rxvlan_cfg.strip_tag2_discard_en = false;
 601         } else {
 602                 rxvlan_cfg.strip_tag1_en = enable;
 603                 rxvlan_cfg.strip_tag2_en = true;
 604                 rxvlan_cfg.strip_tag2_discard_en = true;
 605         }
 606
 607         rxvlan_cfg.strip_tag1_discard_en = false;
 608         rxvlan_cfg.vlan1_vlan_prionly = false;
 609         rxvlan_cfg.vlan2_vlan_prionly = false;
 610         rxvlan_cfg.rx_vlan_offload_en = enable;
 611
 612         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 613         if (ret) {
 614                 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
 615                                 enable ? "enable" : "disable", ret);
 616                 return ret;
 617         }
 618
 619         memcpy(&hns->pf.vtag_config.rx_vcfg, &rxvlan_cfg,
 620                sizeof(struct hns3_rx_vtag_cfg));
 621
 622         return ret;
 623 }
 624
 625 static int
 626 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 627                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 628 {
 629         struct hns3_vlan_filter_ctrl_cmd *req;
 630         struct hns3_cmd_desc desc;
 631         int ret;
 632
 633         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 634
 635         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 636         req->vlan_type = vlan_type;
 637         req->vlan_fe = filter_en ? fe_type : 0;
 638         req->vf_id = vf_id;
 639
 640         ret = hns3_cmd_send(hw, &desc, 1);
 641         if (ret)
 642                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 643
 644         return ret;
 645 }
 646
 647 static int
 648 hns3_vlan_filter_init(struct hns3_adapter *hns)
 649 {
 650         struct hns3_hw *hw = &hns->hw;
 651         int ret;
 652
 653         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 654                                         HNS3_FILTER_FE_EGRESS, false,
 655                                         HNS3_PF_FUNC_ID);
 656         if (ret) {
 657                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 658                 return ret;
 659         }
 660
 661         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 662                                         HNS3_FILTER_FE_INGRESS, false,
 663                                         HNS3_PF_FUNC_ID);
 664         if (ret)
 665                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 666
 667         return ret;
 668 }
 669
 670 static int
 671 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 672 {
 673         struct hns3_hw *hw = &hns->hw;
 674         int ret;
 675
 676         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 677                                         HNS3_FILTER_FE_INGRESS, enable,
 678                                         HNS3_PF_FUNC_ID);
 679         if (ret)
 680                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 681                          enable ? "enable" : "disable", ret);
 682
 683         return ret;
 684 }
 685
 686 static int
 687 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 688 {
 689         struct hns3_adapter *hns = dev->data->dev_private;
 690         struct hns3_hw *hw = &hns->hw;
 691         struct rte_eth_rxmode *rxmode;
 692         unsigned int tmp_mask;
 693         bool enable;
 694         int ret = 0;
 695
 696         rte_spinlock_lock(&hw->lock);
 697         rxmode = &dev->data->dev_conf.rxmode;
 698         tmp_mask = (unsigned int)mask;
 699         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
 700                 /* ignore vlan filter configuration during promiscuous mode */
 701                 if (!dev->data->promiscuous) {
 702                         /* Enable or disable VLAN filter */
 703                         enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ?
 704                                  true : false;
 705
 706                         ret = hns3_enable_vlan_filter(hns, enable);
 707                         if (ret) {
 708                                 rte_spinlock_unlock(&hw->lock);
 709                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 710                                          enable ? "enable" : "disable", ret);
 711                                 return ret;
 712                         }
 713                 }
 714         }
 715
 716         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
 717                 /* Enable or disable VLAN stripping */
 718                 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ?
 719                     true : false;
 720
 721                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 722                 if (ret) {
 723                         rte_spinlock_unlock(&hw->lock);
 724                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 725                                  enable ? "enable" : "disable", ret);
 726                         return ret;
 727                 }
 728         }
 729
 730         rte_spinlock_unlock(&hw->lock);
 731
 732         return ret;
 733 }
 734
 735 static int
 736 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 737                              struct hns3_tx_vtag_cfg *vcfg)
 738 {
 739         struct hns3_vport_vtag_tx_cfg_cmd *req;
 740         struct hns3_cmd_desc desc;
 741         struct hns3_hw *hw = &hns->hw;
 742         uint16_t vport_id;
 743         uint8_t bitmap;
 744         int ret;
 745
 746         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 747
 748         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 749         req->def_vlan_tag1 = vcfg->default_tag1;
 750         req->def_vlan_tag2 = vcfg->default_tag2;
 751         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 752                      vcfg->accept_tag1 ? 1 : 0);
 753         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 754                      vcfg->accept_untag1 ? 1 : 0);
 755         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 756                      vcfg->accept_tag2 ? 1 : 0);
 757         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 758                      vcfg->accept_untag2 ? 1 : 0);
 759         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 760                      vcfg->insert_tag1_en ? 1 : 0);
 761         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 762                      vcfg->insert_tag2_en ? 1 : 0);
 763         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 764
 765         /* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */
 766         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 767                      vcfg->tag_shift_mode_en ? 1 : 0);
 768
 769         /*
 770          * In current version VF is not supported when PF is driven by DPDK
 771          * driver, just need to configure parameters for PF vport.
 772          */
 773         vport_id = HNS3_PF_FUNC_ID;
 774         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 775         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 776         req->vf_bitmap[req->vf_offset] = bitmap;
 777
 778         ret = hns3_cmd_send(hw, &desc, 1);
 779         if (ret)
 780                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 781
 782         return ret;
 783 }
 784
 785 static int
 786 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 787                      uint16_t pvid)
 788 {
 789         struct hns3_hw *hw = &hns->hw;
 790         struct hns3_tx_vtag_cfg txvlan_cfg;
 791         int ret;
 792
 793         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 794                 txvlan_cfg.accept_tag1 = true;
 795                 txvlan_cfg.insert_tag1_en = false;
 796                 txvlan_cfg.default_tag1 = 0;
 797         } else {
 798                 txvlan_cfg.accept_tag1 =
 799                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 800                 txvlan_cfg.insert_tag1_en = true;
 801                 txvlan_cfg.default_tag1 = pvid;
 802         }
 803
 804         txvlan_cfg.accept_untag1 = true;
 805         txvlan_cfg.accept_tag2 = true;
 806         txvlan_cfg.accept_untag2 = true;
 807         txvlan_cfg.insert_tag2_en = false;
 808         txvlan_cfg.default_tag2 = 0;
 809         txvlan_cfg.tag_shift_mode_en = true;
 810
 811         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 812         if (ret) {
 813                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 814                          ret);
 815                 return ret;
 816         }
 817
 818         memcpy(&hns->pf.vtag_config.tx_vcfg, &txvlan_cfg,
 819                sizeof(struct hns3_tx_vtag_cfg));
 820
 821         return ret;
 822 }
 823
 824
 825 static void
 826 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 827 {
 828         struct hns3_user_vlan_table *vlan_entry;
 829         struct hns3_pf *pf = &hns->pf;
 830
 831         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 832                 if (vlan_entry->hd_tbl_status) {
 833                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 834                         vlan_entry->hd_tbl_status = false;
 835                 }
 836         }
 837
 838         if (is_del_list) {
 839                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 840                 while (vlan_entry) {
 841                         LIST_REMOVE(vlan_entry, next);
 842                         rte_free(vlan_entry);
 843                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 844                 }
 845         }
 846 }
 847
 848 static void
 849 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 850 {
 851         struct hns3_user_vlan_table *vlan_entry;
 852         struct hns3_pf *pf = &hns->pf;
 853
 854         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 855                 if (!vlan_entry->hd_tbl_status) {
 856                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 857                         vlan_entry->hd_tbl_status = true;
 858                 }
 859         }
 860 }
 861
 862 static void
 863 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 864 {
 865         struct hns3_hw *hw = &hns->hw;
 866         int ret;
 867
 868         hns3_rm_all_vlan_table(hns, true);
 869         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 870                 ret = hns3_set_port_vlan_filter(hns,
 871                                                 hw->port_base_vlan_cfg.pvid, 0);
 872                 if (ret) {
 873                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 874                                  ret);
 875                         return;
 876                 }
 877         }
 878 }
 879
 880 static int
 881 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 882                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 883 {
 884         struct hns3_hw *hw = &hns->hw;
 885         uint16_t old_pvid;
 886         int ret;
 887
 888         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 889                 old_pvid = hw->port_base_vlan_cfg.pvid;
 890                 if (old_pvid != HNS3_INVALID_PVID) {
 891                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 892                         if (ret) {
 893                                 hns3_err(hw, "failed to remove old pvid %u, "
 894                                                 "ret = %d", old_pvid, ret);
 895                                 return ret;
 896                         }
 897                 }
 898
 899                 hns3_rm_all_vlan_table(hns, false);
 900                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 901                 if (ret) {
 902                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 903                                         new_pvid, ret);
 904                         return ret;
 905                 }
 906         } else {
 907                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 908                 if (ret) {
 909                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 910                                         new_pvid, ret);
 911                         return ret;
 912                 }
 913
 914                 hns3_add_all_vlan_table(hns);
 915         }
 916         return 0;
 917 }
 918
 919 static int
 920 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 921 {
 922         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 923         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 924         bool rx_strip_en;
 925         int ret;
 926
 927         rx_strip_en = old_cfg->rx_vlan_offload_en;
 928         if (on) {
 929                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 930                 rx_vlan_cfg.strip_tag2_en = true;
 931                 rx_vlan_cfg.strip_tag2_discard_en = true;
 932         } else {
 933                 rx_vlan_cfg.strip_tag1_en = false;
 934                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 935                 rx_vlan_cfg.strip_tag2_discard_en = false;
 936         }
 937         rx_vlan_cfg.strip_tag1_discard_en = false;
 938         rx_vlan_cfg.vlan1_vlan_prionly = false;
 939         rx_vlan_cfg.vlan2_vlan_prionly = false;
 940         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 941
 942         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 943         if (ret)
 944                 return ret;
 945
 946         memcpy(&hns->pf.vtag_config.rx_vcfg, &rx_vlan_cfg,
 947                sizeof(struct hns3_rx_vtag_cfg));
 948
 949         return ret;
 950 }
 951
 952 static int
 953 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 954 {
 955         struct hns3_hw *hw = &hns->hw;
 956         uint16_t port_base_vlan_state;
 957         int ret, err;
 958
 959         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 960                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 961                         hns3_warn(hw, "Invalid operation! As current pvid set "
 962                                   "is %u, disable pvid %u is invalid",
 963                                   hw->port_base_vlan_cfg.pvid, pvid);
 964                 return 0;
 965         }
 966
 967         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 968                                     HNS3_PORT_BASE_VLAN_DISABLE;
 969         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 970         if (ret) {
 971                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 972                          ret);
 973                 return ret;
 974         }
 975
 976         ret = hns3_en_pvid_strip(hns, on);
 977         if (ret) {
 978                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 979                          "ret = %d", ret);
 980                 goto pvid_vlan_strip_fail;
 981         }
 982
 983         if (pvid == HNS3_INVALID_PVID)
 984                 goto out;
 985         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 986         if (ret) {
 987                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 988                          ret);
 989                 goto vlan_filter_set_fail;
 990         }
 991
 992 out:
 993         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 994         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 995         return ret;
 996
 997 vlan_filter_set_fail:
 998         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
 999                                         HNS3_PORT_BASE_VLAN_ENABLE);
1000         if (err)
1001                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1002
1003 pvid_vlan_strip_fail:
1004         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1005                                         hw->port_base_vlan_cfg.pvid);
1006         if (err)
1007                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1008
1009         return ret;
1010 }
1011
1012 static int
1013 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1014 {
1015         struct hns3_adapter *hns = dev->data->dev_private;
1016         struct hns3_hw *hw = &hns->hw;
1017         bool pvid_en_state_change;
1018         uint16_t pvid_state;
1019         int ret;
1020
1021         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1022                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1023                          RTE_ETHER_MAX_VLAN_ID);
1024                 return -EINVAL;
1025         }
1026
1027         /*
1028          * If PVID configuration state change, should refresh the PVID
1029          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1030          */
1031         pvid_state = hw->port_base_vlan_cfg.state;
1032         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1033             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1034                 pvid_en_state_change = false;
1035         else
1036                 pvid_en_state_change = true;
1037
1038         rte_spinlock_lock(&hw->lock);
1039         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1040         rte_spinlock_unlock(&hw->lock);
1041         if (ret)
1042                 return ret;
1043         /*
1044          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1045          * need be processed by PMD.
1046          */
1047         if (pvid_en_state_change &&
1048             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1049                 hns3_update_all_queues_pvid_proc_en(hw);
1050
1051         return 0;
1052 }
1053
1054 static int
1055 hns3_default_vlan_config(struct hns3_adapter *hns)
1056 {
1057         struct hns3_hw *hw = &hns->hw;
1058         int ret;
1059
1060         /*
1061          * When vlan filter is enabled, hardware regards packets without vlan
1062          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1063          * table, packets without vlan won't be received. So, add vlan 0 as
1064          * the default vlan.
1065          */
1066         ret = hns3_vlan_filter_configure(hns, 0, 1);
1067         if (ret)
1068                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1069         return ret;
1070 }
1071
1072 static int
1073 hns3_init_vlan_config(struct hns3_adapter *hns)
1074 {
1075         struct hns3_hw *hw = &hns->hw;
1076         int ret;
1077
1078         /*
1079          * This function can be called in the initialization and reset process,
1080          * when in reset process, it means that hardware had been reseted
1081          * successfully and we need to restore the hardware configuration to
1082          * ensure that the hardware configuration remains unchanged before and
1083          * after reset.
1084          */
1085         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1086                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1087                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1088         }
1089
1090         ret = hns3_vlan_filter_init(hns);
1091         if (ret) {
1092                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1093                 return ret;
1094         }
1095
1096         ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER,
1097                                        RTE_ETHER_TYPE_VLAN);
1098         if (ret) {
1099                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1100                 return ret;
1101         }
1102
1103         /*
1104          * When in the reinit dev stage of the reset process, the following
1105          * vlan-related configurations may differ from those at initialization,
1106          * we will restore configurations to hardware in hns3_restore_vlan_table
1107          * and hns3_restore_vlan_conf later.
1108          */
1109         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1110                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1111                 if (ret) {
1112                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1113                         return ret;
1114                 }
1115
1116                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1117                 if (ret) {
1118                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1119                                  ret);
1120                         return ret;
1121                 }
1122         }
1123
1124         return hns3_default_vlan_config(hns);
1125 }
1126
1127 static int
1128 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1129 {
1130         struct hns3_pf *pf = &hns->pf;
1131         struct hns3_hw *hw = &hns->hw;
1132         uint64_t offloads;
1133         bool enable;
1134         int ret;
1135
1136         if (!hw->data->promiscuous) {
1137                 /* restore vlan filter states */
1138                 offloads = hw->data->dev_conf.rxmode.offloads;
1139                 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false;
1140                 ret = hns3_enable_vlan_filter(hns, enable);
1141                 if (ret) {
1142                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1143                                  "ret = %d", ret);
1144                         return ret;
1145                 }
1146         }
1147
1148         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1149         if (ret) {
1150                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1151                 return ret;
1152         }
1153
1154         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1155         if (ret)
1156                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1157
1158         return ret;
1159 }
1160
1161 static int
1162 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1163 {
1164         struct hns3_adapter *hns = dev->data->dev_private;
1165         struct rte_eth_dev_data *data = dev->data;
1166         struct rte_eth_txmode *txmode;
1167         struct hns3_hw *hw = &hns->hw;
1168         int mask;
1169         int ret;
1170
1171         txmode = &data->dev_conf.txmode;
1172         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1173                 hns3_warn(hw,
1174                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1175                           "configuration is not supported! Ignore these two "
1176                           "parameters: hw_vlan_reject_tagged(%u), "
1177                           "hw_vlan_reject_untagged(%u)",
1178                           txmode->hw_vlan_reject_tagged,
1179                           txmode->hw_vlan_reject_untagged);
1180
1181         /* Apply vlan offload setting */
1182         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;
1183         ret = hns3_vlan_offload_set(dev, mask);
1184         if (ret) {
1185                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1186                          ret);
1187                 return ret;
1188         }
1189
1190         /*
1191          * If pvid config is not set in rte_eth_conf, driver needn't to set
1192          * VLAN pvid related configuration to hardware.
1193          */
1194         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1195                 return 0;
1196
1197         /* Apply pvid setting */
1198         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1199                                  txmode->hw_vlan_insert_pvid);
1200         if (ret)
1201                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1202                          txmode->pvid, ret);
1203
1204         return ret;
1205 }
1206
1207 static int
1208 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1209                 unsigned int tso_mss_max)
1210 {
1211         struct hns3_cfg_tso_status_cmd *req;
1212         struct hns3_cmd_desc desc;
1213         uint16_t tso_mss;
1214
1215         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1216
1217         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1218
1219         tso_mss = 0;
1220         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1221                        tso_mss_min);
1222         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1223
1224         tso_mss = 0;
1225         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1226                        tso_mss_max);
1227         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1228
1229         return hns3_cmd_send(hw, &desc, 1);
1230 }
1231
1232 static int
1233 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1234                    uint16_t *allocated_size, bool is_alloc)
1235 {
1236         struct hns3_umv_spc_alc_cmd *req;
1237         struct hns3_cmd_desc desc;
1238         int ret;
1239
1240         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1241         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1242         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1243         req->space_size = rte_cpu_to_le_32(space_size);
1244
1245         ret = hns3_cmd_send(hw, &desc, 1);
1246         if (ret) {
1247                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1248                              is_alloc ? "allocate" : "free", ret);
1249                 return ret;
1250         }
1251
1252         if (is_alloc && allocated_size)
1253                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1254
1255         return 0;
1256 }
1257
1258 static int
1259 hns3_init_umv_space(struct hns3_hw *hw)
1260 {
1261         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1262         struct hns3_pf *pf = &hns->pf;
1263         uint16_t allocated_size = 0;
1264         int ret;
1265
1266         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1267                                  true);
1268         if (ret)
1269                 return ret;
1270
1271         if (allocated_size < pf->wanted_umv_size)
1272                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1273                              pf->wanted_umv_size, allocated_size);
1274
1275         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1276                                                 pf->wanted_umv_size;
1277         pf->used_umv_size = 0;
1278         return 0;
1279 }
1280
1281 static int
1282 hns3_uninit_umv_space(struct hns3_hw *hw)
1283 {
1284         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1285         struct hns3_pf *pf = &hns->pf;
1286         int ret;
1287
1288         if (pf->max_umv_size == 0)
1289                 return 0;
1290
1291         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1292         if (ret)
1293                 return ret;
1294
1295         pf->max_umv_size = 0;
1296
1297         return 0;
1298 }
1299
1300 static bool
1301 hns3_is_umv_space_full(struct hns3_hw *hw)
1302 {
1303         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1304         struct hns3_pf *pf = &hns->pf;
1305         bool is_full;
1306
1307         is_full = (pf->used_umv_size >= pf->max_umv_size);
1308
1309         return is_full;
1310 }
1311
1312 static void
1313 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1314 {
1315         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1316         struct hns3_pf *pf = &hns->pf;
1317
1318         if (is_free) {
1319                 if (pf->used_umv_size > 0)
1320                         pf->used_umv_size--;
1321         } else
1322                 pf->used_umv_size++;
1323 }
1324
1325 static void
1326 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1327                       const uint8_t *addr, bool is_mc)
1328 {
1329         const unsigned char *mac_addr = addr;
1330         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1331                             ((uint32_t)mac_addr[2] << 16) |
1332                             ((uint32_t)mac_addr[1] << 8) |
1333                             (uint32_t)mac_addr[0];
1334         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1335
1336         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1337         if (is_mc) {
1338                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1339                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1340                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1341         }
1342
1343         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1344         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1345 }
1346
1347 static int
1348 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1349                              uint8_t resp_code,
1350                              enum hns3_mac_vlan_tbl_opcode op)
1351 {
1352         if (cmdq_resp) {
1353                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1354                          cmdq_resp);
1355                 return -EIO;
1356         }
1357
1358         if (op == HNS3_MAC_VLAN_ADD) {
1359                 if (resp_code == 0 || resp_code == 1) {
1360                         return 0;
1361                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1362                         hns3_err(hw, "add mac addr failed for uc_overflow");
1363                         return -ENOSPC;
1364                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1365                         hns3_err(hw, "add mac addr failed for mc_overflow");
1366                         return -ENOSPC;
1367                 }
1368
1369                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1370                          resp_code);
1371                 return -EIO;
1372         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1373                 if (resp_code == 0) {
1374                         return 0;
1375                 } else if (resp_code == 1) {
1376                         hns3_dbg(hw, "remove mac addr failed for miss");
1377                         return -ENOENT;
1378                 }
1379
1380                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1381                          resp_code);
1382                 return -EIO;
1383         } else if (op == HNS3_MAC_VLAN_LKUP) {
1384                 if (resp_code == 0) {
1385                         return 0;
1386                 } else if (resp_code == 1) {
1387                         hns3_dbg(hw, "lookup mac addr failed for miss");
1388                         return -ENOENT;
1389                 }
1390
1391                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1392                          resp_code);
1393                 return -EIO;
1394         }
1395
1396         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1397                  op);
1398
1399         return -EINVAL;
1400 }
1401
1402 static int
1403 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1404                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1405                          struct hns3_cmd_desc *desc, uint8_t desc_num)
1406 {
1407         uint8_t resp_code;
1408         uint16_t retval;
1409         int ret;
1410         int i;
1411
1412         if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) {
1413                 for (i = 0; i < desc_num - 1; i++) {
1414                         hns3_cmd_setup_basic_desc(&desc[i],
1415                                                   HNS3_OPC_MAC_VLAN_ADD, true);
1416                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1417                         if (i == 0)
1418                                 memcpy(desc[i].data, req,
1419                                 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1420                 }
1421                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD,
1422                                           true);
1423         } else {
1424                 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD,
1425                                           true);
1426                 memcpy(desc[0].data, req,
1427                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1428         }
1429         ret = hns3_cmd_send(hw, desc, desc_num);
1430         if (ret) {
1431                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1432                          ret);
1433                 return ret;
1434         }
1435         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1436         retval = rte_le_to_cpu_16(desc[0].retval);
1437
1438         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1439                                             HNS3_MAC_VLAN_LKUP);
1440 }
1441
1442 static int
1443 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1444                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1445                       struct hns3_cmd_desc *desc, uint8_t desc_num)
1446 {
1447         uint8_t resp_code;
1448         uint16_t retval;
1449         int cfg_status;
1450         int ret;
1451         int i;
1452
1453         if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) {
1454                 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false);
1455                 memcpy(desc->data, req,
1456                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1457                 ret = hns3_cmd_send(hw, desc, desc_num);
1458                 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff;
1459                 retval = rte_le_to_cpu_16(desc->retval);
1460
1461                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1462                                                           HNS3_MAC_VLAN_ADD);
1463         } else {
1464                 for (i = 0; i < desc_num; i++) {
1465                         hns3_cmd_reuse_desc(&desc[i], false);
1466                         if (i == desc_num - 1)
1467                                 desc[i].flag &=
1468                                         rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1469                         else
1470                                 desc[i].flag |=
1471                                         rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1472                 }
1473                 memcpy(desc[0].data, req,
1474                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1475                 desc[0].retval = 0;
1476                 ret = hns3_cmd_send(hw, desc, desc_num);
1477                 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1478                 retval = rte_le_to_cpu_16(desc[0].retval);
1479
1480                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1481                                                           HNS3_MAC_VLAN_ADD);
1482         }
1483
1484         if (ret) {
1485                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1486                 return ret;
1487         }
1488
1489         return cfg_status;
1490 }
1491
1492 static int
1493 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1494                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1495 {
1496         struct hns3_cmd_desc desc;
1497         uint8_t resp_code;
1498         uint16_t retval;
1499         int ret;
1500
1501         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1502
1503         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1504
1505         ret = hns3_cmd_send(hw, &desc, 1);
1506         if (ret) {
1507                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1508                 return ret;
1509         }
1510         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1511         retval = rte_le_to_cpu_16(desc.retval);
1512
1513         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1514                                             HNS3_MAC_VLAN_REMOVE);
1515 }
1516
1517 static int
1518 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1519 {
1520         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1521         struct hns3_mac_vlan_tbl_entry_cmd req;
1522         struct hns3_pf *pf = &hns->pf;
1523         struct hns3_cmd_desc desc;
1524         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1525         uint16_t egress_port = 0;
1526         uint8_t vf_id;
1527         int ret;
1528
1529         /* check if mac addr is valid */
1530         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1531                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1532                                       mac_addr);
1533                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1534                          mac_str);
1535                 return -EINVAL;
1536         }
1537
1538         memset(&req, 0, sizeof(req));
1539
1540         /*
1541          * In current version VF is not supported when PF is driven by DPDK
1542          * driver, just need to configure parameters for PF vport.
1543          */
1544         vf_id = HNS3_PF_FUNC_ID;
1545         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1546                        HNS3_MAC_EPORT_VFID_S, vf_id);
1547
1548         req.egress_port = rte_cpu_to_le_16(egress_port);
1549
1550         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1551
1552         /*
1553          * Lookup the mac address in the mac_vlan table, and add
1554          * it if the entry is inexistent. Repeated unicast entry
1555          * is not allowed in the mac vlan table.
1556          */
1557         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc,
1558                                         HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1559         if (ret == -ENOENT) {
1560                 if (!hns3_is_umv_space_full(hw)) {
1561                         ret = hns3_add_mac_vlan_tbl(hw, &req, &desc,
1562                                                 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1563                         if (!ret)
1564                                 hns3_update_umv_space(hw, false);
1565                         return ret;
1566                 }
1567
1568                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1569
1570                 return -ENOSPC;
1571         }
1572
1573         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1574
1575         /* check if we just hit the duplicate */
1576         if (ret == 0) {
1577                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1578                 return 0;
1579         }
1580
1581         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1582                  mac_str);
1583
1584         return ret;
1585 }
1586
1587 static int
1588 hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1589 {
1590         struct hns3_mac_vlan_tbl_entry_cmd req;
1591         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1592         int ret;
1593
1594         /* check if mac addr is valid */
1595         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1596                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1597                                       mac_addr);
1598                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1599                          mac_str);
1600                 return -EINVAL;
1601         }
1602
1603         memset(&req, 0, sizeof(req));
1604         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1605         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1606         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1607         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1608                 return 0;
1609         else if (ret == 0)
1610                 hns3_update_umv_space(hw, true);
1611
1612         return ret;
1613 }
1614
1615 static int
1616 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1617                           struct rte_ether_addr *mac_addr)
1618 {
1619         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620         struct rte_ether_addr *oaddr;
1621         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1622         int ret, ret_val;
1623
1624         rte_spinlock_lock(&hw->lock);
1625         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1626         ret = hw->ops.del_uc_mac_addr(hw, oaddr);
1627         if (ret) {
1628                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629                                       oaddr);
1630                 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1631                           mac_str, ret);
1632
1633                 rte_spinlock_unlock(&hw->lock);
1634                 return ret;
1635         }
1636
1637         ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
1638         if (ret) {
1639                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1640                                       mac_addr);
1641                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1642                 goto err_add_uc_addr;
1643         }
1644
1645         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1646         if (ret) {
1647                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1648                 goto err_pause_addr_cfg;
1649         }
1650
1651         rte_ether_addr_copy(mac_addr,
1652                             (struct rte_ether_addr *)hw->mac.mac_addr);
1653         rte_spinlock_unlock(&hw->lock);
1654
1655         return 0;
1656
1657 err_pause_addr_cfg:
1658         ret_val = hw->ops.del_uc_mac_addr(hw, mac_addr);
1659         if (ret_val) {
1660                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1661                                       mac_addr);
1662                 hns3_warn(hw,
1663                           "Failed to roll back to del setted mac addr(%s): %d",
1664                           mac_str, ret_val);
1665         }
1666
1667 err_add_uc_addr:
1668         ret_val = hw->ops.add_uc_mac_addr(hw, oaddr);
1669         if (ret_val) {
1670                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1671                 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1672                                   mac_str, ret_val);
1673         }
1674         rte_spinlock_unlock(&hw->lock);
1675
1676         return ret;
1677 }
1678
1679 static void
1680 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1681 {
1682 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1683         uint8_t word_num;
1684         uint8_t bit_num;
1685
1686         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1687                 word_num = vfid / 32;
1688                 bit_num = vfid % 32;
1689                 if (clr)
1690                         desc[1].data[word_num] &=
1691                             rte_cpu_to_le_32(~(1UL << bit_num));
1692                 else
1693                         desc[1].data[word_num] |=
1694                             rte_cpu_to_le_32(1UL << bit_num);
1695         } else {
1696                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1697                 bit_num = vfid % 32;
1698                 if (clr)
1699                         desc[2].data[word_num] &=
1700                             rte_cpu_to_le_32(~(1UL << bit_num));
1701                 else
1702                         desc[2].data[word_num] |=
1703                             rte_cpu_to_le_32(1UL << bit_num);
1704         }
1705 }
1706
1707 static int
1708 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1709 {
1710         struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM];
1711         struct hns3_mac_vlan_tbl_entry_cmd req;
1712         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1713         uint8_t vf_id;
1714         int ret;
1715
1716         /* Check if mac addr is valid */
1717         if (!rte_is_multicast_ether_addr(mac_addr)) {
1718                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1719                                       mac_addr);
1720                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1721                          mac_str);
1722                 return -EINVAL;
1723         }
1724
1725         memset(&req, 0, sizeof(req));
1726         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1727         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1728         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1729                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1730         if (ret) {
1731                 /* This mac addr do not exist, add new entry for it */
1732                 memset(desc[0].data, 0, sizeof(desc[0].data));
1733                 memset(desc[1].data, 0, sizeof(desc[0].data));
1734                 memset(desc[2].data, 0, sizeof(desc[0].data));
1735         }
1736
1737         /*
1738          * In current version VF is not supported when PF is driven by DPDK
1739          * driver, just need to configure parameters for PF vport.
1740          */
1741         vf_id = HNS3_PF_FUNC_ID;
1742         hns3_update_desc_vfid(desc, vf_id, false);
1743         ret = hns3_add_mac_vlan_tbl(hw, &req, desc,
1744                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1745         if (ret) {
1746                 if (ret == -ENOSPC)
1747                         hns3_err(hw, "mc mac vlan table is full");
1748                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1749                                       mac_addr);
1750                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1751         }
1752
1753         return ret;
1754 }
1755
1756 static int
1757 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1758 {
1759         struct hns3_mac_vlan_tbl_entry_cmd req;
1760         struct hns3_cmd_desc desc[3];
1761         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1762         uint8_t vf_id;
1763         int ret;
1764
1765         /* Check if mac addr is valid */
1766         if (!rte_is_multicast_ether_addr(mac_addr)) {
1767                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1768                                       mac_addr);
1769                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1770                          mac_str);
1771                 return -EINVAL;
1772         }
1773
1774         memset(&req, 0, sizeof(req));
1775         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1776         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1777         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1778                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1779         if (ret == 0) {
1780                 /*
1781                  * This mac addr exist, remove this handle's VFID for it.
1782                  * In current version VF is not supported when PF is driven by
1783                  * DPDK driver, just need to configure parameters for PF vport.
1784                  */
1785                 vf_id = HNS3_PF_FUNC_ID;
1786                 hns3_update_desc_vfid(desc, vf_id, true);
1787
1788                 /* All the vfid is zero, so need to delete this entry */
1789                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1790         } else if (ret == -ENOENT) {
1791                 /* This mac addr doesn't exist. */
1792                 return 0;
1793         }
1794
1795         if (ret) {
1796                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1797                                       mac_addr);
1798                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1799         }
1800
1801         return ret;
1802 }
1803
1804 static int
1805 hns3_check_mq_mode(struct rte_eth_dev *dev)
1806 {
1807         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1808         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1809         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1810         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1811         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1812         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1813         uint8_t num_tc;
1814         int max_tc = 0;
1815         int i;
1816
1817         if (((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) ||
1818             (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB ||
1819              tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) {
1820                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
1821                          rx_mq_mode, tx_mq_mode);
1822                 return -EOPNOTSUPP;
1823         }
1824
1825         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1826         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1827         if ((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
1828                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1829                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1830                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1831                         return -EINVAL;
1832                 }
1833
1834                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1835                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1836                         hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, "
1837                                  "nb_tcs(%d) != %d or %d in rx direction.",
1838                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1839                         return -EINVAL;
1840                 }
1841
1842                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1843                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1844                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1845                         return -EINVAL;
1846                 }
1847
1848                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1849                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1850                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
1851                                          "is not equal to one in tx direction.",
1852                                          i, dcb_rx_conf->dcb_tc[i]);
1853                                 return -EINVAL;
1854                         }
1855                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1856                                 max_tc = dcb_rx_conf->dcb_tc[i];
1857                 }
1858
1859                 num_tc = max_tc + 1;
1860                 if (num_tc > dcb_rx_conf->nb_tcs) {
1861                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1862                                  num_tc, dcb_rx_conf->nb_tcs);
1863                         return -EINVAL;
1864                 }
1865         }
1866
1867         return 0;
1868 }
1869
1870 static int
1871 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
1872                            enum hns3_ring_type queue_type, uint16_t queue_id)
1873 {
1874         struct hns3_cmd_desc desc;
1875         struct hns3_ctrl_vector_chain_cmd *req =
1876                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
1877         enum hns3_opcode_type op;
1878         uint16_t tqp_type_and_id = 0;
1879         uint16_t type;
1880         uint16_t gl;
1881         int ret;
1882
1883         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
1884         hns3_cmd_setup_basic_desc(&desc, op, false);
1885         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
1886                                               HNS3_TQP_INT_ID_L_S);
1887         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
1888                                               HNS3_TQP_INT_ID_H_S);
1889
1890         if (queue_type == HNS3_RING_TYPE_RX)
1891                 gl = HNS3_RING_GL_RX;
1892         else
1893                 gl = HNS3_RING_GL_TX;
1894
1895         type = queue_type;
1896
1897         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
1898                        type);
1899         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
1900         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
1901                        gl);
1902         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
1903         req->int_cause_num = 1;
1904         ret = hns3_cmd_send(hw, &desc, 1);
1905         if (ret) {
1906                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
1907                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
1908                 return ret;
1909         }
1910
1911         return 0;
1912 }
1913
1914 static int
1915 hns3_setup_dcb(struct rte_eth_dev *dev)
1916 {
1917         struct hns3_adapter *hns = dev->data->dev_private;
1918         struct hns3_hw *hw = &hns->hw;
1919         int ret;
1920
1921         if (!hns3_dev_get_support(hw, DCB)) {
1922                 hns3_err(hw, "this port does not support dcb configurations.");
1923                 return -EOPNOTSUPP;
1924         }
1925
1926         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
1927                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
1928                 return -EOPNOTSUPP;
1929         }
1930
1931         ret = hns3_dcb_configure(hns);
1932         if (ret)
1933                 hns3_err(hw, "failed to config dcb: %d", ret);
1934
1935         return ret;
1936 }
1937
1938 static int
1939 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
1940 {
1941         int ret;
1942
1943         /*
1944          * Some hardware doesn't support auto-negotiation, but users may not
1945          * configure link_speeds (default 0), which means auto-negotiation.
1946          * In this case, it should return success.
1947          */
1948         if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG &&
1949             hw->mac.support_autoneg == 0)
1950                 return 0;
1951
1952         if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) {
1953                 ret = hns3_check_port_speed(hw, link_speeds);
1954                 if (ret)
1955                         return ret;
1956         }
1957
1958         return 0;
1959 }
1960
1961 static int
1962 hns3_check_dev_conf(struct rte_eth_dev *dev)
1963 {
1964         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965         struct rte_eth_conf *conf = &dev->data->dev_conf;
1966         int ret;
1967
1968         ret = hns3_check_mq_mode(dev);
1969         if (ret)
1970                 return ret;
1971
1972         return hns3_check_link_speed(hw, conf->link_speeds);
1973 }
1974
1975 static int
1976 hns3_dev_configure(struct rte_eth_dev *dev)
1977 {
1978         struct hns3_adapter *hns = dev->data->dev_private;
1979         struct rte_eth_conf *conf = &dev->data->dev_conf;
1980         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
1981         struct hns3_hw *hw = &hns->hw;
1982         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1983         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1984         struct rte_eth_rss_conf rss_conf;
1985         bool gro_en;
1986         int ret;
1987
1988         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
1989
1990         /*
1991          * Some versions of hardware network engine does not support
1992          * individually enable/disable/reset the Tx or Rx queue. These devices
1993          * must enable/disable/reset Tx and Rx queues at the same time. When the
1994          * numbers of Tx queues allocated by upper applications are not equal to
1995          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
1996          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
1997          * work as usual. But these fake queues are imperceptible, and can not
1998          * be used by upper applications.
1999          */
2000         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2001         if (ret) {
2002                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2003                 hw->cfg_max_queues = 0;
2004                 return ret;
2005         }
2006
2007         hw->adapter_state = HNS3_NIC_CONFIGURING;
2008         ret = hns3_check_dev_conf(dev);
2009         if (ret)
2010                 goto cfg_err;
2011
2012         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2013                 ret = hns3_setup_dcb(dev);
2014                 if (ret)
2015                         goto cfg_err;
2016         }
2017
2018         /* When RSS is not configured, redirect the packet queue 0 */
2019         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2020                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2021                 rss_conf = conf->rx_adv_conf.rss_conf;
2022                 hw->rss_dis_flag = false;
2023                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2024                 if (ret)
2025                         goto cfg_err;
2026         }
2027
2028         ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu);
2029         if (ret != 0)
2030                 goto cfg_err;
2031
2032         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2033         if (ret)
2034                 goto cfg_err;
2035
2036         ret = hns3_dev_configure_vlan(dev);
2037         if (ret)
2038                 goto cfg_err;
2039
2040         /* config hardware GRO */
2041         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
2042         ret = hns3_config_gro(hw, gro_en);
2043         if (ret)
2044                 goto cfg_err;
2045
2046         hns3_init_rx_ptype_tble(dev);
2047         hw->adapter_state = HNS3_NIC_CONFIGURED;
2048
2049         return 0;
2050
2051 cfg_err:
2052         hw->cfg_max_queues = 0;
2053         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2054         hw->adapter_state = HNS3_NIC_INITIALIZED;
2055
2056         return ret;
2057 }
2058
2059 static int
2060 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2061 {
2062         struct hns3_config_max_frm_size_cmd *req;
2063         struct hns3_cmd_desc desc;
2064
2065         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2066
2067         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2068         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2069         req->min_frm_size = RTE_ETHER_MIN_LEN;
2070
2071         return hns3_cmd_send(hw, &desc, 1);
2072 }
2073
2074 static int
2075 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2076 {
2077         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2078         int err;
2079         int ret;
2080
2081         ret = hns3_set_mac_mtu(hw, mps);
2082         if (ret) {
2083                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2084                 return ret;
2085         }
2086
2087         ret = hns3_buffer_alloc(hw);
2088         if (ret) {
2089                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2090                 goto rollback;
2091         }
2092
2093         hns->pf.mps = mps;
2094
2095         return 0;
2096
2097 rollback:
2098         err = hns3_set_mac_mtu(hw, hns->pf.mps);
2099         if (err)
2100                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2101
2102         return ret;
2103 }
2104
2105 static int
2106 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2107 {
2108         struct hns3_adapter *hns = dev->data->dev_private;
2109         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2110         struct hns3_hw *hw = &hns->hw;
2111         int ret;
2112
2113         if (dev->data->dev_started) {
2114                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2115                          "before configuration", dev->data->port_id);
2116                 return -EBUSY;
2117         }
2118
2119         rte_spinlock_lock(&hw->lock);
2120         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2121
2122         /*
2123          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2124          * assign to "uint16_t" type variable.
2125          */
2126         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2127         if (ret) {
2128                 rte_spinlock_unlock(&hw->lock);
2129                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2130                          dev->data->port_id, mtu, ret);
2131                 return ret;
2132         }
2133
2134         rte_spinlock_unlock(&hw->lock);
2135
2136         return 0;
2137 }
2138
2139 static uint32_t
2140 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2141 {
2142         uint32_t speed_capa = 0;
2143
2144         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2145                 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD;
2146         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2147                 speed_capa |= RTE_ETH_LINK_SPEED_10M;
2148         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2149                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
2150         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2151                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
2152         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2153                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2154
2155         return speed_capa;
2156 }
2157
2158 static uint32_t
2159 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2160 {
2161         uint32_t speed_capa = 0;
2162
2163         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2164                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2165         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2166                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
2167         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2168                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
2169         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2170                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
2171         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2172                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
2173         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2174                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
2175         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2176                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
2177
2178         return speed_capa;
2179 }
2180
2181 uint32_t
2182 hns3_get_speed_capa(struct hns3_hw *hw)
2183 {
2184         struct hns3_mac *mac = &hw->mac;
2185         uint32_t speed_capa;
2186
2187         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2188                 speed_capa =
2189                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2190         else
2191                 speed_capa =
2192                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2193
2194         if (mac->support_autoneg == 0)
2195                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
2196
2197         return speed_capa;
2198 }
2199
2200 static int
2201 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2202 {
2203         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2204         int ret;
2205
2206         (void)hns3_update_link_status(hw);
2207
2208         ret = hns3_update_link_info(eth_dev);
2209         if (ret)
2210                 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2211
2212         return ret;
2213 }
2214
2215 static void
2216 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2217                       struct rte_eth_link *new_link)
2218 {
2219         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2220         struct hns3_mac *mac = &hw->mac;
2221
2222         switch (mac->link_speed) {
2223         case RTE_ETH_SPEED_NUM_10M:
2224         case RTE_ETH_SPEED_NUM_100M:
2225         case RTE_ETH_SPEED_NUM_1G:
2226         case RTE_ETH_SPEED_NUM_10G:
2227         case RTE_ETH_SPEED_NUM_25G:
2228         case RTE_ETH_SPEED_NUM_40G:
2229         case RTE_ETH_SPEED_NUM_50G:
2230         case RTE_ETH_SPEED_NUM_100G:
2231         case RTE_ETH_SPEED_NUM_200G:
2232                 if (mac->link_status)
2233                         new_link->link_speed = mac->link_speed;
2234                 break;
2235         default:
2236                 if (mac->link_status)
2237                         new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2238                 break;
2239         }
2240
2241         if (!mac->link_status)
2242                 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2243
2244         new_link->link_duplex = mac->link_duplex;
2245         new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2246         new_link->link_autoneg = mac->link_autoneg;
2247 }
2248
2249 static int
2250 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2251 {
2252 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2253 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2254
2255         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2256         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2257         struct hns3_mac *mac = &hw->mac;
2258         struct rte_eth_link new_link;
2259         int ret;
2260
2261         /* When port is stopped, report link down. */
2262         if (eth_dev->data->dev_started == 0) {
2263                 new_link.link_autoneg = mac->link_autoneg;
2264                 new_link.link_duplex = mac->link_duplex;
2265                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2266                 new_link.link_status = RTE_ETH_LINK_DOWN;
2267                 goto out;
2268         }
2269
2270         do {
2271                 ret = hns3_update_port_link_info(eth_dev);
2272                 if (ret) {
2273                         hns3_err(hw, "failed to get port link info, ret = %d.",
2274                                  ret);
2275                         break;
2276                 }
2277
2278                 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP)
2279                         break;
2280
2281                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2282         } while (retry_cnt--);
2283
2284         memset(&new_link, 0, sizeof(new_link));
2285         hns3_setup_linkstatus(eth_dev, &new_link);
2286
2287 out:
2288         return rte_eth_linkstatus_set(eth_dev, &new_link);
2289 }
2290
2291 static int
2292 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2293 {
2294         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295         int ret;
2296
2297         /*
2298          * The "tx_pkt_burst" will be restored. But the secondary process does
2299          * not support the mechanism for notifying the primary process.
2300          */
2301         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2302                 hns3_err(hw, "secondary process does not support to set link up.");
2303                 return -ENOTSUP;
2304         }
2305
2306         /*
2307          * If device isn't started Rx/Tx function is still disabled, setting
2308          * link up is not allowed. But it is probably better to return success
2309          * to reduce the impact on the upper layer.
2310          */
2311         if (hw->adapter_state != HNS3_NIC_STARTED) {
2312                 hns3_info(hw, "device isn't started, can't set link up.");
2313                 return 0;
2314         }
2315
2316         if (!hw->set_link_down)
2317                 return 0;
2318
2319         rte_spinlock_lock(&hw->lock);
2320         ret = hns3_cfg_mac_mode(hw, true);
2321         if (ret) {
2322                 rte_spinlock_unlock(&hw->lock);
2323                 hns3_err(hw, "failed to set link up, ret = %d", ret);
2324                 return ret;
2325         }
2326
2327         hw->set_link_down = false;
2328         hns3_start_tx_datapath(dev);
2329         rte_spinlock_unlock(&hw->lock);
2330
2331         return 0;
2332 }
2333
2334 static int
2335 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2336 {
2337         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2338         int ret;
2339
2340         /*
2341          * The "tx_pkt_burst" will be set to dummy function. But the secondary
2342          * process does not support the mechanism for notifying the primary
2343          * process.
2344          */
2345         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2346                 hns3_err(hw, "secondary process does not support to set link down.");
2347                 return -ENOTSUP;
2348         }
2349
2350         /*
2351          * If device isn't started or the API has been called, link status is
2352          * down, return success.
2353          */
2354         if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2355                 return 0;
2356
2357         rte_spinlock_lock(&hw->lock);
2358         hns3_stop_tx_datapath(dev);
2359         ret = hns3_cfg_mac_mode(hw, false);
2360         if (ret) {
2361                 hns3_start_tx_datapath(dev);
2362                 rte_spinlock_unlock(&hw->lock);
2363                 hns3_err(hw, "failed to set link down, ret = %d", ret);
2364                 return ret;
2365         }
2366
2367         hw->set_link_down = true;
2368         rte_spinlock_unlock(&hw->lock);
2369
2370         return 0;
2371 }
2372
2373 static int
2374 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2375 {
2376         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2377         struct hns3_pf *pf = &hns->pf;
2378
2379         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2380                 return -EINVAL;
2381
2382         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2383
2384         return 0;
2385 }
2386
2387 static int
2388 hns3_query_function_status(struct hns3_hw *hw)
2389 {
2390 #define HNS3_QUERY_MAX_CNT              10
2391 #define HNS3_QUERY_SLEEP_MSCOEND        1
2392         struct hns3_func_status_cmd *req;
2393         struct hns3_cmd_desc desc;
2394         int timeout = 0;
2395         int ret;
2396
2397         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2398         req = (struct hns3_func_status_cmd *)desc.data;
2399
2400         do {
2401                 ret = hns3_cmd_send(hw, &desc, 1);
2402                 if (ret) {
2403                         PMD_INIT_LOG(ERR, "query function status failed %d",
2404                                      ret);
2405                         return ret;
2406                 }
2407
2408                 /* Check pf reset is done */
2409                 if (req->pf_state)
2410                         break;
2411
2412                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2413         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2414
2415         return hns3_parse_func_status(hw, req);
2416 }
2417
2418 static int
2419 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2420 {
2421         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2422         struct hns3_pf *pf = &hns->pf;
2423
2424         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2425                 /*
2426                  * The total_tqps_num obtained from firmware is maximum tqp
2427                  * numbers of this port, which should be used for PF and VFs.
2428                  * There is no need for pf to have so many tqp numbers in
2429                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2430                  * coming from config file, is assigned to maximum queue number
2431                  * for the PF of this port by user. So users can modify the
2432                  * maximum queue number of PF according to their own application
2433                  * scenarios, which is more flexible to use. In addition, many
2434                  * memories can be saved due to allocating queue statistics
2435                  * room according to the actual number of queues required. The
2436                  * maximum queue number of PF for network engine with
2437                  * revision_id greater than 0x30 is assigned by config file.
2438                  */
2439                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2440                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2441                                  "must be greater than 0.",
2442                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2443                         return -EINVAL;
2444                 }
2445
2446                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2447                                        hw->total_tqps_num);
2448         } else {
2449                 /*
2450                  * Due to the limitation on the number of PF interrupts
2451                  * available, the maximum queue number assigned to PF on
2452                  * the network engine with revision_id 0x21 is 64.
2453                  */
2454                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2455                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2456         }
2457
2458         return 0;
2459 }
2460
2461 static int
2462 hns3_query_pf_resource(struct hns3_hw *hw)
2463 {
2464         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2465         struct hns3_pf *pf = &hns->pf;
2466         struct hns3_pf_res_cmd *req;
2467         struct hns3_cmd_desc desc;
2468         int ret;
2469
2470         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2471         ret = hns3_cmd_send(hw, &desc, 1);
2472         if (ret) {
2473                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2474                 return ret;
2475         }
2476
2477         req = (struct hns3_pf_res_cmd *)desc.data;
2478         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2479                              rte_le_to_cpu_16(req->ext_tqp_num);
2480         ret = hns3_get_pf_max_tqp_num(hw);
2481         if (ret)
2482                 return ret;
2483
2484         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2485         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2486
2487         if (req->tx_buf_size)
2488                 pf->tx_buf_size =
2489                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2490         else
2491                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2492
2493         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2494
2495         if (req->dv_buf_size)
2496                 pf->dv_buf_size =
2497                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2498         else
2499                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2500
2501         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2502
2503         hw->num_msi =
2504                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2505                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2506
2507         return 0;
2508 }
2509
2510 static void
2511 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2512 {
2513         struct hns3_cfg_param_cmd *req;
2514         uint64_t mac_addr_tmp_high;
2515         uint8_t ext_rss_size_max;
2516         uint64_t mac_addr_tmp;
2517         uint32_t i;
2518
2519         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2520
2521         /* get the configuration */
2522         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2523                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2524
2525         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2526                                        HNS3_CFG_PHY_ADDR_M,
2527                                        HNS3_CFG_PHY_ADDR_S);
2528         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2529                                          HNS3_CFG_MEDIA_TP_M,
2530                                          HNS3_CFG_MEDIA_TP_S);
2531         /* get mac address */
2532         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2533         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2534                                            HNS3_CFG_MAC_ADDR_H_M,
2535                                            HNS3_CFG_MAC_ADDR_H_S);
2536
2537         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2538
2539         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2540                                             HNS3_CFG_DEFAULT_SPEED_M,
2541                                             HNS3_CFG_DEFAULT_SPEED_S);
2542         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2543                                            HNS3_CFG_RSS_SIZE_M,
2544                                            HNS3_CFG_RSS_SIZE_S);
2545
2546         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2547                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2548
2549         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2550         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2551
2552         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2553                                             HNS3_CFG_SPEED_ABILITY_M,
2554                                             HNS3_CFG_SPEED_ABILITY_S);
2555         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2556                                         HNS3_CFG_UMV_TBL_SPACE_M,
2557                                         HNS3_CFG_UMV_TBL_SPACE_S);
2558         if (!cfg->umv_space)
2559                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2560
2561         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2562                                                HNS3_CFG_EXT_RSS_SIZE_M,
2563                                                HNS3_CFG_EXT_RSS_SIZE_S);
2564         /*
2565          * Field ext_rss_size_max obtained from firmware will be more flexible
2566          * for future changes and expansions, which is an exponent of 2, instead
2567          * of reading out directly. If this field is not zero, hns3 PF PMD
2568          * uses it as rss_size_max under one TC. Device, whose revision
2569          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2570          * maximum number of queues supported under a TC through this field.
2571          */
2572         if (ext_rss_size_max)
2573                 cfg->rss_size_max = 1U << ext_rss_size_max;
2574 }
2575
2576 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2577  * @hw: pointer to struct hns3_hw
2578  * @hcfg: the config structure to be getted
2579  */
2580 static int
2581 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2582 {
2583         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2584         struct hns3_cfg_param_cmd *req;
2585         uint32_t offset;
2586         uint32_t i;
2587         int ret;
2588
2589         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2590                 offset = 0;
2591                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2592                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2593                                           true);
2594                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2595                                i * HNS3_CFG_RD_LEN_BYTES);
2596                 /* Len should be divided by 4 when send to hardware */
2597                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2598                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2599                 req->offset = rte_cpu_to_le_32(offset);
2600         }
2601
2602         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2603         if (ret) {
2604                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2605                 return ret;
2606         }
2607
2608         hns3_parse_cfg(hcfg, desc);
2609
2610         return 0;
2611 }
2612
2613 static int
2614 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2615 {
2616         switch (speed_cmd) {
2617         case HNS3_CFG_SPEED_10M:
2618                 *speed = RTE_ETH_SPEED_NUM_10M;
2619                 break;
2620         case HNS3_CFG_SPEED_100M:
2621                 *speed = RTE_ETH_SPEED_NUM_100M;
2622                 break;
2623         case HNS3_CFG_SPEED_1G:
2624                 *speed = RTE_ETH_SPEED_NUM_1G;
2625                 break;
2626         case HNS3_CFG_SPEED_10G:
2627                 *speed = RTE_ETH_SPEED_NUM_10G;
2628                 break;
2629         case HNS3_CFG_SPEED_25G:
2630                 *speed = RTE_ETH_SPEED_NUM_25G;
2631                 break;
2632         case HNS3_CFG_SPEED_40G:
2633                 *speed = RTE_ETH_SPEED_NUM_40G;
2634                 break;
2635         case HNS3_CFG_SPEED_50G:
2636                 *speed = RTE_ETH_SPEED_NUM_50G;
2637                 break;
2638         case HNS3_CFG_SPEED_100G:
2639                 *speed = RTE_ETH_SPEED_NUM_100G;
2640                 break;
2641         case HNS3_CFG_SPEED_200G:
2642                 *speed = RTE_ETH_SPEED_NUM_200G;
2643                 break;
2644         default:
2645                 return -EINVAL;
2646         }
2647
2648         return 0;
2649 }
2650
2651 static void
2652 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2653 {
2654         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2655         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2656         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2657         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2658         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2659 }
2660
2661 static void
2662 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2663 {
2664         struct hns3_dev_specs_0_cmd *req0;
2665
2666         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2667
2668         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2669         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2670         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2671         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2672         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2673 }
2674
2675 static int
2676 hns3_check_dev_specifications(struct hns3_hw *hw)
2677 {
2678         if (hw->rss_ind_tbl_size == 0 ||
2679             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
2680                 hns3_err(hw, "the size of hash lookup table configured (%u)"
2681                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
2682                               HNS3_RSS_IND_TBL_SIZE_MAX);
2683                 return -EINVAL;
2684         }
2685
2686         return 0;
2687 }
2688
2689 static int
2690 hns3_query_dev_specifications(struct hns3_hw *hw)
2691 {
2692         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2693         int ret;
2694         int i;
2695
2696         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2697                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2698                                           true);
2699                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2700         }
2701         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2702
2703         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2704         if (ret)
2705                 return ret;
2706
2707         hns3_parse_dev_specifications(hw, desc);
2708
2709         return hns3_check_dev_specifications(hw);
2710 }
2711
2712 static int
2713 hns3_get_capability(struct hns3_hw *hw)
2714 {
2715         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2716         struct rte_pci_device *pci_dev;
2717         struct hns3_pf *pf = &hns->pf;
2718         struct rte_eth_dev *eth_dev;
2719         uint16_t device_id;
2720         int ret;
2721
2722         eth_dev = &rte_eth_devices[hw->data->port_id];
2723         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2724         device_id = pci_dev->id.device_id;
2725
2726         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2727             device_id == HNS3_DEV_ID_50GE_RDMA ||
2728             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2729             device_id == HNS3_DEV_ID_200G_RDMA)
2730                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2731
2732         ret = hns3_get_pci_revision_id(hw, &hw->revision);
2733         if (ret)
2734                 return ret;
2735
2736         if (hw->revision < PCI_REVISION_ID_HIP09_A) {
2737                 hns3_set_default_dev_specifications(hw);
2738                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2739                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2740                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
2741                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
2742                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
2743                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2744                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
2745                 hw->rss_info.ipv6_sctp_offload_supported = false;
2746                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
2747                 pf->support_multi_tc_pause = false;
2748                 return 0;
2749         }
2750
2751         ret = hns3_query_dev_specifications(hw);
2752         if (ret) {
2753                 PMD_INIT_LOG(ERR,
2754                              "failed to query dev specifications, ret = %d",
2755                              ret);
2756                 return ret;
2757         }
2758
2759         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
2760         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
2761         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
2762         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
2763         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
2764         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
2765         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
2766         hw->rss_info.ipv6_sctp_offload_supported = true;
2767         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
2768         pf->support_multi_tc_pause = true;
2769
2770         return 0;
2771 }
2772
2773 static int
2774 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
2775 {
2776         int ret;
2777
2778         switch (media_type) {
2779         case HNS3_MEDIA_TYPE_COPPER:
2780                 if (!hns3_dev_get_support(hw, COPPER)) {
2781                         PMD_INIT_LOG(ERR,
2782                                      "Media type is copper, not supported.");
2783                         ret = -EOPNOTSUPP;
2784                 } else {
2785                         ret = 0;
2786                 }
2787                 break;
2788         case HNS3_MEDIA_TYPE_FIBER:
2789                 ret = 0;
2790                 break;
2791         case HNS3_MEDIA_TYPE_BACKPLANE:
2792                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
2793                 ret = -EOPNOTSUPP;
2794                 break;
2795         default:
2796                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
2797                 ret = -EINVAL;
2798                 break;
2799         }
2800
2801         return ret;
2802 }
2803
2804 static int
2805 hns3_get_board_configuration(struct hns3_hw *hw)
2806 {
2807         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2808         struct hns3_pf *pf = &hns->pf;
2809         struct hns3_cfg cfg;
2810         int ret;
2811
2812         ret = hns3_get_board_cfg(hw, &cfg);
2813         if (ret) {
2814                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2815                 return ret;
2816         }
2817
2818         ret = hns3_check_media_type(hw, cfg.media_type);
2819         if (ret)
2820                 return ret;
2821
2822         hw->mac.media_type = cfg.media_type;
2823         hw->rss_size_max = cfg.rss_size_max;
2824         hw->rss_dis_flag = false;
2825         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2826         hw->mac.phy_addr = cfg.phy_addr;
2827         hw->dcb_info.num_pg = 1;
2828         hw->dcb_info.hw_pfc_map = 0;
2829
2830         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2831         if (ret) {
2832                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
2833                              cfg.default_speed, ret);
2834                 return ret;
2835         }
2836
2837         pf->tc_max = cfg.tc_num;
2838         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2839                 PMD_INIT_LOG(WARNING,
2840                              "Get TC num(%u) from flash, set TC num to 1",
2841                              pf->tc_max);
2842                 pf->tc_max = 1;
2843         }
2844
2845         /* Dev does not support DCB */
2846         if (!hns3_dev_get_support(hw, DCB)) {
2847                 pf->tc_max = 1;
2848                 pf->pfc_max = 0;
2849         } else
2850                 pf->pfc_max = pf->tc_max;
2851
2852         hw->dcb_info.num_tc = 1;
2853         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2854                                      hw->tqps_num / hw->dcb_info.num_tc);
2855         hns3_set_bit(hw->hw_tc_map, 0, 1);
2856         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2857
2858         pf->wanted_umv_size = cfg.umv_space;
2859
2860         return ret;
2861 }
2862
2863 static int
2864 hns3_get_configuration(struct hns3_hw *hw)
2865 {
2866         int ret;
2867
2868         ret = hns3_query_function_status(hw);
2869         if (ret) {
2870                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2871                 return ret;
2872         }
2873
2874         /* Get device capability */
2875         ret = hns3_get_capability(hw);
2876         if (ret) {
2877                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
2878                 return ret;
2879         }
2880
2881         /* Get pf resource */
2882         ret = hns3_query_pf_resource(hw);
2883         if (ret) {
2884                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2885                 return ret;
2886         }
2887
2888         ret = hns3_get_board_configuration(hw);
2889         if (ret) {
2890                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
2891                 return ret;
2892         }
2893
2894         ret = hns3_query_dev_fec_info(hw);
2895         if (ret)
2896                 PMD_INIT_LOG(ERR,
2897                              "failed to query FEC information, ret = %d", ret);
2898
2899         return ret;
2900 }
2901
2902 static int
2903 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2904                       uint16_t tqp_vid, bool is_pf)
2905 {
2906         struct hns3_tqp_map_cmd *req;
2907         struct hns3_cmd_desc desc;
2908         int ret;
2909
2910         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2911
2912         req = (struct hns3_tqp_map_cmd *)desc.data;
2913         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2914         req->tqp_vf = func_id;
2915         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2916         if (!is_pf)
2917                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2918         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2919
2920         ret = hns3_cmd_send(hw, &desc, 1);
2921         if (ret)
2922                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2923
2924         return ret;
2925 }
2926
2927 static int
2928 hns3_map_tqp(struct hns3_hw *hw)
2929 {
2930         int ret;
2931         int i;
2932
2933         /*
2934          * In current version, VF is not supported when PF is driven by DPDK
2935          * driver, so we assign total tqps_num tqps allocated to this port
2936          * to PF.
2937          */
2938         for (i = 0; i < hw->total_tqps_num; i++) {
2939                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
2940                 if (ret)
2941                         return ret;
2942         }
2943
2944         return 0;
2945 }
2946
2947 static int
2948 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2949 {
2950         struct hns3_config_mac_speed_dup_cmd *req;
2951         struct hns3_cmd_desc desc;
2952         int ret;
2953
2954         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2955
2956         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2957
2958         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2959
2960         switch (speed) {
2961         case RTE_ETH_SPEED_NUM_10M:
2962                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2963                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2964                 break;
2965         case RTE_ETH_SPEED_NUM_100M:
2966                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2967                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2968                 break;
2969         case RTE_ETH_SPEED_NUM_1G:
2970                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2971                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2972                 break;
2973         case RTE_ETH_SPEED_NUM_10G:
2974                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2975                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2976                 break;
2977         case RTE_ETH_SPEED_NUM_25G:
2978                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2979                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2980                 break;
2981         case RTE_ETH_SPEED_NUM_40G:
2982                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2983                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2984                 break;
2985         case RTE_ETH_SPEED_NUM_50G:
2986                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2987                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2988                 break;
2989         case RTE_ETH_SPEED_NUM_100G:
2990                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2991                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2992                 break;
2993         case RTE_ETH_SPEED_NUM_200G:
2994                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2995                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
2996                 break;
2997         default:
2998                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2999                 return -EINVAL;
3000         }
3001
3002         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3003
3004         ret = hns3_cmd_send(hw, &desc, 1);
3005         if (ret)
3006                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3007
3008         return ret;
3009 }
3010
3011 static int
3012 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3013 {
3014         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3015         struct hns3_pf *pf = &hns->pf;
3016         struct hns3_priv_buf *priv;
3017         uint32_t i, total_size;
3018
3019         total_size = pf->pkt_buf_size;
3020
3021         /* alloc tx buffer for all enabled tc */
3022         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3023                 priv = &buf_alloc->priv_buf[i];
3024
3025                 if (hw->hw_tc_map & BIT(i)) {
3026                         if (total_size < pf->tx_buf_size)
3027                                 return -ENOMEM;
3028
3029                         priv->tx_buf_size = pf->tx_buf_size;
3030                 } else
3031                         priv->tx_buf_size = 0;
3032
3033                 total_size -= priv->tx_buf_size;
3034         }
3035
3036         return 0;
3037 }
3038
3039 static int
3040 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3041 {
3042 /* TX buffer size is unit by 128 byte */
3043 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3044 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3045         struct hns3_tx_buff_alloc_cmd *req;
3046         struct hns3_cmd_desc desc;
3047         uint32_t buf_size;
3048         uint32_t i;
3049         int ret;
3050
3051         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3052
3053         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3054         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3055                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3056
3057                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3058                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3059                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3060         }
3061
3062         ret = hns3_cmd_send(hw, &desc, 1);
3063         if (ret)
3064                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3065
3066         return ret;
3067 }
3068
3069 static int
3070 hns3_get_tc_num(struct hns3_hw *hw)
3071 {
3072         int cnt = 0;
3073         uint8_t i;
3074
3075         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3076                 if (hw->hw_tc_map & BIT(i))
3077                         cnt++;
3078         return cnt;
3079 }
3080
3081 static uint32_t
3082 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3083 {
3084         struct hns3_priv_buf *priv;
3085         uint32_t rx_priv = 0;
3086         int i;
3087
3088         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3089                 priv = &buf_alloc->priv_buf[i];
3090                 if (priv->enable)
3091                         rx_priv += priv->buf_size;
3092         }
3093         return rx_priv;
3094 }
3095
3096 static uint32_t
3097 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3098 {
3099         uint32_t total_tx_size = 0;
3100         uint32_t i;
3101
3102         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3103                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3104
3105         return total_tx_size;
3106 }
3107
3108 /* Get the number of pfc enabled TCs, which have private buffer */
3109 static int
3110 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3111 {
3112         struct hns3_priv_buf *priv;
3113         int cnt = 0;
3114         uint8_t i;
3115
3116         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3117                 priv = &buf_alloc->priv_buf[i];
3118                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3119                         cnt++;
3120         }
3121
3122         return cnt;
3123 }
3124
3125 /* Get the number of pfc disabled TCs, which have private buffer */
3126 static int
3127 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3128                          struct hns3_pkt_buf_alloc *buf_alloc)
3129 {
3130         struct hns3_priv_buf *priv;
3131         int cnt = 0;
3132         uint8_t i;
3133
3134         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3135                 priv = &buf_alloc->priv_buf[i];
3136                 if (hw->hw_tc_map & BIT(i) &&
3137                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3138                         cnt++;
3139         }
3140
3141         return cnt;
3142 }
3143
3144 static bool
3145 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3146                   uint32_t rx_all)
3147 {
3148         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3149         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3150         struct hns3_pf *pf = &hns->pf;
3151         uint32_t shared_buf, aligned_mps;
3152         uint32_t rx_priv;
3153         uint8_t tc_num;
3154         uint8_t i;
3155
3156         tc_num = hns3_get_tc_num(hw);
3157         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3158
3159         if (hns3_dev_get_support(hw, DCB))
3160                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3161                                         pf->dv_buf_size;
3162         else
3163                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3164                                         + pf->dv_buf_size;
3165
3166         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3167         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3168                              HNS3_BUF_SIZE_UNIT);
3169
3170         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3171         if (rx_all < rx_priv + shared_std)
3172                 return false;
3173
3174         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3175         buf_alloc->s_buf.buf_size = shared_buf;
3176         if (hns3_dev_get_support(hw, DCB)) {
3177                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3178                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3179                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3180                                   HNS3_BUF_SIZE_UNIT);
3181         } else {
3182                 buf_alloc->s_buf.self.high =
3183                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3184                 buf_alloc->s_buf.self.low = aligned_mps;
3185         }
3186
3187         if (hns3_dev_get_support(hw, DCB)) {
3188                 hi_thrd = shared_buf - pf->dv_buf_size;
3189
3190                 if (tc_num <= NEED_RESERVE_TC_NUM)
3191                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3192                                   BUF_MAX_PERCENT;
3193
3194                 if (tc_num)
3195                         hi_thrd = hi_thrd / tc_num;
3196
3197                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3198                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3199                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3200         } else {
3201                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3202                 lo_thrd = aligned_mps;
3203         }
3204
3205         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3206                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3207                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3208         }
3209
3210         return true;
3211 }
3212
3213 static bool
3214 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3215                      struct hns3_pkt_buf_alloc *buf_alloc)
3216 {
3217         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3218         struct hns3_pf *pf = &hns->pf;
3219         struct hns3_priv_buf *priv;
3220         uint32_t aligned_mps;
3221         uint32_t rx_all;
3222         uint8_t i;
3223
3224         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3225         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3226
3227         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3228                 priv = &buf_alloc->priv_buf[i];
3229
3230                 priv->enable = 0;
3231                 priv->wl.low = 0;
3232                 priv->wl.high = 0;
3233                 priv->buf_size = 0;
3234
3235                 if (!(hw->hw_tc_map & BIT(i)))
3236                         continue;
3237
3238                 priv->enable = 1;
3239                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3240                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3241                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3242                                                 HNS3_BUF_SIZE_UNIT);
3243                 } else {
3244                         priv->wl.low = 0;
3245                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3246                                         aligned_mps;
3247                 }
3248
3249                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3250         }
3251
3252         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3253 }
3254
3255 static bool
3256 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3257                              struct hns3_pkt_buf_alloc *buf_alloc)
3258 {
3259         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3260         struct hns3_pf *pf = &hns->pf;
3261         struct hns3_priv_buf *priv;
3262         int no_pfc_priv_num;
3263         uint32_t rx_all;
3264         uint8_t mask;
3265         int i;
3266
3267         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3268         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3269
3270         /* let the last to be cleared first */
3271         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3272                 priv = &buf_alloc->priv_buf[i];
3273                 mask = BIT((uint8_t)i);
3274                 if (hw->hw_tc_map & mask &&
3275                     !(hw->dcb_info.hw_pfc_map & mask)) {
3276                         /* Clear the no pfc TC private buffer */
3277                         priv->wl.low = 0;
3278                         priv->wl.high = 0;
3279                         priv->buf_size = 0;
3280                         priv->enable = 0;
3281                         no_pfc_priv_num--;
3282                 }
3283
3284                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3285                     no_pfc_priv_num == 0)
3286                         break;
3287         }
3288
3289         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3290 }
3291
3292 static bool
3293 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3294                            struct hns3_pkt_buf_alloc *buf_alloc)
3295 {
3296         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3297         struct hns3_pf *pf = &hns->pf;
3298         struct hns3_priv_buf *priv;
3299         uint32_t rx_all;
3300         int pfc_priv_num;
3301         uint8_t mask;
3302         int i;
3303
3304         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3305         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3306
3307         /* let the last to be cleared first */
3308         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3309                 priv = &buf_alloc->priv_buf[i];
3310                 mask = BIT((uint8_t)i);
3311                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3312                         /* Reduce the number of pfc TC with private buffer */
3313                         priv->wl.low = 0;
3314                         priv->enable = 0;
3315                         priv->wl.high = 0;
3316                         priv->buf_size = 0;
3317                         pfc_priv_num--;
3318                 }
3319                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3320                     pfc_priv_num == 0)
3321                         break;
3322         }
3323
3324         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3325 }
3326
3327 static bool
3328 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3329                           struct hns3_pkt_buf_alloc *buf_alloc)
3330 {
3331 #define COMPENSATE_BUFFER       0x3C00
3332 #define COMPENSATE_HALF_MPS_NUM 5
3333 #define PRIV_WL_GAP             0x1800
3334         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3335         struct hns3_pf *pf = &hns->pf;
3336         uint32_t tc_num = hns3_get_tc_num(hw);
3337         uint32_t half_mps = pf->mps >> 1;
3338         struct hns3_priv_buf *priv;
3339         uint32_t min_rx_priv;
3340         uint32_t rx_priv;
3341         uint8_t i;
3342
3343         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3344         if (tc_num)
3345                 rx_priv = rx_priv / tc_num;
3346
3347         if (tc_num <= NEED_RESERVE_TC_NUM)
3348                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3349
3350         /*
3351          * Minimum value of private buffer in rx direction (min_rx_priv) is
3352          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3353          * buffer if rx_priv is greater than min_rx_priv.
3354          */
3355         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3356                         COMPENSATE_HALF_MPS_NUM * half_mps;
3357         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3358         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3359         if (rx_priv < min_rx_priv)
3360                 return false;
3361
3362         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3363                 priv = &buf_alloc->priv_buf[i];
3364                 priv->enable = 0;
3365                 priv->wl.low = 0;
3366                 priv->wl.high = 0;
3367                 priv->buf_size = 0;
3368
3369                 if (!(hw->hw_tc_map & BIT(i)))
3370                         continue;
3371
3372                 priv->enable = 1;
3373                 priv->buf_size = rx_priv;
3374                 priv->wl.high = rx_priv - pf->dv_buf_size;
3375                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3376         }
3377
3378         buf_alloc->s_buf.buf_size = 0;
3379
3380         return true;
3381 }
3382
3383 /*
3384  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3385  * @hw: pointer to struct hns3_hw
3386  * @buf_alloc: pointer to buffer calculation data
3387  * @return: 0: calculate successful, negative: fail
3388  */
3389 static int
3390 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3391 {
3392         /* When DCB is not supported, rx private buffer is not allocated. */
3393         if (!hns3_dev_get_support(hw, DCB)) {
3394                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3395                 struct hns3_pf *pf = &hns->pf;
3396                 uint32_t rx_all = pf->pkt_buf_size;
3397
3398                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3399                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3400                         return -ENOMEM;
3401
3402                 return 0;
3403         }
3404
3405         /*
3406          * Try to allocate privated packet buffer for all TCs without share
3407          * buffer.
3408          */
3409         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3410                 return 0;
3411
3412         /*
3413          * Try to allocate privated packet buffer for all TCs with share
3414          * buffer.
3415          */
3416         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3417                 return 0;
3418
3419         /*
3420          * For different application scenes, the enabled port number, TC number
3421          * and no_drop TC number are different. In order to obtain the better
3422          * performance, software could allocate the buffer size and configure
3423          * the waterline by trying to decrease the private buffer size according
3424          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
3425          * enabled tc.
3426          */
3427         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3428                 return 0;
3429
3430         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3431                 return 0;
3432
3433         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3434                 return 0;
3435
3436         return -ENOMEM;
3437 }
3438
3439 static int
3440 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3441 {
3442         struct hns3_rx_priv_buff_cmd *req;
3443         struct hns3_cmd_desc desc;
3444         uint32_t buf_size;
3445         int ret;
3446         int i;
3447
3448         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3449         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3450
3451         /* Alloc private buffer TCs */
3452         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3453                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3454
3455                 req->buf_num[i] =
3456                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3457                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3458         }
3459
3460         buf_size = buf_alloc->s_buf.buf_size;
3461         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3462                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3463
3464         ret = hns3_cmd_send(hw, &desc, 1);
3465         if (ret)
3466                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3467
3468         return ret;
3469 }
3470
3471 static int
3472 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3473 {
3474 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3475         struct hns3_rx_priv_wl_buf *req;
3476         struct hns3_priv_buf *priv;
3477         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3478         int i, j;
3479         int ret;
3480
3481         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3482                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3483                                           false);
3484                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3485
3486                 /* The first descriptor set the NEXT bit to 1 */
3487                 if (i == 0)
3488                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3489                 else
3490                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3491
3492                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3493                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3494
3495                         priv = &buf_alloc->priv_buf[idx];
3496                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3497                                                         HNS3_BUF_UNIT_S);
3498                         req->tc_wl[j].high |=
3499                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3500                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3501                                                         HNS3_BUF_UNIT_S);
3502                         req->tc_wl[j].low |=
3503                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3504                 }
3505         }
3506
3507         /* Send 2 descriptor at one time */
3508         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3509         if (ret)
3510                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3511                              ret);
3512         return ret;
3513 }
3514
3515 static int
3516 hns3_common_thrd_config(struct hns3_hw *hw,
3517                         struct hns3_pkt_buf_alloc *buf_alloc)
3518 {
3519 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3520         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3521         struct hns3_rx_com_thrd *req;
3522         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3523         struct hns3_tc_thrd *tc;
3524         int tc_idx;
3525         int i, j;
3526         int ret;
3527
3528         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3529                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3530                                           false);
3531                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3532
3533                 /* The first descriptor set the NEXT bit to 1 */
3534                 if (i == 0)
3535                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3536                 else
3537                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3538
3539                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3540                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3541                         tc = &s_buf->tc_thrd[tc_idx];
3542
3543                         req->com_thrd[j].high =
3544                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3545                         req->com_thrd[j].high |=
3546                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3547                         req->com_thrd[j].low =
3548                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3549                         req->com_thrd[j].low |=
3550                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3551                 }
3552         }
3553
3554         /* Send 2 descriptors at one time */
3555         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3556         if (ret)
3557                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3558
3559         return ret;
3560 }
3561
3562 static int
3563 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3564 {
3565         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3566         struct hns3_rx_com_wl *req;
3567         struct hns3_cmd_desc desc;
3568         int ret;
3569
3570         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3571
3572         req = (struct hns3_rx_com_wl *)desc.data;
3573         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3574         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3575
3576         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3577         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3578
3579         ret = hns3_cmd_send(hw, &desc, 1);
3580         if (ret)
3581                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3582
3583         return ret;
3584 }
3585
3586 int
3587 hns3_buffer_alloc(struct hns3_hw *hw)
3588 {
3589         struct hns3_pkt_buf_alloc pkt_buf;
3590         int ret;
3591
3592         memset(&pkt_buf, 0, sizeof(pkt_buf));
3593         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3594         if (ret) {
3595                 PMD_INIT_LOG(ERR,
3596                              "could not calc tx buffer size for all TCs %d",
3597                              ret);
3598                 return ret;
3599         }
3600
3601         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3602         if (ret) {
3603                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3604                 return ret;
3605         }
3606
3607         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3608         if (ret) {
3609                 PMD_INIT_LOG(ERR,
3610                              "could not calc rx priv buffer size for all TCs %d",
3611                              ret);
3612                 return ret;
3613         }
3614
3615         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3616         if (ret) {
3617                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3618                 return ret;
3619         }
3620
3621         if (hns3_dev_get_support(hw, DCB)) {
3622                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3623                 if (ret) {
3624                         PMD_INIT_LOG(ERR,
3625                                      "could not configure rx private waterline %d",
3626                                      ret);
3627                         return ret;
3628                 }
3629
3630                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3631                 if (ret) {
3632                         PMD_INIT_LOG(ERR,
3633                                      "could not configure common threshold %d",
3634                                      ret);
3635                         return ret;
3636                 }
3637         }
3638
3639         ret = hns3_common_wl_config(hw, &pkt_buf);
3640         if (ret)
3641                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3642                              ret);
3643
3644         return ret;
3645 }
3646
3647 static int
3648 hns3_mac_init(struct hns3_hw *hw)
3649 {
3650         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3651         struct hns3_mac *mac = &hw->mac;
3652         struct hns3_pf *pf = &hns->pf;
3653         int ret;
3654
3655         pf->support_sfp_query = true;
3656         mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3657         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3658         if (ret) {
3659                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3660                 return ret;
3661         }
3662
3663         mac->link_status = RTE_ETH_LINK_DOWN;
3664
3665         return hns3_config_mtu(hw, pf->mps);
3666 }
3667
3668 static int
3669 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3670 {
3671 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3672 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3673 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3674 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3675         int return_status;
3676
3677         if (cmdq_resp) {
3678                 PMD_INIT_LOG(ERR,
3679                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3680                              cmdq_resp);
3681                 return -EIO;
3682         }
3683
3684         switch (resp_code) {
3685         case HNS3_ETHERTYPE_SUCCESS_ADD:
3686         case HNS3_ETHERTYPE_ALREADY_ADD:
3687                 return_status = 0;
3688                 break;
3689         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3690                 PMD_INIT_LOG(ERR,
3691                              "add mac ethertype failed for manager table overflow.");
3692                 return_status = -EIO;
3693                 break;
3694         case HNS3_ETHERTYPE_KEY_CONFLICT:
3695                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3696                 return_status = -EIO;
3697                 break;
3698         default:
3699                 PMD_INIT_LOG(ERR,
3700                              "add mac ethertype failed for undefined, code=%u.",
3701                              resp_code);
3702                 return_status = -EIO;
3703                 break;
3704         }
3705
3706         return return_status;
3707 }
3708
3709 static int
3710 hns3_add_mgr_tbl(struct hns3_hw *hw,
3711                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3712 {
3713         struct hns3_cmd_desc desc;
3714         uint8_t resp_code;
3715         uint16_t retval;
3716         int ret;
3717
3718         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3719         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3720
3721         ret = hns3_cmd_send(hw, &desc, 1);
3722         if (ret) {
3723                 PMD_INIT_LOG(ERR,
3724                              "add mac ethertype failed for cmd_send, ret =%d.",
3725                              ret);
3726                 return ret;
3727         }
3728
3729         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3730         retval = rte_le_to_cpu_16(desc.retval);
3731
3732         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3733 }
3734
3735 static void
3736 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3737                      int *table_item_num)
3738 {
3739         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3740
3741         /*
3742          * In current version, we add one item in management table as below:
3743          * 0x0180C200000E -- LLDP MC address
3744          */
3745         tbl = mgr_table;
3746         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3747         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3748         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3749         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3750         tbl->i_port_bitmap = 0x1;
3751         *table_item_num = 1;
3752 }
3753
3754 static int
3755 hns3_init_mgr_tbl(struct hns3_hw *hw)
3756 {
3757 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3758         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3759         int table_item_num;
3760         int ret;
3761         int i;
3762
3763         memset(mgr_table, 0, sizeof(mgr_table));
3764         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3765         for (i = 0; i < table_item_num; i++) {
3766                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3767                 if (ret) {
3768                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3769                                      ret);
3770                         return ret;
3771                 }
3772         }
3773
3774         return 0;
3775 }
3776
3777 static void
3778 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3779                         bool en_mc, bool en_bc, int vport_id)
3780 {
3781         if (!param)
3782                 return;
3783
3784         memset(param, 0, sizeof(struct hns3_promisc_param));
3785         if (en_uc)
3786                 param->enable = HNS3_PROMISC_EN_UC;
3787         if (en_mc)
3788                 param->enable |= HNS3_PROMISC_EN_MC;
3789         if (en_bc)
3790                 param->enable |= HNS3_PROMISC_EN_BC;
3791         param->vf_id = vport_id;
3792 }
3793
3794 static int
3795 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3796 {
3797         struct hns3_promisc_cfg_cmd *req;
3798         struct hns3_cmd_desc desc;
3799         int ret;
3800
3801         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3802
3803         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3804         req->vf_id = param->vf_id;
3805         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3806             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3807
3808         ret = hns3_cmd_send(hw, &desc, 1);
3809         if (ret)
3810                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3811
3812         return ret;
3813 }
3814
3815 static int
3816 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3817 {
3818         struct hns3_promisc_param param;
3819         bool en_bc_pmc = true;
3820         uint8_t vf_id;
3821
3822         /*
3823          * In current version VF is not supported when PF is driven by DPDK
3824          * driver, just need to configure parameters for PF vport.
3825          */
3826         vf_id = HNS3_PF_FUNC_ID;
3827
3828         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3829         return hns3_cmd_set_promisc_mode(hw, &param);
3830 }
3831
3832 static int
3833 hns3_promisc_init(struct hns3_hw *hw)
3834 {
3835         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3836         struct hns3_pf *pf = &hns->pf;
3837         struct hns3_promisc_param param;
3838         uint16_t func_id;
3839         int ret;
3840
3841         ret = hns3_set_promisc_mode(hw, false, false);
3842         if (ret) {
3843                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3844                 return ret;
3845         }
3846
3847         /*
3848          * In current version VFs are not supported when PF is driven by DPDK
3849          * driver. After PF has been taken over by DPDK, the original VF will
3850          * be invalid. So, there is a possibility of entry residues. It should
3851          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3852          * during init.
3853          */
3854         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3855                 hns3_promisc_param_init(&param, false, false, false, func_id);
3856                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3857                 if (ret) {
3858                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
3859                                         " ret = %d", func_id, ret);
3860                         return ret;
3861                 }
3862         }
3863
3864         return 0;
3865 }
3866
3867 static void
3868 hns3_promisc_uninit(struct hns3_hw *hw)
3869 {
3870         struct hns3_promisc_param param;
3871         uint16_t func_id;
3872         int ret;
3873
3874         func_id = HNS3_PF_FUNC_ID;
3875
3876         /*
3877          * In current version VFs are not supported when PF is driven by
3878          * DPDK driver, and VFs' promisc mode status has been cleared during
3879          * init and their status will not change. So just clear PF's promisc
3880          * mode status during uninit.
3881          */
3882         hns3_promisc_param_init(&param, false, false, false, func_id);
3883         ret = hns3_cmd_set_promisc_mode(hw, &param);
3884         if (ret)
3885                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3886                                 " uninit, ret = %d", ret);
3887 }
3888
3889 static int
3890 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3891 {
3892         bool allmulti = dev->data->all_multicast ? true : false;
3893         struct hns3_adapter *hns = dev->data->dev_private;
3894         struct hns3_hw *hw = &hns->hw;
3895         uint64_t offloads;
3896         int err;
3897         int ret;
3898
3899         rte_spinlock_lock(&hw->lock);
3900         ret = hns3_set_promisc_mode(hw, true, true);
3901         if (ret) {
3902                 rte_spinlock_unlock(&hw->lock);
3903                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3904                          ret);
3905                 return ret;
3906         }
3907
3908         /*
3909          * When promiscuous mode was enabled, disable the vlan filter to let
3910          * all packets coming in in the receiving direction.
3911          */
3912         offloads = dev->data->dev_conf.rxmode.offloads;
3913         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
3914                 ret = hns3_enable_vlan_filter(hns, false);
3915                 if (ret) {
3916                         hns3_err(hw, "failed to enable promiscuous mode due to "
3917                                      "failure to disable vlan filter, ret = %d",
3918                                  ret);
3919                         err = hns3_set_promisc_mode(hw, false, allmulti);
3920                         if (err)
3921                                 hns3_err(hw, "failed to restore promiscuous "
3922                                          "status after disable vlan filter "
3923                                          "failed during enabling promiscuous "
3924                                          "mode, ret = %d", ret);
3925                 }
3926         }
3927
3928         rte_spinlock_unlock(&hw->lock);
3929
3930         return ret;
3931 }
3932
3933 static int
3934 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3935 {
3936         bool allmulti = dev->data->all_multicast ? true : false;
3937         struct hns3_adapter *hns = dev->data->dev_private;
3938         struct hns3_hw *hw = &hns->hw;
3939         uint64_t offloads;
3940         int err;
3941         int ret;
3942
3943         /* If now in all_multicast mode, must remain in all_multicast mode. */
3944         rte_spinlock_lock(&hw->lock);
3945         ret = hns3_set_promisc_mode(hw, false, allmulti);
3946         if (ret) {
3947                 rte_spinlock_unlock(&hw->lock);
3948                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3949                          ret);
3950                 return ret;
3951         }
3952         /* when promiscuous mode was disabled, restore the vlan filter status */
3953         offloads = dev->data->dev_conf.rxmode.offloads;
3954         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
3955                 ret = hns3_enable_vlan_filter(hns, true);
3956                 if (ret) {
3957                         hns3_err(hw, "failed to disable promiscuous mode due to"
3958                                  " failure to restore vlan filter, ret = %d",
3959                                  ret);
3960                         err = hns3_set_promisc_mode(hw, true, true);
3961                         if (err)
3962                                 hns3_err(hw, "failed to restore promiscuous "
3963                                          "status after enabling vlan filter "
3964                                          "failed during disabling promiscuous "
3965                                          "mode, ret = %d", ret);
3966                 }
3967         }
3968         rte_spinlock_unlock(&hw->lock);
3969
3970         return ret;
3971 }
3972
3973 static int
3974 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3975 {
3976         struct hns3_adapter *hns = dev->data->dev_private;
3977         struct hns3_hw *hw = &hns->hw;
3978         int ret;
3979
3980         if (dev->data->promiscuous)
3981                 return 0;
3982
3983         rte_spinlock_lock(&hw->lock);
3984         ret = hns3_set_promisc_mode(hw, false, true);
3985         rte_spinlock_unlock(&hw->lock);
3986         if (ret)
3987                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3988                          ret);
3989
3990         return ret;
3991 }
3992
3993 static int
3994 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3995 {
3996         struct hns3_adapter *hns = dev->data->dev_private;
3997         struct hns3_hw *hw = &hns->hw;
3998         int ret;
3999
4000         /* If now in promiscuous mode, must remain in all_multicast mode. */
4001         if (dev->data->promiscuous)
4002                 return 0;
4003
4004         rte_spinlock_lock(&hw->lock);
4005         ret = hns3_set_promisc_mode(hw, false, false);
4006         rte_spinlock_unlock(&hw->lock);
4007         if (ret)
4008                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4009                          ret);
4010
4011         return ret;
4012 }
4013
4014 static int
4015 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4016 {
4017         struct hns3_hw *hw = &hns->hw;
4018         bool allmulti = hw->data->all_multicast ? true : false;
4019         int ret;
4020
4021         if (hw->data->promiscuous) {
4022                 ret = hns3_set_promisc_mode(hw, true, true);
4023                 if (ret)
4024                         hns3_err(hw, "failed to restore promiscuous mode, "
4025                                  "ret = %d", ret);
4026                 return ret;
4027         }
4028
4029         ret = hns3_set_promisc_mode(hw, false, allmulti);
4030         if (ret)
4031                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4032                          ret);
4033         return ret;
4034 }
4035
4036 static int
4037 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4038 {
4039         struct hns3_sfp_info_cmd *resp;
4040         struct hns3_cmd_desc desc;
4041         int ret;
4042
4043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4044         resp = (struct hns3_sfp_info_cmd *)desc.data;
4045         resp->query_type = HNS3_ACTIVE_QUERY;
4046
4047         ret = hns3_cmd_send(hw, &desc, 1);
4048         if (ret == -EOPNOTSUPP) {
4049                 hns3_warn(hw, "firmware does not support get SFP info,"
4050                           " ret = %d.", ret);
4051                 return ret;
4052         } else if (ret) {
4053                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4054                 return ret;
4055         }
4056
4057         /*
4058          * In some case, the speed of MAC obtained from firmware may be 0, it
4059          * shouldn't be set to mac->speed.
4060          */
4061         if (!rte_le_to_cpu_32(resp->sfp_speed))
4062                 return 0;
4063
4064         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4065         /*
4066          * if resp->supported_speed is 0, it means it's an old version
4067          * firmware, do not update these params.
4068          */
4069         if (resp->supported_speed) {
4070                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4071                 mac_info->supported_speed =
4072                                         rte_le_to_cpu_32(resp->supported_speed);
4073                 mac_info->support_autoneg = resp->autoneg_ability;
4074                 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED
4075                                         : RTE_ETH_LINK_AUTONEG;
4076         } else {
4077                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4078         }
4079
4080         return 0;
4081 }
4082
4083 static uint8_t
4084 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4085 {
4086         if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M))
4087                 duplex = RTE_ETH_LINK_FULL_DUPLEX;
4088
4089         return duplex;
4090 }
4091
4092 static int
4093 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4094 {
4095         struct hns3_mac *mac = &hw->mac;
4096         int ret;
4097
4098         duplex = hns3_check_speed_dup(duplex, speed);
4099         if (mac->link_speed == speed && mac->link_duplex == duplex)
4100                 return 0;
4101
4102         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4103         if (ret)
4104                 return ret;
4105
4106         ret = hns3_port_shaper_update(hw, speed);
4107         if (ret)
4108                 return ret;
4109
4110         mac->link_speed = speed;
4111         mac->link_duplex = duplex;
4112
4113         return 0;
4114 }
4115
4116 static int
4117 hns3_update_fiber_link_info(struct hns3_hw *hw)
4118 {
4119         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4120         struct hns3_mac *mac = &hw->mac;
4121         struct hns3_mac mac_info;
4122         int ret;
4123
4124         /* If firmware do not support get SFP/qSFP speed, return directly */
4125         if (!pf->support_sfp_query)
4126                 return 0;
4127
4128         memset(&mac_info, 0, sizeof(struct hns3_mac));
4129         ret = hns3_get_sfp_info(hw, &mac_info);
4130         if (ret == -EOPNOTSUPP) {
4131                 pf->support_sfp_query = false;
4132                 return ret;
4133         } else if (ret)
4134                 return ret;
4135
4136         /* Do nothing if no SFP */
4137         if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE)
4138                 return 0;
4139
4140         /*
4141          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4142          * to reconfigure the speed of MAC. Otherwise, it indicates
4143          * that the current firmware only supports to obtain the
4144          * speed of the SFP, and the speed of MAC needs to reconfigure.
4145          */
4146         mac->query_type = mac_info.query_type;
4147         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4148                 if (mac_info.link_speed != mac->link_speed) {
4149                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4150                         if (ret)
4151                                 return ret;
4152                 }
4153
4154                 mac->link_speed = mac_info.link_speed;
4155                 mac->supported_speed = mac_info.supported_speed;
4156                 mac->support_autoneg = mac_info.support_autoneg;
4157                 mac->link_autoneg = mac_info.link_autoneg;
4158
4159                 return 0;
4160         }
4161
4162         /* Config full duplex for SFP */
4163         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4164                                       RTE_ETH_LINK_FULL_DUPLEX);
4165 }
4166
4167 static void
4168 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4169 {
4170 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4171
4172         struct hns3_phy_params_bd0_cmd *req;
4173         uint32_t supported;
4174
4175         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4176         mac->link_speed = rte_le_to_cpu_32(req->speed);
4177         mac->link_duplex = hns3_get_bit(req->duplex,
4178                                            HNS3_PHY_DUPLEX_CFG_B);
4179         mac->link_autoneg = hns3_get_bit(req->autoneg,
4180                                            HNS3_PHY_AUTONEG_CFG_B);
4181         mac->advertising = rte_le_to_cpu_32(req->advertising);
4182         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4183         supported = rte_le_to_cpu_32(req->supported);
4184         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4185         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4186 }
4187
4188 static int
4189 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4190 {
4191         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4192         uint16_t i;
4193         int ret;
4194
4195         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4196                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4197                                           true);
4198                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4199         }
4200         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4201
4202         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4203         if (ret) {
4204                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4205                 return ret;
4206         }
4207
4208         hns3_parse_copper_phy_params(desc, mac);
4209
4210         return 0;
4211 }
4212
4213 static int
4214 hns3_update_copper_link_info(struct hns3_hw *hw)
4215 {
4216         struct hns3_mac *mac = &hw->mac;
4217         struct hns3_mac mac_info;
4218         int ret;
4219
4220         memset(&mac_info, 0, sizeof(struct hns3_mac));
4221         ret = hns3_get_copper_phy_params(hw, &mac_info);
4222         if (ret)
4223                 return ret;
4224
4225         if (mac_info.link_speed != mac->link_speed) {
4226                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4227                 if (ret)
4228                         return ret;
4229         }
4230
4231         mac->link_speed = mac_info.link_speed;
4232         mac->link_duplex = mac_info.link_duplex;
4233         mac->link_autoneg = mac_info.link_autoneg;
4234         mac->supported_speed = mac_info.supported_speed;
4235         mac->advertising = mac_info.advertising;
4236         mac->lp_advertising = mac_info.lp_advertising;
4237         mac->support_autoneg = mac_info.support_autoneg;
4238
4239         return 0;
4240 }
4241
4242 static int
4243 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4244 {
4245         struct hns3_adapter *hns = eth_dev->data->dev_private;
4246         struct hns3_hw *hw = &hns->hw;
4247         int ret = 0;
4248
4249         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4250                 ret = hns3_update_copper_link_info(hw);
4251         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4252                 ret = hns3_update_fiber_link_info(hw);
4253
4254         return ret;
4255 }
4256
4257 static int
4258 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4259 {
4260         struct hns3_config_mac_mode_cmd *req;
4261         struct hns3_cmd_desc desc;
4262         uint32_t loop_en = 0;
4263         uint8_t val = 0;
4264         int ret;
4265
4266         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4267
4268         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4269         if (enable)
4270                 val = 1;
4271         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4272         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4273         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4274         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4275         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4276         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4277         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4278         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4279         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4280         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4281
4282         /*
4283          * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4284          * when receiving frames. Otherwise, CRC will be stripped.
4285          */
4286         if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
4287                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4288         else
4289                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4290         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4291         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4292         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4293         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4294
4295         ret = hns3_cmd_send(hw, &desc, 1);
4296         if (ret)
4297                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4298
4299         return ret;
4300 }
4301
4302 static int
4303 hns3_get_mac_link_status(struct hns3_hw *hw)
4304 {
4305         struct hns3_link_status_cmd *req;
4306         struct hns3_cmd_desc desc;
4307         int link_status;
4308         int ret;
4309
4310         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4311         ret = hns3_cmd_send(hw, &desc, 1);
4312         if (ret) {
4313                 hns3_err(hw, "get link status cmd failed %d", ret);
4314                 return RTE_ETH_LINK_DOWN;
4315         }
4316
4317         req = (struct hns3_link_status_cmd *)desc.data;
4318         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4319
4320         return !!link_status;
4321 }
4322
4323 static bool
4324 hns3_update_link_status(struct hns3_hw *hw)
4325 {
4326         int state;
4327
4328         state = hns3_get_mac_link_status(hw);
4329         if (state != hw->mac.link_status) {
4330                 hw->mac.link_status = state;
4331                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4332                 return true;
4333         }
4334
4335         return false;
4336 }
4337
4338 void
4339 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4340 {
4341         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4342         struct rte_eth_link new_link;
4343         int ret;
4344
4345         if (query)
4346                 hns3_update_port_link_info(dev);
4347
4348         memset(&new_link, 0, sizeof(new_link));
4349         hns3_setup_linkstatus(dev, &new_link);
4350
4351         ret = rte_eth_linkstatus_set(dev, &new_link);
4352         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4353                 hns3_start_report_lse(dev);
4354 }
4355
4356 static void
4357 hns3_service_handler(void *param)
4358 {
4359         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4360         struct hns3_adapter *hns = eth_dev->data->dev_private;
4361         struct hns3_hw *hw = &hns->hw;
4362
4363         if (!hns3_is_reset_pending(hns))
4364                 hns3_update_linkstatus_and_event(hw, true);
4365         else
4366                 hns3_warn(hw, "Cancel the query when reset is pending");
4367
4368         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4369 }
4370
4371 static int
4372 hns3_init_hardware(struct hns3_adapter *hns)
4373 {
4374         struct hns3_hw *hw = &hns->hw;
4375         int ret;
4376
4377         ret = hns3_map_tqp(hw);
4378         if (ret) {
4379                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4380                 return ret;
4381         }
4382
4383         ret = hns3_init_umv_space(hw);
4384         if (ret) {
4385                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4386                 return ret;
4387         }
4388
4389         ret = hns3_mac_init(hw);
4390         if (ret) {
4391                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4392                 goto err_mac_init;
4393         }
4394
4395         ret = hns3_init_mgr_tbl(hw);
4396         if (ret) {
4397                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4398                 goto err_mac_init;
4399         }
4400
4401         ret = hns3_promisc_init(hw);
4402         if (ret) {
4403                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4404                              ret);
4405                 goto err_mac_init;
4406         }
4407
4408         ret = hns3_init_vlan_config(hns);
4409         if (ret) {
4410                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4411                 goto err_mac_init;
4412         }
4413
4414         ret = hns3_dcb_init(hw);
4415         if (ret) {
4416                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4417                 goto err_mac_init;
4418         }
4419
4420         ret = hns3_init_fd_config(hns);
4421         if (ret) {
4422                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4423                 goto err_mac_init;
4424         }
4425
4426         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4427         if (ret) {
4428                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4429                 goto err_mac_init;
4430         }
4431
4432         ret = hns3_config_gro(hw, false);
4433         if (ret) {
4434                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4435                 goto err_mac_init;
4436         }
4437
4438         /*
4439          * In the initialization clearing the all hardware mapping relationship
4440          * configurations between queues and interrupt vectors is needed, so
4441          * some error caused by the residual configurations, such as the
4442          * unexpected interrupt, can be avoid.
4443          */
4444         ret = hns3_init_ring_with_vector(hw);
4445         if (ret) {
4446                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4447                 goto err_mac_init;
4448         }
4449
4450         return 0;
4451
4452 err_mac_init:
4453         hns3_uninit_umv_space(hw);
4454         return ret;
4455 }
4456
4457 static int
4458 hns3_clear_hw(struct hns3_hw *hw)
4459 {
4460         struct hns3_cmd_desc desc;
4461         int ret;
4462
4463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4464
4465         ret = hns3_cmd_send(hw, &desc, 1);
4466         if (ret && ret != -EOPNOTSUPP)
4467                 return ret;
4468
4469         return 0;
4470 }
4471
4472 static void
4473 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4474 {
4475         uint32_t val;
4476
4477         /*
4478          * The new firmware support report more hardware error types by
4479          * msix mode. These errors are defined as RAS errors in hardware
4480          * and belong to a different type from the MSI-x errors processed
4481          * by the network driver.
4482          *
4483          * Network driver should open the new error report on initialization.
4484          */
4485         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4486         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4487         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4488 }
4489
4490 static uint32_t
4491 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
4492 {
4493         struct hns3_mac *mac = &hw->mac;
4494
4495         switch (mac->link_speed) {
4496         case RTE_ETH_SPEED_NUM_1G:
4497                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
4498         case RTE_ETH_SPEED_NUM_10G:
4499                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
4500         case RTE_ETH_SPEED_NUM_25G:
4501                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
4502         case RTE_ETH_SPEED_NUM_40G:
4503                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
4504         case RTE_ETH_SPEED_NUM_50G:
4505                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
4506         case RTE_ETH_SPEED_NUM_100G:
4507                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
4508         case RTE_ETH_SPEED_NUM_200G:
4509                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
4510         default:
4511                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
4512                 return 0;
4513         }
4514 }
4515
4516 /*
4517  * Validity of supported_speed for fiber and copper media type can be
4518  * guaranteed by the following policy:
4519  * Copper:
4520  *       Although the initialization of the phy in the firmware may not be
4521  *       completed, the firmware can guarantees that the supported_speed is
4522  *       an valid value.
4523  * Firber:
4524  *       If the version of firmware supports the active query way of the
4525  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
4526  *       through it. If unsupported, use the SFP's speed as the value of the
4527  *       supported_speed.
4528  */
4529 static int
4530 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
4531 {
4532         struct hns3_adapter *hns = eth_dev->data->dev_private;
4533         struct hns3_hw *hw = &hns->hw;
4534         struct hns3_mac *mac = &hw->mac;
4535         int ret;
4536
4537         ret = hns3_update_link_info(eth_dev);
4538         if (ret)
4539                 return ret;
4540
4541         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
4542                 /*
4543                  * Some firmware does not support the report of supported_speed,
4544                  * and only report the effective speed of SFP. In this case, it
4545                  * is necessary to use the SFP's speed as the supported_speed.
4546                  */
4547                 if (mac->supported_speed == 0)
4548                         mac->supported_speed =
4549                                 hns3_set_firber_default_support_speed(hw);
4550         }
4551
4552         return 0;
4553 }
4554
4555 static void
4556 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
4557 {
4558         struct hns3_mac *mac = &hns->hw.mac;
4559
4560         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
4561                 hns->pf.support_fc_autoneg = true;
4562                 return;
4563         }
4564
4565         /*
4566          * Flow control auto-negotiation requires the cooperation of the driver
4567          * and firmware. Currently, the optical port does not support flow
4568          * control auto-negotiation.
4569          */
4570         hns->pf.support_fc_autoneg = false;
4571 }
4572
4573 static int
4574 hns3_init_pf(struct rte_eth_dev *eth_dev)
4575 {
4576         struct rte_device *dev = eth_dev->device;
4577         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4578         struct hns3_adapter *hns = eth_dev->data->dev_private;
4579         struct hns3_hw *hw = &hns->hw;
4580         int ret;
4581
4582         PMD_INIT_FUNC_TRACE();
4583
4584         /* Get hardware io base address from pcie BAR2 IO space */
4585         hw->io_base = pci_dev->mem_resource[2].addr;
4586
4587         /* Firmware command queue initialize */
4588         ret = hns3_cmd_init_queue(hw);
4589         if (ret) {
4590                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4591                 goto err_cmd_init_queue;
4592         }
4593
4594         hns3_clear_all_event_cause(hw);
4595
4596         /* Firmware command initialize */
4597         ret = hns3_cmd_init(hw);
4598         if (ret) {
4599                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4600                 goto err_cmd_init;
4601         }
4602
4603         hns3_tx_push_init(eth_dev);
4604
4605         /*
4606          * To ensure that the hardware environment is clean during
4607          * initialization, the driver actively clear the hardware environment
4608          * during initialization, including PF and corresponding VFs' vlan, mac,
4609          * flow table configurations, etc.
4610          */
4611         ret = hns3_clear_hw(hw);
4612         if (ret) {
4613                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4614                 goto err_cmd_init;
4615         }
4616
4617         /* Hardware statistics of imissed registers cleared. */
4618         ret = hns3_update_imissed_stats(hw, true);
4619         if (ret) {
4620                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4621                 goto err_cmd_init;
4622         }
4623
4624         hns3_config_all_msix_error(hw, true);
4625
4626         ret = rte_intr_callback_register(pci_dev->intr_handle,
4627                                          hns3_interrupt_handler,
4628                                          eth_dev);
4629         if (ret) {
4630                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4631                 goto err_intr_callback_register;
4632         }
4633
4634         ret = hns3_ptp_init(hw);
4635         if (ret)
4636                 goto err_get_config;
4637
4638         /* Enable interrupt */
4639         rte_intr_enable(pci_dev->intr_handle);
4640         hns3_pf_enable_irq0(hw);
4641
4642         /* Get configuration */
4643         ret = hns3_get_configuration(hw);
4644         if (ret) {
4645                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4646                 goto err_get_config;
4647         }
4648
4649         ret = hns3_tqp_stats_init(hw);
4650         if (ret)
4651                 goto err_get_config;
4652
4653         ret = hns3_init_hardware(hns);
4654         if (ret) {
4655                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4656                 goto err_init_hw;
4657         }
4658
4659         /* Initialize flow director filter list & hash */
4660         ret = hns3_fdir_filter_init(hns);
4661         if (ret) {
4662                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4663                 goto err_fdir;
4664         }
4665
4666         hns3_rss_set_default_args(hw);
4667
4668         ret = hns3_enable_hw_error_intr(hns, true);
4669         if (ret) {
4670                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4671                              ret);
4672                 goto err_enable_intr;
4673         }
4674
4675         ret = hns3_get_port_supported_speed(eth_dev);
4676         if (ret) {
4677                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
4678                              "by device, ret = %d.", ret);
4679                 goto err_supported_speed;
4680         }
4681
4682         hns3_get_fc_autoneg_capability(hns);
4683
4684         hns3_tm_conf_init(eth_dev);
4685
4686         return 0;
4687
4688 err_supported_speed:
4689         (void)hns3_enable_hw_error_intr(hns, false);
4690 err_enable_intr:
4691         hns3_fdir_filter_uninit(hns);
4692 err_fdir:
4693         hns3_uninit_umv_space(hw);
4694 err_init_hw:
4695         hns3_tqp_stats_uninit(hw);
4696 err_get_config:
4697         hns3_pf_disable_irq0(hw);
4698         rte_intr_disable(pci_dev->intr_handle);
4699         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
4700                              eth_dev);
4701 err_intr_callback_register:
4702 err_cmd_init:
4703         hns3_cmd_uninit(hw);
4704         hns3_cmd_destroy_queue(hw);
4705 err_cmd_init_queue:
4706         hw->io_base = NULL;
4707
4708         return ret;
4709 }
4710
4711 static void
4712 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4713 {
4714         struct hns3_adapter *hns = eth_dev->data->dev_private;
4715         struct rte_device *dev = eth_dev->device;
4716         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4717         struct hns3_hw *hw = &hns->hw;
4718
4719         PMD_INIT_FUNC_TRACE();
4720
4721         hns3_tm_conf_uninit(eth_dev);
4722         hns3_enable_hw_error_intr(hns, false);
4723         hns3_rss_uninit(hns);
4724         (void)hns3_config_gro(hw, false);
4725         hns3_promisc_uninit(hw);
4726         hns3_flow_uninit(eth_dev);
4727         hns3_fdir_filter_uninit(hns);
4728         hns3_uninit_umv_space(hw);
4729         hns3_tqp_stats_uninit(hw);
4730         hns3_config_mac_tnl_int(hw, false);
4731         hns3_pf_disable_irq0(hw);
4732         rte_intr_disable(pci_dev->intr_handle);
4733         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
4734                              eth_dev);
4735         hns3_config_all_msix_error(hw, false);
4736         hns3_cmd_uninit(hw);
4737         hns3_cmd_destroy_queue(hw);
4738         hw->io_base = NULL;
4739 }
4740
4741 static uint32_t
4742 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
4743 {
4744         uint32_t speed_bit;
4745
4746         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
4747         case RTE_ETH_LINK_SPEED_10M:
4748                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
4749                 break;
4750         case RTE_ETH_LINK_SPEED_10M_HD:
4751                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
4752                 break;
4753         case RTE_ETH_LINK_SPEED_100M:
4754                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
4755                 break;
4756         case RTE_ETH_LINK_SPEED_100M_HD:
4757                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
4758                 break;
4759         case RTE_ETH_LINK_SPEED_1G:
4760                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
4761                 break;
4762         default:
4763                 speed_bit = 0;
4764                 break;
4765         }
4766
4767         return speed_bit;
4768 }
4769
4770 static uint32_t
4771 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
4772 {
4773         uint32_t speed_bit;
4774
4775         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
4776         case RTE_ETH_LINK_SPEED_1G:
4777                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
4778                 break;
4779         case RTE_ETH_LINK_SPEED_10G:
4780                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
4781                 break;
4782         case RTE_ETH_LINK_SPEED_25G:
4783                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
4784                 break;
4785         case RTE_ETH_LINK_SPEED_40G:
4786                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
4787                 break;
4788         case RTE_ETH_LINK_SPEED_50G:
4789                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
4790                 break;
4791         case RTE_ETH_LINK_SPEED_100G:
4792                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
4793                 break;
4794         case RTE_ETH_LINK_SPEED_200G:
4795                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
4796                 break;
4797         default:
4798                 speed_bit = 0;
4799                 break;
4800         }
4801
4802         return speed_bit;
4803 }
4804
4805 static int
4806 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
4807 {
4808         struct hns3_mac *mac = &hw->mac;
4809         uint32_t supported_speed = mac->supported_speed;
4810         uint32_t speed_bit = 0;
4811
4812         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
4813                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
4814         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
4815                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
4816
4817         if (!(speed_bit & supported_speed)) {
4818                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
4819                          link_speeds);
4820                 return -EINVAL;
4821         }
4822
4823         return 0;
4824 }
4825
4826 static uint32_t
4827 hns3_get_link_speed(uint32_t link_speeds)
4828 {
4829         uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
4830
4831         if (link_speeds & RTE_ETH_LINK_SPEED_10M ||
4832             link_speeds & RTE_ETH_LINK_SPEED_10M_HD)
4833                 speed = RTE_ETH_SPEED_NUM_10M;
4834         if (link_speeds & RTE_ETH_LINK_SPEED_100M ||
4835             link_speeds & RTE_ETH_LINK_SPEED_100M_HD)
4836                 speed = RTE_ETH_SPEED_NUM_100M;
4837         if (link_speeds & RTE_ETH_LINK_SPEED_1G)
4838                 speed = RTE_ETH_SPEED_NUM_1G;
4839         if (link_speeds & RTE_ETH_LINK_SPEED_10G)
4840                 speed = RTE_ETH_SPEED_NUM_10G;
4841         if (link_speeds & RTE_ETH_LINK_SPEED_25G)
4842                 speed = RTE_ETH_SPEED_NUM_25G;
4843         if (link_speeds & RTE_ETH_LINK_SPEED_40G)
4844                 speed = RTE_ETH_SPEED_NUM_40G;
4845         if (link_speeds & RTE_ETH_LINK_SPEED_50G)
4846                 speed = RTE_ETH_SPEED_NUM_50G;
4847         if (link_speeds & RTE_ETH_LINK_SPEED_100G)
4848                 speed = RTE_ETH_SPEED_NUM_100G;
4849         if (link_speeds & RTE_ETH_LINK_SPEED_200G)
4850                 speed = RTE_ETH_SPEED_NUM_200G;
4851
4852         return speed;
4853 }
4854
4855 static uint8_t
4856 hns3_get_link_duplex(uint32_t link_speeds)
4857 {
4858         if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||
4859             (link_speeds & RTE_ETH_LINK_SPEED_100M_HD))
4860                 return RTE_ETH_LINK_HALF_DUPLEX;
4861         else
4862                 return RTE_ETH_LINK_FULL_DUPLEX;
4863 }
4864
4865 static int
4866 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
4867                                 struct hns3_set_link_speed_cfg *cfg)
4868 {
4869         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4870         struct hns3_phy_params_bd0_cmd *req;
4871         uint16_t i;
4872
4873         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4874                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4875                                           false);
4876                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4877         }
4878         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
4879         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4880         req->autoneg = cfg->autoneg;
4881
4882         /*
4883          * The full speed capability is used to negotiate when
4884          * auto-negotiation is enabled.
4885          */
4886         if (cfg->autoneg) {
4887                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
4888                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
4889                                     HNS3_PHY_LINK_SPEED_100M_BIT |
4890                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
4891                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
4892         } else {
4893                 req->speed = cfg->speed;
4894                 req->duplex = cfg->duplex;
4895         }
4896
4897         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4898 }
4899
4900 static int
4901 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
4902 {
4903         struct hns3_config_auto_neg_cmd *req;
4904         struct hns3_cmd_desc desc;
4905         uint32_t flag = 0;
4906         int ret;
4907
4908         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
4909
4910         req = (struct hns3_config_auto_neg_cmd *)desc.data;
4911         if (enable)
4912                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
4913         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
4914
4915         ret = hns3_cmd_send(hw, &desc, 1);
4916         if (ret)
4917                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
4918
4919         return ret;
4920 }
4921
4922 static int
4923 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
4924                                struct hns3_set_link_speed_cfg *cfg)
4925 {
4926         int ret;
4927
4928         if (hw->mac.support_autoneg) {
4929                 ret = hns3_set_autoneg(hw, cfg->autoneg);
4930                 if (ret) {
4931                         hns3_err(hw, "failed to configure auto-negotiation.");
4932                         return ret;
4933                 }
4934
4935                 /*
4936                  * To enable auto-negotiation, we only need to open the switch
4937                  * of auto-negotiation, then firmware sets all speed
4938                  * capabilities.
4939                  */
4940                 if (cfg->autoneg)
4941                         return 0;
4942         }
4943
4944         /*
4945          * Some hardware doesn't support auto-negotiation, but users may not
4946          * configure link_speeds (default 0), which means auto-negotiation.
4947          * In this case, a warning message need to be printed, instead of
4948          * an error.
4949          */
4950         if (cfg->autoneg) {
4951                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
4952                 return 0;
4953         }
4954
4955         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
4956 }
4957
4958 static int
4959 hns3_set_port_link_speed(struct hns3_hw *hw,
4960                          struct hns3_set_link_speed_cfg *cfg)
4961 {
4962         int ret;
4963
4964         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
4965 #if defined(RTE_HNS3_ONLY_1630_FPGA)
4966                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4967                 if (pf->is_tmp_phy)
4968                         return 0;
4969 #endif
4970
4971                 ret = hns3_set_copper_port_link_speed(hw, cfg);
4972                 if (ret) {
4973                         hns3_err(hw, "failed to set copper port link speed,"
4974                                  "ret = %d.", ret);
4975                         return ret;
4976                 }
4977         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
4978                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
4979                 if (ret) {
4980                         hns3_err(hw, "failed to set fiber port link speed,"
4981                                  "ret = %d.", ret);
4982                         return ret;
4983                 }
4984         }
4985
4986         return 0;
4987 }
4988
4989 static int
4990 hns3_apply_link_speed(struct hns3_hw *hw)
4991 {
4992         struct rte_eth_conf *conf = &hw->data->dev_conf;
4993         struct hns3_set_link_speed_cfg cfg;
4994
4995         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
4996         cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ?
4997                         RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
4998         if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) {
4999                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5000                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5001         }
5002
5003         return hns3_set_port_link_speed(hw, &cfg);
5004 }
5005
5006 static int
5007 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5008 {
5009         struct hns3_hw *hw = &hns->hw;
5010         bool link_en;
5011         int ret;
5012
5013         ret = hns3_update_queue_map_configure(hns);
5014         if (ret) {
5015                 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5016                          ret);
5017                 return ret;
5018         }
5019
5020         /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5021         ret = hns3_tm_conf_update(hw);
5022         if (ret) {
5023                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5024                 return ret;
5025         }
5026
5027         hns3_enable_rxd_adv_layout(hw);
5028
5029         ret = hns3_init_queues(hns, reset_queue);
5030         if (ret) {
5031                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5032                 return ret;
5033         }
5034
5035         link_en = hw->set_link_down ? false : true;
5036         ret = hns3_cfg_mac_mode(hw, link_en);
5037         if (ret) {
5038                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5039                 goto err_config_mac_mode;
5040         }
5041
5042         ret = hns3_apply_link_speed(hw);
5043         if (ret)
5044                 goto err_set_link_speed;
5045
5046         return 0;
5047
5048 err_set_link_speed:
5049         (void)hns3_cfg_mac_mode(hw, false);
5050
5051 err_config_mac_mode:
5052         hns3_dev_release_mbufs(hns);
5053         /*
5054          * Here is exception handling, hns3_reset_all_tqps will have the
5055          * corresponding error message if it is handled incorrectly, so it is
5056          * not necessary to check hns3_reset_all_tqps return value, here keep
5057          * ret as the error code causing the exception.
5058          */
5059         (void)hns3_reset_all_tqps(hns);
5060         return ret;
5061 }
5062
5063 static void
5064 hns3_restore_filter(struct rte_eth_dev *dev)
5065 {
5066         hns3_restore_rss_filter(dev);
5067 }
5068
5069 static int
5070 hns3_dev_start(struct rte_eth_dev *dev)
5071 {
5072         struct hns3_adapter *hns = dev->data->dev_private;
5073         struct hns3_hw *hw = &hns->hw;
5074         bool old_state = hw->set_link_down;
5075         int ret;
5076
5077         PMD_INIT_FUNC_TRACE();
5078         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5079                 return -EBUSY;
5080
5081         rte_spinlock_lock(&hw->lock);
5082         hw->adapter_state = HNS3_NIC_STARTING;
5083
5084         /*
5085          * If the dev_set_link_down() API has been called, the "set_link_down"
5086          * flag can be cleared by dev_start() API. In addition, the flag should
5087          * also be cleared before calling hns3_do_start() so that MAC can be
5088          * enabled in dev_start stage.
5089          */
5090         hw->set_link_down = false;
5091         ret = hns3_do_start(hns, true);
5092         if (ret)
5093                 goto do_start_fail;
5094
5095         ret = hns3_map_rx_interrupt(dev);
5096         if (ret)
5097                 goto map_rx_inter_err;
5098
5099         /*
5100          * There are three register used to control the status of a TQP
5101          * (contains a pair of Tx queue and Rx queue) in the new version network
5102          * engine. One is used to control the enabling of Tx queue, the other is
5103          * used to control the enabling of Rx queue, and the last is the master
5104          * switch used to control the enabling of the tqp. The Tx register and
5105          * TQP register must be enabled at the same time to enable a Tx queue.
5106          * The same applies to the Rx queue. For the older network engine, this
5107          * function only refresh the enabled flag, and it is used to update the
5108          * status of queue in the dpdk framework.
5109          */
5110         ret = hns3_start_all_txqs(dev);
5111         if (ret)
5112                 goto map_rx_inter_err;
5113
5114         ret = hns3_start_all_rxqs(dev);
5115         if (ret)
5116                 goto start_all_rxqs_fail;
5117
5118         hw->adapter_state = HNS3_NIC_STARTED;
5119         rte_spinlock_unlock(&hw->lock);
5120
5121         hns3_rx_scattered_calc(dev);
5122         hns3_set_rxtx_function(dev);
5123         hns3_mp_req_start_rxtx(dev);
5124
5125         hns3_restore_filter(dev);
5126
5127         /* Enable interrupt of all rx queues before enabling queues */
5128         hns3_dev_all_rx_queue_intr_enable(hw, true);
5129
5130         /*
5131          * After finished the initialization, enable tqps to receive/transmit
5132          * packets and refresh all queue status.
5133          */
5134         hns3_start_tqps(hw);
5135
5136         hns3_tm_dev_start_proc(hw);
5137
5138         if (dev->data->dev_conf.intr_conf.lsc != 0)
5139                 hns3_dev_link_update(dev, 0);
5140         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5141
5142         hns3_info(hw, "hns3 dev start successful!");
5143
5144         return 0;
5145
5146 start_all_rxqs_fail:
5147         hns3_stop_all_txqs(dev);
5148 map_rx_inter_err:
5149         (void)hns3_do_stop(hns);
5150 do_start_fail:
5151         hw->set_link_down = old_state;
5152         hw->adapter_state = HNS3_NIC_CONFIGURED;
5153         rte_spinlock_unlock(&hw->lock);
5154
5155         return ret;
5156 }
5157
5158 static int
5159 hns3_do_stop(struct hns3_adapter *hns)
5160 {
5161         struct hns3_hw *hw = &hns->hw;
5162         int ret;
5163
5164         /*
5165          * The "hns3_do_stop" function will also be called by .stop_service to
5166          * prepare reset. At the time of global or IMP reset, the command cannot
5167          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5168          * accessed during the reset process. So the mbuf can not be released
5169          * during reset and is required to be released after the reset is
5170          * completed.
5171          */
5172         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5173                 hns3_dev_release_mbufs(hns);
5174
5175         ret = hns3_cfg_mac_mode(hw, false);
5176         if (ret)
5177                 return ret;
5178         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5179
5180         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5181                 hns3_configure_all_mac_addr(hns, true);
5182                 ret = hns3_reset_all_tqps(hns);
5183                 if (ret) {
5184                         hns3_err(hw, "failed to reset all queues ret = %d.",
5185                                  ret);
5186                         return ret;
5187                 }
5188         }
5189
5190         return 0;
5191 }
5192
5193 static int
5194 hns3_dev_stop(struct rte_eth_dev *dev)
5195 {
5196         struct hns3_adapter *hns = dev->data->dev_private;
5197         struct hns3_hw *hw = &hns->hw;
5198
5199         PMD_INIT_FUNC_TRACE();
5200         dev->data->dev_started = 0;
5201
5202         hw->adapter_state = HNS3_NIC_STOPPING;
5203         hns3_set_rxtx_function(dev);
5204         rte_wmb();
5205         /* Disable datapath on secondary process. */
5206         hns3_mp_req_stop_rxtx(dev);
5207         /* Prevent crashes when queues are still in use. */
5208         rte_delay_ms(hw->cfg_max_queues);
5209
5210         rte_spinlock_lock(&hw->lock);
5211         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5212                 hns3_tm_dev_stop_proc(hw);
5213                 hns3_config_mac_tnl_int(hw, false);
5214                 hns3_stop_tqps(hw);
5215                 hns3_do_stop(hns);
5216                 hns3_unmap_rx_interrupt(dev);
5217                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5218         }
5219         hns3_rx_scattered_reset(dev);
5220         rte_eal_alarm_cancel(hns3_service_handler, dev);
5221         hns3_stop_report_lse(dev);
5222         rte_spinlock_unlock(&hw->lock);
5223
5224         return 0;
5225 }
5226
5227 static int
5228 hns3_dev_close(struct rte_eth_dev *eth_dev)
5229 {
5230         struct hns3_adapter *hns = eth_dev->data->dev_private;
5231         struct hns3_hw *hw = &hns->hw;
5232         int ret = 0;
5233
5234         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5235                 hns3_mp_uninit(eth_dev);
5236                 return 0;
5237         }
5238
5239         if (hw->adapter_state == HNS3_NIC_STARTED)
5240                 ret = hns3_dev_stop(eth_dev);
5241
5242         hw->adapter_state = HNS3_NIC_CLOSING;
5243         hns3_reset_abort(hns);
5244         hw->adapter_state = HNS3_NIC_CLOSED;
5245
5246         hns3_configure_all_mc_mac_addr(hns, true);
5247         hns3_remove_all_vlan_table(hns);
5248         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5249         hns3_uninit_pf(eth_dev);
5250         hns3_free_all_queues(eth_dev);
5251         rte_free(hw->reset.wait_data);
5252         hns3_mp_uninit(eth_dev);
5253         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5254
5255         return ret;
5256 }
5257
5258 static void
5259 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5260                                    bool *tx_pause)
5261 {
5262         struct hns3_mac *mac = &hw->mac;
5263         uint32_t advertising = mac->advertising;
5264         uint32_t lp_advertising = mac->lp_advertising;
5265         *rx_pause = false;
5266         *tx_pause = false;
5267
5268         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5269                 *rx_pause = true;
5270                 *tx_pause = true;
5271         } else if (advertising & lp_advertising &
5272                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5273                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5274                         *rx_pause = true;
5275                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5276                         *tx_pause = true;
5277         }
5278 }
5279
5280 static enum hns3_fc_mode
5281 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5282 {
5283         enum hns3_fc_mode current_mode;
5284         bool rx_pause = false;
5285         bool tx_pause = false;
5286
5287         switch (hw->mac.media_type) {
5288         case HNS3_MEDIA_TYPE_COPPER:
5289                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5290                 break;
5291
5292         /*
5293          * Flow control auto-negotiation is not supported for fiber and
5294          * backplane media type.
5295          */
5296         case HNS3_MEDIA_TYPE_FIBER:
5297         case HNS3_MEDIA_TYPE_BACKPLANE:
5298                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5299                 current_mode = hw->requested_fc_mode;
5300                 goto out;
5301         default:
5302                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5303                          hw->mac.media_type);
5304                 current_mode = HNS3_FC_NONE;
5305                 goto out;
5306         }
5307
5308         if (rx_pause && tx_pause)
5309                 current_mode = HNS3_FC_FULL;
5310         else if (rx_pause)
5311                 current_mode = HNS3_FC_RX_PAUSE;
5312         else if (tx_pause)
5313                 current_mode = HNS3_FC_TX_PAUSE;
5314         else
5315                 current_mode = HNS3_FC_NONE;
5316
5317 out:
5318         return current_mode;
5319 }
5320
5321 static enum hns3_fc_mode
5322 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
5323 {
5324         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5325         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5326         struct hns3_mac *mac = &hw->mac;
5327
5328         /*
5329          * When the flow control mode is obtained, the device may not complete
5330          * auto-negotiation. It is necessary to wait for link establishment.
5331          */
5332         (void)hns3_dev_link_update(dev, 1);
5333
5334         /*
5335          * If the link auto-negotiation of the nic is disabled, or the flow
5336          * control auto-negotiation is not supported, the forced flow control
5337          * mode is used.
5338          */
5339         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
5340                 return hw->requested_fc_mode;
5341
5342         return hns3_get_autoneg_fc_mode(hw);
5343 }
5344
5345 static int
5346 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5347 {
5348         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5350         enum hns3_fc_mode current_mode;
5351
5352         current_mode = hns3_get_current_fc_mode(dev);
5353         switch (current_mode) {
5354         case HNS3_FC_FULL:
5355                 fc_conf->mode = RTE_ETH_FC_FULL;
5356                 break;
5357         case HNS3_FC_TX_PAUSE:
5358                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
5359                 break;
5360         case HNS3_FC_RX_PAUSE:
5361                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
5362                 break;
5363         case HNS3_FC_NONE:
5364         default:
5365                 fc_conf->mode = RTE_ETH_FC_NONE;
5366                 break;
5367         }
5368
5369         fc_conf->pause_time = pf->pause_time;
5370         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
5371
5372         return 0;
5373 }
5374
5375 static int
5376 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
5377 {
5378         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5379
5380         if (!pf->support_fc_autoneg) {
5381                 if (autoneg != 0) {
5382                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
5383                         return -EOPNOTSUPP;
5384                 }
5385
5386                 /*
5387                  * Flow control auto-negotiation of the NIC is not supported,
5388                  * but other auto-negotiation features may be supported.
5389                  */
5390                 if (autoneg != hw->mac.link_autoneg) {
5391                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
5392                         return -EOPNOTSUPP;
5393                 }
5394
5395                 return 0;
5396         }
5397
5398         /*
5399          * If flow control auto-negotiation of the NIC is supported, all
5400          * auto-negotiation features are supported.
5401          */
5402         if (autoneg != hw->mac.link_autoneg) {
5403                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
5404                 return -EOPNOTSUPP;
5405         }
5406
5407         return 0;
5408 }
5409
5410 static int
5411 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5412 {
5413         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5414         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5415         int ret;
5416
5417         if (fc_conf->high_water || fc_conf->low_water ||
5418             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5419                 hns3_err(hw, "Unsupported flow control settings specified, "
5420                          "high_water(%u), low_water(%u), send_xon(%u) and "
5421                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5422                          fc_conf->high_water, fc_conf->low_water,
5423                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5424                 return -EINVAL;
5425         }
5426
5427         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
5428         if (ret)
5429                 return ret;
5430
5431         if (!fc_conf->pause_time) {
5432                 hns3_err(hw, "Invalid pause time %u setting.",
5433                          fc_conf->pause_time);
5434                 return -EINVAL;
5435         }
5436
5437         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5438             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5439                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5440                          "current_fc_status = %d", hw->current_fc_status);
5441                 return -EOPNOTSUPP;
5442         }
5443
5444         if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
5445                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
5446                 return -EOPNOTSUPP;
5447         }
5448
5449         rte_spinlock_lock(&hw->lock);
5450         ret = hns3_fc_enable(dev, fc_conf);
5451         rte_spinlock_unlock(&hw->lock);
5452
5453         return ret;
5454 }
5455
5456 static int
5457 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5458                             struct rte_eth_pfc_conf *pfc_conf)
5459 {
5460         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5461         int ret;
5462
5463         if (!hns3_dev_get_support(hw, DCB)) {
5464                 hns3_err(hw, "This port does not support dcb configurations.");
5465                 return -EOPNOTSUPP;
5466         }
5467
5468         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5469             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5470                 hns3_err(hw, "Unsupported flow control settings specified, "
5471                          "high_water(%u), low_water(%u), send_xon(%u) and "
5472                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5473                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5474                          pfc_conf->fc.send_xon,
5475                          pfc_conf->fc.mac_ctrl_frame_fwd);
5476                 return -EINVAL;
5477         }
5478         if (pfc_conf->fc.autoneg) {
5479                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5480                 return -EINVAL;
5481         }
5482         if (pfc_conf->fc.pause_time == 0) {
5483                 hns3_err(hw, "Invalid pause time %u setting.",
5484                          pfc_conf->fc.pause_time);
5485                 return -EINVAL;
5486         }
5487
5488         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5489             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5490                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5491                              "current_fc_status = %d", hw->current_fc_status);
5492                 return -EOPNOTSUPP;
5493         }
5494
5495         rte_spinlock_lock(&hw->lock);
5496         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5497         rte_spinlock_unlock(&hw->lock);
5498
5499         return ret;
5500 }
5501
5502 static int
5503 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5504 {
5505         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5506         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5507         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5508         int i;
5509
5510         rte_spinlock_lock(&hw->lock);
5511         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
5512                 dcb_info->nb_tcs = pf->local_max_tc;
5513         else
5514                 dcb_info->nb_tcs = 1;
5515
5516         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5517                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5518         for (i = 0; i < dcb_info->nb_tcs; i++)
5519                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5520
5521         for (i = 0; i < hw->num_tc; i++) {
5522                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5523                 dcb_info->tc_queue.tc_txq[0][i].base =
5524                                                 hw->tc_queue[i].tqp_offset;
5525                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5526                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5527                                                 hw->tc_queue[i].tqp_count;
5528         }
5529         rte_spinlock_unlock(&hw->lock);
5530
5531         return 0;
5532 }
5533
5534 static int
5535 hns3_reinit_dev(struct hns3_adapter *hns)
5536 {
5537         struct hns3_hw *hw = &hns->hw;
5538         int ret;
5539
5540         ret = hns3_cmd_init(hw);
5541         if (ret) {
5542                 hns3_err(hw, "Failed to init cmd: %d", ret);
5543                 return ret;
5544         }
5545
5546         ret = hns3_reset_all_tqps(hns);
5547         if (ret) {
5548                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5549                 return ret;
5550         }
5551
5552         ret = hns3_init_hardware(hns);
5553         if (ret) {
5554                 hns3_err(hw, "Failed to init hardware: %d", ret);
5555                 return ret;
5556         }
5557
5558         ret = hns3_enable_hw_error_intr(hns, true);
5559         if (ret) {
5560                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5561                              ret);
5562                 return ret;
5563         }
5564         hns3_info(hw, "Reset done, driver initialization finished.");
5565
5566         return 0;
5567 }
5568
5569 static bool
5570 is_pf_reset_done(struct hns3_hw *hw)
5571 {
5572         uint32_t val, reg, reg_bit;
5573
5574         switch (hw->reset.level) {
5575         case HNS3_IMP_RESET:
5576                 reg = HNS3_GLOBAL_RESET_REG;
5577                 reg_bit = HNS3_IMP_RESET_BIT;
5578                 break;
5579         case HNS3_GLOBAL_RESET:
5580                 reg = HNS3_GLOBAL_RESET_REG;
5581                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5582                 break;
5583         case HNS3_FUNC_RESET:
5584                 reg = HNS3_FUN_RST_ING;
5585                 reg_bit = HNS3_FUN_RST_ING_B;
5586                 break;
5587         case HNS3_FLR_RESET:
5588         default:
5589                 hns3_err(hw, "Wait for unsupported reset level: %d",
5590                          hw->reset.level);
5591                 return true;
5592         }
5593         val = hns3_read_dev(hw, reg);
5594         if (hns3_get_bit(val, reg_bit))
5595                 return false;
5596         else
5597                 return true;
5598 }
5599
5600 bool
5601 hns3_is_reset_pending(struct hns3_adapter *hns)
5602 {
5603         struct hns3_hw *hw = &hns->hw;
5604         enum hns3_reset_level reset;
5605
5606         hns3_check_event_cause(hns, NULL);
5607         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5608         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
5609             hw->reset.level < reset) {
5610                 hns3_warn(hw, "High level reset %d is pending", reset);
5611                 return true;
5612         }
5613         reset = hns3_get_reset_level(hns, &hw->reset.request);
5614         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
5615             hw->reset.level < reset) {
5616                 hns3_warn(hw, "High level reset %d is request", reset);
5617                 return true;
5618         }
5619         return false;
5620 }
5621
5622 static int
5623 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5624 {
5625         struct hns3_hw *hw = &hns->hw;
5626         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5627         struct timeval tv;
5628
5629         if (wait_data->result == HNS3_WAIT_SUCCESS)
5630                 return 0;
5631         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5632                 hns3_clock_gettime(&tv);
5633                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5634                           tv.tv_sec, tv.tv_usec);
5635                 return -ETIME;
5636         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5637                 return -EAGAIN;
5638
5639         wait_data->hns = hns;
5640         wait_data->check_completion = is_pf_reset_done;
5641         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5642                                 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
5643         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5644         wait_data->count = HNS3_RESET_WAIT_CNT;
5645         wait_data->result = HNS3_WAIT_REQUEST;
5646         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5647         return -EAGAIN;
5648 }
5649
5650 static int
5651 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5652 {
5653         struct hns3_cmd_desc desc;
5654         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5655
5656         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5657         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5658         req->fun_reset_vfid = func_id;
5659
5660         return hns3_cmd_send(hw, &desc, 1);
5661 }
5662
5663 static int
5664 hns3_imp_reset_cmd(struct hns3_hw *hw)
5665 {
5666         struct hns3_cmd_desc desc;
5667
5668         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5669         desc.data[0] = 0xeedd;
5670
5671         return hns3_cmd_send(hw, &desc, 1);
5672 }
5673
5674 static void
5675 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5676 {
5677         struct hns3_hw *hw = &hns->hw;
5678         struct timeval tv;
5679         uint32_t val;
5680
5681         hns3_clock_gettime(&tv);
5682         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5683             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5684                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5685                           tv.tv_sec, tv.tv_usec);
5686                 return;
5687         }
5688
5689         switch (reset_level) {
5690         case HNS3_IMP_RESET:
5691                 hns3_imp_reset_cmd(hw);
5692                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5693                           tv.tv_sec, tv.tv_usec);
5694                 break;
5695         case HNS3_GLOBAL_RESET:
5696                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5697                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5698                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5699                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5700                           tv.tv_sec, tv.tv_usec);
5701                 break;
5702         case HNS3_FUNC_RESET:
5703                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5704                           tv.tv_sec, tv.tv_usec);
5705                 /* schedule again to check later */
5706                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5707                 hns3_schedule_reset(hns);
5708                 break;
5709         default:
5710                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5711                 return;
5712         }
5713         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5714 }
5715
5716 static enum hns3_reset_level
5717 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5718 {
5719         struct hns3_hw *hw = &hns->hw;
5720         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5721
5722         /* Return the highest priority reset level amongst all */
5723         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5724                 reset_level = HNS3_IMP_RESET;
5725         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5726                 reset_level = HNS3_GLOBAL_RESET;
5727         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5728                 reset_level = HNS3_FUNC_RESET;
5729         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5730                 reset_level = HNS3_FLR_RESET;
5731
5732         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5733                 return HNS3_NONE_RESET;
5734
5735         return reset_level;
5736 }
5737
5738 static void
5739 hns3_record_imp_error(struct hns3_adapter *hns)
5740 {
5741         struct hns3_hw *hw = &hns->hw;
5742         uint32_t reg_val;
5743
5744         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5745         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5746                 hns3_warn(hw, "Detected IMP RD poison!");
5747                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5748                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5749         }
5750
5751         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5752                 hns3_warn(hw, "Detected IMP CMDQ error!");
5753                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5754                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5755         }
5756 }
5757
5758 static int
5759 hns3_prepare_reset(struct hns3_adapter *hns)
5760 {
5761         struct hns3_hw *hw = &hns->hw;
5762         uint32_t reg_val;
5763         int ret;
5764
5765         switch (hw->reset.level) {
5766         case HNS3_FUNC_RESET:
5767                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5768                 if (ret)
5769                         return ret;
5770
5771                 /*
5772                  * After performaning pf reset, it is not necessary to do the
5773                  * mailbox handling or send any command to firmware, because
5774                  * any mailbox handling or command to firmware is only valid
5775                  * after hns3_cmd_init is called.
5776                  */
5777                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5778                 hw->reset.stats.request_cnt++;
5779                 break;
5780         case HNS3_IMP_RESET:
5781                 hns3_record_imp_error(hns);
5782                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5783                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5784                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5785                 break;
5786         default:
5787                 break;
5788         }
5789         return 0;
5790 }
5791
5792 static int
5793 hns3_set_rst_done(struct hns3_hw *hw)
5794 {
5795         struct hns3_pf_rst_done_cmd *req;
5796         struct hns3_cmd_desc desc;
5797
5798         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5799         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5800         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5801         return hns3_cmd_send(hw, &desc, 1);
5802 }
5803
5804 static int
5805 hns3_stop_service(struct hns3_adapter *hns)
5806 {
5807         struct hns3_hw *hw = &hns->hw;
5808         struct rte_eth_dev *eth_dev;
5809
5810         eth_dev = &rte_eth_devices[hw->data->port_id];
5811         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5812         if (hw->adapter_state == HNS3_NIC_STARTED) {
5813                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5814                 hns3_update_linkstatus_and_event(hw, false);
5815         }
5816
5817         hns3_set_rxtx_function(eth_dev);
5818         rte_wmb();
5819         /* Disable datapath on secondary process. */
5820         hns3_mp_req_stop_rxtx(eth_dev);
5821         rte_delay_ms(hw->cfg_max_queues);
5822
5823         rte_spinlock_lock(&hw->lock);
5824         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5825             hw->adapter_state == HNS3_NIC_STOPPING) {
5826                 hns3_enable_all_queues(hw, false);
5827                 hns3_do_stop(hns);
5828                 hw->reset.mbuf_deferred_free = true;
5829         } else
5830                 hw->reset.mbuf_deferred_free = false;
5831
5832         /*
5833          * It is cumbersome for hardware to pick-and-choose entries for deletion
5834          * from table space. Hence, for function reset software intervention is
5835          * required to delete the entries
5836          */
5837         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5838                 hns3_configure_all_mc_mac_addr(hns, true);
5839         rte_spinlock_unlock(&hw->lock);
5840
5841         return 0;
5842 }
5843
5844 static int
5845 hns3_start_service(struct hns3_adapter *hns)
5846 {
5847         struct hns3_hw *hw = &hns->hw;
5848         struct rte_eth_dev *eth_dev;
5849
5850         if (hw->reset.level == HNS3_IMP_RESET ||
5851             hw->reset.level == HNS3_GLOBAL_RESET)
5852                 hns3_set_rst_done(hw);
5853         eth_dev = &rte_eth_devices[hw->data->port_id];
5854         hns3_set_rxtx_function(eth_dev);
5855         hns3_mp_req_start_rxtx(eth_dev);
5856         if (hw->adapter_state == HNS3_NIC_STARTED) {
5857                 /*
5858                  * This API parent function already hold the hns3_hw.lock, the
5859                  * hns3_service_handler may report lse, in bonding application
5860                  * it will call driver's ops which may acquire the hns3_hw.lock
5861                  * again, thus lead to deadlock.
5862                  * We defer calls hns3_service_handler to avoid the deadlock.
5863                  */
5864                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5865                                   hns3_service_handler, eth_dev);
5866
5867                 /* Enable interrupt of all rx queues before enabling queues */
5868                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5869                 /*
5870                  * Enable state of each rxq and txq will be recovered after
5871                  * reset, so we need to restore them before enable all tqps;
5872                  */
5873                 hns3_restore_tqp_enable_state(hw);
5874                 /*
5875                  * When finished the initialization, enable queues to receive
5876                  * and transmit packets.
5877                  */
5878                 hns3_enable_all_queues(hw, true);
5879         }
5880
5881         return 0;
5882 }
5883
5884 static int
5885 hns3_restore_conf(struct hns3_adapter *hns)
5886 {
5887         struct hns3_hw *hw = &hns->hw;
5888         int ret;
5889
5890         ret = hns3_configure_all_mac_addr(hns, false);
5891         if (ret)
5892                 return ret;
5893
5894         ret = hns3_configure_all_mc_mac_addr(hns, false);
5895         if (ret)
5896                 goto err_mc_mac;
5897
5898         ret = hns3_dev_promisc_restore(hns);
5899         if (ret)
5900                 goto err_promisc;
5901
5902         ret = hns3_restore_vlan_table(hns);
5903         if (ret)
5904                 goto err_promisc;
5905
5906         ret = hns3_restore_vlan_conf(hns);
5907         if (ret)
5908                 goto err_promisc;
5909
5910         ret = hns3_restore_all_fdir_filter(hns);
5911         if (ret)
5912                 goto err_promisc;
5913
5914         ret = hns3_restore_ptp(hns);
5915         if (ret)
5916                 goto err_promisc;
5917
5918         ret = hns3_restore_rx_interrupt(hw);
5919         if (ret)
5920                 goto err_promisc;
5921
5922         ret = hns3_restore_gro_conf(hw);
5923         if (ret)
5924                 goto err_promisc;
5925
5926         ret = hns3_restore_fec(hw);
5927         if (ret)
5928                 goto err_promisc;
5929
5930         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5931                 ret = hns3_do_start(hns, false);
5932                 if (ret)
5933                         goto err_promisc;
5934                 hns3_info(hw, "hns3 dev restart successful!");
5935         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5936                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5937         return 0;
5938
5939 err_promisc:
5940         hns3_configure_all_mc_mac_addr(hns, true);
5941 err_mc_mac:
5942         hns3_configure_all_mac_addr(hns, true);
5943         return ret;
5944 }
5945
5946 static void
5947 hns3_reset_service(void *param)
5948 {
5949         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5950         struct hns3_hw *hw = &hns->hw;
5951         enum hns3_reset_level reset_level;
5952         struct timeval tv_delta;
5953         struct timeval tv_start;
5954         struct timeval tv;
5955         uint64_t msec;
5956         int ret;
5957
5958         /*
5959          * The interrupt is not triggered within the delay time.
5960          * The interrupt may have been lost. It is necessary to handle
5961          * the interrupt to recover from the error.
5962          */
5963         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
5964                             SCHEDULE_DEFERRED) {
5965                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
5966                                   __ATOMIC_RELAXED);
5967                 hns3_err(hw, "Handling interrupts in delayed tasks");
5968                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5969                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5970                 if (reset_level == HNS3_NONE_RESET) {
5971                         hns3_err(hw, "No reset level is set, try IMP reset");
5972                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5973                 }
5974         }
5975         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
5976
5977         /*
5978          * Check if there is any ongoing reset in the hardware. This status can
5979          * be checked from reset_pending. If there is then, we need to wait for
5980          * hardware to complete reset.
5981          *    a. If we are able to figure out in reasonable time that hardware
5982          *       has fully resetted then, we can proceed with driver, client
5983          *       reset.
5984          *    b. else, we can come back later to check this status so re-sched
5985          *       now.
5986          */
5987         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5988         if (reset_level != HNS3_NONE_RESET) {
5989                 hns3_clock_gettime(&tv_start);
5990                 ret = hns3_reset_process(hns, reset_level);
5991                 hns3_clock_gettime(&tv);
5992                 timersub(&tv, &tv_start, &tv_delta);
5993                 msec = hns3_clock_calctime_ms(&tv_delta);
5994                 if (msec > HNS3_RESET_PROCESS_MS)
5995                         hns3_err(hw, "%d handle long time delta %" PRIu64
5996                                      " ms time=%ld.%.6ld",
5997                                  hw->reset.level, msec,
5998                                  tv.tv_sec, tv.tv_usec);
5999                 if (ret == -EAGAIN)
6000                         return;
6001         }
6002
6003         /* Check if we got any *new* reset requests to be honored */
6004         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6005         if (reset_level != HNS3_NONE_RESET)
6006                 hns3_msix_process(hns, reset_level);
6007 }
6008
6009 static unsigned int
6010 hns3_get_speed_capa_num(uint16_t device_id)
6011 {
6012         unsigned int num;
6013
6014         switch (device_id) {
6015         case HNS3_DEV_ID_25GE:
6016         case HNS3_DEV_ID_25GE_RDMA:
6017                 num = 2;
6018                 break;
6019         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6020         case HNS3_DEV_ID_200G_RDMA:
6021                 num = 1;
6022                 break;
6023         default:
6024                 num = 0;
6025                 break;
6026         }
6027
6028         return num;
6029 }
6030
6031 static int
6032 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6033                         uint16_t device_id)
6034 {
6035         switch (device_id) {
6036         case HNS3_DEV_ID_25GE:
6037         /* fallthrough */
6038         case HNS3_DEV_ID_25GE_RDMA:
6039                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6040                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6041
6042                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6043                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6044                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6045                 break;
6046         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6047                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6048                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6049                 break;
6050         case HNS3_DEV_ID_200G_RDMA:
6051                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6052                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6053                 break;
6054         default:
6055                 return -ENOTSUP;
6056         }
6057
6058         return 0;
6059 }
6060
6061 static int
6062 hns3_fec_get_capability(struct rte_eth_dev *dev,
6063                         struct rte_eth_fec_capa *speed_fec_capa,
6064                         unsigned int num)
6065 {
6066         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6067         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6068         uint16_t device_id = pci_dev->id.device_id;
6069         unsigned int capa_num;
6070         int ret;
6071
6072         capa_num = hns3_get_speed_capa_num(device_id);
6073         if (capa_num == 0) {
6074                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6075                          device_id);
6076                 return -ENOTSUP;
6077         }
6078
6079         if (speed_fec_capa == NULL || num < capa_num)
6080                 return capa_num;
6081
6082         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6083         if (ret)
6084                 return -ENOTSUP;
6085
6086         return capa_num;
6087 }
6088
6089 static int
6090 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6091 {
6092         struct hns3_config_fec_cmd *req;
6093         struct hns3_cmd_desc desc;
6094         int ret;
6095
6096         /*
6097          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6098          * in device of link speed
6099          * below 10 Gbps.
6100          */
6101         if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) {
6102                 *state = 0;
6103                 return 0;
6104         }
6105
6106         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6107         req = (struct hns3_config_fec_cmd *)desc.data;
6108         ret = hns3_cmd_send(hw, &desc, 1);
6109         if (ret) {
6110                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6111                          ret);
6112                 return ret;
6113         }
6114
6115         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6116         return 0;
6117 }
6118
6119 static int
6120 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6121 {
6122         struct hns3_sfp_info_cmd *resp;
6123         uint32_t tmp_fec_capa;
6124         uint8_t auto_state;
6125         struct hns3_cmd_desc desc;
6126         int ret;
6127
6128         /*
6129          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6130          * configured FEC mode is returned.
6131          * If link is up, current FEC mode is returned.
6132          */
6133         if (hw->mac.link_status == RTE_ETH_LINK_DOWN) {
6134                 ret = get_current_fec_auto_state(hw, &auto_state);
6135                 if (ret)
6136                         return ret;
6137
6138                 if (auto_state == 0x1) {
6139                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6140                         return 0;
6141                 }
6142         }
6143
6144         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6145         resp = (struct hns3_sfp_info_cmd *)desc.data;
6146         resp->query_type = HNS3_ACTIVE_QUERY;
6147
6148         ret = hns3_cmd_send(hw, &desc, 1);
6149         if (ret == -EOPNOTSUPP) {
6150                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6151                 return ret;
6152         } else if (ret) {
6153                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6154                 return ret;
6155         }
6156
6157         /*
6158          * FEC mode order defined in hns3 hardware is inconsistent with
6159          * that defined in the ethdev library. So the sequence needs
6160          * to be converted.
6161          */
6162         switch (resp->active_fec) {
6163         case HNS3_HW_FEC_MODE_NOFEC:
6164                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6165                 break;
6166         case HNS3_HW_FEC_MODE_BASER:
6167                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6168                 break;
6169         case HNS3_HW_FEC_MODE_RS:
6170                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6171                 break;
6172         default:
6173                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6174                 break;
6175         }
6176
6177         *fec_capa = tmp_fec_capa;
6178         return 0;
6179 }
6180
6181 static int
6182 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6183 {
6184         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6185
6186         return hns3_fec_get_internal(hw, fec_capa);
6187 }
6188
6189 static int
6190 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6191 {
6192         struct hns3_config_fec_cmd *req;
6193         struct hns3_cmd_desc desc;
6194         int ret;
6195
6196         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6197
6198         req = (struct hns3_config_fec_cmd *)desc.data;
6199         switch (mode) {
6200         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6201                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6202                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6203                 break;
6204         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6205                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6206                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6207                 break;
6208         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6209                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6210                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6211                 break;
6212         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6213                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6214                 break;
6215         default:
6216                 return 0;
6217         }
6218         ret = hns3_cmd_send(hw, &desc, 1);
6219         if (ret)
6220                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6221
6222         return ret;
6223 }
6224
6225 static uint32_t
6226 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6227 {
6228         struct hns3_mac *mac = &hw->mac;
6229         uint32_t cur_capa;
6230
6231         switch (mac->link_speed) {
6232         case RTE_ETH_SPEED_NUM_10G:
6233                 cur_capa = fec_capa[1].capa;
6234                 break;
6235         case RTE_ETH_SPEED_NUM_25G:
6236         case RTE_ETH_SPEED_NUM_100G:
6237         case RTE_ETH_SPEED_NUM_200G:
6238                 cur_capa = fec_capa[0].capa;
6239                 break;
6240         default:
6241                 cur_capa = 0;
6242                 break;
6243         }
6244
6245         return cur_capa;
6246 }
6247
6248 static bool
6249 is_fec_mode_one_bit_set(uint32_t mode)
6250 {
6251         int cnt = 0;
6252         uint8_t i;
6253
6254         for (i = 0; i < sizeof(mode); i++)
6255                 if (mode >> i & 0x1)
6256                         cnt++;
6257
6258         return cnt == 1 ? true : false;
6259 }
6260
6261 static int
6262 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6263 {
6264 #define FEC_CAPA_NUM 2
6265         struct hns3_adapter *hns = dev->data->dev_private;
6266         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6267         struct hns3_pf *pf = &hns->pf;
6268         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6269         uint32_t cur_capa;
6270         uint32_t num = FEC_CAPA_NUM;
6271         int ret;
6272
6273         ret = hns3_fec_get_capability(dev, fec_capa, num);
6274         if (ret < 0)
6275                 return ret;
6276
6277         /* HNS3 PMD only support one bit set mode, e.g. 0x1, 0x4 */
6278         if (!is_fec_mode_one_bit_set(mode)) {
6279                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6280                              "FEC mode should be only one bit set", mode);
6281                 return -EINVAL;
6282         }
6283
6284         /*
6285          * Check whether the configured mode is within the FEC capability.
6286          * If not, the configured mode will not be supported.
6287          */
6288         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6289         if (!(cur_capa & mode)) {
6290                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6291                 return -EINVAL;
6292         }
6293
6294         rte_spinlock_lock(&hw->lock);
6295         ret = hns3_set_fec_hw(hw, mode);
6296         if (ret) {
6297                 rte_spinlock_unlock(&hw->lock);
6298                 return ret;
6299         }
6300
6301         pf->fec_mode = mode;
6302         rte_spinlock_unlock(&hw->lock);
6303
6304         return 0;
6305 }
6306
6307 static int
6308 hns3_restore_fec(struct hns3_hw *hw)
6309 {
6310         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6311         struct hns3_pf *pf = &hns->pf;
6312         uint32_t mode = pf->fec_mode;
6313         int ret;
6314
6315         ret = hns3_set_fec_hw(hw, mode);
6316         if (ret)
6317                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6318                          mode, ret);
6319
6320         return ret;
6321 }
6322
6323 static int
6324 hns3_query_dev_fec_info(struct hns3_hw *hw)
6325 {
6326         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6327         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6328         int ret;
6329
6330         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6331         if (ret)
6332                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6333
6334         return ret;
6335 }
6336
6337 static bool
6338 hns3_optical_module_existed(struct hns3_hw *hw)
6339 {
6340         struct hns3_cmd_desc desc;
6341         bool existed;
6342         int ret;
6343
6344         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6345         ret = hns3_cmd_send(hw, &desc, 1);
6346         if (ret) {
6347                 hns3_err(hw,
6348                          "fail to get optical module exist state, ret = %d.\n",
6349                          ret);
6350                 return false;
6351         }
6352         existed = !!desc.data[0];
6353
6354         return existed;
6355 }
6356
6357 static int
6358 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6359                                 uint32_t len, uint8_t *data)
6360 {
6361 #define HNS3_SFP_INFO_CMD_NUM 6
6362 #define HNS3_SFP_INFO_MAX_LEN \
6363         (HNS3_SFP_INFO_BD0_LEN + \
6364         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6365         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6366         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6367         uint16_t read_len;
6368         uint16_t copy_len;
6369         int ret;
6370         int i;
6371
6372         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6373                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6374                                           true);
6375                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6376                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6377         }
6378
6379         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6380         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6381         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6382         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6383
6384         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6385         if (ret) {
6386                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6387                                 ret);
6388                 return ret;
6389         }
6390
6391         /* The data format in BD0 is different with the others. */
6392         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6393         memcpy(data, sfp_info_bd0->data, copy_len);
6394         read_len = copy_len;
6395
6396         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6397                 if (read_len >= len)
6398                         break;
6399
6400                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6401                 memcpy(data + read_len, desc[i].data, copy_len);
6402                 read_len += copy_len;
6403         }
6404
6405         return (int)read_len;
6406 }
6407
6408 static int
6409 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6410                        struct rte_dev_eeprom_info *info)
6411 {
6412         struct hns3_adapter *hns = dev->data->dev_private;
6413         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6414         uint32_t offset = info->offset;
6415         uint32_t len = info->length;
6416         uint8_t *data = info->data;
6417         uint32_t read_len = 0;
6418
6419         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6420                 return -ENOTSUP;
6421
6422         if (!hns3_optical_module_existed(hw)) {
6423                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6424                 return -EIO;
6425         }
6426
6427         while (read_len < len) {
6428                 int ret;
6429                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6430                                                   len - read_len,
6431                                                   data + read_len);
6432                 if (ret < 0)
6433                         return -EIO;
6434                 read_len += ret;
6435         }
6436
6437         return 0;
6438 }
6439
6440 static int
6441 hns3_get_module_info(struct rte_eth_dev *dev,
6442                      struct rte_eth_dev_module_info *modinfo)
6443 {
6444 #define HNS3_SFF8024_ID_SFP             0x03
6445 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6446 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6447 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6448 #define HNS3_SFF_8636_V1_3              0x03
6449         struct hns3_adapter *hns = dev->data->dev_private;
6450         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6451         struct rte_dev_eeprom_info info;
6452         struct hns3_sfp_type sfp_type;
6453         int ret;
6454
6455         memset(&sfp_type, 0, sizeof(sfp_type));
6456         memset(&info, 0, sizeof(info));
6457         info.data = (uint8_t *)&sfp_type;
6458         info.length = sizeof(sfp_type);
6459         ret = hns3_get_module_eeprom(dev, &info);
6460         if (ret)
6461                 return ret;
6462
6463         switch (sfp_type.type) {
6464         case HNS3_SFF8024_ID_SFP:
6465                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6466                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6467                 break;
6468         case HNS3_SFF8024_ID_QSFP_8438:
6469                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6470                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6471                 break;
6472         case HNS3_SFF8024_ID_QSFP_8436_8636:
6473                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6474                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6475                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6476                 } else {
6477                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6478                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6479                 }
6480                 break;
6481         case HNS3_SFF8024_ID_QSFP28_8636:
6482                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6483                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6484                 break;
6485         default:
6486                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6487                          sfp_type.type, sfp_type.ext_type);
6488                 return -EINVAL;
6489         }
6490
6491         return 0;
6492 }
6493
6494 static const struct eth_dev_ops hns3_eth_dev_ops = {
6495         .dev_configure      = hns3_dev_configure,
6496         .dev_start          = hns3_dev_start,
6497         .dev_stop           = hns3_dev_stop,
6498         .dev_close          = hns3_dev_close,
6499         .promiscuous_enable = hns3_dev_promiscuous_enable,
6500         .promiscuous_disable = hns3_dev_promiscuous_disable,
6501         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6502         .allmulticast_disable = hns3_dev_allmulticast_disable,
6503         .mtu_set            = hns3_dev_mtu_set,
6504         .stats_get          = hns3_stats_get,
6505         .stats_reset        = hns3_stats_reset,
6506         .xstats_get         = hns3_dev_xstats_get,
6507         .xstats_get_names   = hns3_dev_xstats_get_names,
6508         .xstats_reset       = hns3_dev_xstats_reset,
6509         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6510         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6511         .dev_infos_get          = hns3_dev_infos_get,
6512         .fw_version_get         = hns3_fw_version_get,
6513         .rx_queue_setup         = hns3_rx_queue_setup,
6514         .tx_queue_setup         = hns3_tx_queue_setup,
6515         .rx_queue_release       = hns3_dev_rx_queue_release,
6516         .tx_queue_release       = hns3_dev_tx_queue_release,
6517         .rx_queue_start         = hns3_dev_rx_queue_start,
6518         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6519         .tx_queue_start         = hns3_dev_tx_queue_start,
6520         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6521         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6522         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6523         .rxq_info_get           = hns3_rxq_info_get,
6524         .txq_info_get           = hns3_txq_info_get,
6525         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6526         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6527         .flow_ctrl_get          = hns3_flow_ctrl_get,
6528         .flow_ctrl_set          = hns3_flow_ctrl_set,
6529         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6530         .mac_addr_add           = hns3_add_mac_addr,
6531         .mac_addr_remove        = hns3_remove_mac_addr,
6532         .mac_addr_set           = hns3_set_default_mac_addr,
6533         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6534         .link_update            = hns3_dev_link_update,
6535         .dev_set_link_up        = hns3_dev_set_link_up,
6536         .dev_set_link_down      = hns3_dev_set_link_down,
6537         .rss_hash_update        = hns3_dev_rss_hash_update,
6538         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6539         .reta_update            = hns3_dev_rss_reta_update,
6540         .reta_query             = hns3_dev_rss_reta_query,
6541         .flow_ops_get           = hns3_dev_flow_ops_get,
6542         .vlan_filter_set        = hns3_vlan_filter_set,
6543         .vlan_tpid_set          = hns3_vlan_tpid_set,
6544         .vlan_offload_set       = hns3_vlan_offload_set,
6545         .vlan_pvid_set          = hns3_vlan_pvid_set,
6546         .get_reg                = hns3_get_regs,
6547         .get_module_info        = hns3_get_module_info,
6548         .get_module_eeprom      = hns3_get_module_eeprom,
6549         .get_dcb_info           = hns3_get_dcb_info,
6550         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6551         .fec_get_capability     = hns3_fec_get_capability,
6552         .fec_get                = hns3_fec_get,
6553         .fec_set                = hns3_fec_set,
6554         .tm_ops_get             = hns3_tm_ops_get,
6555         .tx_done_cleanup        = hns3_tx_done_cleanup,
6556         .timesync_enable            = hns3_timesync_enable,
6557         .timesync_disable           = hns3_timesync_disable,
6558         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6559         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6560         .timesync_adjust_time       = hns3_timesync_adjust_time,
6561         .timesync_read_time         = hns3_timesync_read_time,
6562         .timesync_write_time        = hns3_timesync_write_time,
6563 };
6564
6565 static const struct hns3_reset_ops hns3_reset_ops = {
6566         .reset_service       = hns3_reset_service,
6567         .stop_service        = hns3_stop_service,
6568         .prepare_reset       = hns3_prepare_reset,
6569         .wait_hardware_ready = hns3_wait_hardware_ready,
6570         .reinit_dev          = hns3_reinit_dev,
6571         .restore_conf        = hns3_restore_conf,
6572         .start_service       = hns3_start_service,
6573 };
6574
6575 static void
6576 hns3_init_hw_ops(struct hns3_hw *hw)
6577 {
6578         hw->ops.add_mc_mac_addr = hns3_add_mc_mac_addr;
6579         hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr;
6580         hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr;
6581         hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr;
6582         hw->ops.bind_ring_with_vector = hns3_bind_ring_with_vector;
6583 }
6584
6585 static int
6586 hns3_dev_init(struct rte_eth_dev *eth_dev)
6587 {
6588         struct hns3_adapter *hns = eth_dev->data->dev_private;
6589         struct hns3_hw *hw = &hns->hw;
6590         int ret;
6591
6592         PMD_INIT_FUNC_TRACE();
6593
6594         hns3_flow_init(eth_dev);
6595
6596         hns3_set_rxtx_function(eth_dev);
6597         eth_dev->dev_ops = &hns3_eth_dev_ops;
6598         eth_dev->rx_queue_count = hns3_rx_queue_count;
6599         ret = hns3_mp_init(eth_dev);
6600         if (ret)
6601                 goto err_mp_init;
6602
6603         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6604                 hns3_tx_push_init(eth_dev);
6605                 return 0;
6606         }
6607
6608         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6609         hns->is_vf = false;
6610         hw->data = eth_dev->data;
6611         hns3_parse_devargs(eth_dev);
6612
6613         /*
6614          * Set default max packet size according to the mtu
6615          * default vale in DPDK frame.
6616          */
6617         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6618
6619         ret = hns3_reset_init(hw);
6620         if (ret)
6621                 goto err_init_reset;
6622         hw->reset.ops = &hns3_reset_ops;
6623
6624         hns3_init_hw_ops(hw);
6625         ret = hns3_init_pf(eth_dev);
6626         if (ret) {
6627                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6628                 goto err_init_pf;
6629         }
6630
6631         ret = hns3_init_mac_addrs(eth_dev);
6632         if (ret != 0)
6633                 goto err_init_mac_addrs;
6634
6635         hw->adapter_state = HNS3_NIC_INITIALIZED;
6636
6637         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6638                             SCHEDULE_PENDING) {
6639                 hns3_err(hw, "Reschedule reset service after dev_init");
6640                 hns3_schedule_reset(hns);
6641         } else {
6642                 /* IMP will wait ready flag before reset */
6643                 hns3_notify_reset_ready(hw, false);
6644         }
6645
6646         hns3_info(hw, "hns3 dev initialization successful!");
6647         return 0;
6648
6649 err_init_mac_addrs:
6650         hns3_uninit_pf(eth_dev);
6651
6652 err_init_pf:
6653         rte_free(hw->reset.wait_data);
6654
6655 err_init_reset:
6656         hns3_mp_uninit(eth_dev);
6657
6658 err_mp_init:
6659         eth_dev->dev_ops = NULL;
6660         eth_dev->rx_pkt_burst = NULL;
6661         eth_dev->rx_descriptor_status = NULL;
6662         eth_dev->tx_pkt_burst = NULL;
6663         eth_dev->tx_pkt_prepare = NULL;
6664         eth_dev->tx_descriptor_status = NULL;
6665         return ret;
6666 }
6667
6668 static int
6669 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6670 {
6671         struct hns3_adapter *hns = eth_dev->data->dev_private;
6672         struct hns3_hw *hw = &hns->hw;
6673
6674         PMD_INIT_FUNC_TRACE();
6675
6676         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6677                 hns3_mp_uninit(eth_dev);
6678                 return 0;
6679         }
6680
6681         if (hw->adapter_state < HNS3_NIC_CLOSING)
6682                 hns3_dev_close(eth_dev);
6683
6684         hw->adapter_state = HNS3_NIC_REMOVED;
6685         return 0;
6686 }
6687
6688 static int
6689 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6690                    struct rte_pci_device *pci_dev)
6691 {
6692         return rte_eth_dev_pci_generic_probe(pci_dev,
6693                                              sizeof(struct hns3_adapter),
6694                                              hns3_dev_init);
6695 }
6696
6697 static int
6698 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6699 {
6700         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6701 }
6702
6703 static const struct rte_pci_id pci_id_hns3_map[] = {
6704         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6705         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6706         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6707         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6708         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6709         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6710         { .vendor_id = 0, }, /* sentinel */
6711 };
6712
6713 static struct rte_pci_driver rte_hns3_pmd = {
6714         .id_table = pci_id_hns3_map,
6715         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
6716         .probe = eth_hns3_pci_probe,
6717         .remove = eth_hns3_pci_remove,
6718 };
6719
6720 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6721 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6722 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6723 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6724                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6725                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
6726                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
6727                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
6728 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
6729 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);